Yield analysis method and device based on maximum sorting mode and electronic equipment

Abstract

The invention provides a yield analysis method and device based on a maximum sorting mode and electronic equipment, and the method comprises the steps: selecting a part of collected circuit samples for simulation, carrying out the training of a replacement model through employing the circuit samples carrying a simulation result and employing a maximum sorting index as the guidance, and obtaining the replacement model meeting a preset requirement. The maximum sorting index is a range in which a set number of failure points determined based on the simulation result of the circuit sample are completely covered by the prediction result of the substitution model. And obtaining prediction results of the residual circuit samples by using the substitution model, and screening out a preset number of circuit samples with the worst prediction result. And performing simulation on the screened circuit samples to determine failure points so as to obtain the yield of the target circuit. In the scheme, the substitution model is trained under the guidance of the maximum sorting index, so that the substitution model has relatively high capability of finding out a failure point under the condition of a relatively small number of samples, and the precision of an analysis result can be improved while the time cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a yield analysis method, device and electronic equipment based on a maximum sorting method. Background Art

[0002] As chip manufacturing technology becomes increasingly sophisticated, the dimensions of components such as transistors have shrunk to the nanometer level, making the internal structures of chips increasingly complex. However, this also presents significant challenges. Even the slightest deviation in parameters during the manufacturing process can significantly affect the electrical properties of a component, even causing device failure. Therefore, accurate analysis of the yield of integrated circuits is crucial to ensuring product quality.

[0003] In existing circuit yield analysis, Monte Carlo (MC) sampling methods are typically used to sample the circuit. Circuit performance is then simulated using circuit simulation tools such as SPICE (Simulation Program with Integrated Circuit Emphasis). Failure points are then determined based on the simulation results, thereby calculating the circuit yield.

[0004] However, for devices with extremely high yield requirements, yield assessment is a problem with extremely low probability. This means that traditional MC methods require tens of millions of simulations to capture failure points. Each simulation requires calling a transistor-level simulator, such as a SPICE simulator, which will incur huge time overhead and lead to problems such as low efficiency. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a yield analysis method, device and electronic device based on a maximum sorting method, so as to reduce time cost and improve the accuracy of analysis results.

[0006] In a first aspect, the present invention provides a yield analysis method based on a maximum sorting method, the method comprising: Collect circuit samples in the target circuit, select some of the circuit samples for simulation to obtain simulation results; Using a circuit sample with simulation results and using a maximum ranking index as a guide, a surrogate model is trained to obtain a surrogate model that meets preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the surrogate model; Using the trained substitution model to obtain prediction results for the remaining circuit samples in the collected circuit samples, and screening out a preset number of circuit samples with the worst prediction results; Failure points are determined from the screened circuit samples based on a simulation method, and the yield of the target circuit is obtained based on the determined failure points.

[0007] In an optional embodiment, the maximum ranking index is calculated in the following manner: Obtaining simulation results, prediction results, and a set number of settings for each of the circuit samples; performing a first sorting of the circuit samples according to the simulation results of the circuit samples, and determining a set number of circuit samples with the worst performance in the first sorting; The circuit samples are sorted in a second order according to the prediction results of each circuit sample, and the index when the second order completely covers the set number of circuit samples with the worst performance in the first order is determined as the index value of the maximum sorting index.

[0008] In an optional embodiment, the set number is determined by: Obtain accuracy and confidence requirements for simulation results regarding simulation methods; Determine the minimum number of failure samples based on accuracy and confidence requirements; The set number is determined based on the minimum value of the failed samples.

[0009] In an optional embodiment, the step of selecting some of the circuit samples for simulation to obtain simulation results includes: dividing the collected circuit samples into a first number of first circuit samples and a second number of second circuit samples; A simulation tool is used to perform circuit performance simulation on each of the first circuit samples to obtain a simulation result of each of the first circuit samples.

[0010] In an optional embodiment, the step of using the trained substitution model to obtain prediction results for the remaining circuit samples in the collected circuit samples and screening out a preset number of circuit samples with the worst prediction results includes: Obtaining prediction results for each of the second circuit samples using the trained substitution model; sorting the second circuit samples based on the prediction results of the second circuit samples; Based on the sorted second circuit samples, a preset number of second circuit samples with the worst prediction results are screened out.

[0011] In an optional embodiment, the step of training the replacement model using the circuit sample carrying the simulation result and guided by the maximum ranking index includes: Constructing multiple initial models, and iteratively training each of the initial models using circuit samples carrying simulation results and with the maximum ranking index as a guide; When a preset iteration stop condition is met, obtaining the index value of the maximum ranking index of each of the initial models; Based on the index value of the maximum ranking index of each of the initial models, the initial model with the best performance is screened out as an alternative model that meets the preset requirements.

[0012] In an optional embodiment, the step of determining the failure point from the screened circuit samples based on simulation includes: Using a simulation tool to obtain simulation results of each of the screened circuit samples; The simulation result of each circuit sample is compared with a preset value, and whether the circuit sample is a failure point is determined based on the comparison result.

[0013] In an optional embodiment, the step of obtaining the yield of the target circuit based on the determined failure point includes: Obtaining the number of determined failure points and the total number of circuit samples collected in the target circuit; The yield of the target circuit is obtained by dividing the number of failure points by the total number of collected circuit samples.

[0014] In a second aspect, the present invention provides a yield analysis device based on a maximum sorting method, the device comprising: An acquisition module is used to acquire circuit samples in a target circuit and select some of the circuit samples for simulation to obtain simulation results; a training module for training a surrogate model using a circuit sample with simulation results and guided by a maximum ranking index to obtain a surrogate model that meets preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the surrogate model; A prediction module is used to obtain prediction results of the remaining circuit samples in the collected circuit samples using the trained substitution model, and screen out a preset number of circuit samples with the worst prediction results; The determination module is used to determine the failure points from the screened circuit samples based on a simulation method, and obtain the yield of the target circuit based on the determined failure points.

[0015] In a third aspect, the present invention provides an electronic device, comprising: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform an operation corresponding to the method in any one of the aforementioned embodiments.

[0016] The present invention provides a yield analysis method, device and electronic device based on the maximum sorting method. After collecting circuit samples in the target circuit, some of the circuit samples are selected for simulation. The circuit samples carrying the simulation results are used to train the replacement model under the guidance of the maximum sorting index to obtain a replacement model that meets the preset requirements. The maximum sorting index is the range required for the set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the replacement model. The replacement model is then used to obtain the prediction results of the remaining circuit samples, and the preset number of circuit samples with the worst prediction results are screened out. The simulation is then performed on the screened circuit samples to determine the failure points, and then the yield of the target circuit is obtained. In this solution, the replacement model is trained under the guidance of the maximum sorting index, so that the replacement model has a higher ability to find failure points when the number of samples is small, thereby reducing the time cost while improving the accuracy of the analysis results. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A flowchart of a yield analysis method based on a maximum sorting method provided by an embodiment of the present invention; Figure 2 A flowchart of a method for determining a maximum sorting index provided by an embodiment of the present invention; Figure 3 for Figure 1 Flowchart of the sub-steps included in S12; Figure 4 for Figure 1 Flowchart of the sub-steps included in S13; Figure 5 for Figure 1 Flowchart of the sub-steps included in S14; Figure 6 for Figure 1 Flowchart of the sub-steps included in S15; Figure 7 A functional module block diagram of a yield analysis device based on a maximum sorting method provided by an embodiment of the present invention; Figure 8 This is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] Based on the above, the existing traditional method uses the MC method to perform circuit yield analysis. However, for reliability analysis of devices such as memory, since memory is composed of millions of unit circuits, tens of thousands of MC simulations need to be run, and each time transistor-level simulation performance evaluation is required, resulting in a huge time overhead and low analysis efficiency.

[0021] Specifically, if we define for dimensional mutually independent random process variables, such as the threshold voltage, gate thickness and electron mobility of each MOS tube, etc. for The joint probability density function of The simulation results of the circuit performance are shown in Figure 2.

[0022] make For failure domain, introduce indicator function :

[0023] The failure rate is:

[0024] Based on the above formula, the failure rate is difficult to calculate directly because it is impossible to know In order to solve the calculation formula of failure rate, the most classic method is to approximate it through Monte Carlo simulation MC, that is, MC directly obtains Sampling is used to evaluate the failure rate. As a result, the failure rate The unbiased estimate of is given by:

[0025] in, Failure rate An unbiased estimate of , N represents the total number of sampling times, Indicates the number of times the simulation results are in the failure domain among all sampling times.

[0026] However, for memory, the yield requirement is extremely high. For example, if a 1KB static random access memory (SRAM) is required to have a 99.73% (3 sigma) yield, then the yield of each SRAM cell is 0.999999669964462 (4.6 sigma). Therefore, for memory, yield assessment is an extremely low-probability problem. As a result, traditional MC methods require tens of millions of simulations to detect a single failure point. Each simulation requires invoking a transistor-level simulator (such as SPICE), which incurs a significant time overhead and is unacceptable.

[0027] To address this shortcoming of traditional methods, a new approach is currently introducing predictive models to predict the performance of sampling points. Compared with traditional MC analysis methods, using predictive models can shorten analysis time, reduce simulation overhead, and improve circuit yield analysis efficiency.

[0028] However, existing prediction models are trained using relative error as a guide to ensure accuracy near the failure domain. This approach offers high accuracy when applied to small-scale circuits. However, as the circuit scale increases, the number of input parameters becomes enormous, significantly increasing the modeling overhead and making accuracy difficult to guarantee. Furthermore, for yield analysis, the most crucial failure points are located in the failure domain, but these points are difficult to obtain as test sets. Furthermore, due to the multitude of process variables that affect circuits, ensuring model accuracy near the failure domain requires a large number of training samples.

[0029] Therefore, the existing method requires a large number of training samples, which has the problem of high time and resource costs. On the other hand, it is difficult to obtain enough failure points to add to the test set, which affects the accuracy.

[0030] In response to the defects of the above-mentioned existing methods, the present invention provides a yield analysis solution based on the maximum sorting method, which uses the maximum sorting index determined by the range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the alternative model as a guide for training the alternative model, so that the alternative model has a higher ability to find failure points when there are fewer samples, thereby achieving the effect of reducing time costs while improving the accuracy of the analysis results.

[0031] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0032] Figure 1 A flow chart of the steps of a yield analysis method based on the maximum sorting method provided by an embodiment of the present invention. Figure 1As shown, the yield analysis method based on the maximum sorting mode of this embodiment includes the following steps: S11, collecting circuit samples in the target circuit, selecting some of the circuit samples for simulation to obtain simulation results.

[0033] S12, using the circuit sample carrying the simulation result and taking the maximum ranking index as a guide to train the replacement model, to obtain the replacement model that meets the preset requirements.

[0034] The maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the alternative model.

[0035] S13, using the trained replacement model to obtain prediction results of the remaining circuit samples in the collected circuit samples, and screening out a preset number of circuit samples with the worst prediction results.

[0036] S14, determining a failure point from the screened circuit samples based on a simulation method.

[0037] S15: Obtaining the yield of the target circuit based on the determined failure point.

[0038] In this embodiment, the circuit sample can be a process variable related to a MOS tube in the circuit. For example, the circuit sample can be recorded as , X is dimensional mutually independent random process variables, such as the threshold voltage, gate thickness, and electron mobility of each MOS tube. The MC sampling method can be used to sample the target circuit to collect a large number of circuit samples. The number of collected circuit samples can be recorded as .

[0039] However, in order to avoid a large number of simulations, only some circuit samples are selected from the sampled circuit samples for simulation to obtain simulation results. For example, the number of selected circuit samples can be recorded as , circuit performance simulation is performed through SPICE simulation tools.

[0040] Specifically, the collected circuit samples may be divided into a first number of first circuit samples and a second number of second circuit samples, and a simulation tool may be used to perform circuit performance simulation on each first circuit sample to obtain a simulation result of each first circuit sample.

[0041] The surrogate model is trained using circuit samples with simulation results. The training process is guided by a maximum ranking metric. This metric is defined as the range required for the surrogate model's predictions to fully cover a set number of failure points, as determined by the circuit sample's simulation results. A smaller range indicates a greater ability of the surrogate model to find failure points.

[0042] See also Figure 2 In this embodiment, during the training of the alternative model, the maximum ranking index can be calculated as follows: S21, obtaining simulation results, prediction results and set numbers of each circuit sample.

[0043] S22 , performing a first sorting of the circuit samples according to the simulation results of the circuit samples, and determining a set number of circuit samples with the worst performance in the first sorting.

[0044] S23, performing a second sorting on the circuit samples according to the prediction results of each circuit sample, and determining the index when the second sorting completely covers the set number of circuit samples with the worst performance in the first sorting, as the index value of the maximum sorting index.

[0045] In this embodiment, the number of circuit samples selected for alternative model training is ,get The simulation results of each circuit sample in the circuit samples are collected, and the circuit samples are sorted from worst to best based on the simulation results. For ease of distinction, this sorting process is referred to as the first sorting. In addition, the first index of each circuit sample in the first sorting is marked.

[0046] In the first sorting, a set number of circuit samples with the worst performance are determined, that is, the circuit samples ranked in the top set positions.

[0047] After each circuit sample is processed by the surrogate model, the surrogate model outputs a corresponding prediction result for each circuit sample, i.e., the predicted circuit performance. Similarly, based on the prediction results, the circuit samples are sorted from worst to best performance, referred to as a second sorting. Furthermore, a second index for each circuit sample in the second sorting is determined.

[0048] The set number of circuit samples determined in the first sorting are searched in the second sorting to find circuit samples in the second sorting that correspond to the set number of circuit samples. Furthermore, a second index in the second sorting is determined for each found circuit sample. For example, if the set number is 20, and when searching in the second sorting, index 40 is found, all circuit samples corresponding to the 20 circuit samples are found. Then, index 40 is the index in the second sorting that completely covers the set number of circuit samples with the worst performance in the first sorting. That is, this index can be used as the index value of the maximum sorting index.

[0049] In this embodiment, the surrogate model is trained using the maximum ranking index as a guide. Model training is performed in a direction that minimizes the maximum ranking index until a surrogate model that meets preset requirements is obtained. This surrogate model can then be used for performance prediction. For example, if the maximum ranking index is less than a preset threshold, it can be determined that the surrogate model meets the preset requirements.

[0050] The pseudo code for calculating the maximum sorting index is as follows: Input: Real circuit performance obtained from SPICE , the model predicts the circuit performance , and the required number of failure samples ; Output: the value of the maximum ranking index (Rating); function

[0051] for do if then return

[0052] end if end for end function Bundle Sort and return its index and store it in ; Bundle Sort and return its index and store it in ; definition

[0053] for do r = GetElementPosition ( y 2, y1[ i ]) if then m = r end if end for return

[0054] In this embodiment, the maximum ranking metric is used to determine whether the surrogate model in the yield analysis scenario can filter out a set number of circuit samples with the worst performance at a relatively low cost, rather than focusing on the specific relative error. In this way, even if the surrogate model's accuracy cannot be achieved with a limited number of training samples, the surrogate model's prediction of circuit performance can maintain relative consistency with the ranking of the circuit simulation results, thus achieving accurate yield prediction.

[0055] In the above process, the numerical setting of the set number is involved. The set number can be determined by the following methods: Obtaining accuracy requirements and confidence requirements for simulation results of the simulation method; determining a minimum value of failure samples based on the accuracy requirements and the confidence requirements; and determining the set number based on the minimum value of failure samples.

[0056] In the above MC failure rate approximation formula, It's real The more N is, the more The closer But it is not possible to Therefore, confidence and accuracy are generally used to determine N that makes the MC results converge, as shown in the following formula:

[0057] in, Indicates confidence, Indicates accuracy. The value of N here indicates that the evaluation result of MC is within (1- )100% confidence level and The quality factor of the MC method is defined as follows:

[0058] in, yes The variance of . This means that the current assessment has reached Accuracy and For example, it is generally necessary to make , which means 90% accuracy and confidence. In this case, N should be greater than 100 / , which means that at least 100 failure samples are required ( ). Therefore, the set number can be determined based on the minimum value of failure samples (such as 100), for example, the set number is greater than or equal to the minimum value of failure samples.

[0059] In this embodiment, considering that the scales of different circuits are different, the number of process variables that affect their performance is different, that is, The dimensions are different, depending on the size of the circuit, The dimensions of the dataset can range from a dozen to tens of thousands. This results in different models being required in different scenarios. Therefore, this solution builds an adaptive model selection scheme.

[0060] Specifically, see Figure 3 In the above step of using circuit samples with simulation results and training the replacement model with the maximum ranking index as a guide, this can be achieved in the following ways: S121, constructing multiple initial models, using circuit samples carrying simulation results and using the maximum ranking index as a guide to iteratively train each of the initial models.

[0061] S122, when a preset iteration stopping condition is met, obtaining the index value of the maximum ranking index of each of the initial models.

[0062] S123: Screening out the initial model with the best performance based on the index value of the maximum ranking index of each of the initial models as a replacement model that meets the preset requirements.

[0063] In this embodiment, the multiple initial models may include linear models, LASSO regression models, neural network models, etc. The circuit samples with simulation results are used to train the initial models simultaneously, and the performance of the initial models is evaluated using the maximum ranking index.

[0064] When the preset iteration stopping conditions are met, such as when the number of iterative training iterations reaches a preset maximum, when the iterative training duration reaches a preset maximum, or when the maximum ranking index reaches convergence and no longer changes, the maximum ranking index value for each initial model can be obtained. The smaller the maximum ranking index, the stronger the model's ability to find failure points and the better the performance. Therefore, based on the maximum ranking index values ​​of each initial model, the initial model with the smallest index value is selected as the replacement model that meets the preset requirements.

[0065] In this way, based on the actual application scenario, the model with the best performance in the current scenario can be screened out for subsequent prediction processing.

[0066] Based on the substitution model trained in the above manner, the trained substitution model is used to obtain prediction results of the remaining circuit samples in the collected circuit samples, and a preset number of circuit samples with the worst prediction results are screened out. For details, please refer to Figure 4 , this step can be achieved by: S131: Obtain prediction results for each of the second circuit samples using the trained substitution model.

[0067] S132: Sort the second circuit samples based on the prediction results of the second circuit samples.

[0068] S133 : Filter out a preset number of second circuit samples with the worst prediction results based on the sorted second circuit samples.

[0069] Using the surrogate model to obtain circuit performance predictions for the remaining circuit samples in the target circuit eliminates the need for simulation tools, significantly improving analysis efficiency and saving time. Similarly, the remaining circuit samples are sorted from worst to best in terms of predicted results. After sorting, a predetermined number of second circuit samples with the worst predicted results are selected.

[0070] The size of the preset number here is determined by the performance of the alternative model, specifically, by the index value of the maximum sorting index of the alternative model. The larger the index value of the maximum sorting index, the larger the preset number required to be screened for re-simulation.

[0071] After screening out a preset number of circuit samples, the failure points are determined from the screened circuit samples based on simulation. For details, please refer to Figure 5 , this step can be achieved by: S141: Using a simulation tool, obtain a simulation result of each of the screened circuit samples.

[0072] S142 , comparing the simulation result of each circuit sample with a preset value, and determining whether the circuit sample is a failure point based on the comparison result.

[0073] In this embodiment, the simulation tool SPICE is used to simulate the circuit performance of each selected circuit sample, obtaining simulation results for each circuit sample. The simulation results are compared with preset values. If the simulation result exceeds the preset value, it can be determined that the corresponding circuit sample is in the failure domain, that is, the failure point. If the simulation result is less than or equal to the preset value, it can be determined that the corresponding circuit sample is not in the failure domain.

[0074] In this way, by screening a preset number of circuit samples based on the surrogate model, we can ensure that the preset number of circuit samples screened out contain the set number of circuit samples with the worst performance. Based on this, re-simulation using simulation tools can accurately obtain simulation results for each circuit sample, and then accurately determine the failure point.

[0075] Finally, the yield of the target circuit is obtained based on the determined failure points. Figure 6 , this step can be achieved by: S151 , obtaining the number of determined failure points and the total number of circuit samples collected in the target circuit.

[0076] S152 , dividing the number of failure points by the total number of collected circuit samples to obtain the yield of the target circuit.

[0077] From the above, the total number of circuit samples collected for the target circuit is , assuming that the number of failure points finally determined is , then the yield of the target circuit is .

[0078] The yield analysis method based on maximum ranking provided in this embodiment uses the maximum ranking metric to measure the model's ability to capture failure points, thereby enabling circuit yield analysis and prediction under extremely low probability conditions with minimal training costs. This avoids the high time and resource costs associated with the large number of training samples required in the prior art, as well as the difficulty in obtaining sufficient failure points for training in extremely low probability scenarios, which can affect accuracy. This solution can reduce time costs while improving the accuracy of analysis results.

[0079] Figure 7 FIG. 1 is a structural block diagram of a yield analysis device based on a maximum sorting method according to an embodiment of the present invention. Figure 7 As shown, the yield analysis device based on the maximum sorting method of this embodiment includes: An acquisition module is used to acquire circuit samples in a target circuit and select some of the circuit samples for simulation to obtain simulation results; a training module for training a surrogate model using a circuit sample with simulation results and guided by a maximum ranking index to obtain a surrogate model that meets preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the surrogate model; A prediction module is used to obtain prediction results of the remaining circuit samples in the collected circuit samples using the trained substitution model, and screen out a preset number of circuit samples with the worst prediction results; The determination module is used to determine the failure points from the screened circuit samples based on a simulation method, and obtain the yield of the target circuit based on the determined failure points.

[0080] As a possible implementation, the maximum ranking index is calculated in the following way: Obtaining simulation results, prediction results, and a set number of settings for each of the circuit samples; performing a first sorting of the circuit samples according to the simulation results of the circuit samples, and determining a set number of circuit samples with the worst performance in the first sorting; The circuit samples are sorted in a second order according to the prediction results of each circuit sample, and the index when the second order completely covers the set number of circuit samples with the worst performance in the first order is determined as the index value of the maximum sorting index.

[0081] As a possible implementation, the set number is determined by: Obtain accuracy and confidence requirements for simulation results regarding simulation methods; Determine the minimum number of failure samples based on accuracy and confidence requirements; The set number is determined based on the minimum value of the failed samples.

[0082] As a possible implementation method, the acquisition module is used to select some circuit samples for simulation to obtain simulation results in the following manner: dividing the collected circuit samples into a first number of first circuit samples and a second number of second circuit samples; A simulation tool is used to perform circuit performance simulation on each of the first circuit samples to obtain a simulation result of each of the first circuit samples.

[0083] As a possible implementation, the above training module is trained in the following way: Constructing multiple initial models, and iteratively training each of the initial models using circuit samples carrying simulation results and with the maximum ranking index as a guide; When a preset iteration stop condition is met, obtaining the index value of the maximum ranking index of each of the initial models; Based on the index value of the maximum ranking index of each of the initial models, the initial model with the best performance is screened out as an alternative model that meets the preset requirements.

[0084] As a possible implementation, the prediction module is configured to perform prediction and select a preset number of circuit samples with the worst prediction results by: Obtaining prediction results for each of the second circuit samples using the trained substitution model; sorting the second circuit samples based on the prediction results of the second circuit samples; Based on the sorted second circuit samples, a preset number of second circuit samples with the worst prediction results are screened out.

[0085] As a possible implementation, the determination module is configured to determine the failure point from the screened circuit samples based on simulation in the following manner: Using a simulation tool to obtain simulation results of each of the screened circuit samples; The simulation result of each circuit sample is compared with a preset value, and whether the circuit sample is a failure point is determined based on the comparison result.

[0086] As a possible implementation, the determination module is configured to obtain the yield of the target circuit based on the determined failure points in the following manner: Obtaining the number of determined failure points and the total number of circuit samples collected in the target circuit; The yield of the target circuit is obtained by dividing the number of failure points by the total number of collected circuit samples.

[0087] The yield analysis device based on maximum sorting provided in this embodiment is used to implement the corresponding yield analysis methods based on maximum sorting in the aforementioned multiple method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described in detail here. In addition, the functional implementation of each module in the yield analysis device based on maximum sorting in this embodiment can refer to the corresponding descriptions in the aforementioned method embodiments, and will not be described in detail here.

[0088] Reference Figure 8 , shows a schematic structural diagram of an electronic device according to an exemplary embodiment of the present invention. The specific embodiments of the present invention do not limit the specific implementation of the electronic device.

[0089] like Figure 8 As shown, the electronic device may include: a processor, a memory, a communication bus, and a communication interface.

[0090] The processor, memory and communication interface communicate with each other through a communication bus.

[0091] Communication interface, used to communicate with other electronic devices or servers.

[0092] The processor is configured to execute a program, and specifically may execute the steps of the yield analysis method based on the maximum sorting method described in any one of the above embodiments.

[0093] Specifically, the program may include program codes including computer operation instructions.

[0094] The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs, or processors of different types, such as one or more CPUs and one or more ASICs.

[0095] Memory, used to store programs. Memory may include high-speed RAM (RAM) or non-volatile memory, such as at least one disk drive.

[0096] The program can be specifically configured to cause a processor to execute the steps of any of the yield analysis methods based on the maximum sorting method described in the embodiments. The specific implementation of each step in the program can be found in the corresponding descriptions of the steps and units executed in any of the yield analysis methods based on the maximum sorting method described above, and will not be repeated here.

[0097] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding process descriptions in the aforementioned method embodiments.

[0098] An embodiment of the present invention further provides a computer storage medium storing a computer program, which, when executed by a processor, implements the yield analysis method based on the maximum sorting method as described in any one of the above-mentioned method embodiments.

[0099] An embodiment of the present invention further provides a computer program product, including computer instructions, which instruct a computing device to execute operations corresponding to the yield analysis method based on the maximum sorting method described in any of the above-mentioned method embodiments.

[0100] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, the indirect coupling or communication connection of the device or unit may be electrical, mechanical or other forms.

[0101] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] Furthermore, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0103] It should be noted that if a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0105] The foregoing description is merely an embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A yield analysis method based on maximum sorting, characterized in that: The method comprises: Collect circuit samples in the target circuit, select some of the circuit samples for simulation to obtain simulation results; Using a circuit sample with simulation results and using a maximum ranking index as a guide, a surrogate model is trained to obtain a surrogate model that meets preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the surrogate model; Using the trained substitution model to obtain prediction results for the remaining circuit samples in the collected circuit samples, and screening out a preset number of circuit samples with the worst prediction results; Determine the failure point from the screened circuit samples based on simulation; The yield of the target circuit is obtained based on the determined failure points.

2. The yield analysis method based on maximum sorting according to claim 1, characterized in that: The maximum ranking index is calculated as follows: Obtaining simulation results, prediction results, and a set number of settings for each of the circuit samples; performing a first sorting of the circuit samples according to the simulation results of the circuit samples, and determining a set number of circuit samples with the worst performance in the first sorting; The circuit samples are sorted in a second order according to the prediction results of each circuit sample, and the index when the second order completely covers the set number of circuit samples with the worst performance in the first order is determined as the index value of the maximum sorting index.

3. The yield analysis method based on maximum sorting according to claim 2, characterized in that: The set number is determined by the following method: Obtain accuracy and confidence requirements for simulation results regarding simulation methods; Determine the minimum number of failure samples based on accuracy and confidence requirements; The set number is determined based on the minimum value of the failed samples.

4. The yield analysis method based on maximum sorting according to claim 1, characterized in that: The step of selecting some of the circuit samples to perform simulation and obtain simulation results includes: dividing the collected circuit samples into a first number of first circuit samples and a second number of second circuit samples; A simulation tool is used to perform circuit performance simulation on each of the first circuit samples to obtain a simulation result of each of the first circuit samples.

5. The yield analysis method based on maximum sorting according to claim 4, characterized in that: The step of using the trained substitution model to obtain prediction results of the remaining circuit samples in the collected circuit samples and screening out a preset number of circuit samples with the worst prediction results includes: Obtaining prediction results for each of the second circuit samples using the trained substitution model; sorting the second circuit samples based on the prediction results of the second circuit samples; Based on the sorted second circuit samples, a preset number of second circuit samples with the worst prediction results are screened out.

6. The yield analysis method based on maximum sorting according to claim 1, characterized in that: The step of using the circuit sample with the simulation result and training the replacement model with the maximum ranking index as a guide includes: Constructing multiple initial models, and iteratively training each of the initial models using circuit samples carrying simulation results and with the maximum ranking index as a guide; When a preset iteration stop condition is met, obtaining the index value of the maximum ranking index of each of the initial models; Based on the index value of the maximum ranking index of each of the initial models, the initial model with the best performance is screened out as a replacement model that meets the preset requirements.

7. The yield analysis method based on maximum sorting according to claim 1, characterized in that: The step of determining the failure point from the screened circuit samples based on the simulation method includes: Using a simulation tool to obtain simulation results of each of the screened circuit samples; The simulation result of each circuit sample is compared with a preset value, and whether the circuit sample is a failure point is determined based on the comparison result.

8. The yield analysis method based on maximum sorting according to claim 1, characterized in that: The step of obtaining the yield of the target circuit based on the determined failure point includes: Obtaining the number of determined failure points and the total number of circuit samples collected in the target circuit; The yield of the target circuit is obtained by dividing the number of failure points by the total number of collected circuit samples.

9. A yield analysis device based on maximum sorting method, characterized in that: The device comprises: An acquisition module is used to acquire circuit samples in a target circuit and select some of the circuit samples for simulation to obtain simulation results; a training module for training a surrogate model using a circuit sample with simulation results and guided by a maximum ranking index to obtain a surrogate model that meets preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit sample to be completely covered by the prediction results of the surrogate model; A prediction module is used to obtain prediction results of the remaining circuit samples in the collected circuit samples using the trained substitution model, and screen out a preset number of circuit samples with the worst prediction results; The determination module is used to determine the failure points from the screened circuit samples based on a simulation method, and obtain the yield of the target circuit based on the determined failure points.

10. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, where the executable instruction enables the processor to perform an operation corresponding to the method according to any one of claims 1 to 8.

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