Semiconductor surface defect detection method and system based on machine vision

Abstract

The invention provides a semiconductor surface defect detection method and system based on machine vision. The method comprises the following steps: contrastively analyzing surface machine vision identification data of a plurality of wafers, determining defect distribution generality of all the wafers, extracting system defects of the wafers, and accurately and comprehensively calibrating defects generated by equipment or process reasons in the wafers; the method comprises the following steps: generating a defect distribution characterization diagram of a wafer in all manufacturing threads according to the defect distribution characterization diagram, thereby determining the surface defect clustering characteristics of the wafer, comprehensively calibrating the defect type and distribution of the wafer in each manufacturing thread, identifying whether the defects of the wafer have great influence on the quality or not, and accurately judging whether the wafer is in a failure state or not. The overall performance of the wafer is effectively evaluated; in addition, defect formation reproduction identification is carried out on all wafers in a failure state in the same manufacturing thread, improperly executed manufacturing threads are determined, the manufacturing threads with defects are accurately traced, the corresponding manufacturing threads can be debugged and corrected, and the wafer processing yield can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection, and in particular to a method and system for detecting semiconductor surface defects based on machine vision. Background Art

[0002] Integrated circuits are fabricated by integrating numerous electronic components onto the surface of a semiconductor wafer, creating a corresponding circuit layout. The integrity of the wafer surface directly impacts the quality of the integrated circuit. The more and more widely distributed defects on the wafer surface, the greater the impact on the circuit layout. Currently, machine vision recognition technology is used to detect defects on the wafer surface, identifying the type and number of surface defects, which provides a basis for identifying wafer performance indicators. Considering that a wafer typically undergoes multiple manufacturing processes to form a complete circuit layout on its surface, and each manufacturing process may form defect structures on the wafer surface during execution, the aforementioned machine vision recognition only detects defects on wafers that have completed all manufacturing processes. This can only assess the overall defect status of the wafer itself and cannot comprehensively and accurately trace defects that may occur in each manufacturing process. It is also impossible to accurately locate the manufacturing process that caused the defect, making it impossible to debug the corresponding manufacturing process, thereby reducing the yield rate of subsequent wafer processing. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor surface defect detection method and system based on machine vision, compare and analyze the surface machine vision recognition data of several wafers, determine the commonality of defect distribution of all wafers, extract the system defects of the wafers, and accurately and comprehensively calibrate the defects caused by equipment or process reasons in the wafers; generate defect distribution characterization diagrams of the wafers in all manufacturing threads, thereby determining the surface defect clustering characteristics of the wafers, and comprehensively calibrate the defect types and distributions generated by the wafers in each manufacturing thread, thereby identifying whether the defects existing in the wafers have a significant impact on the quality, accurately judging whether the wafers are in a failed state, and effectively evaluating the overall performance of the wafers; also performing defect formation reproduction identification on all wafers in a failed state in the same manufacturing thread, determining the improperly executed manufacturing threads, and accurately tracing the manufacturing threads that caused the defects, which is helpful to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

[0004] The present invention is achieved through the following technical solutions:

[0005] A method for detecting semiconductor surface defects based on machine vision, comprising:

[0006] Comparing and analyzing surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers; and extracting systematic defects of the wafers based on the commonality of defect distribution;

[0007] Generating a defect distribution representation diagram of the wafer in a corresponding manufacturing thread based on the defect morphology of the wafer's system defects; determining a surface defect clustering feature of the wafer based on the defect distribution representation diagram of the wafer in all manufacturing threads;

[0008] Based on the surface defect clustering characteristics, it is determined whether the wafer is in a failed state; defect formation reproduction identification is performed on all wafers in a failed state to determine the improperly executed manufacturing thread.

[0009] Optionally, surface machine vision recognition data of several wafers are compared and analyzed to determine the commonality of defect distribution of all wafers; and based on the commonality of defect distribution, systematic defects of the wafers are extracted, including:

[0010] After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the surface of the wafer;

[0011] Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing thread to determine the commonality of defect distribution across all wafers; wherein the commonality of defect distribution includes the positional distribution correlation of surface defects across all wafers;

[0012] Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

[0013] Optionally, generating a defect distribution representation diagram of the wafer in a corresponding manufacturing thread based on the defect morphology of the systematic defects of the wafer; and determining the surface defect clustering characteristics of the wafer based on the defect distribution representation diagrams of the wafer in all manufacturing threads, including:

[0014] Perform defect image pixel recognition on systematic defects of the wafer to obtain three-dimensional morphology and contour data of the systematic defects; generate a defect distribution representation map of the wafer in the corresponding manufacturing thread based on the three-dimensional morphology and contour data; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread;

[0015] According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the surface of the wafer.

[0016] Optionally, judging whether the wafer is in a failed state based on the surface defect clustering characteristics; performing defect formation recurrence identification on all wafers in a failed state to determine improperly executed manufacturing threads includes:

[0017] estimating a spatial proportion of a failure region on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface; wherein the spatial proportion of the failure region refers to a spatial overlap ratio between the failure region and the circuit wiring region on the wafer surface; and determining whether the wafer is in a failure state based on the spatial proportion of the failure region;

[0018] Defect formation reproduction identification is performed on the surface machine vision recognition data of all wafers in a failed state corresponding to the same manufacturing thread to obtain the defect recurrence probability of the wafer in the same manufacturing thread; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

[0019] Optionally, estimating a spatial proportion of a failure area on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface includes:

[0020] Extracting the number of periodic defect clusters of structural defects on the surface of the wafer;

[0021] Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster;

[0022] The structural defect period factor is obtained by the following formula:

[0023]

[0024] Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S a represents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3;

[0025] Extracting the number of foreign matter defects on the surface of the wafer;

[0026] Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect;

[0027] Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect;

[0028] The foreign matter defect distribution factor is obtained by the following formula:

[0029]

[0030] Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test (3.84 at 95% confidence level);

[0031] Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor;

[0032] The ratio of the failure area on the wafer surface is obtained by the following formula:

[0033]

[0034] Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

[0035] A semiconductor surface defect detection system based on machine vision, comprising:

[0036] The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers;

[0037] A system defect extraction module, configured to extract system defects of the wafer based on the commonality of the defect distribution;

[0038] A defect representation diagram generating module, configured to generate a defect distribution representation diagram of the wafer in a corresponding manufacturing thread according to the defect morphology of the system defects of the wafer;

[0039] A defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization diagram of the wafer in all manufacturing threads;

[0040] A failure state judgment module, configured to judge whether the wafer is in a failure state based on the surface defect clustering characteristics;

[0041] The manufacturing thread calibration module is used to identify the recurrence of defects on all wafers in a failed state and determine the improperly executed manufacturing thread.

[0042] Optionally, the defect commonality identification module is used to compare and analyze surface machine vision recognition data of several wafers to determine the commonality of defect distribution of all wafers, including:

[0043] After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the surface of the wafer;

[0044] Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing thread to determine the commonality of defect distribution across all wafers; wherein the commonality of defect distribution includes the positional distribution correlation of surface defects across all wafers;

[0045] The system defect extraction module is used to extract the system defects of the wafer according to the commonality of the defect distribution, including:

[0046] Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

[0047] Optionally, the defect representation map generating module is used to generate a defect distribution representation map of the wafer in a corresponding manufacturing thread according to the defect morphology of the system defects of the wafer, including:

[0048] Perform defect image pixel recognition on systematic defects of the wafer to obtain three-dimensional morphology and contour data of the systematic defects; generate a defect distribution representation map of the wafer in the corresponding manufacturing thread based on the three-dimensional morphology and contour data; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread;

[0049] The defect cluster feature determination module is used to determine the surface defect cluster features of the wafer according to the defect distribution characterization diagram of the wafer in all manufacturing threads, including:

[0050] According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the surface of the wafer.

[0051] Optionally, the failure state judgment module is used to judge whether the wafer is in a failure state according to the surface defect clustering characteristics, including:

[0052] estimating a spatial proportion of a failure region on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface; wherein the spatial proportion of the failure region refers to a spatial overlap ratio between the failure region and the circuit wiring region on the wafer surface; and determining whether the wafer is in a failure state based on the spatial proportion of the failure region;

[0053] The manufacturing thread calibration module is used to perform defect formation recurrence identification on all wafers in a failed state and determine the improperly executed manufacturing thread, including:

[0054] Defect formation reproduction identification is performed on the surface machine vision recognition data of all wafers in a failed state corresponding to the same manufacturing thread to obtain the defect recurrence probability of the wafer in the same manufacturing thread; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

[0055] Optionally, estimating a spatial proportion of a failure area on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface includes:

[0056] Extracting the number of periodic defect clusters of structural defects on the surface of the wafer;

[0057] Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster;

[0058] The structural defect period factor is obtained by the following formula:

[0059]

[0060] Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S arepresents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3;

[0061] Extracting the number of foreign matter defects on the surface of the wafer;

[0062] Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect;

[0063] Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect;

[0064] The foreign matter defect distribution factor is obtained by the following formula:

[0065]

[0066] Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test (3.84 at 95% confidence level);

[0067] Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor;

[0068] The ratio of the failure area on the wafer surface is obtained by the following formula:

[0069]

[0070] Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

[0071] Compared with the prior art, the present invention has the following beneficial effects:

[0072] The machine vision-based semiconductor surface defect detection method and system provided in the present application compare and analyze the surface machine vision recognition data of several wafers, determine the commonality of defect distribution of all wafers, extract the systematic defects of the wafers, and accurately and comprehensively calibrate the defects caused by equipment or process reasons in the wafers; generate defect distribution characterization diagrams of the wafers in all manufacturing threads to determine the surface defect clustering characteristics of the wafers, and comprehensively calibrate the defect types and distributions generated by the wafers in each manufacturing thread, so as to identify whether the defects existing in the wafers have a significant impact on the quality, accurately judge whether the wafers are in a failed state, and effectively evaluate the overall performance of the wafers; also perform defect formation reproduction identification on all wafers in a failed state in the same manufacturing thread, determine the improperly executed manufacturing thread, and accurately trace the manufacturing thread that caused the defect, which is helpful to debug and correct the corresponding manufacturing thread and improve the wafer processing yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. Among them:

[0074] Figure 1 A schematic flow chart of a method for detecting semiconductor surface defects based on machine vision provided by the present invention.

[0075] Figure 2 It is a schematic diagram of the random defect distribution on the wafer surface.

[0076] Figure 3 It is a schematic diagram of the overall defect distribution on the wafer surface.

[0077] Figure 4 This is a structural schematic diagram of a semiconductor surface defect detection system based on machine vision provided by the present invention. DETAILED DESCRIPTION

[0078] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0079] As used herein, the terms "comprise," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0080] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0081] See also Figure 1 As shown, an embodiment of the present application provides a method for detecting semiconductor surface defects based on machine vision. The method for detecting semiconductor surface defects based on machine vision includes:

[0082] Compare and analyze surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers; based on the commonality of defect distribution, extract the systematic defects of the wafers;

[0083] Generate a defect distribution representation diagram of the wafer in the corresponding manufacturing thread based on the defect morphology of the wafer's systematic defects; and determine the surface defect clustering characteristics of the wafer based on the defect distribution representation diagram of the wafer in all manufacturing threads.

[0084] Based on the surface defect clustering characteristics, determine whether the wafer is in a failed state; perform defect formation reproduction identification on all wafers in a failed state to determine the improperly executed manufacturing thread.

[0085] The beneficial effects of the above embodiments are as follows: the semiconductor surface defect detection method based on machine vision compares and analyzes the surface machine vision recognition data of several wafers, determines the commonality of defect distribution of all wafers, extracts the system defects of the wafers, and accurately and comprehensively calibrates the defects caused by equipment or process reasons in the wafers; generates defect distribution characterization diagrams of the wafers in all manufacturing threads, thereby determining the surface defect clustering characteristics of the wafers, and comprehensively calibrates the defect types and distributions generated by the wafers in each manufacturing thread, thereby identifying whether the defects existing in the wafers have a significant impact on the quality, accurately judging whether the wafers are in a failed state, and effectively evaluating the overall performance of the wafers; it also performs defect formation reproduction identification on all wafers in a failed state in the same manufacturing thread, determines the improperly executed manufacturing threads, and accurately traces the manufacturing threads that produce defects, which is helpful to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

[0086] In another embodiment, surface machine vision recognition data of several wafers are compared and analyzed to determine the commonality of defect distribution among all wafers; and systematic defects of the wafers are extracted based on the commonality of defect distribution, including:

[0087] After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the wafer surface;

[0088] Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing process to determine the commonality of defect distribution across all wafers. This commonality includes the correlation of the positional distribution of surface defects across all wafers.

[0089] Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

[0090] Integrated circuit production uses wafers as substrates, and through multiple manufacturing processes (multiple manufacturing processes), a large number of electronic components and their wiring are manufactured on the wafer surface, forming a complete circuit layout. Due to factors such as the manufacturing environment, hardware equipment operating performance, and process parameters, each wafer manufacturing process may cause unexpected defects. These unexpected defects can be categorized into, but not limited to, random defects and systematic defects based on their causes. Furthermore, these unexpected defects can be categorized into, structural defects and foreign matter defects based on their physical form. Random defects are defects caused by manufacturing environmental conditions. Random defects are distributed with significant randomness on the wafer surface, making it difficult to accurately determine their cause. Systematic defects are defects caused by hardware equipment operating performance and process parameters. The number and physical form of systematic defects are closely related to these characteristics, and can be significantly reduced by improving them. Structural defects are structural defects such as scratches and dents that form on the wafer surface. Foreign matter defects are defects caused by foreign matter such as dust or oil. During the manufacturing process of wafers, random defects and systematic defects will be generated at the same time. The above two defects are superimposed on the surface of the wafer at the same time. Considering that random defects and systematic defects have different causes and have the same structural defects and foreign matter defect morphologies, it is impossible to accurately distinguish between random defects and systematic defects in the same wafer alone, and thus it is impossible to identify the systematic defects of the wafer separately, and it is impossible to provide a basis for improving the hardware equipment operation and process parameters corresponding to the manufacturing thread that produces the above systematic defects.

[0091] Taking into account that several wafers are in the process of implementing the same manufacturing thread, the manufacturing environment conditions where all wafers are located are the same, it can be considered that all wafers have similarities in structure and spatial distribution when implementing the random defects generated by the same manufacturing thread. When the number of wafers implementing the same manufacturing thread is sufficient, the surface defect similarity information generated after all wafers are passed through the same manufacturing thread can be identified by comparing and analyzing the surface defect data of all wafers passing through the same manufacturing thread, and the random defects generated after the wafers are passed through the corresponding manufacturing thread can be determined. Specifically, whenever all wafers complete an identical manufacturing thread respectively, the respective processing surface images of all wafers (i.e., the global image of the surface of the wafer manufacturing electronic component) are collected, and the processing surface images are carried out machine vision recognition using a deep learning neural network model, and the surface defect distribution position data after each wafer corresponding to each manufacturing thread are obtained, wherein the above-mentioned surface defect distribution position data simultaneously include random defects and systematic defect distribution position data on the wafer surface. Then, the surface machine vision recognition data of all wafers after completing the same manufacturing thread are input into a neural network model such as a support vector machine (SVM) for spatial distribution comparative analysis to obtain the position distribution correlation of surface defects of all wafers. The above-mentioned position distribution correlation of surface defects can be but is not limited to the similarity of the surface defect distribution position vector clusters of the wafers, thereby obtaining the commonality of defect distribution of all wafers, which provides a reliable basis for the subsequent determination of random defects generated after all wafers complete the corresponding manufacturing threads.

[0092] The above analysis shows that the random defects generated by all wafers in the same manufacturing process have similarities in structure, morphology and spatial distribution. The commonality of defect distribution of all wafers is directly and strongly correlated with the random defects. Therefore, transfer learning is performed based on the commonality of defect distribution of all wafers to identify the random defects on the surface of all wafers. Figure 2 As shown in the figure, the random defect distribution on a wafer surface is obtained after the transfer learning process of the commonality of defect distribution. Figure 2 It can be seen that the defects on the wafer surface are randomly distributed, and the range of defects is small, which is indeed consistent with the above description of random absence. It can be determined that by comparing and analyzing the surface machine vision recognition data of all wafers, the common characteristics of defect distribution can be obtained and the random defect distribution on the wafer surface can be further determined. Figure 3 As shown, the overall defect distribution of a wafer surface after the corresponding manufacturing thread is shown. It can be understood that Figure 3 The overall defect distribution of the wafer surface includes both random defects and systematic defects. The random defects on the wafer surface are compared with the overall surface defects after the wafer completes the corresponding manufacturing thread, and the systematic defects generated by the wafer in the corresponding manufacturing thread are extracted. Figure 2 and Figure 3 Compare pixel features from Figure 3 Eliminate Figure 2 The corresponding defect features can be extracted to obtain the systematic defects generated on the wafer surface by the current manufacturing thread.

[0093] In another embodiment, a defect distribution representation diagram of the wafer in a corresponding manufacturing thread is generated based on the defect morphology of the wafer's systematic defects; and a surface defect clustering feature of the wafer is determined based on the defect distribution representation diagram of the wafer in all manufacturing threads, including:

[0094] Perform defect image pixel recognition on the wafer's systematic defects to obtain three-dimensional morphology and contour data of the systematic defects; based on the three-dimensional morphology and contour data, generate a defect distribution representation map of the wafer in the corresponding manufacturing thread; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread;

[0095] According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; among them, the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the wafer surface.

[0096] Through the above analysis, it can be seen that the defects on the surface of the wafer can be divided into structural defects and foreign body defects from the physical form. The causes of the above two defects are also different. For example, structural defects can be scratches or dents caused by improper operation of hardware equipment or improper setting of process parameters, and foreign body defects can be caused by hardware equipment failure, resulting in dust or oil attached to the surface of the wafer. In addition, the forms of structural defects and foreign body defects on the surface of the wafer are quite different. Structural defects are direct physical damage to a part of the wafer surface, while foreign body defects are foreign objects attached to the surface of the wafer. In order to effectively eliminate structural defects and foreign body defects on the surface of the wafer in the subsequent manufacturing thread process, it is necessary to accurately and comprehensively distinguish the above two defects. Specifically, the defect image pixel recognition of the system defects of the wafer is performed to obtain the three-dimensional morphology and contour data of the system defects, thereby generating a defect distribution representation map of the wafer in the corresponding manufacturing thread, and a distribution position representation map of the structural defects and foreign body defects formed in the corresponding manufacturing thread is characterized globally on the wafer surface, and the distribution of structural defects and foreign body defects on the wafer surface is fully characterized from the aspects of position, shape and size.

[0097] Wafer needs to go through multiple manufacturing threads to fully manufacture the circuit layout on the surface of the wafer. It is impossible to accurately judge whether the wafer is valid based solely on the defect distribution on the surface of the wafer after it passes through a manufacturing thread. For this reason, it is necessary to integrate and identify the defect distribution characterization diagrams corresponding to each of the wafers after all manufacturing threads, so as to judge whether the circuit layout on the wafer is affected by defects and cannot work normally. Specifically, according to the peripheral shape contour of the wafer, the defect distribution characterization diagrams of the wafer in all manufacturing threads are aligned and overlapped to obtain the defect distribution characterization overall diagram of the wafer, the above-mentioned defect distribution characterization overall diagram fully reflects the defects (including structural defects and foreign body defects) formed on the surface of the wafer by all manufacturing threads, and then the neural network model of the support vector machine (SVM) is used to analyze the defect distribution characterization overall diagram to determine the clustering characteristics of the structural defects and foreign body defects on the surface of the wafer, thereby achieving unified characterization of the spatial distribution positions and spatial occupancy range of all structural defects and foreign body defects on the surface of the wafer, providing a basis for subsequent judgment of whether the wafer has failed.

[0098] In another embodiment, determining whether a wafer is in a failed state based on surface defect clustering characteristics; performing defect formation recurrence identification on all wafers in a failed state to determine improperly executed manufacturing threads includes:

[0099] Estimate the spatial proportion of the failed area on the wafer surface based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface. The spatial proportion of the failed area refers to the spatial overlap ratio between the failed area and the circuit wiring area on the wafer surface. Based on the spatial proportion of the failed area, determine whether the wafer is in a failed state.

[0100] The surface machine vision recognition data of all wafers in the failed state corresponding to the same manufacturing thread are used to perform defect formation reproduction identification to obtain the probability of defect recurrence in the same manufacturing thread of the wafer; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

[0101] When the area occupied by structural defects and foreign matter defects on the wafer surface overlaps significantly with the circuit layout area on the wafer surface, these defects will inevitably affect the normal operation of the circuit, leading to circuit failure of the entire wafer. In order to determine whether the wafer is in a failed state, the spatial proportion of the failed area on the wafer surface is first estimated based on the clustering characteristics of the structural defects and foreign matter defects on the wafer surface, and a threshold comparison is performed on the above-mentioned spatial proportion of the failed area. If the spatial proportion of the failed area exceeds the preset proportion threshold, the wafer is judged to be in a failed state; otherwise, the wafer is judged to be not in a failed state, which facilitates the rapid and accurate quality control screening of the wafer after all manufacturing threads are completed.

[0102] When a wafer is in a failed state, it must be caused by a hardware equipment operation failure and / or process parameter setting error in at least one manufacturing thread that the wafer has gone through. If a certain manufacturing thread is missing and there is a hardware equipment operation failure and / or process parameter setting error, each wafer that has passed through the above manufacturing thread will also have the same or similar defects (including structural defects and / or foreign matter defects) on its surface. It can be seen that by analyzing the repeated occurrence of surface defects on all wafers after passing through the same manufacturing thread, it is possible to inversely determine whether the corresponding manufacturing thread has a hardware equipment operation failure and / or improper process parameter setting. Specifically, defect formation reproduction identification is performed on the surface machine vision recognition data of all wafers in a failed state corresponding to the same manufacturing thread to obtain the probability of defect recurrence of wafers in the same manufacturing thread, that is, defect data labeling and defect data reproduction comparison are performed on the surface machine vision recognition data corresponding to all wafers after passing through the same manufacturing thread to determine whether the defect types, defect locations, defect shapes and sizes that appear on the surfaces of all wafers after passing through the same manufacturing thread are the same or extremely similar, thereby calculating the probability of defect recurrence of all wafers in the same manufacturing thread; if the above-mentioned defect recurrence probability exceeds the preset probability threshold, it is judged that the corresponding manufacturing thread belongs to an improperly executed manufacturing thread; otherwise, it is judged that the corresponding manufacturing thread does not belong to an improperly executed manufacturing thread, which is convenient for subsequent direct hardware equipment operation and process parameter debugging of the improperly executed manufacturing thread, thereby improving the wafer processing yield.

[0103] In another embodiment, estimating the spatial proportion of the failure area on the wafer surface based on the clustering characteristics of the structural defects and foreign matter defects on the wafer surface includes:

[0104] Extracting the number of periodic defect clusters of structural defects on the surface of the wafer;

[0105] Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster;

[0106] The structural defect period factor is obtained by the following formula:

[0107]

[0108] Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S a represents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3;

[0109] Extracting the number of foreign matter defects on the surface of the wafer;

[0110] Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect;

[0111] Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect;

[0112] The foreign matter defect distribution factor is obtained by the following formula:

[0113]

[0114] Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test (3.84 at 95% confidence level);

[0115] Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor;

[0116] The ratio of the failure area on the wafer surface is obtained by the following formula:

[0117]

[0118] Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

[0119] By comprehensively considering both structural defects and foreign matter defects on the wafer surface, this technical solution can more accurately assess the spatial distribution of wafer failure areas. This helps manufacturers promptly identify and address potential quality issues during the production process, thereby improving overall product quality and reliability. By extracting the number of periodic defect clusters and foreign matter defects from the wafer surface and calculating them using correlation factors, this technical solution can quickly and accurately identify wafer failure areas. This significantly improves inspection efficiency, shortens production cycle time, and reduces production costs. The structural defect period factor and foreign matter defect distribution factor in this technical solution are closely related to the wafer manufacturing process. By calculating and analyzing these two factors, manufacturers can gain a deeper understanding of potential process issues, allowing them to adjust and optimize process parameters in a targeted manner to improve product quality and consistency. The formulas and parameters in this technical solution can be customized based on different wafer types, manufacturing processes, and circuit wiring density distribution functions. This makes this technical solution more flexible and adaptable, meeting the needs of different manufacturers and products. By accurately assessing the percentage of wafer failure areas, manufacturers can pay more attention to these potential problem areas during product design and production, and take appropriate measures to improve product reliability and stability. This helps extend product life and reduce repair and replacement costs.

[0120] See also Figure 4 As shown, an embodiment of the present application provides a semiconductor surface defect detection system based on machine vision. The semiconductor surface defect detection system based on machine vision includes:

[0121] The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers;

[0122] System defect extraction module, used to extract the system defects of wafers based on the common characteristics of defect distribution;

[0123] A defect representation diagram generation module is used to generate a defect distribution representation diagram of the wafer in the corresponding manufacturing thread according to the defect morphology of the wafer's system defects;

[0124] A defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization diagram of the wafer in all manufacturing threads;

[0125] A failure state judgment module is used to judge whether the wafer is in a failure state based on the surface defect clustering characteristics;

[0126] The manufacturing thread calibration module is used to identify the recurrence of defects on all wafers in a failed state and determine the improperly executed manufacturing thread.

[0127] In another embodiment, the defect commonality identification module is used to compare and analyze surface machine vision recognition data of multiple wafers to determine the commonality of defect distribution across all wafers, including:

[0128] After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the wafer surface;

[0129] Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing process to determine the commonality of defect distribution across all wafers. This commonality includes the correlation of the positional distribution of surface defects across all wafers.

[0130] The system defect extraction module is used to extract the system defects of the wafer based on the common characteristics of the defect distribution, including:

[0131] Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

[0132] In another embodiment, the defect representation map generating module is configured to generate a defect distribution representation map of the wafer in a corresponding manufacturing thread based on the defect morphology of the systematic defects of the wafer, including:

[0133] Perform defect image pixel recognition on the wafer's systematic defects to obtain three-dimensional morphology and contour data of the systematic defects; based on the three-dimensional morphology and contour data, generate a defect distribution representation map of the wafer in the corresponding manufacturing thread; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread;

[0134] The defect cluster feature determination module is used to determine the surface defect cluster features of the wafer based on the defect distribution characterization diagram of the wafer in all manufacturing threads, including:

[0135] According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; among them, the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the wafer surface.

[0136] In another embodiment, the failure state judgment module is used to judge whether the wafer is in a failure state based on the surface defect clustering characteristics, including:

[0137] Estimate the spatial proportion of the failed area on the wafer surface based on the clustering characteristics of structural defects and foreign matter defects on the wafer surface. The spatial proportion of the failed area refers to the spatial overlap ratio between the failed area and the circuit wiring area on the wafer surface. Based on the spatial proportion of the failed area, determine whether the wafer is in a failed state.

[0138] The manufacturing thread calibration module is used to identify defect formation recurrences on all wafers in a failed state and determine the improperly executed manufacturing thread, including:

[0139] The surface machine vision recognition data of all wafers in the failed state corresponding to the same manufacturing thread are used to perform defect formation reproduction identification to obtain the probability of defect recurrence in the same manufacturing thread of the wafer; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

[0140] The operation and effects of the semiconductor surface defect detection system based on machine vision of the present invention are corresponding to and consistent with the above-mentioned semiconductor surface defect detection method based on machine vision, and the semiconductor surface defect detection system based on machine vision will not be repeated here.

[0141] In another embodiment, estimating the spatial proportion of the failure area on the wafer surface based on the clustering characteristics of the structural defects and foreign matter defects on the wafer surface includes:

[0142] Extracting the number of periodic defect clusters of structural defects on the surface of the wafer;

[0143] Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster;

[0144] The structural defect period factor is obtained by the following formula:

[0145]

[0146] Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S a represents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3;

[0147] Extracting the number of foreign matter defects on the surface of the wafer;

[0148] Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect;

[0149] Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect;

[0150] The foreign matter defect distribution factor is obtained by the following formula:

[0151]

[0152] Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test (3.84 at 95% confidence level);

[0153] Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor;

[0154] The ratio of the failure area on the wafer surface is obtained by the following formula:

[0155]

[0156] Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

[0157] By comprehensively considering both structural defects and foreign matter defects on the wafer surface, this technical solution can more accurately assess the spatial distribution of wafer failure areas. This helps manufacturers promptly identify and address potential quality issues during the production process, thereby improving overall product quality and reliability. By extracting the number of periodic defect clusters and foreign matter defects from the wafer surface and calculating them using correlation factors, this technical solution can quickly and accurately identify wafer failure areas. This significantly improves inspection efficiency, shortens production cycle time, and reduces production costs. The structural defect period factor and foreign matter defect distribution factor in this technical solution are closely related to the wafer manufacturing process. By calculating and analyzing these two factors, manufacturers can gain a deeper understanding of potential process issues, allowing them to adjust and optimize process parameters in a targeted manner to improve product quality and consistency. The formulas and parameters in this technical solution can be customized based on different wafer types, manufacturing processes, and circuit wiring density distribution functions. This makes this technical solution more flexible and adaptable, meeting the needs of different manufacturers and products. By accurately assessing the percentage of wafer failure areas, manufacturers can pay more attention to these potential problem areas during product design and production, and take appropriate measures to improve product reliability and stability. This helps extend product life and reduce repair and replacement costs.

[0158] In general, the machine vision-based semiconductor surface defect detection method and system compares and analyzes the surface machine vision recognition data of several wafers, determines the commonality of defect distribution of all wafers, extracts the systematic defects of wafers, and accurately and comprehensively calibrates defects caused by equipment or process reasons in the wafer; generates defect distribution characterization diagrams of wafers in all manufacturing threads to determine the surface defect clustering characteristics of wafers, and comprehensively calibrates the defect types and distributions generated by wafers in each manufacturing thread, so as to identify whether the defects in the wafers have a great impact on quality, accurately judge whether the wafers are in a failed state, and effectively evaluate the overall performance of the wafers; it also performs defect formation reproduction identification on all wafers in a failed state in the same manufacturing thread, determines the improperly executed manufacturing threads, and accurately traces the manufacturing threads that produce defects, which helps to debug and correct the corresponding manufacturing threads and improve the wafer processing yield.

[0159] The above is only a specific embodiment of the present invention, and any other improvements made based on the concept of the present invention are considered to be within the scope of protection of the present invention.

Claims

1. A method for detecting semiconductor surface defects based on machine vision, characterized in that: include: Compare and analyze surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers; Extracting systematic defects of the wafer based on the commonality of the defect distribution; Generating a defect distribution representation diagram of the wafer in a corresponding manufacturing thread based on the defect morphology of the wafer's system defects; determining a surface defect clustering feature of the wafer based on the defect distribution representation diagram of the wafer in all manufacturing threads; determining whether the wafer is in a failed state according to the surface defect clustering characteristics; Reproduce defect formation on all wafers in a failed state to pinpoint the improperly executed manufacturing thread.

2. The method for detecting semiconductor surface defects based on machine vision according to claim 1, wherein: Compare and analyze surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers; Based on the common characteristics of the defect distribution, the systematic defects of the wafer are extracted, including: After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the surface of the wafer; Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing thread to determine the commonality of defect distribution across all wafers; wherein the commonality of defect distribution includes the positional distribution correlation of surface defects across all wafers; Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

3. The method for detecting semiconductor surface defects based on machine vision according to claim 1, wherein: Generating a defect distribution representation diagram of the wafer in a corresponding manufacturing thread according to the defect morphology of the wafer's system defects; and determining a surface defect clustering feature of the wafer according to the defect distribution representation diagram of the wafer in all manufacturing threads, including: Perform defect image pixel recognition on systematic defects of the wafer to obtain three-dimensional morphology and contour data of the systematic defects; generate a defect distribution representation map of the wafer in the corresponding manufacturing thread based on the three-dimensional morphology and contour data; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread; According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the surface of the wafer.

4. The method for detecting semiconductor surface defects based on machine vision according to claim 1, wherein: determining whether the wafer is in a failed state according to the surface defect clustering characteristics; Reproducible identification of defect formation on all wafers in failed states to pinpoint improperly executed manufacturing threads, including: estimating a spatial proportion of a failure region on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface; wherein the spatial proportion of the failure region refers to a spatial overlap ratio between the failure region and the circuit wiring region on the wafer surface; and determining whether the wafer is in a failure state based on the spatial proportion of the failure region; Defect formation reproduction identification is performed on the surface machine vision recognition data of all wafers in a failed state corresponding to the same manufacturing thread to obtain the defect recurrence probability of the wafer in the same manufacturing thread; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

5. The method for detecting semiconductor surface defects based on machine vision according to claim 4, wherein: Estimating the spatial proportion of the failure area on the wafer surface based on the clustering characteristics of the structural defects and foreign matter defects on the wafer surface includes: Extracting the number of periodic defect clusters of structural defects on the surface of the wafer; Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster; The structural defect period factor is obtained by the following formula: Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S a represents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3; Extracting the number of foreign matter defects on the surface of the wafer; Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect; Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect; The foreign matter defect distribution factor is obtained by the following formula: Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test; Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor; The ratio of the failure area on the wafer surface is obtained by the following formula: Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

6. A semiconductor surface defect detection system based on machine vision, characterized in that: include: The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution across all wafers; A system defect extraction module, configured to extract system defects of the wafer based on the commonality of the defect distribution; A defect representation diagram generating module, configured to generate a defect distribution representation diagram of the wafer in a corresponding manufacturing thread according to the defect morphology of the system defects of the wafer; A defect clustering feature determination module is used to determine the surface defect clustering features of the wafer based on the defect distribution characterization diagram of the wafer in all manufacturing threads; A failure state judgment module, configured to judge whether the wafer is in a failure state based on the surface defect clustering characteristics; The manufacturing thread calibration module is used to identify the recurrence of defects on all wafers in a failed state and determine the improperly executed manufacturing thread.

7. The semiconductor surface defect detection system based on machine vision according to claim 6, characterized in that: The defect commonality identification module is used to compare and analyze the surface machine vision recognition data of several wafers to determine the commonality of defect distribution of all wafers, including: After each manufacturing thread is completed for each of the plurality of wafers, a processed surface image is collected, and machine vision recognition is performed on the processed surface image to obtain surface machine vision recognition data of the wafer corresponding to each manufacturing thread; wherein the surface machine vision recognition data includes defect distribution position data on the surface of the wafer; Performing a spatial distribution comparison analysis on the surface machine vision recognition data of all wafers after they have completed the same manufacturing thread to determine the commonality of defect distribution across all wafers; wherein the commonality of defect distribution includes the positional distribution correlation of surface defects across all wafers; The system defect extraction module is used to extract the system defects of the wafer according to the commonality of the defect distribution, including: Based on the common defect distribution characteristics of all wafers, the random defects on the surfaces of all wafers are identified; the random defects on the wafer surfaces are compared with the overall surface defects of the wafers after completing the corresponding manufacturing threads, and the systematic defects of the wafers in the corresponding manufacturing threads are extracted.

8. The semiconductor surface defect detection system based on machine vision according to claim 6, characterized in that: The defect representation map generating module is used to generate a defect distribution representation map of the wafer in the corresponding manufacturing thread according to the defect morphology of the system defects of the wafer, including: Perform defect image pixel recognition on systematic defects of the wafer to obtain three-dimensional morphology and contour data of the systematic defects; generate a defect distribution representation map of the wafer in the corresponding manufacturing thread based on the three-dimensional morphology and contour data; wherein the defect distribution representation map includes a distribution position representation map of structural defects and foreign matter defects formed on the wafer in the corresponding manufacturing thread; The defect cluster feature determination module is used to determine the surface defect cluster features of the wafer according to the defect distribution characterization diagram of the wafer in all manufacturing threads, including: According to the outer contour of the wafer, the defect distribution characterization maps of the wafer in all manufacturing threads are aligned and overlapped, and the overall defect distribution characterization map after alignment and overlap is analyzed to determine the surface defect clustering characteristics of the wafer; wherein the surface defect clustering characteristics include the clustering characteristics of the structural defects and foreign matter defects on the surface of the wafer.

9. The semiconductor surface defect detection system based on machine vision according to claim 6, characterized in that: The failure state judgment module is used to judge whether the wafer is in a failure state according to the surface defect clustering characteristics, including: estimating a spatial proportion of a failure region on the wafer surface based on clustering characteristics of structural defects and foreign matter defects on the wafer surface; wherein the spatial proportion of the failure region refers to a spatial overlap ratio between the failure region and the circuit wiring region on the wafer surface; and determining whether the wafer is in a failure state based on the spatial proportion of the failure region; The manufacturing thread calibration module is used to perform defect formation recurrence identification on all wafers in a failed state and determine the improperly executed manufacturing thread, including: Defect formation reproduction identification is performed on the surface machine vision recognition data of all wafers in a failed state corresponding to the same manufacturing thread to obtain the defect recurrence probability of the wafer in the same manufacturing thread; based on the defect recurrence probability, it is determined whether the manufacturing thread is an improperly executed manufacturing thread.

10. The semiconductor surface defect detection system based on machine vision according to claim 9, characterized in that: Estimating the spatial proportion of the failure area on the wafer surface based on the clustering characteristics of the structural defects and foreign matter defects on the wafer surface includes: Extracting the number of periodic defect clusters of structural defects on the surface of the wafer; Obtaining a structural defect periodic factor according to the area of ​​the structural defect cluster corresponding to each periodic defect cluster; The structural defect period factor is obtained by the following formula: Where E represents the structural defect period factor; N c represents the number of periodic defect clusters of structural defects on the wafer surface; S i represents the area of ​​the structural defect cluster corresponding to the i-th periodic defect cluster; S p represents the average cluster area of ​​structural defects; S a represents the surface area of ​​the wafer surface; α represents the process sensitivity coefficient, which ranges from 0.7 to 1.3; Extracting the number of foreign matter defects on the surface of the wafer; Obtain the vertical distance between each foreign body defect and the adjacent structural defect according to the position of each foreign body defect; Obtaining a foreign matter defect distribution factor based on a vertical distance between each foreign matter defect and an adjacent structural defect; The foreign matter defect distribution factor is obtained by the following formula: Where K represents the foreign matter defect distribution factor; N p Indicates the number of foreign body defects; D i represents the vertical distance between the ith foreign body defect and the adjacent structural defect; D p It represents the average vertical distance between the foreign body defect and the adjacent structural defect; R represents the critical value of the chi-square test; Obtaining a spatial proportion of a failure area on the surface of the wafer using the structural defect period factor and the foreign matter defect distribution factor; The ratio of the failure area on the wafer surface is obtained by the following formula: Wherein, G represents the spatial proportion of the failure area on the wafer surface; λ represents the preset defect type weight factor; and D(x, y) represents the circuit wiring density distribution function of the circuit wiring area.

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