Display substrate, display and display equipment

Abstract

The embodiment of the invention provides a display substrate, a display and display equipment. The display substrate comprises a gating module, a plurality of switch elements and a plurality of sub-pixels, the gating module is respectively connected with each switch element, and the switch elements are connected with the sub-pixels; the gating module is configured as follows: for a first image frame and a second image frame which are adjacent in time sequence, when the first image frame is displayed, the switching element is controlled to enable sub-pixels in odd-numbered lines to be displayed; and when the second image frame is displayed, the switching elements are controlled to display the sub-pixels in the even-numbered lines. Only odd-numbered lines of sub-pixels are displayed in the first image frame and only even-numbered lines of sub-pixels are displayed in the second image frame under the control of the gating module, so that the situation of color crossing of display pictures is reduced.

Description

Technical Field

[0001] The present application relates to the field of digital circuit technology, and in particular to a display substrate, a display, and a display device. Background Art

[0002] Hardware Super Resolution (HSR) technology is a technology that achieves high resolution and high refresh rate. HSR technology is mainly used in devices such as televisions and monitors. At a high refresh rate, the refresh time for each frame is short. When the resolution of the display device is very high, the refresh time for each row of sub-pixels in a frame is even shorter. When the display images of adjacent rows of sub-pixels differ significantly, their data voltages are easily affected by each other, resulting in inaccurate display images of adjacent rows and causing color cross-talk.

[0003] Existing technologies filter or process images at the software level to ensure output image accuracy and reduce color crosstalk. This software-based image processing requires high computing power from the display device motherboard, is costly, and is susceptible to interference from noisy data, making it difficult to achieve the desired reduction in color crosstalk. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a display substrate, a display, and a display device to reduce the occurrence of color crosstalk in the display screen. The specific technical solutions are as follows:

[0005] An embodiment of the present application provides a display substrate, comprising:

[0006] A gating module, a plurality of switching elements, and a plurality of sub-pixels;

[0007] The gating modules are respectively connected to the switch elements, and the switch elements are connected to the sub-pixels;

[0008] The selection module is configured as follows: for a first image frame and a second image frame that are adjacent in time sequence, when displaying the first image frame, the sub-pixels of each odd row are displayed by controlling the switching element; when displaying the second image frame, the sub-pixels of each even row are displayed by controlling the switching element.

[0009] In a possible implementation, the gating module includes a first counter, a second counter, and a logic gate;

[0010] The first counter is connected to the first input terminal of the logic gate, the second counter is connected to the second input terminal of the logic gate, and the output terminal of the logic gate is connected to each of the switch elements respectively;

[0011] The first counter is configured to: output a first value when the currently displayed image frame is an odd frame, and output a second value when the currently displayed image frame is an even frame;

[0012] The second counter is configured to: output a first value during a refresh period of the odd-numbered rows of sub-pixels, and output a second value during a refresh period of the even-numbered rows of sub-pixels; or output a second value during a refresh period of the odd-numbered rows of sub-pixels, and output a first value during a refresh period of the even-numbered rows of sub-pixels;

[0013] The logic gate is configured to: control each of the switch elements to be turned on when the values ​​input to the first input terminal or the second input terminal are the same, and control each of the switch elements to be turned off when the values ​​input to the first input terminal or the second input terminal are different; or control each of the switch elements to be turned on when the values ​​input to the first input terminal or the second input terminal are different, and control each of the switch elements to be turned off when the values ​​input to the first input terminal or the second input terminal are the same;

[0014] The switching element is configured to transmit a driving signal to the sub-pixel connected thereto when the switching element is turned on.

[0015] In one possible implementation, an input end of the first counter is connected to a first signal, an input end of the second counter is connected to a second signal, and an output end of the logic gate is respectively connected to a control end of each of the switch elements; the total number of the switch elements is the same as the total number of sub-pixel rows, the input end of the i-th switch element is connected to the third signal of the i-th row of sub-pixels, and the output end of the i-th switch element is connected to the third signal input end of the i-th row of sub-pixels, wherein i is a positive integer, the first signal is a signal that is refreshed once every time a frame of an image is refreshed, the second signal is a signal that is refreshed once every time a row of sub-pixels is refreshed, and the third signal is a row drive signal for refreshing a row of sub-pixels;

[0016] The first counter is configured to: output a first value after receiving the first signal for an odd number of times; and output a second value after receiving the first signal for an even number of times;

[0017] The second counter is configured to: output a first value after receiving the second signal for an odd number of times, and output a second value after receiving the second signal for an even number of times; or output a second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

[0018] In a possible implementation, the first signal is a vertical synchronization signal STV signal, the second signal is a Gate signal, and the third signal is a Gate signal.

[0019] In a possible implementation manner, both the first counter and the second counter are D flip-flops, and the switch element is a thin film transistor (TFT).

[0020] In one possible implementation, an input end of the first counter is connected to a first signal, an input end of the second counter is connected to a second signal, and an output end of the logic gate is respectively connected to a control end of each of the switch elements; the total number of the switch elements is the same as the total number of sub-pixel columns, the input end of the j-th switch element is connected to the fourth signal of the sub-pixel in the j-th column, and the output end of the j-th switch element is connected to the fourth signal input end of the sub-pixel in the j-th row, where j is a positive integer; the first signal is a signal that is refreshed once every time a frame of an image is refreshed; the second signal is a signal that is refreshed once every time a row of sub-pixels is refreshed; and the fourth signal is a column drive signal for refreshing a column of sub-pixels;

[0021] The first counter is configured to: output a first value when receiving the first signal for an odd number of times; and output a second value when receiving the first signal for an even number of times;

[0022] The second counter is configured to: output a first value after receiving the second signal for an odd number of times, and output a second value after receiving the second signal for an even number of times; or output a second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

[0023] In a possible implementation manner, the first signal is a vertical synchronization signal STV signal, the second signal is a touch signal TP signal, and the fourth signal is a source signal Source signal.

[0024] In a possible implementation manner, both the first counter and the second counter are D flip-flops, and the switch element is a tri-state buffer.

[0025] An embodiment of the present application provides a display, comprising any display substrate described in the embodiments of the present application.

[0026] An embodiment of the present application provides a display device, including the display described in the embodiment of the present application.

[0027] Beneficial effects of the embodiments of the present application:

[0028] The display substrate provided in an embodiment of the present application includes: a gating module, multiple switching elements, and multiple sub-pixels; the gating module is respectively connected to each of the switching elements, and the switching elements are connected to the sub-pixels; the gating module is configured to: for a first image frame and a second image frame that are adjacent in time sequence, when displaying the first image frame, control the switching elements to display the sub-pixels in each odd-numbered row; when displaying the second image frame, control the switching elements to display the sub-pixels in each even-numbered row. The gating module controls the display of only the odd-numbered rows of sub-pixels in the first image frame and only the even-numbered rows of sub-pixels in the second image frame, thereby reducing the occurrence of color crosstalk in the display screen.

[0029] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0031] FIG1( a ) is a schematic diagram of a first display substrate in an embodiment of the present application;

[0032] FIG1( b ) is a second schematic diagram of a display substrate in an embodiment of the present application;

[0033] FIG2( a ) is a first schematic diagram of a display substrate displaying a first image frame according to an embodiment of the present application;

[0034] FIG2( b ) is a second schematic diagram of a display substrate displaying a first image frame according to an embodiment of the present application;

[0035] FIG3( a ) is a first schematic diagram of a display substrate displaying a second image frame according to an embodiment of the present application;

[0036] FIG3( b ) is a second schematic diagram of a display substrate displaying a second image frame according to an embodiment of the present application;

[0037] Figure 4 A schematic diagram of a display screen displayed by a display substrate according to an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a gating module in a display substrate according to an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a display substrate connection signal according to an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a counter in a display substrate according to an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a switch element in a display substrate according to an embodiment of the present application;

[0042] FIG9( a ) is a first timing diagram showing a first image frame in an embodiment of the present application;

[0043] FIG9( b ) is a first timing diagram showing a second image frame in an embodiment of the present application;

[0044] Figure 10 This is a third schematic diagram showing a substrate in an embodiment of the present application;

[0045] FIG11( a ) is a second timing diagram showing a first image frame according to an embodiment of the present application;

[0046] FIG11( b ) is a second timing diagram showing a second image frame in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0048] Hardware Super Resolution (HSR) technology is a technology that achieves high resolution and high refresh rate. HSR is primarily used in devices such as televisions and monitors. Display devices using HSR offer high resolution and extremely fast refresh times for each row of sub-pixels. When adjacent rows display significantly different images, the data voltages of these rows can experience significant jumps, even causing crosstalk. This makes it difficult to accurately charge the sub-pixels in such a short time, resulting in inaccurate images between adjacent rows, often referred to as cross-color.

[0049] Related technologies use software to filter or process images to ensure output image accuracy and reduce color crosstalk. Using software to process images requires high computing power from the display device motherboard, is costly, and is susceptible to interference from noisy data, making it difficult to achieve the desired reduction in color crosstalk.

[0050] The present invention provides a display substrate, a display, and a display device. By changing the hardware circuit, the problem of color crosstalk in the display screen is reduced. The following is a detailed description:

[0051] The present application provides a display substrate, as shown in FIG1( a ) and FIG1( b ), including:

[0052] A gating module 10, a plurality of switching elements 20, and a plurality of sub-pixels 30;

[0053] The gating module 10 is connected to each switching element 20 respectively, and the switching element 20 is connected to the sub-pixel 30;

[0054] The selection module 10 is configured as follows: for the first image frame and the second image frame that are adjacent in time sequence, when displaying the first image frame, the sub-pixels 30 of each odd row are displayed by controlling the switching element 20; when displaying the second image frame, the sub-pixels 30 of each even row are displayed by controlling the switching element.

[0055] The switching element 20 is used to control whether the sub-pixel 30 emits light. Typically, a pixel includes three sub-pixels 30: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In some scenarios, there are other possible sub-pixel combinations in a pixel, but this application does not limit the combination of sub-pixels 30 in a pixel. The selection module 10 is connected to each switching element 20 respectively to control the disconnection and conduction of the switching element 20; the switching element 20 is connected to the sub-pixel 30, and the number of the switching elements 20 is the same as the number of rows of sub-pixels 30 or the number of columns of sub-pixels 30.

[0056] In one possible embodiment, referring to FIG1(a), the number of switching elements 20 is the same as the number of sub-pixel rows, each switching element 20 is connected to each sub-pixel row, and each switching element 20 controls the sub-pixels 30 of a row; when displaying the first image frame, referring to FIG2(a), when scanning to the odd rows line by line, the gating module 10 controls the switching elements 20 to open, and when scanning to the even rows line by line, the switching elements 20 are controlled to close, so that the sub-pixels 30 of each odd row are displayed, and the sub-pixels 30 of each even row are not displayed, and the display effect is shown in FIG2(b); when displaying the second image frame, referring to FIG3(a), when scanning to the even rows line by line, the gating module 10 controls the switching elements 20 to open, and when scanning to the odd rows line by line, the switching elements 20 are controlled to close, so that the sub-pixels 30 of each even row are displayed, and the sub-pixels 30 of each odd row are not displayed, and the display effect is shown in FIG3(b).

[0057] In another possible embodiment, referring to FIG1( b ), the number of switch elements 20 is the same as the number of sub-pixel columns, and each switch element 20 is connected to each sub-pixel column; when displaying the first image frame, when scanning the odd rows row by row, the gating module 10 controls the switch element 20 to open, and when scanning the even rows row by row, the switch element 20 is controlled to close, so that the sub-pixels 30 of each odd row are displayed and the sub-pixels 30 of each even row are not displayed, and the display effect is shown in FIG2( b ); when displaying the second image frame, when scanning the even rows row by row, the gating module 10 controls the switch element 20 to open, and when scanning the odd rows row by row, the switch element 20 is controlled to close, so that the sub-pixels 30 of each even row are displayed and the sub-pixels 30 of each odd row are not displayed, and the display effect is shown in FIG3( b ). It should be noted that in the embodiment of the present application, the number of sub-pixels 30 rows and columns is the same, but in practice, the number of sub-pixels 30 rows and columns can be the same or different, and can be selected according to different application requirements.

[0058] The first image frame and the second image frame are temporally adjacent image frames. When the first image frame is an odd image frame, the second image frame is an even image frame, that is, the sub-pixels 30 in odd rows are displayed in odd image frames, and the sub-pixels 30 in even rows are displayed in even image frames. When the first image frame is an even image frame, the second image frame is an odd image frame, that is, the sub-pixels 30 in even rows are displayed in odd image frames, and the sub-pixels 30 in even rows are displayed in odd image frames. In display devices that apply HSR technology, the screen refresh rate is relatively high, usually reaching 120 frames per second or even higher. Due to the visual persistence effect of the human eye, when the first image frame and the second image frame are temporally adjacent image frames, the display effect seen by the human eye is as follows: Figure 4 As shown, the complete display screen can be seen.

[0059] The embodiment of the present application modifies the hardware circuit to display odd-numbered rows of sub-pixels 30 in the first image frame and even-numbered rows of sub-pixels 30 in the second image frame, thereby reducing the occurrence of color bleed when the images of adjacent rows of sub-pixels 30 differ significantly, and displaying a more accurate image. The circuit structure is simple and easy to implement. Furthermore, compared to software-based approaches, hardware modifications achieve a more stable effect. Furthermore, based on the hardware improvements of the present application, software processing can also be combined with the embodiments of the present application to further reduce the effect of color bleed.

[0060] In one possible implementation, see Figure 5 , the gating module 10 includes a first counter 101, a second counter 102 and a logic gate 103;

[0061] The first counter 101 is connected to the first input terminal of the logic gate 103, the second counter 102 is connected to the second input terminal of the logic gate 103, and the output terminal of the logic gate 103 is connected to each switch element 20 respectively;

[0062] The first counter 101 is configured to: output a first value when the currently displayed image frame is an odd frame, and output a second value when the currently displayed image frame is an even frame;

[0063] The second counter 102 is configured to: output the first value during the refresh period of the odd-numbered rows of sub-pixels 30, and output the second value during the refresh period of the even-numbered rows of sub-pixels 30; or output the second value during the refresh period of the odd-numbered rows of sub-pixels 30, and output the first value during the refresh period of the even-numbered rows of sub-pixels 30;

[0064] The logic gate 103 is configured to: control each switch element 20 to be turned on when the values ​​input to its first input terminal or second input terminal are the same, and control each switch element 20 to be turned off when the values ​​input to its first input terminal or second input terminal are different; or control each switch element 20 to be turned on when the values ​​input to its first input terminal or second input terminal are different, and control each switch element 20 to be turned off when the values ​​input to its first input terminal or second input terminal are the same;

[0065] The switching element 20 is configured to transmit a driving signal to the sub-pixel 30 connected thereto when the switching element 20 is turned on.

[0066] The first counter 101 and the second counter 102 can be flip-flops; the logic gate 103 can be an XOR gate or an XOR gate, and the first value and the second value are logically opposite values. For example, the first value can be a logical value of 1 and the second value can be a logical value of 0; or the first value can be a logical value of 0 and the second value can be a logical value of 1. In one example, the first value is a logical value of 1 and the second value is a logical value of 0, and the logic gate 103 is an XOR gate. The truth table of the logic gate 103 is shown in Table 1:

[0067] Table 1

[0068]

[0069]

[0070] In an odd frame, the first counter 101 outputs a first value, the second counter 102 outputs a first value in the refresh period of the odd-numbered row sub-pixels 30, and outputs a second value in the refresh period of the even-numbered row sub-pixels 30. That is, when scanning row by row to the odd-numbered rows, the first counter 101 and the second counter 102 output the same value, the logic gate 103 controls each switching element 20 to turn on, and the odd-numbered row sub-pixels 30 are displayed. When scanning row by row to the even-numbered rows, the first counter 101 and the second counter 102 output different values, the logic gate 103 controls each switching element 20 to turn off, and the even-numbered row sub-pixels 30 are not displayed.

[0071] In the even frame, the first counter 101 outputs the second value, the second counter 102 outputs the first value in the refresh period of the odd-numbered row sub-pixels 30, and outputs the second value in the refresh period of the even-numbered row sub-pixels 30. That is, when scanning row by row to the even-numbered rows, the first counter 101 and the second counter 102 output the same value, the logic gate 103 controls each switching element 20 to turn on, and the even-numbered row sub-pixels 30 are displayed. When scanning row by row to the odd-numbered rows, the first counter 101 and the second counter 102 output different values, the logic gate 103 controls each switching element 20 to turn off, and the odd-numbered row sub-pixels 30 are not displayed.

[0072] In another example, the first value is a logic value of 1, the second value is a logic value of 0, and the logic gate 103 is an XOR gate. The truth table of the logic gate 103 is shown in Table 2:

[0073] Table 2

[0074] The first counter 101 outputs a value The second counter 102 outputs a value Logic gate 103 output value 1 0 1 0 1 1 1 1 0 0 0 0

[0075] In odd frames, the first counter 101 outputs a first value, the second counter 102 outputs a second value in the refresh period of the odd-numbered row sub-pixels 30, and outputs a first value in the refresh period of the even-numbered row sub-pixels 30. That is, when scanning row by row to the odd-numbered rows, the first counter 101 and the second counter 102 output different values, the logic gate 103 controls each switching element 20 to turn on, and the odd-numbered row sub-pixels 30 are displayed. When scanning row by row to the even-numbered rows, the first counter 101 and the second counter 102 output the same value, the logic gate 103 controls each switching element 20 to turn off, and the even-numbered row sub-pixels 30 are not displayed.

[0076] In an even frame, the first counter 101 outputs a second value, the second counter 102 outputs a second value in the refresh period of the odd-numbered row sub-pixels 30, and outputs a first value in the refresh period of the even-numbered row sub-pixels 30. That is, when scanning row by row to the even-numbered rows, the first counter 101 and the second counter 102 output different values, the logic gate 103 controls each switching element 20 to turn on, and the even-numbered row sub-pixels 30 are displayed. When scanning row by row to the odd-numbered rows, the first counter 101 and the second counter 102 output the same value, the logic gate 103 controls each switching element 20 to turn off, and the odd-numbered row sub-pixels 30 are not displayed.

[0077] The above is an embodiment of displaying odd-row sub-pixels 30 in odd frames and even-row sub-pixels 30 in even frames. The embodiment of displaying even-row sub-pixels 30 in odd frames and odd-row sub-pixels 30 in even frames is similar to the above embodiment and can be achieved by changing the value output by the second counter 102 or changing the value output by the first counter 101, which will not be repeated here.

[0078] The first counter 101, the second counter 102 and the logic gate 103 are used to make the display substrate display odd and even rows in adjacent image frames respectively, which can reduce the occurrence of cross-color when the images of adjacent rows are very different. The circuit structure is simple, the cost is low and it is easy to implement.

[0079] In one possible implementation, see Figure 6 , an input end of the first counter 101 is connected to the first signal, an input end of the second counter 102 is connected to the second signal, and an output end of the logic gate 103 is respectively connected to the control end of each switching element 20; the total number of switching elements 20 is the same as the total number of sub-pixel rows, the input end of the i-th switching element is connected to the third signal of the i-th row of sub-pixels 30, and the output end of the i-th switching element is connected to the third signal input end of the i-th row of sub-pixels 30, wherein i is a positive integer, the first signal is a signal that is refreshed once every time a frame of the image is refreshed, the second signal is a signal that is refreshed once every time a row of sub-pixels 30 is refreshed, and the third signal is a row drive signal for refreshing a row of sub-pixels 30;

[0080] The first counter 101 is configured to: output a first value after receiving the first signal for an odd number of times; and output a second value after receiving the first signal for an even number of times;

[0081] The second counter 102 is configured to: output the first value after receiving the second signal for an odd number of times, and output the second value after receiving the second signal for an even number of times; or output the second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

[0082] The first signal is a signal that is refreshed every time a frame of the image is refreshed. The first counter 101 receives the first signal for an odd number of times and outputs a first value, that is, the first counter 101 outputs the first value in an odd frame; the first counter 101 receives the first signal for an even number of times and outputs a second value, that is, the first counter 101 outputs the second value in an even frame.

[0083] The second signal is a signal that is refreshed once every time a row of sub-pixels 30 is refreshed. The second counter 102 outputs the first value after receiving the second signal for an odd number of times, and outputs the second value after receiving the second signal for an even number of times. That is, the second counter 102 outputs the first value when scanning to the odd rows line by line, and then the second signal is refreshed, and the second value is output when scanning to the even rows line by line; the second counter 102 outputs the second value after receiving the second signal for an odd number of times, and outputs the first value after receiving the second signal for an even number of times. That is, the second counter 102 outputs the second value when scanning to the odd rows line by line, and then the second signal is refreshed, and the first value is output when scanning to the even rows line by line.

[0084] The output end of the logic gate 103 is respectively connected to the control end of each switching element 20. When the display image frame is an odd frame, the control switching element 20 is turned on when the odd rows are scanned line by line, and is turned off when the even rows are scanned line by line; when the display image frame is an even frame, the control switching element 20 is turned off when the odd rows are scanned line by line, and is turned on when the even rows are scanned line by line; or, when the display image frame is an even frame, the control switching element 20 is turned on when the odd rows are scanned line by line, and is turned off when the even rows are scanned line by line; when the display image frame is an odd frame, the control switching element 20 is turned off when the odd rows are scanned line by line, and is turned on when the even rows are scanned line by line.

[0085] The input end of the i-th switching element is connected to the third signal of the i-th row sub-pixel 30, and the output end of the i-th switching element is connected to the third signal input end of the i-th row sub-pixel 30, that is, the i-th switching element is connected between the third signal output end and the i-th row sub-pixel 30; the third signal is the row drive signal of the sub-pixel 30, and a switching element is set at the row drive signal input end of each row of sub-pixels 30 to control whether the third signal is input into the i-th row sub-pixel 30 to drive the sub-pixel 30 to display.

[0086] A switch element 20 is added to the row drive signal input terminal of each row of sub-pixels 30. By controlling the switch element 20, the entire row of sub-pixels 30 can be controlled to display or not display. The circuit structure is simple and the manufacturing cost is low.

[0087] In one possible implementation, see Figure 6 , the first signal is a vertical synchronization signal, the second signal is a Gate signal, and the third signal is a Gate signal.

[0088] The refresh rate of the vertical synchronization signal (Sync Top Video, STV) is the same as the refresh rate of the image frame, refreshing once per frame. For example, when the refresh rate of the display substrate is 60Hz, the STV signal refreshes 60 times per second.

[0089] The Gate signal is a row driving signal for the sub-pixels 30 . The Gate signal is scanned row by row. By controlling the switch element 20 , the Gate signal of a row is controlled to be output to the sub-pixels 30 in the row, thereby controlling the display or non-display of the sub-pixel row.

[0090] A switch element 20 is added to the gate signal input terminal of each row of sub-pixels 30. By controlling the switch element 20, the entire row of sub-pixels 30 can be controlled to display or not display. The circuit structure is simple and the manufacturing cost is low.

[0091] In a possible implementation, the first counter 101 and the second counter 102 are both D-type flip-flops, and the switch element 20 is a thin film transistor (TFT).

[0092] The D flip-flop is level triggered or edge triggered. The first counter 101 and the second counter 102 can both use a D flip-flop. Figure 7 As shown, Q is the positive output terminal of the trigger, and Q' is the negative output terminal of the trigger. The input terminal of the D trigger is connected to its negative output terminal Q'. Each time it is triggered, its output flips once, that is, Q n+1 =Q n ', Q n+1 is the n+1th output, Q n ' is the nth reverse output, where n is a positive integer; the CLK terminal is used to connect the signal to be counted. For example, the CLK terminal of the first counter 101 is connected to the STV signal and is refreshed once per frame; the CLK terminal of the second counter 102 is connected to the Gate signal or the touch panel (TP) signal and is refreshed once per scan line.

[0093] The switch element 20 may be a thin film transistor (TFT), see Figure 8 The first end (signal input end) of the switching element 20 is connected to the Gate signal, the second end (signal output end) of the switching element 20 is connected to the Gate signal input end of the sub-pixel 30, and the control end of the switching element 20 is connected to the output end of the logic gate 103. When the output value of the logic gate 103 is 1, the switching element 20 is turned on, and the Gate signal is output to the sub-pixel 30, driving the sub-pixel 30 to display; when the output value of the logic gate 103 is 0, the switching element 20 is disconnected, the Gate signal cannot drive the sub-pixel 30 through the switching element 20, and the sub-pixel 30 does not display.

[0094] Let logic gate 103 be an XNOR gate. The initial values ​​of the first counter 101 and the second counter 102 are the same, both 1. The initial value refers to the value output when the signal is first received. In the first image frame, the signal actually received by the sub-pixels in the display substrate is shown in Figure 9(a). In the first image frame, the STV signal triggers the first counter 101 once, and the first counter 101 outputs 1. The Gate signal of the first row of sub-pixels output by the driver chip triggers the second counter 102. The output 1 of the second counter 102 is the same as the output 1 of the first counter 101. After being controlled by logic gate 103, the switch element 20 is turned on, and the Gate signal of the first row of sub-pixels is transmitted to each sub-pixel 30 in the first row through the switch element 20. Among them, the Gate signal received by the sub-pixel 30 in the i-th row is represented as OGi, where i is a positive integer. The Gate signal of the second row of sub-pixels triggers the second counter 102 again. The output 0 of the second counter 102 is different from the output 1 of the first counter 101. After being controlled by the logic gate 103, the switch element 20 is disconnected, and the Gate signal of the second row of sub-pixels is blocked by the switch element 20. The sub-pixels 30 in the second row cannot receive OG2, and the sub-pixels in the second row are not displayed. This process is repeated until all sub-pixel rows of the display substrate are scanned and the first image frame ends.

[0095] Entering the second image frame, see Figure 9(b), where the Gate signal received by the i-th row of sub-pixels 30 is represented as OGi, where i is a positive integer. In the second image frame, the STV signal triggers the first counter 101 once. At this time, the output of the first counter 101 is 0. The Gate signal of the first row of sub-pixels output by the driver chip triggers the second counter 102. The output 1 of the second counter 102 is different from the output 0 of the first counter 101. After the control of the logic gate 103, the switch element 20 is turned off, and the Gate signal of the first row of sub-pixels is blocked by the switch element 20. The sub-pixels 30 in the first row cannot receive OG1, and the sub-pixels in the first row do not display. The Gate signal of the second row of sub-pixels triggers the second counter 102 again. The output 0 of the second counter 102 is the same as the output 0 of the first counter 101. After the control of the logic gate 103, the switch element 20 is turned on. The sub-pixels 30 in the second row receive OG2, and the sub-pixels in the second row display. This process continues in this way until all sub-pixel rows of the display substrate have been scanned, and the second image frame ends.

[0096] Generally, the total number of rows of sub-pixels in the display substrate is an even number. In this case, there is no need to reset the second counter 102. If the total number of rows of sub-pixels in the display substrate is an odd number, the second counter 102 needs to be reset every time a frame is refreshed.

[0097] The first counter 101 and the second counter 102 can be JK flip-flops, T flip-flops, etc., which can be selected according to actual needs. When other components are used as counters, the timing of the clock signal needs to be adaptively adjusted so that the first counter 101 is triggered once per frame and the second counter 102 is triggered once per row.

[0098] In the embodiment of the present application, the requirements for the counter are relatively low and it can be implemented using only a D flip-flop. The circuit cost is low and easy to implement.

[0099] In one possible implementation, an input end of the first counter 101 is connected to a first signal, an input end of the second counter 102 is connected to a second signal, and an output end of the logic gate 103 is respectively connected to a control end of each switching element 20; the total number of switching elements 20 is the same as the total number of sub-pixel columns, the input end of the j-th switching element is connected to the fourth signal of the sub-pixel 30 in the j-th column, and the output end of the j-th switching element is connected to the fourth signal input end of the sub-pixel 30 in the j-th row, where j is a positive integer, the first signal is a signal that is refreshed once each time a frame of an image is refreshed, the second signal is a signal that is refreshed once each time a row of sub-pixels 30 is refreshed, and the fourth signal is a column drive signal for refreshing a column of sub-pixels 30;

[0100] The first counter 101 is configured to: output a first value when receiving the first signal for an odd number of times; and output a second value when receiving the first signal for an even number of times;

[0101] The second counter 102 is configured to: output the first value after receiving the second signal for an odd number of times, and output the second value after receiving the second signal for an even number of times; or output the second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

[0102] The first signal is a signal that is refreshed every time a frame of the image is refreshed. The first counter 101 receives the first signal for an odd number of times and outputs a first value, that is, the first counter 101 outputs the first value in an odd frame; the first counter 101 receives the first signal for an even number of times and outputs a second value, that is, the first counter 101 outputs the second value in an even frame.

[0103] The second signal is a signal that is refreshed once every time a row of sub-pixels 30 is refreshed. The second counter 102 outputs a first value after receiving the second signal for an odd number of times, and outputs a second value after receiving the second signal for an even number of times. That is, the second counter 102 outputs a first value when scanning to odd rows line by line, and outputs a second value when scanning to even rows line by line.

[0104] The second counter 102 outputs the second value after receiving the second signal for an odd number of times, and outputs the first value after receiving the second signal for an even number of times. That is, the second counter 102 outputs the second value when scanning to the odd rows line by line, and outputs the first value when scanning to the even rows line by line.

[0105] The output end of the logic gate 103 is connected to the control end of each switching element 20. When the display image frame is an odd frame, the logic gate 103 controls the switching element 20 to be turned on when the progressive scanning reaches the odd row, and controls the switching element 20 to be turned off when the progressive scanning reaches the even row. When the display image frame is an even frame, the logic gate 103 controls the switching element 20 to be turned off when the progressive scanning reaches the odd row, and controls the switching element 20 to be turned on when the progressive scanning reaches the even row.

[0106] Alternatively, when the display image frame is an even frame, the logic gate 103 controls the switch element 20 to be turned on when the progressive scanning reaches the odd-numbered rows, and controls the switch element 20 to be turned off when the progressive scanning reaches the even-numbered rows. When the display image frame is an odd frame, the logic gate 103 controls the switch element 20 to be turned off when the progressive scanning reaches the odd-numbered rows, and controls the switch element 20 to be turned on when the progressive scanning reaches the even-numbered rows.

[0107] The input end of the jth switching element is connected to the fourth signal of the jth column sub-pixel 30, and the output end of the jth switching element is connected to the fourth signal input end of the jth row sub-pixel 30, that is, the jth switching element is connected between the fourth signal output end and the jth column sub-pixel 30; the fourth signal is a data signal, and a switching element is set at the data signal input end of each column. When scanning to the sub-pixel row that needs to be displayed, the switching element 20 is turned on, so that the data signal is output to the sub-pixel row, and the sub-pixel row displays the picture; when scanning to the sub-pixel row that does not need to be displayed, the switching element 20 is disconnected, the data signal cannot be output, and the sub-pixels 30 in this row do not display the picture.

[0108] A switch element 20 is added to the data signal input end of each column. By controlling the switch element 20, the entire row of sub-pixels 30 can be controlled to display or not display. The circuit structure is simple and the manufacturing cost is low.

[0109] In a possible implementation, the first signal is a vertical synchronization signal STV signal, the second signal is a touch signal TP signal, and the fourth signal is a source signal Source signal.

[0110] The touch signal (TP signal) refreshes each time a row of sub-pixels is refreshed. The source signal (Source signal), also known as a data signal, is used to control the light emission of the sub-pixels 30.

[0111] For an example, see Figure 10The driver chip provides a Gate signal to the sub-pixel, the data chip provides a source signal to the circuit, the STV signal is the input to the first counter 101, and the TP signal is the input to the second counter 102. When the Gate signal is input normally, when the source signal is input to the sub-pixel 30, the sub-pixel 30 displays an image, and when there is no passive signal, the sub-pixel 30 does not display an image.

[0112] By controlling the source signal output to control whether the image is displayed, the sub-pixel 30 is always in the on state, reducing the loss caused by frequent switching and increasing the service life of the circuit.

[0113] In a possible implementation, the first counter 101 and the second counter 102 are both D flip-flops, and the switch element 20 is a tri-state buffer.

[0114] The switch element 20 can be a TFT, a tri-state buffer or other transistor capable of performing a switching function. The first counter 101 and the second counter 102 are both D flip-flops. The timing diagrams of the signals received by two adjacent image frames are shown in Figures 11(a) and 11(b) respectively.

[0115] Let logic gate 103 be an XNOR gate. The initial values ​​of the first counter 101 and the second counter 102 are the same, both 1. The initial value refers to the value output when the signal is first received. In the first image frame, the signal actually received by the sub-pixels in the display substrate is shown in Figure 11(a). In the first image frame, the STV signal triggers the first counter 101 once, and the first counter 101 outputs 1. When the Gate signal of the first row of sub-pixels output by the driver chip is output, the TP signal is also output, and the TP signal triggers the second counter 102. The output 1 of the second counter 102 is the same as the output 1 of the first counter 101. After being controlled by logic gate 103, the switch element 20 is turned on, and the Source signal is transmitted to each sub-pixel 30 in the first row through the switch element 20. Among them, the Gate signal received by the sub-pixel 30 in the i-th row is represented as OGi, where i is a positive integer. When the driver chip outputs the Gate signal for the second row of sub-pixels, the TP signal triggers the second counter 102 again. The output 0 of the second counter 102 is different from the output 1 of the first counter 101. After being controlled by the logic gate 103, the switch element 20 is turned off, and the Source signal is blocked by the switch element 20. The sub-pixels 30 in the second row cannot receive the Source signal. Although the sub-pixels 30 in the second row now receive the Gate signal, because they cannot receive the Source signal, OG2 is now an invalid signal NA, and the sub-pixels in the second row do not display. This process continues in this way until all sub-pixel rows of the display substrate are scanned, and the first image frame ends.

[0116] Entering the second image frame, see Figure 11(b), where the Gate signal received by the i-th row of sub-pixels 30 is represented as OGi, where i is a positive integer. In the second image frame, the STV signal triggers the first counter 101 once. At this time, the output of the first counter 101 is 0. When the driver chip outputs the Gate signal for the first row of sub-pixels, the TP signal is also output. The TP signal triggers the second counter 102. The output of the second counter 102 is 1, which is different from the output 0 of the first counter 101. After being controlled by the logic gate 103, the switch element 20 is disconnected, and the Source signal of the first row of sub-pixels is blocked by the switch element 20. The sub-pixels 30 in the first row cannot receive the Source signal, and the sub-pixels in the first row are not displayed. When the driver chip outputs the Gate signal of the second row of sub-pixels, the TP signal triggers the second counter 102 again. The output 0 of the second counter 102 is the same as the output 0 of the first counter 101. After being controlled by the logic gate 103, the switch element 20 is turned on, and each sub-pixel 30 in the second row receives the Source signal, and the sub-pixels in the second row are displayed. This process continues until all sub-pixel rows of the display substrate are scanned and the second image frame ends.

[0117] The first counter 101 and the second counter 102 can be JK flip-flops, T flip-flops, etc., which can be selected according to actual needs. When other components are used as counters, the timing of the clock signal needs to be adaptively adjusted so that the first counter 101 is triggered once per frame and the second counter 102 is triggered once per row.

[0118] In the embodiment of the present application, the requirements for the counter are relatively low and it can be implemented using only a D flip-flop. The circuit cost is low and easy to implement.

[0119] An embodiment of the present application provides a display, comprising any display substrate described in the embodiments of the present application.

[0120] The display provided in the embodiment of the present application has a display effect. Figure 4 By changing the hardware circuit, the problem of color bleeding when adjacent rows have large differences in image quality can be reduced, resulting in lower manufacturing costs and more accurate display images. Furthermore, compared to software-based solutions, hardware changes can achieve more stable results. Software processing can also be combined with the embodiments of this application to further reduce the effect of color bleeding.

[0121] An embodiment of the present application provides a display device, including the display described in the embodiment of the present application.

[0122] The display device provided in the embodiments of the present application reduces the occurrence of color crosstalk when adjacent rows have significantly different images by modifying the hardware circuitry, resulting in lower manufacturing costs and more accurate display. Furthermore, compared to software-based approaches, hardware modifications achieve a more stable effect. Software processing can also be combined with the embodiments of the present application to further reduce the effect of color crosstalk.

[0123] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0124] Each embodiment in this specification is described in a related manner. Similar parts between the embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. The above description is only a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application are included in the scope of protection of this application.

Claims

1. A display substrate, characterized in that: include: A gating module, a plurality of switching elements, and a plurality of sub-pixels; The gating modules are respectively connected to the switch elements, and the switch elements are connected to the sub-pixels; The selection module is configured as follows: for a first image frame and a second image frame that are adjacent in time sequence, when displaying the first image frame, the sub-pixels of each odd row are displayed by controlling the switching element; when displaying the second image frame, the sub-pixels of each even row are displayed by controlling the switching element.

2. The display substrate according to claim 1, wherein: The gating module includes a first counter, a second counter and a logic gate; The first counter is connected to the first input terminal of the logic gate, the second counter is connected to the second input terminal of the logic gate, and the output terminal of the logic gate is connected to each of the switch elements respectively; The first counter is configured to: output a first value when the currently displayed image frame is an odd frame, and output a second value when the currently displayed image frame is an even frame; The second counter is configured to: output a first value during a refresh period of the odd-numbered rows of sub-pixels, and output a second value during a refresh period of the even-numbered rows of sub-pixels; or output a second value during a refresh period of the odd-numbered rows of sub-pixels, and output a first value during a refresh period of the even-numbered rows of sub-pixels; The logic gate is configured to: control each of the switch elements to be turned on when the values ​​input to the first input terminal or the second input terminal are the same, and control each of the switch elements to be turned off when the values ​​input to the first input terminal or the second input terminal are different; or control each of the switch elements to be turned on when the values ​​input to the first input terminal or the second input terminal are different, and control each of the switch elements to be turned off when the values ​​input to the first input terminal or the second input terminal are the same; The switching element is configured to transmit a driving signal to the sub-pixel connected thereto when the switching element is turned on.

3. The display substrate according to claim 2, wherein: An input end of the first counter is connected to a first signal, an input end of the second counter is connected to a second signal, and an output end of the logic gate is respectively connected to a control end of each of the switch elements; the total number of the switch elements is the same as the total number of sub-pixel rows, the input end of the i-th switch element is connected to the third signal of the i-th row of sub-pixels, and the output end of the i-th switch element is connected to the third signal input end of the i-th row of sub-pixels, wherein i is a positive integer, the first signal is a signal that is refreshed once every time a frame of an image is refreshed, the second signal is a signal that is refreshed once every time a row of sub-pixels is refreshed, and the third signal is a row drive signal for refreshing a row of sub-pixels; The first counter is configured to: output a first value after receiving the first signal for an odd number of times; and output a second value after receiving the first signal for an even number of times; The second counter is configured to: output a first value after receiving the second signal for an odd number of times, and output a second value after receiving the second signal for an even number of times; or output a second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

4. The display substrate according to claim 3, wherein: The first signal is a vertical synchronization signal STV signal, the second signal is a Gate signal, and the third signal is a Gate signal.

5. The display substrate according to claim 3, wherein: The first counter and the second counter are both D flip-flops, and the switch element is a thin film transistor (TFT).

6. The display substrate according to claim 2, wherein: An input terminal of the first counter is connected to a first signal, an input terminal of the second counter is connected to a second signal, and an output terminal of the logic gate is respectively connected to a control terminal of each of the switch elements; the total number of the switch elements is the same as the total number of sub-pixel columns, the input terminal of the j-th switch element is connected to the fourth signal of the sub-pixel in the j-th column, and the output terminal of the j-th switch element is connected to the fourth signal input terminal of the sub-pixel in the j-th row, wherein j is a positive integer, the first signal is a signal that is refreshed once every time a frame of an image is refreshed, the second signal is a signal that is refreshed once every time a row of sub-pixels is refreshed, and the fourth signal is a column drive signal for refreshing a column of sub-pixels; The first counter is configured to: output a first value when receiving the first signal for an odd number of times; and output a second value when receiving the first signal for an even number of times; The second counter is configured to: output a first value after receiving the second signal for an odd number of times, and output a second value after receiving the second signal for an even number of times; or output a second value after receiving the second signal for an odd number of times, and output the first value after receiving the second signal for an even number of times.

7. The display substrate according to claim 6, wherein: The first signal is a vertical synchronization signal STV signal, the second signal is a touch signal TP signal, and the fourth signal is a source signal Source signal.

8. The display substrate according to claim 6, wherein: The first counter and the second counter are both D flip-flops, and the switch element is a tri-state buffer.

9. A display, characterized in that: The display substrate comprises any one of claims 1 to 8.

10. A display device, characterized in that: A display comprising the display of claim 9.

Images