Display device and method of operating the same

Abstract

A display device and a method of operating a display device are provided, the display device including: a display panel including a plurality of pixels; and a panel driver configured to drive the display panel. At least one of the plurality of pixels includes: a first light emitting element having a first viewing angle; a second light emitting element having a second viewing angle different from the first viewing angle; a pixel circuit configured to generate a driving current; a first transistor configured to supply a driving current to the first light emitting element in response to a first signal; and a second transistor configured to supply the driving current to the second light emitting element in response to a second signal. In response to the mode switching signal, the panel driver gradually changes an on period of at least one of the first signal and the second signal than during the plurality of frame periods.

Description

Technical Field

[0001] Embodiments of the invention relate to a display apparatus, and more particularly, to a display apparatus supporting a public mode and a private mode and a method of operating the display apparatus. Background Art

[0002] Typically, display devices can display images with a wide viewing angle, allowing the images to be viewed not only by users in front of the display device but also by users to the sides. However, recently, in order to protect personal information or to ensure the safety of display devices installed in vehicles, a private mode (or privacy mode) has been developed in which the display device displays images only to users in front of the display device. For example, a vehicle display device positioned to correspond to a passenger seat in a vehicle can operate not only in a public mode, in which images are displayed with a wide viewing angle so that the images are provided to both the driver and the passenger, but also in a private mode, in which images are displayed with a narrow viewing angle so that the images are provided only to the passenger. Summary of the Invention

[0003] Some embodiments provide a display device capable of providing smooth mode switching.

[0004] Some embodiments provide a method of operating a display device capable of providing smooth mode switching.

[0005] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels; and a panel driver configured to drive the display panel. At least one of the plurality of pixels comprises: a first light-emitting element having a first viewing angle; a second light-emitting element having a second viewing angle different from the first viewing angle; a pixel circuit configured to generate a drive current; a first transistor configured to supply the drive current to the first light-emitting element in response to a first signal; and a second transistor configured to supply the drive current to the second light-emitting element in response to a second signal. In response to a mode switching signal, the panel driver gradually changes an on-period ratio of at least one of the first signal and the second signal over a plurality of frame periods.

[0006] In an embodiment, the first viewing angle may be a wide viewing angle, and the second viewing angle may be a narrow viewing angle narrower than the first viewing angle.

[0007] In an embodiment, the first light-emitting element may be a public light-emitting element configured to provide light to both a first user located in front of the display device and a second user located on the side of the display device, and the second light-emitting element may be a private light-emitting element configured to provide light to the first user but not to the second user.

[0008] In an embodiment, a display device is installed in a vehicle. When the vehicle changes from a stationary state to a moving state, a panel driver may receive a mode switching signal instructing switching from a public mode to a private mode. In the public mode, an image displayed by the display device is visible to both a first user located in front of the display device and a second user located to the side of the display device. In the private mode, the image displayed by the display device is visible to the first user but not to the second user.

[0009] In an embodiment, when the vehicle changes from a moving state to a stationary state, the panel driver may receive a mode switching signal instructing switching from the private mode to the public mode.

[0010] In an embodiment, when the mode switching signal indicates switching from the public mode to the private mode, the panel driver may gradually reduce the on-period ratio of the first signal during a plurality of first frame periods, and gradually increase the on-period ratio of the second signal during a plurality of first frame periods. When the mode switching signal indicates switching from the private mode to the public mode, the panel driver may gradually reduce the on-period ratio of the second signal during a plurality of second frame periods, and gradually increase the on-period ratio of the first signal during a plurality of second frame periods.

[0011] In an embodiment, when the mode switching signal indicates switching from the public mode to the fully off mode, the panel driver may gradually reduce the on-period ratio of the first signal during a plurality of first frame periods. When the mode switching signal indicates switching from the fully off mode to the private mode, the panel driver may gradually increase the on-period ratio of the second signal during a plurality of second frame periods.

[0012] In an embodiment, when the mode switching signal indicates switching from the private mode to the fully off mode, the panel driver may gradually reduce the on-period ratio of the second signal during a plurality of first frame periods. When the mode switching signal indicates switching from the fully off mode to the public mode, the panel driver may gradually increase the on-period ratio of the first signal during a plurality of second frame periods.

[0013] In an embodiment, when the mode switching signal indicates switching from the public mode to the private mode, the panel driver may perform a first fade-out operation for switching from the public mode to the fully off mode by gradually decreasing the on-period ratio of the first signal during a plurality of first frame periods, and after the first fade-out operation, may perform a first fade-in operation for switching from the fully off mode to the private mode by gradually increasing the on-period ratio of the second signal during a plurality of second frame periods. When the mode switching signal indicates switching from the private mode to the public mode, the panel driver may perform a second fade-out operation for switching from the private mode to the fully off mode by gradually decreasing the on-period ratio of the second signal during a plurality of third frame periods, and after the second fade-out operation, may perform a second fade-in operation for switching from the fully off mode to the public mode by gradually increasing the on-period ratio of the first signal during a fourth frame period.

[0014] In an embodiment, the first signal may be a first global signal applied to the plurality of pixels substantially simultaneously, and the second signal may be a second global signal applied to the plurality of pixels substantially simultaneously.

[0015] In an embodiment, the pixel circuit may include: a third transistor including a gate, a first terminal connected to a first power supply voltage line, and a second terminal; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line, and a second terminal; a first capacitor including a first electrode connected to the first power supply voltage line and a second electrode connected to the second terminal of the fourth transistor; a second capacitor including a first electrode connected to the second terminal of the fourth transistor and a second electrode connected to the gate of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to the initialization voltage line; a seventh transistor including a gate connected to the compensation signal line, a first terminal connected to the first electrode of the second capacitor, and a second terminal connected to a reference voltage line; an eighth transistor including a gate connected to an emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first transistor and the second transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light-emitting element, and a second terminal connected to the anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light-emitting element, and a second terminal connected to the anode initialization voltage line. The first transistor may include a gate connected to the first global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the first light-emitting element, and the second transistor may include a gate connected to the second global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the second light-emitting element.

[0016] In an embodiment, the pixel circuit may include: a third transistor including a gate, a first terminal and a second terminal; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line and a second terminal connected to the first terminal of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor and a second terminal connected to the gate of the third transistor; a first capacitor including a first electrode connected to a first power supply voltage line and a second electrode connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor and a second terminal connected to the initialization voltage line; a seventh transistor including a gate connected to an emission signal line, a first terminal connected to the first power supply voltage line and a second terminal connected to the first terminal of the third transistor; an eighth transistor including a gate connected to an emission signal line, a first terminal connected to the second terminal of the third transistor and a second terminal connected to the first transistor and the second transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light-emitting element and a second terminal connected to the anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light-emitting element and a second terminal connected to the anode initialization voltage line. The first transistor may include a gate connected to the first global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the first light-emitting element, and the second transistor may include a gate connected to the second global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the second light-emitting element.

[0017] In an embodiment, the first signal may be a first emission signal sequentially applied to the plurality of pixels on a row basis, and the second signal may be a second emission signal sequentially applied to the plurality of pixels on a row basis.

[0018] In an embodiment, the pixel circuit may include: a third transistor including a gate, a first terminal connected to a first power supply voltage line, and a second terminal connected to the first transistor and the second transistor; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line, and a second terminal; a first capacitor including a first electrode connected to the first power supply voltage line and a second electrode connected to the second terminal of the fourth transistor; a second capacitor including a first electrode connected to the second terminal of the fourth transistor and a second electrode connected to the gate of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to the initialization voltage line; a seventh transistor including: a gate connected to the compensation signal line, a first terminal connected to the first electrode of the second capacitor, and a second terminal connected to the reference voltage line; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light-emitting element, and a second terminal connected to the anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light-emitting element, and a second terminal connected to the anode initialization voltage line. The first transistor may include a gate connected to the first emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first light-emitting element, and the second transistor may include a gate connected to the second emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the second light-emitting element.

[0019] In an embodiment, the pixel circuit may include: a third transistor including a gate, a first terminal, and a second terminal; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line, and a second terminal connected to the first terminal of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a first capacitor including a first electrode connected to a first power supply voltage line and a second electrode connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to the initialization voltage line; a seventh transistor including a gate connected to an emission signal line, a first terminal connected to the first power supply voltage line, and a second terminal connected to the first terminal of the third transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to a first light-emitting element, and a second terminal connected to an anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to a second light-emitting element, and a second terminal connected to the anode initialization voltage line. The first transistor may include a gate connected to the first emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first light-emitting element, and the second transistor may include a gate connected to the second emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the second light-emitting element.

[0020] According to an embodiment, a method for operating a display device is provided in which at least one pixel includes a first light-emitting element and a second light-emitting element having different viewing angles. In this method, a mode switching signal is received, and an on-time ratio of at least one of a first signal for supplying a drive current to the first light-emitting element and a second signal for supplying a drive current to the second light-emitting element is gradually changed over multiple frame periods.

[0021] In an embodiment, to receive the mode switching signal, a first mode switching signal indicating switching from the public mode to the private mode may be received. To gradually change the on-period ratio of at least one of the first signal and the second signal, the on-period ratio of the first signal may be gradually reduced during a plurality of first frame periods in response to the first mode switching signal, and the on-period ratio of the second signal may be gradually increased during a plurality of first frame periods in response to the first mode switching signal.

[0022] In an embodiment, in order to receive the mode switching signal, a second mode switching signal indicating switching from the private mode to the public mode may be received. In order to gradually change the on-period ratio of at least one of the first signal and the second signal, the on-period ratio of the second signal may be gradually reduced during a plurality of second frame periods in response to the second mode switching signal, and the on-period ratio of the first signal may be gradually increased during a plurality of second frame periods in response to the second mode switching signal.

[0023] In an embodiment, to receive a mode switching signal, a first mode switching signal indicating a switch from the public mode to the fully off mode may be received, and a second mode switching signal indicating a switch from the fully off mode to the private mode may be received. To gradually change the on-period ratio of at least one of the first signal and the second signal, the on-period ratio of the first signal may be gradually reduced during a plurality of first frame periods in response to the first mode switching signal, and the on-period ratio of the second signal may be gradually increased during a plurality of second frame periods in response to the second mode switching signal.

[0024] In an embodiment, in order to receive the mode switching signal, a third mode switching signal indicating switching from the private mode to the fully off mode may be received, and a fourth mode switching signal indicating switching from the fully off mode to the public mode may be received. In order to gradually change the on-period ratio of at least one of the first signal and the second signal, the on-period ratio of the second signal may be gradually reduced during multiple third frame periods in response to the third mode switching signal, and the on-period ratio of the first signal may be gradually increased during multiple fourth frame periods in response to the fourth mode switching signal.

[0025] As described above, in the display device and the method of operating the display device according to the embodiment, at least one pixel may include a first light-emitting element and a second light-emitting element having different viewing angles, and the on-period ratio of the first signal for supplying a driving current to the first light-emitting element and the second signal for supplying a driving current to the second light-emitting element may be gradually changed over a plurality of frame periods. Therefore, the display device according to the embodiment can perform smooth mode switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0028] Figure 2 is a diagram illustrating at least one pixel included in a display device according to an embodiment.

[0029] Figure 3is a circuit diagram illustrating an example of at least one pixel included in a display device according to an embodiment.

[0030] Figure 4 is a circuit diagram illustrating another example of at least one pixel included in a display device according to an embodiment.

[0031] Figure 5 is a timing diagram illustrating an example in which the voltage level of the first global signal and the voltage level of the second global signal gradually change in a mode switching period.

[0032] Figure 6 is a timing diagram illustrating first and second global signals in a case where a mode of a display device is switched from a public mode to a private mode according to an embodiment.

[0033] Figure 7 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a public mode to a private mode according to an embodiment.

[0034] Figure 8 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a private mode to a public mode according to an embodiment.

[0035] Figure 9 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from a private mode to a public mode.

[0036] Figure 10 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a public mode to a private mode according to an embodiment.

[0037] Figure 11 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from the common mode to the all-off mode.

[0038] Figure 12 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from the all-off mode to the private mode.

[0039] Figure 13 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a private mode to a public mode according to an embodiment.

[0040] Figure 14 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from a privacy mode to a full-off mode.

[0041] Figure 15 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from the all-off mode to the common mode.

[0042] Figure 16 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a public mode to a private mode according to an embodiment.

[0043] Figure 17 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a private mode to a public mode according to an embodiment.

[0044] Figure 18 is a block diagram illustrating a display device according to an embodiment.

[0045] Figure 19 is a diagram illustrating at least one pixel included in a display device according to an embodiment.

[0046] Figure 20 is a circuit diagram illustrating an example of at least one pixel included in a display device according to an embodiment.

[0047] Figure 21 is a circuit diagram illustrating another example of at least one pixel included in a display device according to an embodiment.

[0048] Figure 22 is a timing diagram illustrating a first transmission signal and a second transmission signal in a case where a mode of a display device is switched from a public mode to a private mode according to an embodiment.

[0049] Figure 23 is a timing diagram illustrating a first transmission signal and a second transmission signal in a case where a mode of a display device is switched from a private mode to a public mode according to an embodiment.

[0050] Figure 24 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0051] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (one / a kind)", "said" and "at least one (at least one / at least one)" do not represent quantitative limitations and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (at least one / at least one)" should not be interpreted as limiting "one" or "one (one / a kind)". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that when the terms "comprise" and / or "comprising" or variations thereof are used in this specification, the description indicates the presence of the stated features, regions, entireties, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or their groups.

[0052] It will be understood that although the terms "first", "second", "third" etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part. Hereinafter, embodiments are described more fully with reference to the accompanying drawings. The same or similar reference numerals always refer to the same or similar elements.

[0053] Figure 1 is a block diagram showing a display device according to an embodiment, Figure 2 is a diagram illustrating at least one pixel included in a display device according to an embodiment, Figure 3 is a circuit diagram illustrating an example of at least one pixel included in a display device according to an embodiment, Figure 4 is a circuit diagram illustrating another example of at least one pixel included in a display device according to an embodiment, Figure 5 is a timing diagram showing an example in which the voltage levels of the first global signal and the second global signal gradually change in a mode switching period, Figure 6 is a timing diagram illustrating first and second global signals in a case where a mode of a display device is switched from a public mode to a private mode according to an embodiment.

[0054] Reference Figure 1According to an embodiment, the display device 100 may include a display panel 110 including a plurality of pixels PX and a panel driver 120 driving the display panel 110. In some embodiments, the panel driver 120 may include a data driver 130 that provides a data signal DS to the plurality of pixels PX, a scan driver 140 that provides a scan signal SS to the plurality of pixels PX, an emission driver 150 that provides an emission signal EM to the plurality of pixels PX, and a controller 160 that controls the operation of the display device 100 and provides a first global signal GS1 and a second global signal GS2 to the plurality of pixels PX.

[0055] The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of emission lines, and a plurality of pixels PX connected to the plurality of data lines, the plurality of scan lines, and the plurality of emission lines. Figure 2 As shown in , at least one pixel PX among the plurality of pixels PX may include a first light emitting element EL1 , a second light emitting element EL2 , a pixel circuit PC, a first transistor T1 , and a second transistor T2 .

[0056] The first light-emitting element EL1 may have a first viewing angle, and the second light-emitting element EL2 may have a second viewing angle different from the first viewing angle. Here, the viewing angle of a light-emitting element may be the viewing angle of the light emitted from the light-emitting element. In some embodiments, the first viewing angle may be relatively wide, and the second viewing angle may be relatively narrow. For example, to achieve a narrow viewing angle, the second light-emitting element EL2 may include, but is not limited to, a light-emitting layer and a partition for preventing light emitted by the light-emitting layer from spreading to the sides. Furthermore, in some embodiments, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be, but is not limited to, an organic light-emitting diode ("OLED"). In other embodiments, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be any suitable light-emitting element. For example, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be a micro light-emitting diode, a nano light-emitting diode ("NLED"), a quantum dot ("QD") light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In some embodiments, the first light-emitting element EL1 may include an anode connected to the first transistor T1 and a cathode connected to a second power supply voltage line transmitting a second power supply voltage ELVSS (e.g., a low power supply voltage). The second light-emitting element EL2 may include an anode connected to the second transistor T2 and a cathode connected to the second power supply voltage line.

[0057] The pixel circuit PC can generate a driving current IDR based on the scan signal SS, the emission signal EM and the data signal DS. Figure 3As shown in , the pixel PXa may include a first light-emitting element EL1, a second light-emitting element EL2, a first transistor T1, a second transistor T2 and a pixel circuit PCa, and the pixel circuit PCa may include a third transistor T3a, a fourth transistor T4a, a first capacitor C1a, a second capacitor C2a, a fifth transistor T5a and a sixth transistor T6a, a seventh transistor T7a, an eighth transistor T8a, a ninth transistor T9a and a tenth transistor T10a.

[0058] The third transistor T3a may be a driving transistor for generating a driving current IDR. In some embodiments, the third transistor T3a may include a gate connected to the second capacitor C2a, a first terminal connected to a first power supply voltage line transmitting a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second terminal connected to the fifth transistor T5a and the eighth transistor T8a.

[0059] The fourth transistor T4a can transmit the data signal DS of the data line DL to the first capacitor C1a and the second capacitor C2a in response to the write signal GW. In some embodiments, the fourth transistor T4a may include a gate connected to the write signal line transmitting the write signal GW, a first terminal connected to the data line DL, and a second terminal connected to the first capacitor C1a and the second capacitor C2a.

[0060] The first capacitor C1a can store the data signal DS transmitted by the fourth transistor T4a. For example, the first capacitor C1a can be a storage capacitor. In some embodiments, the first capacitor C1a can include a first electrode connected to the first power supply voltage line and a second electrode connected to the second terminal of the fourth transistor T4a.

[0061] The second capacitor C2a can be connected between the second electrode of the first capacitor C1a and the gate of the third transistor T3a. For example, the second capacitor C2a can be a holding capacitor. In some embodiments, the second capacitor C2a can include a first electrode connected to the second terminal of the fourth transistor T4a and the second electrode of the first capacitor C1a, and a second electrode connected to the gate of the third transistor T3a. Therefore, when the voltage of the first electrode of the second capacitor C2a changes from the reference voltage VREF to the data signal DS, the voltage of the second electrode of the second capacitor C2a can also change (for example, from a voltage obtained by subtracting the absolute value of the threshold voltage of the third transistor T3a from the first power supply voltage ELVDD) according to the voltage difference between the reference voltage VREF and the data signal DS.

[0062] The fifth transistor T5a can diode-connect the third transistor T3a in response to the compensation signal GC. For example, when the third transistor T3a is diode-connected, the voltage of the second electrode of the second capacitor C2a can be changed (e.g., from the initialization voltage VINT) to a voltage obtained by subtracting the absolute value of the threshold voltage of the third transistor T3a from the first power supply voltage ELVDD. This operation can be referred to as a threshold voltage compensation operation and can be performed before the data signal DS is transmitted through the fourth transistor T4a. In some embodiments, the fifth transistor T5a can include a gate connected to a compensation signal line that transmits the compensation signal GC, a first terminal connected to the second terminal of the third transistor T3a, and a second terminal connected to the gate of the third transistor T3a.

[0063] The sixth transistor T6a may transmit the initialization voltage VINT to the gate of the third transistor T3a and the second electrode of the second capacitor C2a in response to the initialization signal GI. In some embodiments, the sixth transistor T6a may include a gate connected to an initialization signal line transmitting the initialization signal GI, a first terminal connected to the gate of the third transistor T3a and the second electrode of the second capacitor C2a, and a second terminal connected to an initialization voltage line transmitting the initialization voltage VINT.

[0064] The seventh transistor T7a can transmit the reference voltage VREF to the second electrode of the first capacitor C1a and the first electrode of the second capacitor C2a in response to the compensation signal GC. In some embodiments, the seventh transistor T7a may include a gate connected to the compensation signal line, a first terminal connected to the second electrode of the first capacitor C1a and the first electrode of the second capacitor C2a, and a second terminal connected to a reference voltage line for transmitting the reference voltage VREF.

[0065] The eighth transistor T8a may connect the third transistor T3a to the first transistor T1 and the second transistor T2 in response to the emission signal EM. In some embodiments, the eighth transistor T8a may include a gate connected to an emission signal line transmitting the emission signal EM, a first terminal connected to the second terminal of the third transistor T3a, and a second terminal connected to the first transistor T1 and the second transistor T2.

[0066] The ninth transistor T9a can provide the anode initialization voltage VAINT to the first light-emitting element EL1 in response to the bypass signal GB, and the tenth transistor T10a can provide the anode initialization voltage VAINT to the second light-emitting element EL2 in response to the bypass signal GB. In some embodiments, the ninth transistor T9a may include a gate connected to a bypass signal line transmitting the bypass signal GB, a first terminal connected to the first light-emitting element EL1, and a second terminal connected to an anode initialization voltage line transmitting the anode initialization voltage VAINT, and the tenth transistor T10a may include a gate connected to the bypass signal line, a first terminal connected to the second light-emitting element EL2, and a second terminal connected to the anode initialization voltage line.

[0067] In some embodiments, as Figure 3 As shown in , the first to tenth transistors T1 to T10a may be P-type metal oxide semiconductor (PMOS) transistors. In other embodiments, at least one of the first to tenth transistors T1 to T10a may be an N-type metal oxide semiconductor (NMOS) transistor. For example, the first transistor T1, the second transistor T2, the third transistor T3a, the eighth transistor T8a, the ninth transistor T9a, and the tenth transistor T10a may be PMOS transistors, while the fourth transistor T4a, the fifth transistor T5a, the sixth transistor T6a, and the seventh transistor T7a may be NMOS transistors, but the present invention is not limited thereto.

[0068] Furthermore, in some embodiments, at least one of the first to tenth transistors T10a may include a plurality of sub-transistors connected in series. Figure 3 As shown in , each of the fourth transistor T4a, the fifth transistor T5a, and the seventh transistor T7a may include two sub-transistors connected in series, and the sixth transistor T6a may include three sub-transistors connected in series. In this case, since one terminal (e.g., source and / or drain) of the fourth transistor T4a, the fifth transistor T5a, the sixth transistor T6a, and the seventh transistor T7a is connected to the first capacitor C1a and / or the second capacitor C2a, leakage current passing through the fourth transistor T4a, the fifth transistor T5a, the sixth transistor T6a, and the seventh transistor T7a can be reduced, and distortion of the voltage stored in the first capacitor C1a and / or the second capacitor C2a can be prevented or reduced.

[0069] In other embodiments, Figure 4As shown in , the pixel PXb may include a first light emitting element EL1, a second light emitting element EL2, a first transistor T1, a second transistor T2 and a pixel circuit PCb, and the pixel circuit PCb may include a third transistor T3b, a fourth transistor T4b, a fifth transistor T5b, a first capacitor C1b, a sixth transistor T6b, a seventh transistor T7b, an eighth transistor T8b, a ninth transistor T9b and a tenth transistor T10b.

[0070] The third transistor T3b may be a driving transistor for generating a driving current IDR. In some embodiments, the third transistor T3b may include a gate connected to the first capacitor C1b, a first terminal connected to the fourth transistor T4b and the seventh transistor T7b, and a second terminal connected to the fifth transistor T5b and the eighth transistor T8b.

[0071] The fourth transistor T4b can transmit the data signal DS of the data line DL to the first terminal of the third transistor T3b in response to the write signal GW. In some embodiments, the fourth transistor T4b may include a gate connected to the write signal line, a first terminal connected to the data line DL, and a second terminal connected to the first terminal of the third transistor T3b.

[0072] The fifth transistor T5b may diode-connect the third transistor T3b in response to the compensation signal GC. In some embodiments, the fifth transistor T5b may include a gate connected to the compensation signal line, a first terminal connected to the second terminal of the third transistor T3b, and a second terminal connected to the gate of the third transistor T3b.

[0073] The first capacitor C1b may store the data signal DS transmitted through the fourth transistor T4b and the diode-connected third transistor T3b. In some embodiments, the first capacitor C1b includes a first electrode connected to the first power voltage line and a second electrode connected to the gate of the third transistor T3b.

[0074] The sixth transistor T6b may transmit the initialization voltage VINT to the gate of the third transistor T3b and the second electrode of the first capacitor C1b in response to the initialization signal GI. In some embodiments, the sixth transistor T6b may include a gate connected to the initialization signal line, a first terminal connected to the gate of the third transistor T3b and the second electrode of the first capacitor C1b, and a second terminal connected to the initialization voltage line.

[0075] The seventh transistor T7b may connect the first power supply voltage line to the third transistor T3b in response to the emission signal EM, and the eighth transistor T8b may connect the third transistor T3b to the first transistor T1 and the second transistor T2 in response to the emission signal EM. In some embodiments, the seventh transistor T7b may include a gate connected to the emission signal line, a first terminal connected to the first power supply voltage line, and a second terminal connected to the first terminal of the third transistor T3b, and the eighth transistor T8b may include a gate connected to the emission signal line, a first terminal connected to the second terminal of the third transistor T3b, and a second terminal connected to the first transistor T1 and the second transistor T2.

[0076] The ninth transistor T9b can provide the anode initialization voltage VAINT to the first light-emitting element EL1 in response to the bypass signal GB, and the tenth transistor T10b can provide the anode initialization voltage VAINT to the second light-emitting element EL2 in response to the bypass signal GB. In some embodiments, the ninth transistor T9b may include a gate connected to the bypass signal line, a first terminal connected to the first light-emitting element EL1, and a second terminal connected to the anode initialization voltage line, and the tenth transistor T10b may include a gate connected to the bypass signal line, a first terminal connected to the second light-emitting element EL2, and a second terminal connected to the anode initialization voltage line.

[0077] In some embodiments, as Figure 4 As shown in , the first to tenth transistors T10b may be PMOS transistors. In other embodiments, at least one of the first to tenth transistors T10b may be an NMOS transistor. Furthermore, in some embodiments, at least one of the first to tenth transistors T10b may include a plurality of sub-transistors connected in series.

[0078] although Figure 3 An example is shown in which the pixel circuit PCa includes third to tenth transistors T3a to T10a and first and second capacitors C1a and C2a. Figure 4 An example is shown in which the pixel circuit PCb includes the third to tenth transistors T3b to T10b and the first capacitor C1b, but the pixel circuit PC of the pixel PX of the display device 100 according to the embodiment is not limited to Figure 3 and Figure 4 , and may have any circuit configuration that generates the drive current IDR.

[0079] Reference Figure 2 , the first transistor T1 can respond to a first signal (eg, Figure 3GS1 in the figure provides the driving current IDR to the first light emitting element EL1, and the second transistor T2 can respond to the second signal (for example, Figure 3 GS2 in the display 100 supplies a drive current IDR to the second light-emitting element EL2. In some embodiments, the first signal may be a first global signal GS1 applied to the plurality of pixels PX substantially simultaneously, and the second signal may be a second global signal GS2 applied to the plurality of pixels PX substantially simultaneously. In some embodiments, the first and second global signals GS1 and GS2 may be generated by the controller 160 and applied directly to the plurality of pixels PX. In other embodiments, the display device 100 may further include a level shifter (or a level shifter integrated circuit) that converts the voltage levels of the first and second global signals GS1 and GS2 generated by the controller 160 to voltage levels suitable for the plurality of pixels PX, and the first and second global signals GS1 and GS2 may be supplied from the controller 160 to the plurality of pixels PX via the level shifter. In still other embodiments, the display device 100 may further include a power management circuit (or a power management integrated circuit), and the first and second global signals GS1 and GS2 may be supplied from the controller 160 to the plurality of pixels PX via the power management circuit. In yet other embodiments, the first global signal GS1 and the second global signal GS2 may be provided from the controller 160 to the plurality of pixels PX through a level shifter and a power management circuit.

[0080] In some embodiments, each pixel PX of the display device 100 may be Figure 3 In the pixel PXa shown in , the first transistor T1 may include a gate connected to the first global signal line transmitting the first global signal GS1, a first terminal connected to the second terminal of the eighth transistor T8a, and a second terminal connected to the first light-emitting element EL1, and the second transistor T2 may include a gate connected to the second global information line transmitting the second global signal GS2, a first terminal connected to the second terminal of the eighth transistor T8a, and a second terminal connected to the second light-emitting element EL2.

[0081] In other embodiments, each pixel PX of the display device 100 may be Figure 4 In the pixel PXb shown in , the first transistor T1 may include a gate connected to the first global signal line, a first terminal connected to the second terminal of the eighth transistor T8b, and a second terminal connected to the first light-emitting element EL1, and the second transistor T2 may include a gate connected to the second global signal line, a first terminal connected to the second terminal of the eighth transistor T8b, and a second terminal connected to the second light-emitting element EL2.

[0082] When the first global signal GS1 has a turn-on level (eg, a low level) and the second global signal GS2 has a turn-off level (eg, a high level), the first transistor T1 may be turned on and the second transistor T2 may be turned off. Figure 3 The third transistor T3a and Figure 4 The driving current IDR generated by the third transistor T3b shown in FIG3 can be provided to the first light-emitting element EL1, and the first light-emitting element EL1 with a wide viewing angle can emit light based on the driving current IDR. In some embodiments, the first light-emitting element EL1 can be configured to provide light to both a first user USER1 located in front of the display device 100 and a second user USER2 located at the side of the display device 100. Such a light-emitting element can be referred to as a "common light-emitting element." Therefore, when the first global signal GS1 has an on-level, the image displayed by the display device 100 can be viewed by both the first user USER1 and the second user USER2. In some embodiments, the mode of the display device 100 in which the image displayed by the display device 100 is visible to both the first user USER1 located in front of the display device 100 and the second user USER2 located at the side of the display device 100 can be referred to as a "common mode."

[0083] On the contrary, when the first global signal GS1 has an off level and the second global signal GS2 has an on level, the first transistor T1 may be turned off and the second transistor T2 may be turned on. Figure 3 The third transistor T3a and Figure 4 The driving current IDR generated by the third transistor T3b shown in FIG3 can be provided to the second light-emitting element EL2, and the second light-emitting element EL2 with a narrow viewing angle can emit light based on the driving current IDR. In some embodiments, the second light-emitting element EL2 can be configured to provide light to the first user USER1 located in front of the display device 100, but not to the second user USER2 located at the side of the display device 100. Such a light-emitting element can be referred to as a "privacy light-emitting element." Therefore, when the first global signal GS1 has an off-level and the second global signal GS2 has an on-level, the image displayed by the display device 100 can be visible to the first user USER1 but not to the second user USER2. In some embodiments, the mode of the display device 100 in which the image displayed by the display device 100 is visible to the first user USER1 located in front of the display device 100 but not to the second user USER2 located at the side of the display device 100 can be referred to as a "privacy mode."

[0084] In some embodiments, each of all pixels PX of the display panel 110 may include Figures 2 to 4 In other embodiments, a portion of the pixels PX may include first and second light emitting elements EL1 and EL2 with different viewing angles, and the remaining pixels PX may include only one light emitting element.

[0085] Refer again Figure 1 The data driver 130 may generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 160, and may provide the data signal DS to a plurality of pixels PX. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. Furthermore, in some embodiments, the data driver 130 and the controller 160 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver ("TED"). In other embodiments, the data driver 130 and the controller 160 may be implemented as separate integrated circuits.

[0086] The scan driver 140 may generate a scan signal SS based on a scan control signal SCTRL received from the controller 160 and may sequentially provide the scan signal SS to a plurality of pixels PX on a row basis. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. Furthermore, in some embodiments, the scan signal SS applied to each pixel PX may include, but is not limited to, a write signal GW, a compensation signal GC, an initialization signal GI, and a bypass signal GB. In some embodiments, the scan driver 140 may be integrated or formed in the display panel 110. In other embodiments, the scan driver 140 may be implemented as an integrated circuit.

[0087] The emission driver 150 may generate an emission signal EM based on an emission control signal EMCTRL received from the controller 160 and may sequentially provide the emission signal EM to a plurality of pixels PX on a row basis. In some embodiments, the emission control signal EMCTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some embodiments, the emission driver 150 may be integrated or formed in the display panel 110. In other embodiments, the emission driver 150 may be implemented as an integrated circuit.

[0088] The controller 160 (e.g., a timing controller) may receive input image data IDAT and control signals CTRL from an external host processor (e.g., an application processor (AP), a graphics processing unit (GPU), a graphics card, etc.). The control signals CTRL may include a mode switching signal SMODE that instructs switching from a first mode of the display device 100 to a second mode of the display device 100. In some embodiments, the control signals CTRL may also include, but are not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal. Based on the input image data IDAT and the control signals CTRL, the controller 160 may generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and an emission control signal EMCTRL. The controller 160 may control the operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL, control the operation of the scan driver 140 by providing the scan control signal SCTRL, and control the operation of the emission driver 150 by providing the emission control signal EMCTRL.

[0089] In the display device 100 according to an embodiment, the panel driver 120 (or controller 160) may receive a mode switching signal SMODE from a host processor that instructs or requests that the display device 100 switch from a first mode (or current mode) to a second mode (or next mode). In some embodiments, to indicate a switch from the current mode to the next mode, the mode switching signal SMODE may have a value indicating the next mode. In other embodiments, the mode switching signal SMODE may have a first value indicating the current mode and a second value indicating the next mode. Furthermore, in some embodiments, the modes of the display device 100 may include a public mode, a private mode, and an all-off mode. For example, in the public mode, the first light-emitting elements EL1 of the plurality of pixels PX of the display panel 110 may emit light, and the image displayed by the display device 100 may be visible to both a first user USER1 located in front of the display device 100 and a second user USER2 located to the side of the display device 100. Furthermore, in the private mode, the second light emitting elements EL2 of the plurality of pixels PX of the display panel 110 may emit light, and an image displayed by the display device 100 may be visible to a first user USER1 located in front of the display device 100, but not to a second user USER2 located at the side of the display device 100. Furthermore, in the all-off mode, the first light emitting elements EL1 and the second light emitting elements EL2 of the plurality of pixels PX of the display panel 110 may not emit light, and the display device 100 may not display an image.

[0090] In some embodiments, the display device 100 may be a vehicle display device installed in a vehicle. When the vehicle changes from a stationary state to a mobile state (e.g., when the vehicle's gear position changes from parking mode or neutral mode to driving mode or reverse mode), the panel driver 120 may receive a mode switching signal SMODE indicating a switch from public mode to private mode. Furthermore, when the vehicle changes from a mobile state to a stationary state (e.g., when the vehicle's gear position changes from driving mode or reverse mode to parking mode or neutral mode), the panel driver 120 may receive a mode switching signal SMODE indicating a switch from private mode to public mode.

[0091] In response to the mode switching signal SMODE, in order to switch the mode of the display device 100 from the first mode (e.g., one of the public mode, the private mode, and the all-off mode) to the second mode (e.g., the other of the public mode, the private mode, and the all-off mode), the panel driver 120 (or the controller 160) may change the first global signal GS1 and / or the second global signal GS2. In addition, in order to provide a gradual mode switching from the first mode to the second mode, as shown in FIG. Figure 5 As shown in , the panel driver 120 (or the controller 160) may gradually change the voltage levels of the first global signal GS1 and the second global signal GS2 in the mode switching period MSP between the first mode and the second mode. Figure 5 As shown in , when the mode switching signal SMODE indicates switching from the public mode to the private mode, the panel driver 120 (or the controller 160) may gradually change the voltage level of the first global signal GS1 from the on level (e.g., low level) to the off level (e.g., high level), and may gradually change the voltage level of the second global signal GS2 from the off level to the on level. However, in this case, the first transistors T1 of the plurality of pixels PX may have different threshold voltages, and thus the first transistors T1 of the plurality of pixels PX may be turned off at different times within the mode switching period MSP. In addition, the second transistors T2 of the plurality of pixels PX may have different threshold voltages, and thus the second transistors T2 of the plurality of pixels PX may be turned on at different times within the mode switching period MSP. Therefore, as Figure 5 As shown in , when the voltage levels of the first and second global signals GS1 and GS2 gradually change in the mode switching period MSP, a mura defect may occur in the display panel 110 due to the threshold voltage distribution of the first and second transistors T1 and T2 of the plurality of pixels PX.

[0092] However, in the display device 100 according to the embodiment, in the mode switching signal SMODE indicating switching from the first mode to the second mode, the panel driver 120 (or the controller 160) can gradually change the on-period ratio of at least one of the first global signal GS1 and the second global signal GS2 during a plurality of frame periods. Here, the on-period ratio of the first global signal GS1 can represent the ratio of the time length of the on-period (for example, the period during which the signal level is low) of the first global signal GS1 to the time length of each frame period, and the on-period ratio of the second global signal GS2 can represent the ratio of the time length of the on-period of the second global signal GS2 to the time length of each frame period. For example, Figure 6 As shown in , when the mode switching signal SMODE indicates switching from the public mode to the private mode, the panel driver 120 (or the controller 160) can gradually reduce the on-period of the first global signal GS1 during a plurality of frame periods FP1, FP2, ..., FPN. That is, during Figure 6 In the example of , the first global signal GS1 may have a first on-period OP1_1 shorter than the first frame period FP1 in the first frame period FP1, and may have a second on-period OP1_2 shorter than the first on-period OP1_1 in the second frame period FP2. In addition, the on-period of the first global signal GS1 may gradually decrease in the third frame period to the Nth frame period FPN. In addition, the panel driver 120 (or the controller 160) may gradually increase the on-period of the second global signal GS2 during the plurality of frame periods FP1, FP2, ..., FPN. That is, in Figure 6In the example shown in FIG5 , the second global signal GS2 may have a first on-period OP2_1 in the first frame period FP1, and may have a second on-period OP2_2 that is longer than the first on-period OP2_1 in the second frame period FP2. Furthermore, the on-period of the second global signal GS2 may gradually increase from the third frame period to the Nth frame period FPN. In this case, since the on-periods OP1_1, OP1_2, ..., OP1_N of the first global signal GS1 gradually decrease over the multiple frame periods FP1, FP2, ..., FPN, the time period during which the first light-emitting elements EL1 of the multiple pixels PX emit light may gradually decrease over the multiple frame periods FP1, FP2, ..., FPN. Furthermore, since the on-periods OP2_1, OP2_2, ..., OP2_N of the second global signal GS2 gradually increase over the multiple frame periods FP1, FP2, ..., FPN, the time period during which the second light-emitting elements EL2 of the multiple pixels PX emit light may gradually increase over the multiple frame periods FP1, FP2, ..., FPN. In addition, since each of the first global signal GS1 and the second global signal GS2 has an on-level (e.g., a low level) or an off-level (e.g., a high level) in the plurality of frame periods FP1, FP2, ..., FPN, uneven defects due to the threshold voltage distribution of the first transistors T1 and the second transistors T2 of the plurality of pixels PX do not occur in the display device 100 according to the embodiment. That is, the display device 100 according to the embodiment can perform smooth mode switching without uneven defects due to the threshold voltage distribution.

[0093] although Figure 6 An example is shown in which the falling edge of the second global signal GS2 lags behind the rising edge of the first global signal GS1 by a predetermined time in each frame period (for example, the first frame period FP1) so that the on-period OP1_1 of the first global signal GS1 does not overlap with the on-period OP2_1 of the second global signal GS2, but the first global signal GS1 and the second global signal GS2 are not limited to Figure 6 In other embodiments, the first global signal GS1 may have a rising edge, and the second global signal GS2 may have a falling edge at substantially the same time point. In still other embodiments, in each frame period (e.g., the first frame period FP1), the falling edge of the second global signal GS2 may lead the rising edge of the first global signal GS1 by a predetermined time, so that the on-period OP1_1 of the first global signal GS1 partially overlaps with the on-period OP2_1 of the second global signal GS2.

[0094] As described above, in the display device 100 according to the embodiment, at least one pixel PX may include a first light-emitting element EL1 and a second light-emitting element EL2 having different viewing angles, and the panel driver 120 may gradually change the on-period ratio of at least one of the first signal (or first global signal GS1) for supplying the drive current IDR to the first light-emitting element EL1 and the second signal (or second global signal GS2) for supplying the drive current IDR to the second light-emitting element EL2 during a plurality of frame periods FP1, FP2, ..., FPN in response to the mode switching signal SMODE. Therefore, the display device 100 according to the embodiment can perform smooth mode switching without causing uneven defects due to threshold voltage distribution.

[0095] Figure 7 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a public mode to a private mode according to an embodiment.

[0096] Reference Figure 1 and Figure 7 , the panel driver 120 of the display device 100 operating in the public mode may receive a mode switching signal SMODE instructing switching from the public mode to the private mode (S210). In some embodiments, the display device 100 may be a vehicle display device installed in a vehicle, and the panel driver 120 may receive the mode switching signal SMODE instructing switching from the public mode to the private mode when the vehicle changes from a stationary state to a moving state.

[0097] In response to the mode switching signal SMODE indicating switching from the public mode to the private mode, the Figure 6 As shown in , during a plurality of frame periods FP1, FP2, ..., FPN, the panel driver 120 may gradually reduce the on-period ratio of the first global signal GS1 (S230), and may gradually increase the on-period ratio of the second global signal GS2 (S250). That is, as Figure 6 As shown in , the on-periods OP1_1, OP1_2, ..., OP1_N of the first global signal GS1 may gradually decrease over a plurality of frame periods FP1, FP2, ..., FPN, and the on-periods OP2_1, OP2_2, ..., OP2_N of the second global signal GS2 may gradually increase over a plurality of frame periods FP1, FP2, ..., FPN. Therefore, the display device 100 may perform smooth mode switching from the public mode to the private mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX.

[0098] Figure 8is a flowchart illustrating a method of operating a display device in a case where a mode of the display device is switched from a private mode to a public mode according to an embodiment, Figure 9 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from a private mode to a public mode.

[0099] Reference Figure 1 and Figure 8 , the panel driver 120 of the display device 100 operating in the private mode may receive a mode switching signal SMODE instructing switching from the private mode to the public mode (S310). In some embodiments, the display device 100 may be a vehicle display device installed in a vehicle, and the panel driver 120 may receive the mode switching signal SMODE instructing switching from the private mode to the public mode when the vehicle changes from a moving state to a stationary state.

[0100] In response to the mode switching signal SMODE indicating switching from the private mode to the public mode, the Figure 9 As shown in , during a plurality of frame periods FP1, FP2, ..., FPN, the panel driver 120 may gradually reduce the on-period ratio of the second global signal GS2 (S330), and may gradually increase the on-period ratio of the first global signal GS1 (S350). That is, as Figure 9 As shown in FIG, the on-periods OP2_1, OP2_2, ..., OP2_N of the second global signal GS2 may gradually decrease over a plurality of frame periods FP1, FP2, ..., FPN, and the on-periods OP1_1, OP1_2, ..., OP1_N of the first global signal GS1 may gradually increase over a plurality of frame periods FP1, FP2, ..., FPN. Therefore, the display device 100 may perform smooth mode switching from the private mode to the public mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX.

[0101] Figure 10 is a flowchart illustrating a method of operating a display device in a case where a mode of the display device is switched from a public mode to a private mode according to an embodiment, Figure 11 is a timing diagram showing a first global signal and a second global signal in a case where the mode of the display device is switched from the common mode to the full-off mode, Figure 12 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from the all-off mode to the private mode.

[0102] Reference Figure 1 and Figure 10, the panel driver 120 of the display device 100 operating in the public mode may receive a mode switching signal SMODE instructing switching from the public mode to the full-off mode (S410). In some embodiments, the display device 100 may be a vehicle display device installed in a vehicle, and the panel driver 120 may receive the mode switching signal SMODE instructing switching from the public mode to the full-off mode when the vehicle changes from a stationary state to a moving state or when the engine of the vehicle is turned off.

[0103] In response to the mode switching signal SMODE indicating switching from the common mode to the full-off mode, the Figure 11 As shown in , the panel driver 120 can gradually reduce the on-period ratio of the first global signal GS1 during the plurality of first frame periods FP1_1, FP1_2, ..., FP1_N (S430). That is, as Figure 11 As shown in , the on-periods OP1_1, OP1_2, ..., OP1_N of the first global signal GS1 may gradually decrease over a plurality of first frame periods FP1_1, FP1_2, ..., FP1_N. Therefore, the brightness of images viewed by a first user USER1 located in front of the display device 100 and a second user USER2 located at the side of the display device 100 may gradually decrease. This operation may be referred to as a "fade-out operation."

[0104] In some embodiments, when the engine of the vehicle is turned off, the panel driver 120 may perform a fade-out operation and the display device 100 may be powered off.

[0105] In other embodiments, the display device 100 may operate in the full-off mode until receiving the next mode switching signal SMODE (S450). In the full-off mode, the display device 100 may not display an image. In addition, the panel driver 120 of the display device 100 operating in the full-off mode may receive a mode switching signal SMODE (S470) indicating switching from the full-off mode to the private mode. In response to the mode switching signal SMODE indicating switching from the full-off mode to the private mode, as shown in FIG. Figure 12 As shown in , the panel driver 120 may gradually increase the on-period ratio of the second global signal GS2 during a plurality of second frame periods FP2_1, FP2_2, ..., FP2_N (S490). That is, as Figure 12As shown in , the on-periods OP2_1, OP2_2, ..., OP2_N of the second global signal GS2 may gradually increase over the plurality of second frame periods FP2_1, FP2_2, ..., FP2_N. Consequently, the brightness of an image viewed by a first user USER1 located in front of the display device 100 may gradually increase. This operation may be referred to as a "fade-in operation." Consequently, the display device 100 may perform smooth mode switching from a public mode to a fully off mode and / or from a fully off mode to a private mode without causing unevenness defects due to the threshold voltage distribution of the plurality of pixels PX.

[0106] Figure 13 is a flowchart illustrating a method of operating a display device in a case where a mode of the display device is switched from a private mode to a public mode according to an embodiment, Figure 14 is a timing diagram showing a first global signal and a second global signal in a case where the mode of the display device is switched from a privacy mode to a full-off mode, Figure 15 is a timing diagram illustrating a first global signal and a second global signal in a case where the mode of the display device is switched from the all-off mode to the common mode.

[0107] Reference Figure 1 and Figure 13 , the panel driver 120 of the display device 100 operating in the privacy mode may receive a mode switching signal SMODE instructing switching from the privacy mode to the fully off mode (S510). In some embodiments, the display device 100 may be a vehicle display device installed in a vehicle, and the panel driver 120 may receive the mode switching signal SMODE instructing switching from the privacy mode to the fully off mode when the vehicle changes from a moving state to a stationary state.

[0108] In response to the mode switching signal SMODE indicating switching from the privacy mode to the full-off mode, the Figure 14 As shown in , the panel driver 120 can gradually reduce the on-period ratio of the second global signal GS2 during the plurality of first frame periods FP1_1, FP1_2, ..., FP1_N (S530). That is, as Figure 14 As shown in , the on-periods OP2_1, OP2_2, ..., OP2_N of the second global signal GS2 may gradually decrease over a plurality of first frame periods FP1_1, FP1_2, ..., FP1_N. Therefore, the brightness of an image viewed by a first user USER1 located in front of the display device 100 may gradually decrease, and this operation may be referred to as a "fading operation."

[0109] The display device 100 may operate in the full-off mode until receiving the next mode switching signal SMODE (S550). In the full-off mode, the display device 100 may not display an image. In addition, the panel driver 120 of the display device 100 operating in the full-off mode may receive a mode switching signal SMODE (S570) indicating switching from the full-off mode to the public mode. In response to the mode switching signal SMODE indicating switching from the full-off mode to the public mode, as shown in FIG. Figure 15 As shown in , the panel driver 120 may gradually increase the on-period ratio of the first global signal GS1 during a plurality of second frame periods FP2_1, FP2_2, ..., FP2_N (S590). That is, as Figure 15 As shown in , the on-periods OP1_1, OP1_2, ..., OP1_N of the first global signal GS1 can gradually increase over the plurality of second frame periods FP2_1, FP2_2, ..., FP2_N. Therefore, the brightness of the image viewed by the first user USER1 located in front of the display device 100 and the second user USER2 located to the side of the display device 100 can gradually increase, and this operation can be referred to as a "fading-in operation." Therefore, the display device 100 can perform smooth mode switching from the private mode to the fully off mode and / or from the fully off mode to the public mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX.

[0110] Figure 16 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a public mode to a private mode according to an embodiment.

[0111] Reference Figure 1 and Figure 16 The panel driver 120 of the display device 100 operating in the public mode may receive a mode switching signal SMODE (S610) indicating a switch from the public mode to the private mode. In response to the mode switching signal SMODE indicating a switch from the public mode to the private mode, the panel driver 120 may perform a fade-out operation (S630) to gradually reduce the on-period ratio of the first global signal GS1 over a plurality of first frame periods. As a result, the mode of the display device 100 may gradually change from the public mode to the fully off mode.

[0112] The display device 100 may operate in the full-off mode for a predetermined time (S650), and after the predetermined time, the panel driver 120 may perform a fade-in operation to gradually increase the on-period ratio of the second global signal GS2 over a plurality of second frame periods (S670). Thus, the display device 100 may perform smooth mode switching from the public mode to the full-off mode and / or from the full-off mode to the private mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX.

[0113] Figure 17 is a flowchart illustrating a method of operating a display apparatus if a mode of the display apparatus is switched from a private mode to a public mode according to an embodiment.

[0114] Reference Figure 1 and Figure 17 The panel driver 120 of the display device 100 operating in the private mode may receive a mode switching signal SMODE (S710) indicating a switch from the private mode to the public mode. In response to the mode switching signal SMODE indicating a switch from the private mode to the public mode, the panel driver 120 may perform a fade-out operation (S730) to gradually reduce the on-period ratio of the second global signal GS2 over a plurality of first frame periods. Thus, the mode of the display device 100 may gradually change from the private mode to the fully off mode.

[0115] The display device 100 may operate in the full-off mode for a predetermined time (S750), and after the predetermined time, the panel driver 120 may perform a fade-in operation to gradually increase the on-period ratio of the first global signal GS1 over a plurality of second frame periods (S770). Thus, the display device 100 may perform smooth mode switching from the private mode to the full-off mode and / or from the full-off mode to the public mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX.

[0116] Figure 18 is a block diagram showing a display device according to an embodiment, Figure 19 is a diagram illustrating at least one pixel included in a display device according to an embodiment, Figure 20 is a circuit diagram illustrating an example of at least one pixel included in a display device according to an embodiment, Figure 21 is a circuit diagram illustrating another example of at least one pixel included in a display device according to an embodiment, Figure 22 is a timing diagram showing a first transmission signal and a second transmission signal in a case where a mode of a display device is switched from a public mode to a private mode according to an embodiment, Figure 23is a timing diagram illustrating a first transmission signal and a second transmission signal in a case where a mode of a display device is switched from a private mode to a public mode according to an embodiment.

[0117] Reference Figure 18 , the display device 800 according to the embodiment may include a display panel 810 and a panel driver 820. The panel driver 820 may include a data driver 830, a scan driver 840, a first emission driver 850 that sequentially provides a first emission signal EM1 to a plurality of pixels PX' on a row basis, a second emission driver 855 that sequentially provides a second emission signal EM2 to a plurality of pixels PX' on a row basis, and a controller 860. In addition to the first emission driver 850 and the second emission driver 855 (instead of Figure 1 , or together with the emission driver 150 shown in FIG. 1 ), the controller 860 may not provide a plurality of pixels PX′. Figure 1 In addition to the first global signal GS1 and the second global signal GS2 shown in FIG, the first emission driver 850 and the second emission driver 855 may provide the first emission signal EM1 and the second emission signal EM2 to the plurality of pixels PX′. Figure 18 The display device 800 may have Figure 1 The display device 100 has a similar configuration and similar operation.

[0118] like Figure 19 As shown in FIG, at least one pixel PX′ of the display panel 810 may include a first light emitting element EL1, a second light emitting element EL2, a pixel circuit PC′, a first transistor T1′, and a second transistor T2′.

[0119] In some embodiments, as Figure 20 As shown in FIG, the pixel PXa' may include a first light emitting element EL1, a second light emitting element EL2, a first transistor T1', a second transistor T2' and a pixel circuit PCa', and the pixel circuit PCa' may include a third transistor T3a, a fourth transistor T4a, a first capacitor C1a, a second capacitor C2a, a fifth transistor T5a, a sixth transistor T6a, a seventh transistor T7a, a ninth transistor T9a and a tenth transistor T10a. In addition, the pixel circuit PCa' may not include Figure 3 In addition to the eighth transistor T8a shown in FIG, Figure 20 The pixel circuit PCa' shown in FIG can have Figure 3 The pixel circuit PCa shown in FIG. 1 has a similar configuration and similar operation.

[0120] In other embodiments, Figure 21As shown in FIG, the pixel PXb' may include a first light emitting element EL1, a second light emitting element EL2, a first transistor T1', a second transistor T2' and a pixel circuit PCb', and the pixel circuit PCb' may include a third transistor T3b, a fourth transistor T4b, a fifth transistor T5b, a first capacitor C1b, a sixth transistor T6b, a seventh transistor T7b, a ninth transistor T9b and a tenth transistor T10b. In addition, the pixel circuit PCb' may not include Figure 4 In addition to the eighth transistor T8b shown in FIG, Figure 21 The pixel circuit PCb' shown in FIG can have Figure 4 The pixel circuit PCb shown in FIG. 1 has a similar configuration and similar operation.

[0121] The first transistor T1' can provide a drive current IDR to the first light emitting element EL1 in response to a first signal, and the second transistor T2' can provide a drive current IDR to the second light emitting element EL2 in response to a second signal. In some embodiments, the first signal can be a first emission signal EM1 applied to a plurality of pixels PX' sequentially on a row basis, and the second signal can be a second emission signal EM2 applied to the plurality of pixels PX' sequentially on a row basis.

[0122] In some embodiments, the pixel PX' may be Figure 20 In the pixel PXa' shown in , the first transistor T1' may include a gate connected to the first emission signal line transmitting the first emission signal EM1, a first terminal connected to the second terminal of the third transistor T3a, and a second terminal connected to the first light-emitting element EL1, and the second transistor T2' may include a gate connected to the second emission signal line transmitting the second emission signal EM2, a first terminal connected to the second terminal of the third transistor T3a, and a second terminal connected to the second light-emitting element EL2.

[0123] In other embodiments, the pixel PX' may be Figure 21 In the pixel PXb' shown in , the first transistor T1' may include a gate connected to the first emission signal line, a first terminal connected to the second terminal of the third transistor T3b, and a second terminal connected to the first light-emitting element EL1, and the second transistor T2' may include a gate connected to the second emission signal line, a first terminal connected to the second terminal of the third transistor T3b, and a second terminal connected to the second light-emitting element EL2.

[0124] The first emission driver 850 may generate a first emission signal EM1 based on a first emission control signal EMCTRL1 received from the controller 860, and may sequentially provide the first emission signal EM1 to a plurality of pixels PX' on a row basis. Furthermore, the second emission driver 855 may generate a second emission signal EM2 based on a second emission control signal EMCTRL2 received from the controller 860, and may sequentially provide the second emission signal EM2 to a plurality of pixels PX' on a row basis. In some embodiments, the first emission control signal EMCTRL1 may include, but is not limited to, a first emission start signal EM_FLM1 and a first emission clock signal, and the second emission control signal EMCTRL2 may include, but is not limited to, a second emission start signal EM_FLM2 and a second emission clock signal. In some embodiments, the first emission driver 850 and the second emission driver 855 may be integrated or formed in the display panel 810. For example, the first emission driver 850 may be formed in the left peripheral region of the display panel 810, and the second emission driver 855 may be formed in the right peripheral region of the display panel 810, but are not limited thereto. In other embodiments, the first transmit driver 850 and the second transmit driver 855 may be implemented as integrated circuits.

[0125] In the display device 800 according to an embodiment, in response to a mode switching signal SMODE indicating switching from a first mode (e.g., one of the public mode, the private mode, and the all-off mode) to a second mode (e.g., the other of the public mode, the private mode, and the all-off mode), the panel driver 820 may gradually change a turn-on period ratio of at least one of the first emission signal EM1 and the second emission signal EM2 applied to each pixel PX′ during a plurality of frame periods.

[0126] For example, when the mode switching signal SMODE indicates switching from the public mode to the private mode, Figure 22 As shown in , during a plurality of frame periods FP1, FP2, ..., FPN, the panel driver 820 may gradually reduce the on-period ratio of the first emission signal EM1 applied to each pixel PX', and may gradually increase the on-period ratio of the second emission signal EM2 applied to each pixel PX'. In some embodiments, the on-period ratio of the first emission signal EM1 may be adjusted by adjusting the on-period ratio of the first emission start signal EM_FLM1 provided to the first emission driver 850, and the on-period ratio of the second emission signal EM2 may be adjusted by adjusting the on-period ratio of the second emission start signal EM_FLM2 provided to the second emission driver 855. That is, as Figure 22As shown in FIG, the on-periods OP1_1, OP1_2, ..., OP1_N of the first emission signal EM1 may gradually decrease over a plurality of frame periods FP1, FP2, ..., FPN, and the on-periods OP2_1, OP2_2, ..., OP2_N of the second emission signal EM2 may gradually increase over a plurality of frame periods FP1, FP2, ..., FPN. Therefore, the display device 800 can perform smooth mode switching from the public mode to the private mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX'.

[0127] In another example, when the mode switching signal SMODE indicates switching from the private mode to the public mode, Figure 23 As shown in , during a plurality of frame periods FP1, FP2, ..., FPN, the panel driver 820 may gradually reduce the on-period ratio of the second emission signal EM2 applied to each pixel PX', and may gradually increase the on-period ratio of the first emission signal EM1 applied to each pixel PX'. That is, as Figure 23 As shown in FIG, the on-periods OP2_1, OP2_2, ..., OP2_N of the second emission signal EM2 may gradually decrease over a plurality of frame periods FP1, FP2, ..., FPN, and the on-periods OP1_1, OP1_2, ..., OP1_N of the first emission signal EM1 may gradually increase over a plurality of frame periods FP1, FP2, ..., FPN. Therefore, the display device 800 may perform smooth mode switching from the private mode to the public mode without causing uneven defects due to the threshold voltage distribution of the plurality of pixels PX'.

[0128] As described above, in the display device 800 according to the embodiment, at least one pixel PX' may include a first light-emitting element EL1 and a second light-emitting element EL2 having different viewing angles, and the panel driver 820 may gradually change the on-period ratio of at least one of the first signal (or first emission signal EM1) for supplying the drive current IDR to the first light-emitting element EL1 and the second signal (or second emission signal EM2) for supplying the drive current IDR to the second light-emitting element EL2 during a plurality of frame periods FP1, FP2, ..., FPN in response to the mode switching signal SMODE. Therefore, the display device 100 according to the embodiment can perform smooth mode switching without causing unevenness defects due to threshold voltage distribution.

[0129] Figure 24 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0130] Reference Figure 24, the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0131] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. Processor 1110 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, processor 1110 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0132] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0133] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, or the like, and / or an output device such as a printer, a speaker, or the like. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0134] In the display device 1160, at least one pixel may include a first light-emitting element and a second light-emitting element having different viewing angles, and the on-period ratio of at least one of a first signal for supplying a drive current to the first light-emitting element and a second signal for supplying a drive current to the second light-emitting element may be gradually changed over a plurality of frame periods in response to a mode switching signal instructing switching from a first mode to a second mode. Therefore, the display device 1160 according to an embodiment can perform smooth mode switching.

[0135] According to an embodiment, the electronic device 1100 may be any electronic device including a display device 1160, such as a digital TV, a 3D TV, a personal computer (PC), a home appliance, a laptop computer, a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0136] The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: a display panel comprising a plurality of pixels; as well as a panel driver configured to drive the display panel, Wherein, at least one pixel among the plurality of pixels comprises: a first light-emitting element having a first viewing angle; a second light-emitting element having a second viewing angle different from the first viewing angle; a pixel circuit configured to generate a drive current; a first transistor configured to supply the driving current to the first light emitting element in response to a first signal; and a second transistor configured to supply the driving current to the second light emitting element in response to a second signal, and Wherein, in response to a mode switching signal, the panel driver gradually changes an on-period ratio of at least one of the first signal and the second signal during a plurality of frame periods.

2. The display device according to claim 1, wherein The first viewing angle is a wide viewing angle, and The second viewing angle is narrower than the first viewing angle.

3. The display device according to claim 1, wherein The first light emitting element is a common light emitting element configured to provide light to both a first user located in front of the display device and a second user located to the side of the display device, and The second light emitting element is a privacy light emitting element configured to provide light to the first user but not to provide light to the second user.

4. The display device according to claim 1, wherein The display device is installed in a vehicle, and Wherein, when the vehicle changes from a stationary state to a moving state, the panel driver receives the mode switching signal indicating switching from a public mode to a private mode, wherein in the public mode, the image displayed by the display device is visible to both a first user located in front of the display device and a second user located to the side of the display device, while in the private mode, the image displayed by the display device is visible to the first user but not to the second user.

5. The display device according to claim 4, wherein When the vehicle changes from the moving state to the stationary state, the panel driver receives the mode switching signal instructing switching from the private mode to the public mode. The display device according to claim 1 , wherein: When the mode switching signal indicates switching from the public mode to the private mode, the panel driver gradually reduces the on-time ratio of the first signal during a plurality of first frame periods, and gradually increases the on-time ratio of the second signal during the plurality of first frame periods, and When the mode switching signal indicates switching from the private mode to the public mode, the panel driver gradually reduces the on-time ratio of the second signal during multiple second frame periods, and gradually increases the on-time ratio of the first signal during the multiple second frame periods.

7. The display device according to claim 1, wherein When the mode switching signal indicates switching from the common mode to the full-off mode, the panel driver gradually reduces the on-period ratio of the first signal during a plurality of first frame periods, and When the mode switching signal indicates switching from the full-off mode to the privacy mode, the panel driver gradually increases the on-period ratio of the second signal during a plurality of second frame periods.

8. The display device according to claim 1, wherein When the mode switching signal indicates switching from the privacy mode to the full-off mode, the panel driver gradually reduces the on-period ratio of the second signal during a plurality of first frame periods, and When the mode switching signal indicates switching from the full-off mode to the common mode, the panel driver gradually increases the on-period ratio of the first signal during a plurality of second frame periods.

9. The display device according to claim 1, wherein When the mode switching signal indicates switching from the public mode to the private mode, the panel driver performs a first fade-out operation for switching from the public mode to the full-off mode by gradually decreasing the on-period ratio of the first signal during a plurality of first frame periods, and after the first fade-out operation, performs a first fade-in operation for switching from the full-off mode to the private mode by gradually increasing the on-period ratio of the second signal during a plurality of second frame periods, and Wherein, when the mode switching signal indicates switching from the private mode to the public mode, the panel driver performs a second fade-out operation for switching from the private mode to the fully-off mode by gradually reducing the on-time ratio of the second signal during multiple third frame periods, and after the second fade-out operation, performs a second fade-in operation for switching from the fully-off mode to the public mode by gradually increasing the on-time ratio of the first signal during a fourth frame period.

10. The display device according to claim 1, wherein The first signal is a first global signal applied to the plurality of pixels simultaneously, and The second signal is a second global signal applied to the plurality of pixels simultaneously.

11. The display device according to claim 1, wherein The pixel circuit comprises: a third transistor including a gate, a first terminal connected to the first power supply voltage line, and a second terminal; a fourth transistor including a gate connected to the write signal line, a first terminal connected to the data line, and a second terminal; a first capacitor including a first electrode connected to the first power supply voltage line and a second electrode connected to the second terminal of the fourth transistor; a second capacitor comprising a first electrode connected to the second terminal of the fourth transistor and a second electrode connected to the gate of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to an initialization voltage line; a seventh transistor including a gate connected to the compensation signal line, a first terminal connected to the first electrode of the second capacitor, and a second terminal connected to a reference voltage line; an eighth transistor including a gate connected to an emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first transistor and the second transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light emitting element, and a second terminal connected to an anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light emitting element, and a second terminal connected to the anode initialization voltage line, wherein the first transistor includes a gate connected to a first global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the first light emitting element, and The second transistor includes a gate connected to a second global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the second light-emitting element.

12. The display device according to claim 1, wherein The pixel circuit comprises: a third transistor comprising a gate, a first terminal, and a second terminal; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line, and a second terminal connected to the first terminal of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a first capacitor including a first electrode connected to a first power supply voltage line and a second electrode connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to an initialization voltage line; a seventh transistor including a gate connected to an emission signal line, a first terminal connected to the first power supply voltage line, and a second terminal connected to the first terminal of the third transistor; an eighth transistor including a gate connected to the emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first transistor and the second transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light emitting element, and a second terminal connected to an anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light emitting element, and a second terminal connected to the anode initialization voltage line, wherein the first transistor includes a gate connected to a first global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the first light emitting element, and The second transistor includes a gate connected to a second global signal line, a first terminal connected to the second terminal of the eighth transistor, and a second terminal connected to the second light-emitting element.

13. The display device according to claim 1, wherein The first signal is a first emission signal applied to the plurality of pixels sequentially on a row basis, and The second signal is a second emission signal applied to the plurality of pixels sequentially on a row basis.

14. The display device according to claim 1, wherein The pixel circuit comprises: a third transistor including a gate, a first terminal connected to a first power supply voltage line, and a second terminal connected to the first transistor and the second transistor; a fourth transistor including a gate connected to the write signal line, a first terminal connected to the data line, and a second terminal; a first capacitor including a first electrode connected to the first power supply voltage line and a second electrode connected to the second terminal of the fourth transistor; a second capacitor comprising a first electrode connected to the second terminal of the fourth transistor and a second electrode connected to the gate of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to an initialization voltage line; a seventh transistor including a gate connected to the compensation signal line, a first terminal connected to the first electrode of the second capacitor, and a second terminal connected to a reference voltage line; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light emitting element, and a second terminal connected to an anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light emitting element, and a second terminal connected to the anode initialization voltage line, wherein the first transistor includes a gate connected to a first emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first light emitting element, and The second transistor includes a gate connected to a second emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the second light emitting element.

15. The display device according to claim 1, wherein The pixel circuit comprises: a third transistor comprising a gate, a first terminal, and a second terminal; a fourth transistor including a gate connected to a write signal line, a first terminal connected to a data line, and a second terminal connected to the first terminal of the third transistor; a fifth transistor including a gate connected to a compensation signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the gate of the third transistor; a first capacitor including a first electrode connected to a first power supply voltage line and a second electrode connected to the gate of the third transistor; a sixth transistor including a gate connected to an initialization signal line, a first terminal connected to the gate of the third transistor, and a second terminal connected to an initialization voltage line; a seventh transistor including a gate connected to an emission signal line, a first terminal connected to the first power supply voltage line, and a second terminal connected to the first terminal of the third transistor; a ninth transistor including a gate connected to a bypass signal line, a first terminal connected to the first light emitting element, and a second terminal connected to an anode initialization voltage line; and a tenth transistor including a gate connected to the bypass signal line, a first terminal connected to the second light emitting element, and a second terminal connected to the anode initialization voltage line, wherein the first transistor includes a gate connected to a first emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the first light emitting element, and The second transistor includes a gate connected to a second emission signal line, a first terminal connected to the second terminal of the third transistor, and a second terminal connected to the second light emitting element.

16. A method for operating a display device, wherein at least one pixel includes a first light-emitting element and a second light-emitting element having different viewing angles from each other, the method comprising the following steps: Receive mode switching signal; as well as An on-period ratio of at least one of a first signal for supplying a drive current to the first light emitting element and a second signal for supplying a drive current to the second light emitting element is gradually changed during a plurality of frame periods.

17. The method according to claim 16, wherein: The step of receiving the mode switching signal includes: receiving a first mode switching signal indicating switching from the public mode to the private mode, and Among them, the step of gradually changing the on-time ratio of at least one of the first signal and the second signal includes: gradually reducing the on-time ratio of the first signal during multiple first frame periods in response to the first mode switching signal; and gradually increasing the on-time ratio of the second signal during the multiple first frame periods in response to the first mode switching signal.

18. The method according to claim 17, wherein: The step of receiving the mode switching signal further includes: receiving a second mode switching signal indicating switching from the private mode to the public mode, and Among them, the step of gradually changing the on-time ratio of at least one of the first signal and the second signal also includes: gradually reducing the on-time ratio of the second signal during multiple second frame periods in response to the second mode switching signal; and gradually increasing the on-time ratio of the first signal during the multiple second frame periods in response to the second mode switching signal.

19. The method according to claim 16, wherein: The step of receiving the mode switching signal includes: receiving a first mode switching signal indicating switching from the public mode to the fully closed mode; and receiving a second mode switching signal indicating switching from the fully closed mode to the private mode, and Among them, the step of gradually changing the on-time ratio of at least one of the first signal and the second signal includes: gradually reducing the on-time ratio of the first signal during multiple first frame periods in response to the first mode switching signal; and gradually increasing the on-time ratio of the second signal during multiple second frame periods in response to the second mode switching signal.

20. The method according to claim 19, wherein The step of receiving the mode switching signal further includes: receiving a third mode switching signal indicating switching from the private mode to the fully closed mode; and receiving a fourth mode switching signal indicating switching from the fully closed mode to the public mode, and Among them, the step of gradually changing the on-time ratio of at least one of the first signal and the second signal also includes: gradually reducing the on-time ratio of the second signal during multiple third frame periods in response to the third mode switching signal; and gradually increasing the on-time ratio of the first signal during multiple fourth frame periods in response to the fourth mode switching signal.

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