Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a plurality of pixel units arranged in an array; each pixel unit comprises a light-emitting device and a pixel driving circuit; the pixel driving circuit comprises a driving transistor and a storage capacitor. The driving transistor and the light-emitting device are connected in series between a first power line and a second power line; a control electrode of the driving transistor and one end of the storage capacitor are connected to a first node; the other end of the storage capacitor is connected to a third power line; the potential of a first power signal transmitted by the first power line is greater than that of a second power signal transmitted by the second power line; and a third power signal transmitted by the third power line is adjusted according to the display brightness of the display panel within the display time of the display panel, so that the potential of the first node is kept stable within the display time. Therefore, the problems of splash screen and color cast caused by long-time display of the display panel are solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of electroluminescent displays, dynamic refresh rate adjustment technologies (such as 1 Hz to 120 Hz adaptive) and optimized electroluminescent organic materials have been gradually adopted to reduce power consumption in pursuit of ultra-long display times. However, a significant reduction in refresh rate (especially at ultra-low refresh rates of 1 Hz) can cause flickering and color shift in the display panel due to shifts in the threshold voltage of the drive transistors and leakage current between pixels. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, which dynamically adjust the voltage of the control electrode of the driving transistor of the pixel unit to maintain the stability of the voltage controlled by the driving transistor during the display time of the display panel, thereby solving the flickering and color shift problems when the display surface is displayed for a long time.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a plurality of pixel units arranged in an array; the pixel units include a light-emitting device and a pixel driving circuit; the pixel driving circuit includes: a driving transistor and a storage capacitor; the driving transistor and the light-emitting device are connected in series between a first power line and a second power line; the control electrode of the driving transistor and one end of the storage capacitor are connected to a first node; the other end of the storage capacitor is connected to a third power line; wherein the potential of the first power signal transmitted by the first power line is greater than the potential of the second power signal transmitted by the second power line; the third power signal transmitted by the third power line is adjusted according to the display brightness of the display panel during the display time of the display panel, so that the potential of the first node remains stable during the display time.

[0005] In the second aspect, an embodiment of the present application also provides a display device, comprising a display panel and a power management chip as described in any one of the above items, wherein the power management chip is connected to the other end of the storage capacitor in the display panel via the third power line, and is used to provide the third power signal to the storage capacitor via the third power line; the third power signal is adjusted according to the display brightness of the display panel during the display time of the display panel, so that the potential of the first node remains stable during the display time.

[0006] The display panel and display device provided by the embodiments of the present application connect one end of the storage capacitor within the pixel unit to the control electrode of the drive transistor, and the other end to a third power supply signal that is dynamically adjustable according to the display brightness of the display panel. This maintains the potential of the control electrode of the drive transistor stable during the display time of the display panel, thereby resolving the problem of brightness flicker and color shift during the display time of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0008] Figure 1 This is a structural block diagram of the display panel provided in an embodiment of the present application.

[0009] Figure 2 Schematic diagram of the circuit structure of the pixel unit provided in the embodiment of the present application Figure 1 .

[0010] Figure 3 A schematic diagram of a driving timing provided in an embodiment of the present application.

[0011] Figure 4 Schematic diagram of the circuit structure of the pixel unit provided in the embodiment of the present application Figure 2 .

[0012] Figure 5 This is a structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0014] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. Mention of "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0015] As mentioned above, with the development of electroluminescent displays, dynamic refresh rate adjustment technology has gradually been applied to ultra-long display scenarios. However, when the refresh rate is reduced, especially at ultra-low refresh rates, the threshold voltage shift of the driver transistor and the leakage current between pixel cells can cause flickering and color shift in the display, seriously affecting display quality and user experience.

[0016] In order to solve the above problems, an embodiment of the present application provides a display panel, in which the potential of the power signal connected to one end of the storage capacitor in the pixel unit is dynamically adjusted according to the display brightness, thereby compensating the control electrode potential of the driving transistor to maintain the stability of the control electrode potential of the driving transistor, which can be used to offset the negative effects of leakage current and threshold voltage offset.

[0017] The display panel and display device provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0018] The display panel provided in the embodiment of the present application may be, for example, an organic light emitting diode (OLED) display panel. Of course, the display panel may also be a Mini-LED display panel or a Micro-LED display panel. Figure 1 As shown, the display panel 100 may include a plurality of pixel units 101 arranged in an array, a plurality of gate lines G1 to Gn, and a plurality of data lines B1 to Bm. The pixel units 101 are arranged in an array to form a pixel array, and are arranged in a first direction (exemplarily as Figure 1 The pixel units 101 arranged in the horizontal direction (shown in FIG. 1 ) can be defined as pixel rows, and the pixel units 101 arranged in the second direction (exemplarily as FIG. 1 ) can be defined as pixel rows. Figure 1 The pixel units 101 arranged in the vertical direction (as shown) can be defined as pixel columns. The pixel units 101 may include red (R) pixel units, green (G) pixel units, and blue (B) pixel units. An exemplary arrangement of the red pixel units, the green pixel units, and the blue pixel units may be: the pixel units 101 in the same pixel row have the same color, the pixel units in the same pixel column have different colors, and the pixel units of different colors are alternately arranged along the second direction. Another exemplary arrangement of the red pixel units, the green pixel units, and the blue pixel units may be: the pixel units 101 in the same pixel column have the same color, the pixel units in the same pixel row have different colors, and the pixel units of different colors are alternately arranged along the first direction.

[0019] like Figure 1As shown, the plurality of gate lines may exemplarily include a gate line G1, a gate line G2, ..., a gate line Gn arranged along the second direction, and each gate line is connected to a pixel unit in a pixel row for transmitting a scan signal. The plurality of data lines may exemplarily include a data line D1, a data line D2, ..., a data line Dm arranged along the first direction, and each data line is connected to the pixel unit in at least one pixel column for transmitting a data signal.

[0020] In some embodiments, as Figure 2 As shown, the pixel unit 101 may include a light-emitting device 1011 and a pixel driving circuit 1012. The light-emitting devices of pixel units 101 of different colors emit light of different colors. For example, the light-emitting device of a red pixel unit can emit red light, the light-emitting device of a green pixel unit can emit green light, and the light-emitting device of a blue pixel unit can emit blue light. The pixel driving circuit 1012 may include a driving transistor T1 and a storage capacitor Cst; the driving transistor T1 and the light-emitting device 1011 are connected in series between a first power line and a second power line; the control electrode of the driving transistor T1 and one end of the storage capacitor Cst are connected to a first node N1; the other end of the storage capacitor Cst is connected to a third power line; wherein, in combination with the following Figure 4 and Figure 5 As shown, the first power signal VDD transmitted by the first power line and the second power signal VSS transmitted by the second power line are both DC signals, and the potential of the first power signal VDD is greater than the potential of the second power signal VSS. The third power signal Data_scan transmitted by the third power line is also a DC signal, and the voltage value of the third power signal Data_scan is adjusted according to the display brightness of the display panel during the display time of the display panel to keep the potential of the first node N1 stable during the display time.

[0021] It should be noted that the third power line may refer to a power supply line connected to the non-node end of the storage capacitor Cst (the end not connected to the first node). The third power signal may be independently provided by a voltage source different from the first power line and the second power line, and the voltage value of the third power signal may be adjusted according to the display brightness during the display time of the display panel. These voltage sources may be different voltage sources within the power management chip. Specifically, the driving transistor T1 and the light-emitting device 1011 are connected in series between the first power line and the second power line to form a light-emitting circuit. The storage capacitor Cst transmits a third power signal with adjustable (amplitude or) potential through the third power line. In actual application, when the display brightness of the display panel changes, the voltage value of the third power signal is adjusted accordingly, and the potential of the first node is changed through the coupling effect of the storage capacitor Cst. For example, when the display brightness decreases, if the driving transistor is an N-type device, the voltage value of the third power signal is appropriately increased to compensate for the potential drop of the first node caused by leakage current and / or threshold voltage shift. In this way, the threshold voltage drift and leakage current effects are continuously offset during the display time of the display panel, and the gate potential of the driving transistor is maintained stable, thereby solving the flickering and color shift phenomena of the display screen when the display panel is displayed for a long time at a low refresh rate, and optimizing the display quality and user experience.

[0022] In some embodiments, the driving transistor may be an N-type thin-film driving transistor, and as time passes during the display time, the voltage value of the third power signal is negatively correlated with the display brightness of the display panel; or the driving transistor may be a P-type thin-film driving transistor, and as time passes during the display time, the voltage value of the third power signal is positively correlated with the display brightness of the display panel. The N-type thin-film driving transistor may be a thin-film transistor made of an N-type semiconductor material, whose conductive channel is primarily carried by electrons. Specifically, it may be implemented using low-temperature polysilicon or an oxide semiconductor material, such as indium gallium zinc oxide. In this case, as time passes during the display time, the voltage value of the third power signal is negatively correlated with the display brightness of the display panel, which may mean that as the display brightness increases, the voltage value of the third power signal decreases, and as the display brightness decreases, the voltage value of the third power signal increases. This can be achieved by a power management chip adjusting the voltage output in real time based on brightness data. Specifically, when the driving transistor is N-type, its threshold voltage may drift negatively during long-term driving, causing the potential of the first node to increase, thereby increasing the drive current and causing an abnormal increase in display brightness. At this time, by reducing the voltage value of the third power supply signal, according to the capacitive coupling effect, the potential of the first node is pulled down, thereby offsetting the abnormal rise in the potential of the first node and maintaining the stability of the driving current. For example, when the display brightness is 100 nits, the potential of the third power supply signal can be set to 3 volts; when the display brightness is increased to 200 nits, the potential can be adjusted to 2.5 volts. In the scenario described in the embodiment of the present application, when the driving transistor is N-type, at a low refresh rate, when the display panel is displayed for a long time, due to the presence of leakage current, the potential of the first node N1 drops abnormally, causing the display brightness of the display panel to decay. At this time, the voltage value of the third power supply signal needs to be increased, so that according to the capacitive coupling effect, the potential of the first node is pulled up, thereby offsetting the abnormal drop in the potential of the first node and maintaining the stability of the driving current.

[0023] The so-called P-type thin film drive transistor may refer to a thin film transistor made of P-type semiconductor material, whose conductive channel is composed of holes as the main carriers, and may be specifically implemented using amorphous silicon material. At this time, the voltage value of the third power supply signal and the display brightness change with time during the display time, which may mean that when the display brightness increases, the voltage value of the third power supply signal increases synchronously; when the display brightness decreases, the voltage value of the third power supply signal decreases. Specifically, when the drive transistor is P-type, its threshold voltage may drift positively during long-term driving, causing the potential of the first node to drop, causing an abnormal increase in display brightness. At this time, by increasing the voltage value of the third power supply signal, according to the capacitive coupling effect, the potential of the first node is pulled up, compensating for the abnormal drop in the potential of the first node. For example, under the same brightness change scenario, the potential of the third power supply signal can be increased from 3 volts to 3.5 volts. Similarly, in the scenario described in the embodiment of the present application, when the driving transistor is P-type, at a low refresh rate, when the display panel is displayed for a long time, the abnormal rise in the potential of the first node causes the display brightness of the display panel to decay. At this time, the voltage value of the third power supply signal needs to be lowered so that according to the coupling effect, the potential of the first node is pulled up, thereby offsetting the abnormal rise in the potential of the first node and maintaining the stability of the driving current.

[0024] In some display scenarios, within the display time, the display panel may include at least one display cycle; each display cycle may include a refresh frame and at least one hold frame; within the refresh frame, the voltage value of the third power supply signal is a preset voltage value; within the at least one hold frame, the voltage value of the third power supply signal increases or decreases based on the preset voltage value according to the display brightness of the display panel in the hold frame.

[0025] Thus, in some display scenarios, the display time may include one or more display cycles. Each display cycle includes a refresh frame (Refresh Frame) and at least one hold frame (Hold Frame). The refresh frame may refer to a frame type that updates the picture in a completely new way. Within a refresh frame, the drive of the pixel unit includes a reset period, a write period, and a compensation period, in which the picture is completely re-updated. The hold frame may refer to a frame type that does not need to update the picture. Within a hold frame, the drive of the pixel unit may include a reset period, and a compensation period, in which the picture updated by the refresh frame is maintained without rewriting the data. For example, as Figure 3As shown in the figure, assuming that the refresh rate of the display panel is 10 Hz, but the drive scanning frequency is 120 Hz, a display cycle can include one refresh frame and 11 hold frames. Based on this example, within a display cycle, only the drive timing of the refresh frame contains a data writing period (data is written), and the drive timing of the remaining 11 hold frames does not contain a data writing period (no data is written).

[0026] On the basis of the above-mentioned display cycle including a refresh frame and at least one hold frame, if the voltage value of the third power signal in the refresh frame is a fixed preset voltage value, the data signal is written to the storage capacitor through the driving transistor and the threshold voltage compensation is completed, so that the potential of the first node forms a stable corresponding relationship with the data signal. After entering the hold frame stage, the third power signal is adjusted in real time based on the preset voltage value according to the current display brightness requirement. Exemplarily, when the driving transistor is an N-type device, when the display brightness is reduced, the potential of the third power signal is increased to pull up the potential of the first node (for example, by increasing the voltage value of the third power signal), suppressing the potential drift caused by leakage current, and maintaining the potential of the first node stable. When the driving transistor is a P-type device, when the display brightness is reduced, the potential of the third power signal is decreased to pull down the potential of the first node (for example, by reducing the voltage value of the third power signal), suppressing the potential drift caused by leakage current, and maintaining the potential of the first node stable.

[0027] In actual application, the display period may include at least one hold frame, and therefore, the adjustment methods of the voltage value of the third power signal may include at least the following methods.

[0028] The first is that all the holding frames in the at least one holding frame use the same voltage value of the third power signal. In other words, the voltage value of the third power signal is adjusted only once, and the potential of the third power is equal in all holding frames. One implementation method may be to calculate a preset adjustment value based on the average value of the display brightness in at least one holding frame of the display time, and according to the type of driving transistor, increase or decrease the preset adjustment value on the basis of the preset voltage value to obtain the adjusted voltage value of the third power signal. For example, as above Figure 3 As shown, at a low refresh rate, in each of the subsequent 11 hold frames, the voltage value of the third power signal is the same.

[0029] The second type is that the display cycle may include two or more holding frames; within the display time, in the holding frame adjacent to the refresh frame, the voltage value of the third power supply signal increases or decreases as time changes according to the preset voltage value according to the display brightness of the display panel in the holding frame adjacent to the refresh frame; in the holding frame non-adjacent to the refresh frame, the voltage value of the third power supply signal in the subsequent holding frame increases or decreases according to the display brightness of the display panel in the subsequent holding frame based on the voltage value of the third power supply signal in the previous holding frame, wherein the changing trend of the voltage value of the third power supply signal in the holding frame adjacent to the refresh frame is consistent with that in the holding frame adjacent to the refresh frame.

[0030] In this way, the third power signal within the two or more hold frames is adjusted, and the basis for the subsequent adjustment is the voltage value of the third power signal within the previous hold frame or refresh frame. For example, in the adjacent hold frame after the refresh frame, the third power signal is initially adjusted based on a preset voltage value. In subsequent non-adjacent hold frames, the third power signal is incrementally adjusted based on the potential of the previous hold frame. Taking an N-type driver transistor as an example, if the voltage value of the third power signal in the previous hold frame has been adjusted to V1, when the current display brightness continues to decrease, the voltage value of the third power signal in the subsequent hold frame can be further adjusted to V1+ΔV. The adjustment direction of adjacent hold frames is constrained to be consistent, for example, an incremental adjustment method is used to prevent node potential oscillations caused by sudden changes in the adjustment direction. This phased adjustment mechanism not only ensures the stability of the potential reference of the initial hold frame, but also continuously compensates for the effects of long-term leakage current through cumulative adjustment. Whether the voltage value of the third power signal increases or decreases or is determined based on the display brightness and the type of driver transistor can be understood based on the previous description and will not be further elaborated here.

[0031] The third type is that the two or more holding frames are divided into multiple frame sequences; each frame sequence includes at least one holding frame; within the display time, as time changes, the voltage value of the third power signal in the latter frame sequence increases or decreases based on the voltage value of the third power signal in the previous frame sequence or the preset voltage value; the voltage value of the third power signal corresponding to each holding frame in each frame sequence is the same.

[0032] Here, the frame sequence may refer to dividing at least one holding frame in a display period into several groups in chronological order. Each group contains at least one holding frame. For example, this may be achieved by grouping the holding frames using a timing controller connected to the display panel, thereby reducing the number of voltage value adjustments of the third power supply signal through grouping to save resources. The voltage value adjustment method of the third power supply signal refers to the voltage of the subsequent frame sequence being increased or decreased based on the voltage of the previous frame sequence or a preset voltage value, and the voltage value of the third power supply signal in the same frame sequence is the same. The voltage value of the third power supply signal in the same frame sequence being the same may refer to the voltage value of the third power supply signal being maintained constant during the holding frames of the same group, which may be achieved specifically by using a latch circuit or a voltage holding circuit to avoid frequent potential adjustments within the same group to save costs.

[0033] For example, in the low refresh rate display stage of the display panel, if there are ten hold frames, they can be divided into three frame sequences, and each frame sequence contains three, three and four hold frames respectively. For each frame sequence, the voltage value of the third power supply signal is increased or decreased based on the potential of the previous frame sequence or the preset voltage value according to the display brightness requirement. For example, when the driving transistor is N-type, when the display brightness gradually decreases, the voltage value of the third power supply signal can be reduced frame by frame; all hold frames in the same frame sequence use the same potential, and there is no need to adjust the potential in a single hold frame. As a result, the potential adjustment frequency is reduced from frame-by-frame adjustment to sequence-by-sequence adjustment, reducing the number of changes in the circuit control signal. At the same time, the potential of the latter frame sequence is adjusted based on the potential of the previous frame sequence to avoid fluctuations in the potential of the first node caused by sudden potential changes, thereby ensuring the potential stability of the control electrode of the driving transistor.

[0034] In summary, the embodiment of the present application can effectively suppress the abnormal fluctuation of the gate potential of the driving transistor under the low refresh rate working state by introducing a third voltage signal with adjustable potential (or voltage), thereby eliminating the display screen flickering and color deviation caused by leakage current and threshold drift, and significantly improving the image stability and color accuracy under the ultra-low refresh rate display state.

[0035] To understand the above solution, the following examples of this application are Figure 3 The pixel unit shown is taken as an example to illustrate the inventive concept of the present application in detail.

[0036] like Figure 4As shown, the pixel unit may include a driving transistor T1, a data writing transistor T2, a first reset transistor T3, a compensation transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, and a storage capacitor Cst. The driving transistor T1 is connected in series between the second node N2 and the third node N3, with the control electrode of the driving transistor T1 connected to the first node N1. The data writing transistor T2 is connected in series between the data line and the second node N2, with the control electrode of the data writing transistor T2 connected to the second scan line, the data line is used to transmit the data signal DATA, and the second scan line transmits the second scan signal PSCAN[n]. The first reset transistor T3 is connected in series between the first reset line and the first node, with the control electrode of the first reset transistor T3 connected to the first scan line, the first reset line is used to transmit the first reset signal VI_Gate, and the first scan line is used to transmit the first scan signal PSCAN[n-1]. The compensation transistor T4 is connected in series between the first node N1 and the third node N3, with the control electrode of the compensation transistor T4 connected to the second scan line. The first emission control transistor T5 is connected in series between the first power line and the second node N2. The control electrode of the first emission control transistor T5 is connected to the emission control line, which is used to transmit the emission control signal EM. The second emission control transistor T6 is connected in series between the anode of the light-emitting device and the third node N3. The control electrode of the second emission control transistor T6 is connected to the emission control line, and the cathode of the light-emitting device is connected to the second power line. The second reset transistor T7 is connected in series between the second reset line and the anode of the light-emitting device. The control electrode of the second reset transistor T7 is connected to the first scan line, which is used to transmit the second reset signal VI_ANO. One end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the third power signal Data_scan via the third power line.

[0037] It should be noted that Figure 4 The driving transistor T1, data writing transistor T2, first reset transistor T3, compensation transistor T4, first light emission control transistor T5, second light emission control transistor T6, and second reset transistor T7 in the pixel unit shown are illustratively all P-type devices, wherein at least the driving transistor T1 is a P-type thin film driving transistor.

[0038] In some embodiments, the first reset transistor T3 and the compensation transistor T4 may be dual-gate transistors. A dual-gate transistor may refer to a transistor having two independent gate structures, which may be implemented using a double-layer polysilicon stacked structure or a split-type gate layout. Specifically, when the display panel is in a low refresh rate operating state, the first reset transistor T3 is in the cut-off state, and a double barrier is formed through the dual-gate structure, which effectively suppresses the leakage current between the first node and the first reset line, thereby avoiding the influence of the reset residual voltage on the compensation accuracy of the threshold voltage of the driving transistor. In the threshold voltage compensation stage, the compensation transistor T4 controls the channel carriers in both directions through the dual-gate structure, eliminates the leakage current drift caused by the uneven electric field distribution of the single-gate structure, and ensures that the data voltage is accurately written to the control electrode of the driving transistor. This dual control mechanism enables the potential of the first node to remain stable during the switching process between the refresh frame and the hold frame, thereby eliminating the screen flickering and color deviation caused by the accumulation of leakage current.

[0039] based on Figure 4 The refresh frame of the pixel unit shown in the aforementioned display cycle may include a reset period, a data write period, and a light-emitting period. Specifically, during the reset period of the refresh frame, the first scan signal PSCAN[n-1] transmitted by the first scan line is at an active level, the first reset transistor T3 is turned on, and transmits the first reset signal VI_Gate transmitted via the first reset line to the first node N1 to reset the first node N1. The second reset transistor T7 is turned on, and transmits the second reset signal VI_ANO transmitted via the second reset line to the anode of the light-emitting device to reset the anode of the light-emitting device. During the data write period of the refresh frame, when the second scan signal PSCAN[n] transmitted by the second scan line is at an active level, the data write transistor T2 is turned on, and the compensation transistor T4 is turned on, transmitting the data signal DATA transmitted by the data line to the second node N2, causing the drive transistor T1 to be turned on, transmitting the data signal DATA to the first node N1, and performing threshold voltage compensation on the drive transistor T1. During the light-emitting period within the refresh frame, the light-emitting control signal EM transmitted by the light-emitting control line is at an effective level, the first light-emitting control transistor T5 is turned on, and the second light-emitting control transistor T6 is turned on, and the driving transistor T1 generates a driving current according to the data signal DATA to drive the light-emitting device to emit light.

[0040] For the holding frame within the display cycle, it includes a reset period and a light-emitting period, wherein only a partial reset is performed during the reset period, for example, only the anode of the light-emitting device is reset. The data writing period is completely skipped and no data is updated. Specifically, when the first scanning signal PSCAN[n-1] transmitted by the first scanning line is at a valid level, the second reset transistor T7 transmits the second reset signal VI_ANO transmitted via the second reset line to the anode of the light-emitting device to reset the anode of the light-emitting device; and during the light-emitting period within the holding frame, the light-emitting control signal EM transmitted by the light-emitting control line is at a valid level, the first light-emitting control transistor T5 is turned on, and the second light-emitting control transistor T6 is turned on, and the driving transistor T1 generates a driving current according to the data signal DATA to drive the light-emitting device to emit light. Here, the first reset transistor T3 and the data writing transistor T2 are both cut off within the holding frame, and the control signals connected to their control electrodes are at an invalid level. Due Figure 4 The transistors shown are all P-type, so the effective level mentioned here can refer to the low level. The ineffective level mentioned here can refer to the high level. Figure 4 Each transistor shown is of N-type, with an active level being a high level and an inactive level being a low level.

[0041] exist Figure 4 In the pixel unit shown, one end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the third power line to receive the third power signal Data_scan. According to the embodiment of the present application, the method for maintaining the stability of the first node N1 can be to dynamically adjust the potential of the third power signal Data_scan according to the display brightness within the hold frame. Based on the coupling effect of the storage capacitor Cst, the potential of the first node N1 is dynamically adjusted to maintain the stability of the first node N1, thereby eliminating the screen flicker and color shift caused by leakage current accumulation. For example, the potential of the third power signal Data_scan can be adjusted based on the display brightness of the current hold frame based on the previous hold frame or refresh frame for each hold frame.

[0042] In some embodiments, the embodiments of the present application also provide a display device comprising any one of the aforementioned display panels and a power management chip, wherein the power management chip is connected to the other end of the storage capacitor in the display panel via the third power line, and is used to provide the third power signal to the storage capacitor via the third power line; the third power signal is adjusted according to the display brightness of the display panel during the display time of the display panel, so that the potential of the first node remains stable during the display time.

[0043] It should be noted that the power management chip is used to provide the required operating voltages for various parts of the display panel, such as the first power signal VDD, the second power signal VSS, and the third power signal Data_scan provided in the embodiments of the present application. During the display time of the display panel, a timing controller connected to the power management chip adjusts the voltage value of the third power signal according to the display brightness of the display panel, and controls the power management chip to output the adjusted third power signal so that the potential of the first node remains stable during the display time. The display panel has been described in detail above and will not be repeated here.

[0044] For example, Figure 5 As shown, the display device 200 may include a display panel, a power management chip, a source driver circuit, a gate driver circuit, a timing controller, a light controller, a substrate, a data line for transmitting a data signal DATA, a scan line for transmitting a scan signal SCAN, a power line for transmitting a first power signal VDD, a second power signal VSS or a third power signal Data_scan (a collective term for the first power line, the second power line, and the third power line), a light control line for transmitting a light control signal EM, an encapsulation layer, a polarizer, a color filter, etc. Among them, the display panel and the power management chip have been described in detail above and will not be repeated here. The substrate may be, for example, a glass substrate, a flexible substrate (for example, a polyimide substrate), etc. Gate driver on array (GOA) technology is a technology that directly integrates a gate driver circuit on a display panel array substrate. In GOA technology, GOA is mainly used for row-by-row scanning drive of multiple rows of pixel units, wherein each level of gate driver unit in the GOA controls a row of pixel units to achieve pixel unit gating. In some embodiments, GOA can adopt unilateral drive or bilateral drive for multiple rows of pixel units, wherein the unilateral drive can be to arrange the gate drive unit only on one side (such as the left or right side), and drive the multiple rows of pixel units by scanning line by line in a cascade manner. The bilateral drive can be to arrange the drive units on both the left and right sides of the multiple rows of pixel units, and drive the multiple rows of pixel units by scanning line by line through the cooperation of both sides. The source drive circuit is used to provide data signals to the pixel units. The timing controller is used to receive external input image data and synchronization signals, and generate the signals required by the gate drive circuit and the source drive circuit. It should be noted that Figure 5 This is an exemplary diagram, and the connection relationship of the components shown is only used to explain the functional logical relationship of the display panel, rather than to limit the actual physical structure. Figure 5For the display device shown, an exemplary implementation process of the solution of the embodiment of the present application can be as follows: the timing controller detects the display brightness of the holding frame, and then calculates the voltage adjustment value based on the display brightness, and obtains the adjusted third power signal based on the type of the driving transistor, the voltage value of the third power signal of the previous holding frame or refresh frame and the calculated voltage adjustment value, and controls the power management chip to output the adjusted third power signal to the corresponding pixel unit to adjust the potential of the first node and maintain the stability of the potential of the first node.

[0045] The above is a detailed introduction to the display panel and display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel units arranged in an array; The pixel unit includes a light emitting device and a pixel driving circuit; The pixel driving circuit includes: a driving transistor and a storage capacitor; the driving transistor and the light-emitting device are connected in series between a first power line and a second power line; the control electrode of the driving transistor and one end of the storage capacitor are connected to a first node; the other end of the storage capacitor is connected to a third power line; wherein the potential of the first power signal transmitted by the first power line is greater than the potential of the second power signal transmitted by the second power line; the third power signal transmitted by the third power line is adjusted according to the display brightness of the display panel during the display time of the display panel, so that the potential of the first node remains stable during the display time.

2. The display panel according to claim 1, wherein: The driving transistor is an N-type thin film driving transistor, and within the display time, the voltage value of the third power signal is negatively correlated with the display brightness of the display panel as time changes; or The driving transistor is a P-type thin film driving transistor. During the display time, as time changes, the voltage value of the third power signal is positively correlated with the display brightness of the display panel.

3. The display panel according to claim 2, wherein: During the display time, the display panel includes at least one display cycle; each display cycle includes a refresh frame and at least one hold frame; within the refresh frame, the voltage value of the third power signal is a preset voltage value; In the at least one holding frame, a voltage value of the third power signal is increased or decreased based on the preset voltage value according to the display brightness of the display panel in the holding frame.

4. The display panel according to claim 3, wherein: The at least one holding frame includes two or more holding frames; within the display time, the voltage value of the third power signal in the holding frame adjacent to the refresh frame increases or decreases with time based on the preset voltage value according to the display brightness of the display panel in the holding frame adjacent to the refresh frame; in the holding frame non-adjacent to the refresh frame, the voltage value of the third power signal in the subsequent holding frame increases or decreases based on the voltage value of the third power signal in the previous holding frame according to the display brightness of the display panel in the subsequent holding frame, wherein the change trend of the voltage value of the third power signal in the holding frame adjacent to the refresh frame is consistent with that in the holding frame adjacent to the refresh frame.

5. The display panel according to claim 4, wherein: The two or more holding frames are divided into multiple frame sequences; each frame sequence includes at least one holding frame; within the display time, as time changes, the voltage value of the third power signal in the latter frame sequence increases or decreases based on the voltage value of the third power signal in the previous frame sequence or the preset voltage value; the voltage value of the third power signal corresponding to each holding frame in each frame sequence is the same.

6. The display panel according to claim 1, wherein: The pixel driving circuit further includes: a first reset transistor, a second reset transistor, a data writing transistor, a compensation transistor, a first light emission control transistor, and a second light emission control transistor; Wherein, the first reset transistor is connected in series between the first reset line and the first node, and the control electrode of the first reset transistor is connected to the first scan line; The second reset transistor is connected in series between the second reset line and the anode of the light emitting device, and the control electrode of the second reset transistor is connected to the first scan line; The data writing transistor is connected in series between the data line and the second node, and the control electrode of the data writing transistor is connected to the second scan line; The compensation transistor is connected in series between the first node and the third node, and the control electrode of the compensation transistor is connected to the second scan line; The first light emitting control transistor is connected in series between the first power line and the second node, and the control electrode of the first light emitting control transistor is connected to the light emitting control line; The second light emitting control transistor is connected in series between the anode of the light emitting device and the third node, and the control electrode of the second light emitting control transistor is connected to the light emitting control line; the cathode of the light emitting device is connected to the second power line.

7. The display panel according to claim 6, wherein: During the display time, the display panel includes at least one display cycle; each display cycle includes a refresh frame and at least one hold frame; during a reset period within the refresh frame, the first scan signal transmitted by the first scan line is at an active level, the first reset transistor is turned on, and transmits the first reset signal transmitted via the first reset line to the first node to reset the first node; the second reset transistor is turned on, and transmits the second reset signal transmitted via the second reset line to the anode of the light-emitting device to reset the anode of the light-emitting device; During a data writing period within the refresh frame, when the second scan signal transmitted by the second scan line is at an effective level, the data writing transistor and the compensation transistor are turned on to transmit the data signal transmitted by the data line to the second node, so that the driving transistor is turned on to transmit the data signal to the first node, and threshold voltage compensation is performed on the driving transistor; During the light-emitting period within the refresh frame, the light-emitting control signal transmitted by the light-emitting control line is at a valid level, the first light-emitting control transistor is turned on and the second light-emitting control transistor is turned on, and the driving transistor generates a driving current according to the data signal to drive the light-emitting device to emit light.

8. The display panel according to claim 7, wherein: During a reset period within the hold frame, when the first scan signal transmitted by the first scan line is at an active level, the second reset transistor transmits a second reset signal transmitted via the second reset line to the anode of the light-emitting device to reset the anode of the light-emitting device; as well as During the light-emitting period within the holding frame, the light-emitting control signal transmitted by the light-emitting control line is at an effective level, the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the driving transistor generates a driving current according to the data signal to drive the light-emitting device to emit light.

9. The display panel according to claim 6, wherein: The first reset transistor and the compensation transistor are dual-gate transistors.

10. A display device, characterized in that: The display panel according to any one of claims 1 to 9 and a power management chip, wherein the power management chip is connected to the other end of the storage capacitor in the display panel via the third power line, and is configured to provide the third power signal to the storage capacitor via the third power line; The third power signal is adjusted according to the display brightness of the display panel during the display time of the display panel, so that the potential of the first node remains stable during the display time.

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