Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a video signal source, a time sequence control module, an interface module and a driving circuit module. The video signal source is electrically connected with the time sequence control module, the time sequence control module is used for generating an input signal according to a video signal of the video signal source, and the input signal is a differential signal. The interface module comprises a plurality of differential signal receivers, the input ends of the differential signal receivers are electrically connected with the time sequence control module, the output ends of the differential signal receivers are electrically connected with the driving circuit module, and the differential signal receivers are used for converting input signals of a differential signal type into output signals of a digital signal type; at least part of the differential signal receiver comprises a dynamic comparison device. Thus, the interface module converts the input signal of the differential signal type into the output signal of the digital signal type through the dynamic comparison device in a dynamic comparison mode, static power consumption is eliminated, and therefore the overall power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With advancements in display technology, microdisplays have become a hot topic. OLED (Organic Light Emitting Diode) microdisplays are rapidly developing, gradually replacing Liquid Crystal Displays (LCDs) as the mainstream screen in the microdisplay field. Compared to LCD panels, OLED microdisplays offer small size and light weight, high display resolution, fast response speed, and low power consumption. Silicon-based OLEDs, as a key offshoot of OLED microdisplays, offer better compatibility with chip processing, meeting the demands of new display technologies and forming a crucial component of near-eye display systems.

[0003] Compared to traditional analog drive methods, digital drive offers higher grayscale levels and lower power consumption, making it a leading driver strategy. In recent years, research on digitally driven silicon-based OLED microdisplays, both domestically and internationally, has focused on display algorithms, using various scanning strategies to improve the display quality of microdisplays. These efforts address issues such as resolution, refresh rate, grayscale, gamma correction, flicker, and dynamic false contouring. However, as microdisplay performance improves, power consumption also increases. This increased power consumption can lead to overheating and reduced battery life in portable devices, even impacting device stability. Reducing power consumption has become a pressing issue. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, wherein a dynamic comparison device of an interface module converts a differential signal type input signal into a digital signal type output signal using a dynamic comparison method, thereby eliminating static power consumption and reducing overall power consumption.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, the display panel comprising:

[0006] Video signal source, timing control module, interface module and driving circuit module;

[0007] The video signal source is electrically connected to the timing control module, and the timing control module is used to generate an input signal according to the video signal of the video signal source, wherein the input signal is a differential signal;

[0008] The interface module includes a plurality of differential signal receivers;

[0009] The input end of the differential signal receiver is electrically connected to the timing control module, and the output end of the differential signal receiver is electrically connected to the driving circuit module. The differential signal receiver is used to convert the input signal of the differential signal type into an output signal of the digital signal type and output it to the driving circuit module;

[0010] At least some of the differential signal receivers include dynamic comparison means.

[0011] Optionally, the input signal of the differential signal type includes a first differential input signal and a second differential input signal;

[0012] The differential signal receiver includes a transmitting unit and a receiving unit, and the receiving unit of some of the differential signal receivers includes the dynamic comparison device;

[0013] The first input terminal of the sending unit receives the first differential input signal, the second input terminal of the sending unit receives the second differential input signal, the first output terminal of the sending unit outputs the first differential output signal to the first input terminal of the receiving unit, the second output terminal of the sending unit outputs the second differential output signal to the second input terminal of the receiving unit, and the output terminal of the receiving unit outputs the output signal to the driving circuit module;

[0014] A phase difference between the first differential input signal and the second differential input signal is 180°;

[0015] A phase difference between the first differential output signal and the second differential output signal is 180°.

[0016] Optionally, the dynamic comparison device includes a first dynamic comparator, a second dynamic comparator, a first NOT gate, and a second NOT gate;

[0017] The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator both receive the first differential output signal, and the second output terminal of the first dynamic comparator and the second output terminal of the second dynamic comparator both receive the second differential output signal;

[0018] The output signal includes a clock output signal;

[0019] A first end of the first NOT gate receives the clock output signal, and the other end is electrically connected to the first end of the second NOT gate and the clock signal end of the second dynamic comparator respectively;

[0020] The second terminal of the second NOT gate is electrically connected to the clock signal terminal of the first dynamic comparator;

[0021] A load resistor is further connected in parallel between the first input terminal and the second input terminal of the first dynamic comparator.

[0022] Optionally, the dynamic comparison device further includes a first NOR gate, a second NOR gate, a first D flip-flop, and a second D flip-flop;

[0023] The output terminal of the first dynamic comparator is electrically connected to the first D flip-flop through the first NOR gate;

[0024] The output terminal of the second dynamic comparator is electrically connected to the second D flip-flop through the second NOR gate.

[0025] Optionally, in the first dynamic comparator, the gates of the first transistor, the second transistor, and the fifth transistor all receive the output clock signal, the gate of the third transistor receives the first output differential signal, the gate of the fourth transistor receives the second output differential signal, the first electrode of the fifth transistor is electrically connected to the ground terminal, the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor, respectively, the first electrode of the first transistor and the second electrode of the third transistor are connected to a first node, the second electrode of the second transistor and the second electrode of the fourth transistor are connected to a second node, and the first electrodes of the first transistor and the second transistor are both electrically connected to the power supply terminal;

[0026] The first electrodes of the sixth transistor and the seventh transistor are both electrically connected to the power supply terminal, the second electrode of the sixth transistor is electrically connected to the first electrode of the eighth transistor, the second electrode of the eighth transistor and the first electrode of the eleventh transistor are connected to the first output terminal, the gate of the eighth transistor is electrically connected to the first node, the gate of the sixth transistor is electrically connected to the gate of the eleventh transistor and the second electrode of the ninth transistor, the second electrode of the seventh transistor is electrically connected to the first electrode of the ninth transistor, the gate of the seventh transistor is electrically connected to the gate of the twelfth transistor and the second electrode of the eighth transistor, the gate of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor and the first electrode of the twelfth transistor are connected to the second output terminal;

[0027] The gate of the tenth transistor and the gate of the thirteenth transistor both receive the reverse output clock signal, the second electrode of the tenth transistor and the second electrode of the eleventh transistor are both electrically connected to the ground terminal, and the first electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0028] The second electrode of the twelfth transistor and the second electrode of the thirteenth transistor are both electrically connected to the ground terminal, and the first electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor.

[0029] Optionally, the differential signal receiver includes a first differential signal receiver and a plurality of second differential signal receivers, the first differential signal receiver includes an analog comparison device, and the second differential signal receiver includes a dynamic comparison device;

[0030] The input signal includes a clock input signal and a data input signal, and the output signal includes a clock output signal and a data output signal;

[0031] The input end of the first differential signal receiver receives the clock input signal, and the output end outputs the clock output signal;

[0032] The input terminal of the second differential signal receiver receives the data input signal, and the output terminal outputs the data output signal.

[0033] Optionally, the second differential signal receiver includes a first sub-differential signal receiver and a second sub-differential signal receiver;

[0034] The data input signal includes a first data input signal and a second data input signal;

[0035] The data output signal includes pixel data and row selection data;

[0036] The driving circuit module includes a row driving circuit and a column driving circuit;

[0037] The input end of the first sub-differential signal receiver receives the first data input signal, and the output end outputs the pixel data to the row driving circuit;

[0038] The input end of the second sub-differential signal receiver receives the second data input signal, and the output end outputs the row selection data to the column driving circuit.

[0039] Optionally, the sending unit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

[0040] The first electrode of the fourteenth transistor and the first electrode of the fifteenth transistor are both electrically connected to the power supply terminal, the second electrode of the fourteenth transistor and the first electrode of the sixteenth transistor are connected to a third node, the second electrode of the fifteenth transistor and the first electrode of the seventeenth transistor are connected to a fourth node, and the second electrode of the sixteenth transistor and the second electrode of the seventeenth transistor are both electrically connected to the ground terminal;

[0041] The gate of the fourteenth transistor and the gate of the sixteenth transistor both receive the first differential input signal;

[0042] The gate of the fifteenth transistor and the gate of the seventeenth transistor both receive the second differential input signal.

[0043] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the first aspect of the present invention.

[0044] The display panel provided by an embodiment of the present invention includes a video signal source, a timing control module, an interface module and a driving circuit module. The video signal source is electrically connected to the timing control module, and the timing control module is used to generate an input signal based on the video signal of the video signal source, and the input signal is a differential signal. The interface module includes a plurality of differential signal receivers, the input end of the differential signal receiver is electrically connected to the timing control module, and the output end of the differential signal receiver is electrically connected to the driving circuit module. The differential signal receiver is used to convert the input signal of the differential signal type into an output signal of the digital signal type and output it to the driving circuit module, and at least some of the differential signal receivers include a dynamic comparison device. In this way, the interface module converts the input signal of the differential signal type into an output signal of the digital signal type using a dynamic comparison method through the dynamic comparison device, thereby eliminating static power consumption and reducing overall power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0046] Figure 2 is a structural diagram of an interface circuit provided by an embodiment of the present invention;

[0047] Figure 3 1 is a schematic structural diagram of a differential signal receiver provided by an embodiment of the present invention;

[0048] Figure 4 1 is a structural diagram of a dynamic comparison device provided by an embodiment of the present invention;

[0049] Figure 5 is a structural diagram of a first dynamic comparator provided by an embodiment of the present invention;

[0050] Figure 6 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be fully described below in conjunction with the accompanying drawings of the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0052] Figure 1 is a structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 FIG is a schematic diagram of the structure of an interface circuit provided by an embodiment of the present invention. Figure 1 and Figure 2 The display panel includes a video signal source 10, a timing control module 20, an interface module 30, and a driving circuit module 40. The video signal source 10 is electrically connected to the timing control module 20. The timing control module 20 is used to generate an input signal based on the video signal of the video signal source 10, wherein the input signal is a differential signal. The interface module 30 includes a plurality of differential signal receivers 310. The input end of the differential signal receiver 310 is electrically connected to the timing control module 20, and the output end of the differential signal receiver 310 is electrically connected to the driving circuit module 40. The differential signal receiver 310 is used to convert the input signal of the differential signal type into an output signal of the digital signal type and output it to the driving circuit module 40. At least some of the differential signal receivers 310 include a dynamic comparison device 311.

[0053] Specifically, such as Figure 1 and Figure 2 As shown, the display panel includes a video signal source 10, which includes multiple video signals, including display information for the display panel. The video signal source 10 is electrically connected to a timing control module 20. One end of the timing control module 20 is electrically connected to the video signal source 10, and the other end is electrically connected to an interface module 30. The timing control module 20 is configured to convert the video signal provided by the video signal source 10 into a differential signal-type input signal. A differential signal is a signal type that uses two complementary (opposite) voltage signals to transmit the same information. In other words, the same type of input signal includes two differential signals. For example, the input signal may include a data input signal Dm, and the differential signal-type data input signal includes a positive phase data input signal and a negative phase data input signal. The interface circuit 30 includes multiple differential signal receivers 310. The input terminals of the differential signal receivers 310 are electrically connected to the timing control module 20. The input terminals of the differential signal receivers 310 are also electrically connected to the drive circuit module 40. The differential signal receivers 310 are used to convert the input signals generated by the timing controller 20 into digital output signals and transmit the digital output signals to the drive circuit module 40. The drive circuit module 40 controls the lighting and shutoff of the multiple pixel units in the display area AA according to the digital signals to achieve display in the display area AA. It will be understood that the differential signal receivers 310 include two input terminals and one output terminal. One input terminal is electrically connected to the positive phase input signal, and the other input terminal is electrically connected to the negative phase input signal. The output terminal is electrically connected to the drive circuit module 40, thereby converting the differential input signals into digital output signals.

[0054] Furthermore, the interface circuit 30 includes multiple differential signal receivers 310. Different differential signal receivers 310 can convert the same type of input signal into digital signals. For example, if the number of pixel cells arranged in the array is large, the output of one differential signal receiver 310 can provide a data output signal D[47:0] for the left half of the pixel cells in the display area AA, and the output of another differential signal receiver 310 can provide a data output signal D[95:48] for the right half of the pixel cells in the display area AA. Furthermore, different differential signal receivers 310 can also convert different types of input signals into digital signals. For example, if the input signal includes a data input signal and a control input signal, the data input signal is used to control the lighting of the pixel cells, and the control input signal indicates the start of signal transmission when it is a specific pattern. Therefore, the output of one differential signal receiver 310 can provide a data output signal for the pixel cells in the display area AA, and the output of another differential signal receiver 310 can provide a control output signal for the pixel cells.

[0055] In existing technologies, differential signal receivers use analog comparators for pre-amplification, converting small differential signals into digital output levels. Analog comparators amplify the input differential signal, thereby amplifying the input signal. When the input signal is small and changes rapidly, the comparator needs to increase current to ensure accurate readings, which increases power consumption.

[0056] To this end, an embodiment of the present invention provides that at least part of the differential signal receiver 310 includes a dynamic comparator 311. When the dynamic comparator 311 is working, it mainly converts the input signal of the differential signal type into an output signal of the digital signal according to the switching state of the transistor inside the dynamic comparator 311, that is, the conversion is performed by dynamic comparison. In this process, there is no channel from the power supply to the ground. Therefore, the static power consumption can be ignored, which reduces the static power consumption and thus reduces the overall power consumption of the display panel.

[0057] In summary, the display panel provided by the embodiment of the present invention includes a video signal source, a timing control module, an interface module and a driving circuit module. The video signal source is electrically connected to the timing control module, and the timing control module is used to generate an input signal according to the video signal of the video signal source, and the input signal is a differential signal. The interface module includes a plurality of differential signal receivers, the input end of the differential signal receiver is electrically connected to the timing control module, and the output end of the differential signal receiver is electrically connected to the driving circuit module. The differential signal receiver is used to convert the input signal of the differential signal type into an output signal of the digital signal type, and output it to the driving circuit module, and at least part of the differential signal receiver includes a dynamic comparison device. In this way, the interface module converts the input signal of the differential signal type into an output signal of the digital signal type by using a dynamic comparison method through the dynamic comparison device, thereby eliminating static power consumption and reducing overall power consumption.

[0058] Optionally, based on the above embodiment, Figure 3 Schematic diagram of a differential signal receiver provided by an embodiment of the present invention. Figure 2 and Figure 3 The differential signal type input signal includes a first differential input signal VinP and a second differential input signal VinN. The differential signal receiver 310 includes a transmitting unit 301 and a receiving unit 302. The receiving unit 302 of the differential signal receiver 310 includes a dynamic comparison device 311. The first input terminal of the transmitting unit 301 receives the first differential input signal VinP, and the second input terminal of the transmitting unit 301 receives the second differential input signal VinN. The first output terminal of the transmitting unit 301 outputs the first differential output signal OutP to the first input terminal of the receiving unit 302. The second output terminal of the transmitting unit 301 outputs the second differential output signal OutN to the second input terminal of the receiving unit 302. The output terminal of the receiving unit 302 outputs the output signal to the driving circuit module 40. The phase difference between the first differential input signal VinP and the second differential input signal VinN is 180°, and the phase difference between the first differential output signal OutP and the second differential output signal OutN is also 180°.

[0059] Specifically, the differential signal receiver 310 includes a transmitting unit 301 and a receiving unit 302. The transmitting unit 301 can output currents in different directions depending on the input level. In this case, a 100mV voltage drop with different phases can be generated on the load resistor R of the receiving unit 302. The receiving unit 302 converts the low-voltage differential signal into a high- and low-level digital signal by comparing the phase differences. For example, the differential signal type input signal includes a first differential input signal VinP and a second differential input signal VinN. Assuming that the input signal includes a data input signal, the first differential input signal VinP can be a positive phase data input signal DmP, and the second differential input signal VinN can be a negative phase data input signal DmN. The phase difference between the first differential input signal VinP and the second differential input signal VinN is 180°. The transmitting unit 301 outputs a first differential output signal OutP and a second differential output signal OutN based on the first differential input signal VinP and the second differential input signal VinN. The receiving unit 302 of the partial differential signal receiver 310 includes a dynamic comparison device 311, which can convert the first differential output signal OutP and the second differential output signal OutN output by the sending unit 301 into an output signal of a digital signal type through dynamic comparison, thereby reducing static power consumption and thus reducing overall power consumption.

[0060] It should be noted that the receiving units 302 of some differential signal receivers 310 also include analog comparison devices, that is, these input signals need to be converted into output signals using analog comparison to ensure normal operation of the circuit.

[0061] Optionally, based on the above embodiment, Figure 4 The figure is a schematic diagram of the structure of a dynamic comparison device provided by an embodiment of the present invention. The dynamic comparison device 311 includes a first dynamic comparator 311a, a second dynamic comparator 311b, a first NOT gate 311c, and a second NOT gate 311d. The first input of the first dynamic comparator 311a and the first input of the second dynamic comparator 311b both receive the first differential output signal OutP, and the second output of the first dynamic comparator 311a and the second output of the second dynamic comparator 311b both receive the second differential output signal OutN. The output signal includes a clock output signal CLK. The first terminal of the first NOT gate 311c receives the clock output signal CLK, and the other terminal is electrically connected to the first terminal of the second NOT gate 311d and the clock signal terminal of the second dynamic comparator 311b, respectively. The second terminal of the second NOT gate 311d is electrically connected to the clock signal terminal of the first dynamic comparator 311a. A load resistor R is also connected in parallel between the first input and the second input of the first dynamic comparator 311a.

[0062] Specifically, such as Figure 4As shown, the operating states of the dynamic comparator include a precharge state and a comparison state. Half of the clock cycle (precharge state) of its output is in a return-to-zero state, which halves the effective time of the high level, resulting in insufficient data retention time. At the same time, the dynamic comparator cannot perform real-time comparisons. If a continuous 01 signal input is used as a clock, only half of the data can be sampled. To this end, the embodiment of the present invention provides a dynamic comparison device 311 comprising a first dynamic comparator 311a, a second dynamic comparator 311b, a first NOT gate 311c, and a second NOT gate 311d. The first end of the first NOT gate 311c is configured to receive the clock output signal CLK, and the other end is electrically connected to the first end of the second NOT gate 311d and the clock signal end of the second dynamic comparator 311b, respectively. The second end of the second NOT gate 311d is electrically connected to the clock signal end of the first dynamic comparator 311a, so that the first dynamic comparator 311a and the second dynamic comparator 311b use reverse clocks, respectively, and can perform sampling and comparison on the rising and falling edges of the clock output signal CLK. In addition, the dynamic comparison device 311 also includes a first NOR gate 311e, a second NOR gate 311f, a first D flip-flop 311m, and a second D flip-flop 311n. The output of the first dynamic comparator 311a is electrically connected to the first D flip-flop 311m via the first NOR gate 311e, and the output of the second dynamic comparator 311b is electrically connected to the second D flip-flop 311n via the second NOR gate 311f. The first NOR gate 311e, the second NOR gate 311f, the first D flip-flop 311m, and the second D flip-flop 311n constitute the recovery circuit of the dynamic comparison device 311. After the first dynamic comparator 311a and the second dynamic comparator 311b complete the comparison, the NOR gates of the recovery circuit compare the outputs of the dynamic comparators to determine the time point when the data comparison is completed. The D flip-flops are then used to store the data, thereby restoring the data width and performing a data separation.

[0063] Optionally, based on the above embodiment, Figure 5 FIG is a structural diagram of a first dynamic comparator provided by an embodiment of the present invention. Figure 5In the first dynamic comparator 311a, the gates of the first transistor M1, the second transistor M2, and the fifth transistor M5 all receive the output clock signal CLK, the gate of the third transistor M3 receives the first differential output signal OutP, the gate of the fourth transistor M4 receives the second differential output signal OutN, a first electrode of the fifth transistor M5 is electrically connected to the ground terminal GND, a second electrode of the fifth transistor M5 is electrically connected to the first electrode of the third transistor M3 and the first electrode of the fourth transistor M4, respectively, a first electrode of the first transistor M1 and the second electrode of the third transistor M3 are connected to the first node X, a second electrode of the second transistor M2 and the second electrode of the fourth transistor M4 are connected to the second node Y, and the first electrodes of the first transistor M1 and the second transistor M2 are both electrically connected to the power supply terminal VDD. The first electrodes of the sixth transistor M6 and the seventh transistor M7 are both electrically connected to the power supply terminal VDD, the second electrode of the sixth transistor M6 is electrically connected to the first electrode of the eighth transistor M8, the second electrode of the eighth transistor M8 and the first electrode of the eleventh transistor M11 are connected to the first output terminal Vo, the gate of the eighth transistor M8 is electrically connected to the first node X, the gate of the sixth transistor M6 is electrically connected to the gate of the eleventh transistor M11 and the second electrode of the ninth transistor M9, the second electrode of the seventh transistor M7 is electrically connected to the first electrode of the ninth transistor M9, the gate of the seventh transistor M7 is electrically connected to the gate of the twelfth transistor M12 and the second electrode of the eighth transistor M8, the gate of the ninth transistor M9 is electrically connected to the second node Y, and the second electrode of the ninth transistor M9 and the first electrode of the twelfth transistor M12 are connected to the second output terminal Vob. The gates of the tenth transistor M10 and the thirteenth transistor M13 both receive the inverted output clock signal CLKB. The second electrode of the tenth transistor M10 and the second electrode of the eleventh transistor M11 are both electrically connected to the ground terminal GND, and the first electrode of the tenth transistor M10 is electrically connected to the first electrode of the eleventh transistor M11. The second electrode of the twelfth transistor M12 and the second electrode of the thirteenth transistor M13 are both electrically connected to the ground terminal GND, and the first electrode of the twelfth transistor M12 is electrically connected to the first electrode of the thirteenth transistor M13. The first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are all P-type transistors. The third transistor M3, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all N-type transistors.

[0064] Specifically, the P-type transistor is turned on by a low-level signal and turned off by a high-level signal. The N-type transistor is turned on by a high-level signal and turned off by a low-level signal. The inverse output clock signal CLKB is the inverse clock signal of the output clock signal CLK; that is, when the output clock signal CLK is high, the inverse output clock signal CLKB is low. The first dynamic comparator 311a includes a first transistor, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13, connected as described above. The operation of the first dynamic comparator 311a includes a pre-charge state and a comparison state. When the output clock signal CLK is low, the first dynamic comparator 311a operates in the pre-charge state. At this time, the fifth transistor M5 is turned off, the first transistor and the second transistor M2 are turned on, and the first node X and the second node Y are charged to the power supply voltage. At this time, the inverted output clock signal CLKB is high, the tenth transistor M10 and the thirteenth transistor M13 are turned on, and the output is pulled low. When the output clock signal CLK is high, the first dynamic comparator 311a operates in a comparison state, the fifth transistor M5 is turned on, and the first node X and the second node Y are discharged through the third transistor M3 and the fourth transistor M4. At this time, the inverted output clock signal CLKB is low, the tenth transistor M10 and the thirteenth transistor M13 are turned off, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 form a first latch structure, and the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 form a second latch structure. At this time, when the first differential output signal OutP is greater than the second differential output signal OutN, the discharge rate of the first node X is greater than the discharge rate of the second node Y. The eighth transistor M8 turns on first, causing the voltage of the first output terminal Vo to increase, while simultaneously accelerating the shutdown of the seventh transistor M7, causing the twelfth transistor M12 to turn on, pulling the voltage outputted by the second output terminal Vob to a low level. The voltage output by the second output terminal Vob simultaneously accelerates the conduction of the sixth transistor M6 and the turning off of the eleventh transistor M11, increasing the voltage at the first output terminal Vo, thereby forming positive feedback to latch the input comparison result. During the above operation, the differential input signal is converted into a digital output signal primarily based on the switching state of the transistors within the first dynamic comparator 311a. This conversion is performed using a dynamic comparison method. During this process, there is no path from power to ground. Therefore, static power consumption is negligible, reducing static power consumption and, consequently, the overall power consumption of the display panel.

[0065] It is understandable that the second dynamic comparator 311 b has the same structure and function as the first dynamic comparator 311 a , and the present invention will not elaborate on them one by one here.

[0066] Optionally, based on the above embodiment, continue to refer to Figure 2 The differential signal receiver 310 includes a first differential signal receiver 310a and multiple second differential signal receivers 310b. The first differential signal receiver 310a includes an analog comparator, and the second differential signal receivers 310b include a dynamic comparator 311. Input signals include a clock input signal CK (CKP and CKN) and data input signals (DmP and DmN). Output signals include a clock output signal CLK and a data output signal Dm. The first differential signal receiver 310a receives the clock input signal CK (CKP and CKN) at its input and outputs the clock output signal CLK at its output. The second differential signal receiver 310b receives the data input signal (DmP and DmN) at its input and outputs the data output signal Dm at its output.

[0067] Specifically, because the clock input signals CK (CKP and CKN) cannot be converted into digital signals using a dynamic comparison method, the first differential signal receiver 310a is configured to include an analog comparison device. The first differential signal receiver 310a receives the clock input signals CK (CKP and CKN) at its input and outputs the clock output signal CLK at its output to ensure normal conversion of the clock output signal CLK. The second differential signal receiver 310b includes a dynamic comparison device 311. The second differential signal receiver 310b receives the data input signals (DmP and DmN) at its input and outputs the data output signal Dm at its output. Specifically, the data input signals (DmP and DmN) are converted using a dynamic comparison method by the dynamic comparison device 311, thereby reducing power consumption. Furthermore, the input signals may also include control input signals (CTP and CTN). The second differential signal receiver 310b also receives the control input signals (CTP and CTN) at its input and outputs the control output signal CT at its output.

[0068] Optional, see Figure 1 and Figure 2, the second differential signal receiver 310b includes a first sub-differential signal receiver (not shown in the figure) and a second sub-differential signal receiver (not shown in the figure). The data input signal includes a first data input signal and a second data input signal. The data output signal includes pixel data and row selection data. Among them, the first data input signal corresponds to pixel data, and the second data input signal corresponds to row selection data. The driving circuit module 40 includes a row driving circuit 410 and a column driving circuit 420. The input end of the first sub-differential signal receiver receives the first data input signal, and the output end outputs the pixel data to the row driving circuit 410. The input end of the second sub-differential signal receiver receives the second data input signal, and the output end outputs the row selection data to the column driving circuit 420. The pixel units in the display area AA are controlled to be turned on and off through the row selection data and the pixel data. In addition, the data input signal may further include a third data input signal, which may be a control input signal (CTP and CTN). The second differential signal receiver 310b may further include a third sub-differential signal receiver, the input end of the third sub-differential signal receiver receives the control input signal (CTP and CTN), and the output end outputs the control output signal CT.

[0069] It should be noted that Figure 2 The data input signal includes a first data input signal and a third data input signal as an example for illustration, but this is not limiting, and those skilled in the art can set it as needed.

[0070] Optionally, based on the above embodiment, continue to refer to Figure 3 The transmitting unit 301 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The first electrode of the fourteenth transistor M14 and the first electrode of the fifteenth transistor M15 are both electrically connected to the power supply terminal VDD. The second electrode of the fourteenth transistor M14 and the first electrode of the sixteenth transistor M16 are connected to a third node. The second electrode of the fifteenth transistor M15 and the first electrode of the seventeenth transistor M17 are connected to a fourth node. The second electrode of the sixteenth transistor M16 and the second electrode of the seventeenth transistor M17 are both electrically connected to the ground terminal GND. The gates of the fourteenth transistor M14 and the sixteenth transistor M16 receive the first differential input signal VinP. The gates of the fifteenth transistor M15 and the seventeenth transistor M17 receive the second differential input signal VinN. The fourteenth transistor M14 and the fifteenth transistor M15 are both N-type transistors. The sixteenth transistor M16 and the seventeenth transistor M17 are both P-type transistors. These connections ensure the normal operation of the transmitting unit 301.

[0071] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 6 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 6 As shown, the display device 100 includes the display panel 1 described in any of the above embodiments. Therefore, the display device 100 provided by the embodiment of the present invention has the corresponding beneficial effects of the above embodiments, which will not be repeated here. For example, the display device 100 can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and an in-vehicle display device, which is not limited in the embodiment of the present invention.

[0072] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes a video signal source, a timing control module, an interface module and a driving circuit module; The video signal source is electrically connected to the timing control module, and the timing control module is used to generate an input signal according to the video signal of the video signal source, wherein the input signal is a differential signal; The interface module includes a plurality of differential signal receivers; The input end of the differential signal receiver is electrically connected to the timing control module, and the output end of the differential signal receiver is electrically connected to the driving circuit module. The differential signal receiver is used to convert the input signal of the differential signal type into an output signal of the digital signal type and output it to the driving circuit module; At least some of the differential signal receivers include dynamic comparison means.

2. The display panel according to claim 1, wherein: The input signal of the differential signal type includes a first differential input signal and a second differential input signal; The differential signal receiver includes a transmitting unit and a receiving unit, and the receiving unit of some of the differential signal receivers includes the dynamic comparison device; The first input terminal of the sending unit receives the first differential input signal, the second input terminal of the sending unit receives the second differential input signal, the first output terminal of the sending unit outputs the first differential output signal to the first input terminal of the receiving unit, the second output terminal of the sending unit outputs the second differential output signal to the second input terminal of the receiving unit, and the output terminal of the receiving unit outputs the output signal to the driving circuit module; A phase difference between the first differential input signal and the second differential input signal is 180°; A phase difference between the first differential output signal and the second differential output signal is 180°.

3. The display panel according to claim 2, wherein: The dynamic comparison device includes a first dynamic comparator, a second dynamic comparator, a first NOT gate and a second NOT gate; The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator both receive the first differential output signal, and the second output terminal of the first dynamic comparator and the second output terminal of the second dynamic comparator both receive the second differential output signal; The output signal includes a clock output signal; A first end of the first NOT gate receives the clock output signal, and the other end is electrically connected to the first end of the second NOT gate and the clock signal end of the second dynamic comparator respectively; The second terminal of the second NOT gate is electrically connected to the clock signal terminal of the first dynamic comparator; A load resistor is further connected in parallel between the first input terminal and the second input terminal of the first dynamic comparator.

4. The display panel according to claim 3, wherein: The dynamic comparison device further includes a first NOR gate, a second NOR gate, a first D flip-flop and a second D flip-flop; The output terminal of the first dynamic comparator is electrically connected to the first D flip-flop through the first NOR gate; The output terminal of the second dynamic comparator is electrically connected to the second D flip-flop through the second NOR gate.

5. The display panel according to claim 3, wherein: In the first dynamic comparator, the gates of the first transistor, the second transistor, and the fifth transistor all receive the output clock signal, the gate of the third transistor receives the first output differential signal, the gate of the fourth transistor receives the second output differential signal, the first electrode of the fifth transistor is electrically connected to the ground terminal, the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor and the first electrode of the fourth transistor, respectively, the first electrode of the first transistor and the second electrode of the third transistor are connected to a first node, the second electrode of the second transistor and the second electrode of the fourth transistor are connected to a second node, and the first electrodes of the first transistor and the second transistor are both electrically connected to a power supply terminal; The first electrodes of the sixth transistor and the seventh transistor are both electrically connected to the power supply terminal, the second electrode of the sixth transistor is electrically connected to the first electrode of the eighth transistor, the second electrode of the eighth transistor and the first electrode of the eleventh transistor are connected to the first output terminal, the gate of the eighth transistor is electrically connected to the first node, the gate of the sixth transistor is electrically connected to the gate of the eleventh transistor and the second electrode of the ninth transistor, the second electrode of the seventh transistor is electrically connected to the first electrode of the ninth transistor, the gate of the seventh transistor is electrically connected to the gate of the twelfth transistor and the second electrode of the eighth transistor, the gate of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor and the first electrode of the twelfth transistor are connected to the second output terminal; The gate of the tenth transistor and the gate of the thirteenth transistor both receive the reverse output clock signal, the second electrode of the tenth transistor and the second electrode of the eleventh transistor are both electrically connected to the ground terminal, and the first electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor; The second electrode of the twelfth transistor and the second electrode of the thirteenth transistor are both electrically connected to the ground terminal, and the first electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor.

6. The display panel according to claim 5, wherein: The first transistor, the second transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are all P-type transistors; The third transistor, the fifth transistor, the fourth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are all N-type transistors.

7. The display panel according to claim 1, wherein: The differential signal receiver includes a first differential signal receiver and a plurality of second differential signal receivers, the first differential signal receiver includes an analog comparison device, and the second differential signal receiver includes a dynamic comparison device; The input signal includes a clock input signal and a data input signal, and the output signal includes a clock output signal and a data output signal; The input end of the first differential signal receiver receives the clock input signal, and the output end outputs the clock output signal; The input terminal of the second differential signal receiver receives the data input signal, and the output terminal outputs the data output signal.

8. The display panel according to claim 7, wherein: The second differential signal receiver includes a first sub-differential signal receiver and a second sub-differential signal receiver; The data input signal includes a first data input signal and a second data input signal; The data output signal includes pixel data and row selection data; The driving circuit module includes a row driving circuit and a column driving circuit; The input end of the first sub-differential signal receiver receives the first data input signal, and the output end outputs the pixel data to the row driving circuit; The input end of the second sub-differential signal receiver receives the second data input signal, and the output end outputs the row selection data to the column driving circuit.

9. The display panel according to claim 2, wherein: The sending unit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor; The first electrode of the fourteenth transistor and the first electrode of the fifteenth transistor are both electrically connected to the power supply terminal, the second electrode of the fourteenth transistor and the first electrode of the sixteenth transistor are connected to a third node, the second electrode of the fifteenth transistor and the first electrode of the seventeenth transistor are connected to a fourth node, and the second electrode of the sixteenth transistor and the second electrode of the seventeenth transistor are both electrically connected to the ground terminal; The gate of the fourteenth transistor and the gate of the sixteenth transistor both receive the first differential input signal; The gate of the fifteenth transistor and the gate of the seventeenth transistor both receive the second differential input signal.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

Images