Method and system for detecting false capacity expansion of memory card

Abstract

The invention discloses a memory card false capacity expansion detection method and system, and relates to the field of memory card detection, and the method comprises the steps: obtaining the nominal capacity information of a to-be-detected memory card, and dividing a logic address into a plurality of test address blocks based on the capacity; respectively executing distributed small data write-in operation in each test address block, and recording write-in delay; reading the data and comparing consistency results, generating a delay behavior curve taking the logic address as a horizontal axis and the write-in delay as a longitudinal axis, and marking a read-back consistency state on the curve; and identifying a local fluctuation abnormal region in the curve, and if the region is overlapped with the read-back consistency failure region, preferentially judging the intersection as a pseudo capacity expansion region. According to the invention, the problem of capacity false bidding of the memory card can be effectively solved without writing in the whole disk.

Description

Technical Field

[0001] The present invention relates to the field of memory card detection, and more particularly to a method and system for detecting false capacity expansion of a memory card. Background Art

[0002] With the widespread adoption of flash memory technology, memory cards are widely used as portable storage media in devices such as digital cameras, smartphones, and dashcams. In pursuit of higher capacity and lower costs, some unscrupulous manufacturers tamper with memory card firmware to create "fake expansion cards" with nominal capacities far exceeding their actual capacity. The capacity reported by these memory cards in the system significantly differs from the actual available physical storage space. This discrepancy is difficult for users to detect during the initial data writing phase. However, once data written exceeds the actual capacity limit, data loss, file corruption, or device crashes may occur, posing serious data security risks to users.

[0003] Existing memory card detection technologies often rely on filling the entire drive and then comparing each section to determine available capacity. However, this approach often has the following problems: 1. The detection process is time-consuming and causes significant damage to the device. Specifically, the traditional "full write detection" method requires traversing all logical addresses to write and verify a large amount of data, which is time-consuming and may cause excessive write damage to the memory card, affecting its subsequent normal use; 2. Unable to identify firmware-level camouflage. Specifically, some fake expansion cards use circular address mapping, fake data readback, or fake response mechanisms. Even before the physical space is fully used, they may still "disguise normal writes" through caching or repeated response mechanisms. 3. Lack of in-depth analysis of behavioral characteristics. Specifically, existing detection methods are mostly based on direct judgment of the success or failure of capacity writing, ignoring the delay changes and consistency behavior of memory cards during the writing and reading processes. These behaviors often show identifiable abnormal characteristics in pseudo-capacity expansion scenarios.

[0004] Therefore, there is an urgent need for a non-destructive, efficient detection method and system based on access behavior analysis. This method can accurately identify fake expansion cards by modeling the characteristics of their write latency and data consistency behavior without destroying the memory card data, and assist in locating suspicious areas, thereby improving the reliability, practicality and engineering deployability of detection. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and system for detecting false capacity expansion of a memory card, so as to solve the problems mentioned in the background technology.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: A method for detecting false expansion of a memory card comprises the following steps: Obtaining nominal capacity information of the memory card to be tested, and dividing the logical address into a plurality of test address blocks based on the nominal capacity information; Perform distributed small data write operations in each test address block and record the write latency of each write operation; Perform a read operation on the data of each test address block, and compare the read result with the original written data to obtain a readback consistency result; Generate a delay behavior curve, wherein the delay behavior curve has the logical address as the horizontal axis and the write delay as the vertical axis, and the readback consistency result is marked on the horizontal axis; A local fluctuation abnormal area in the delay behavior curve is identified. If a readback consistency failure area overlaps with the local fluctuation abnormal area, an intersection area of ​​the local fluctuation abnormal area and the readback consistency failure area is preferentially determined as a pseudo expansion area.

[0007] In some embodiments, when an area within a sliding window has the following conditions, the area within the sliding window is determined to be a local fluctuation abnormal area: the local fluctuation amplitude of the delay curve within the sliding window is greater than a preset allowable range.

[0008] In some embodiments, a template comparison method is used to identify the local fluctuation abnormal area, which specifically includes the following steps: Establishing a delay behavior template library, wherein the delay behavior template library includes a plurality of delay template curves generated by a normal capacity memory card; The delay behavior curve of the memory card under test is segmented using a sliding window method. Each sliding window corresponds to a local area, and the delay subsequence within the window is extracted as the detection segment. Comparing each detection segment with the template segment at the corresponding position in the delay behavior template library for similarity; If the similarity between any detection segment and the template segment is lower than a preset threshold, the area covered by the corresponding sliding window is marked as a local fluctuation abnormality area.

[0009] In some embodiments, the similarity measurement method includes any one of the following: Euclidean distance, cosine similarity or dynamic time warping distance.

[0010] In some embodiments, the method further includes: determining a union area of ​​the local fluctuation abnormal area and the consistency failure area, after deducting the intersection area, as a candidate area of ​​the pseudo expansion segment.

[0011] In some embodiments, the method further includes: performing a write operation on the candidate area, performing a power-off or device restart operation, and reading the original data from the candidate area again. If a consistency failure occurs, the candidate area is determined to be a pseudo-expansion segment.

[0012] In some embodiments, the method further includes: performing write and read operations on the candidate area, and comparing the read data with the previously written data of other address blocks; if the degree of matching exceeds a preset threshold, the candidate area is determined to be a pseudo-expansion segment.

[0013] The present invention also discloses a memory card pseudo expansion detection system, comprising: A capacity analysis module, configured to obtain the nominal capacity information of the memory card to be tested, and divide the logical address into a plurality of test address blocks based on the nominal capacity information; A write control module is used to perform distributed small data write operations in each test address block and record the write delay of each write operation; A read verification module is used to perform a read operation on the data of each test address block, and compare the read result with the original written data for consistency, to obtain a readback consistency result; A curve generating module is used to generate a delay behavior curve, wherein the delay behavior curve has a logical address as a horizontal axis and a write delay as a vertical axis, and a readback consistency result is marked on the horizontal axis; an abnormality identification module, configured to identify a local fluctuation abnormal region in the delay behavior curve and detect whether the abnormal region overlaps with a readback consistency failure region; The pseudo expansion determination module is configured to preferentially determine an intersection area between the local fluctuation abnormal area and the readback consistency failure area as a pseudo expansion area.

[0014] In some embodiments, the anomaly identification module determines that an area within a sliding window is a local fluctuation anomaly area when the following conditions exist in an area within the sliding window: the local fluctuation amplitude of the delay curve within the sliding window is greater than a preset allowable range.

[0015] In some embodiments, the pseudo expansion determination module further determines a union area of ​​the local fluctuation abnormal area and the consistency failure area, after deducting the intersection area, as a candidate area for the pseudo expansion segment.

[0016] The advantages of the present invention over the prior art are: The present invention replaces the entire disk write strategy with distributed small data block writing, avoiding write damage to the memory card and significantly reducing detection time. It is suitable for deployment in consumer application terminals or quality inspection links. Compared to traditional consistency detection methods, this invention innovatively introduces write latency as a behavioral feature dimension. Based on the latency curve, it reveals potential anomalies in the physical write path of the memory card, such as latency mutation, invalid write, or latency drift, which helps to discover hidden firmware-level pseudo-expansion tricks. By generating a delay behavior curve and annotating it with consistency results, the present invention makes the pseudo-capacity expansion area present with identifiable structural features in the curve, providing graphical interpretation capabilities, facilitating intuitive interpretation by technicians and assisting in locating the true capacity boundary. Accuracy can be further improved through methods such as template matching. The present invention proposes to prioritize the intersection of the "local fluctuation abnormal area" and the "consistency failure area" as a pseudo expansion segment, and at the same time deduct the intersection part from the union to form a candidate area. Combined with further verification mechanisms (such as power-off retest and address wraparound analysis) for dynamic judgment, it effectively reduces the false alarm rate and enhances the stability and flexibility of the detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is an overall flow chart of the memory card false expansion detection method of the present invention; Figure 2 This is a flow chart of test address block division and small data write sampling in the present invention; Figure 3 is a flow chart of the present invention for generating a delay behavior curve and identifying an abnormal local fluctuation area; Figure 4 This is a flowchart of the present invention's processing of pseudo expansion candidate areas. DETAILED DESCRIPTION

[0018] The specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0019] The present invention proposes an efficient and accurate method and system for detecting pseudo-capacity expansion of memory cards, aiming to identify the pseudo-capacity expansion areas hidden in memory cards through distributed small data block writing, write delay behavior analysis and data consistency verification.

[0020] As shown in FIG1 , the method of the present invention comprises the following steps: Obtaining nominal capacity information of the memory card to be tested, and dividing the logical address into a plurality of test address blocks based on the nominal capacity information; Perform distributed small data write operations in each test address block and record the write latency of each write operation; Perform a read operation on the data of each test address block, and compare the read result with the original written data to obtain a readback consistency result; Generate a delay behavior curve, wherein the delay behavior curve has the logical address as the horizontal axis and the write delay as the vertical axis, and the readback consistency result is marked on the horizontal axis; A local fluctuation abnormal area in the delay behavior curve is identified. If a readback consistency failure area overlaps with the local fluctuation abnormal area, an intersection area of ​​the local fluctuation abnormal area and the readback consistency failure area is preferentially determined as a pseudo expansion area.

[0021] In a specific embodiment, the nominal capacity is usually provided by the memory card manufacturer through firmware or device interface, in bytes. For example, a memory card with a nominal capacity of 32GB has a nominal capacity of approximately 32×1024×1024×1024 bytes, or 34,359,738,368 bytes. After obtaining this information, the logical address space of the memory card needs to be divided into multiple test address blocks. The purpose of the division is to ensure that subsequent distributed write operations can cover the entire address space, while ensuring that the size of each test address block is small enough to reduce the burden on the memory card for a single operation.

[0022] As shown in Figure 2, when dividing the test address blocks, the number and size of the blocks can be dynamically adjusted according to the size of the nominal capacity. C Bytes, dividing the logical address space into N test address blocks, the size of each test address block is S It can be expressed as: ; Here, N is an adjustable parameter, and its value needs to balance the accuracy and efficiency of detection. If N is too small, each test address block is too large, which may lead to insufficient detection granularity and difficulty in detecting local anomalies; if N is too large, the number of test address blocks is too large, which will increase computing and storage overhead. Usually, the value range of N can be set between 100 and 10,000. For example, for a 32GB memory card, if N = 1024, the size of each test address block is: ; This division method ensures that the test address block can cover the entire logical address space and facilitates subsequent distributed small data write operations.

[0023] Within each test address block, distributed small data write operations are performed. Specifically, several logical addresses are randomly selected within each test address block, and small blocks of data are written to these addresses. The amount of data written each time should be kept within a small range, such as 4KB (4096 bytes) or 8KB (8192 bytes). This design is for two reasons: first, to avoid excessive write damage to the memory card; second, by writing small data blocks, potential latency differences are amplified, making abnormal behavior in the pseudo-expansion area more easily exposed.

[0024] During write operations, record the latency of each write. Write latency refers to the time from issuing a write command to the completion of the write operation, typically measured in milliseconds. This time can be measured using the system clock or a high-precision timer. For example, on a real 32GB memory card, the latency for writing 4KB of data might be around 1ms. However, in a pseudo-expanded area, the latency might increase significantly or fluctuate due to firmware tampering or address wraparound.

[0025] To ensure comprehensive testing, the number of writes within each test address block can be set between 5 and 20. For example, if each test address block is written 10 times, with each write adding 4KB, the total amount of data written to a 33.55MB address block is 40KB, far less than the address block capacity. This distributed write strategy ensures coverage while avoiding the inefficiency and high loss of writing to the entire drive.

[0026] After writing is complete, a read operation is performed on the written data in each test address block and the read result is compared with the original written data to assess data consistency. If the read data is exactly the same as the written data, the readback consistency result for that address block is considered "consistent"; if there is a difference, it is marked as "failed." This consistency check is important for identifying false expansion, as false expansion areas often fail to store data correctly, resulting in read errors.

[0027] For example, suppose that in a write to a test address block, A If the data "0x1234" is written and the data returned when read is also "0x1234", the consistency result is "consistent". If "0x0000" or a random value is returned, it is "failed". By writing and reading each test address block multiple times, the overall consistency performance of the block can be statistically analyzed.

[0028] As shown in Figure 3, a latency behavior curve is generated based on the write latency and consistency results. The horizontal axis of this curve is the logical address, and the vertical axis is the write latency, typically measured in milliseconds (ms). For ease of analysis, the write latency for each test address block can be averaged over multiple writes. For example, if a block of addresses is written 10 times with latencies of 1.2ms, 1.3ms, 1.1ms, and so on, the average latency for that block is: ; When plotting the curve, the horizontal axis arranges all test address blocks in logical address order, while the vertical axis plots the corresponding average latency value. The horizontal axis also displays the readback consistency results for each address block, with a green dot indicating "consistent" and a red cross indicating "failed." This visualization allows technicians to intuitively observe the relationship between latency and consistency.

[0029] The significance of the latency behavior curve lies in its ability to translate the memory card's write behavior into identifiable structural features. Latency in normal capacity areas is typically relatively stable, while latency in areas with false expansion may exhibit sudden changes or fluctuations. Combined with consistency results, this allows for more accurate identification of abnormal areas.

[0030] After the latency behavior curve is generated, it is necessary to identify areas of abnormal local fluctuations. These areas are parts of the latency curve where the fluctuation amplitude increases significantly within certain local segments, which may indicate abnormal write behavior of the memory card at the corresponding logical address. There are two ways to identify them: Method 1: Fluctuation amplitude detection based on sliding window.

[0031] The delay curve is segmented using a sliding window. The size of the sliding window W (i.e. the number of address blocks included) can be set according to the actual situation, for example, 5 to 20 address blocks. For each window, calculate the fluctuation range of the delay curve. Common indicators include standard deviation or range. Taking standard deviation as an example, suppose the window W The delay value of each address block is , the average delay is , then the standard deviation The calculation formula is: ; If a window Greater than the preset allowable range T , the area within the window is considered to be a local fluctuation abnormal area. T The value of is related to the performance of the memory card and the detection accuracy requirements, and can usually be set between 3ms and 10ms. T = 5ms, a window , the area is marked as abnormal.

[0032] The advantage of this method is its simplicity and ability to quickly locate areas of significant latency fluctuations. The standard deviation in the formula reflects the degree of latency dispersion and is suitable for capturing latency mutations in areas of pseudo-expansion.

[0033] Method 2: Anomaly detection based on template comparison.

[0034] Another identification method uses template comparison. First, a latency behavior template library is created, containing multiple latency template curves generated from memory cards with normal capacities. These template curves are generated by performing the same write operation on memory cards with known actual capacities and represent normal latency behavior. For example, the latency behavior template library might include latency curves for memory cards with different capacities, such as 32GB and 64GB.

[0035] The delay curve of the memory card to be tested is also segmented using a sliding window method. A delay subsequence is extracted from each window as a detection segment. Then, the detection segment is compared with the template segment at the corresponding position in the template library for similarity. The similarity metric can be Euclidean distance, cosine similarity, or dynamic time warping distance (DTW). Taking cosine similarity as an example, let the detection segment be vector , the template fragment is Represent the delay values ​​within the sliding window respectively, and the cosine similarity is: ; like If the value is less than a preset threshold (e.g., 0.9), the detected segment is considered to be significantly different from the template, and the corresponding window is marked as a local fluctuation anomaly region. The preset threshold can range from 0.85 to 0.95, depending on the diversity of the template library and the detection sensitivity requirements.

[0036] This method can identify anomalies more accurately by comparing them with normal behavior, and is particularly suitable for scenarios with complex firmware disguises.

[0037] After identifying the local fluctuation anomaly areas, it is necessary to further determine which areas are pseudo-expansion areas. First, check whether these anomaly areas overlap with the readback consistency failure area. The readback consistency failure area refers to the logical address range where the consistency result is "failed". If a local fluctuation anomaly area intersects with the consistency failure area, the intersection is preferentially determined to be a pseudo-expansion area. The basis for this priority determination is that pseudo-expansion areas usually exhibit both latency anomalies and data storage failures.

[0038] To improve detection comprehensiveness, we also need to analyze the union of the local fluctuation anomaly areas and the consistency failure areas. After deducting the intersection area from the union area, the remaining area is used as a candidate area for the pseudo-expansion segment. These candidate areas may contain under-confirmed anomalies and require additional verification.

[0039] like Figure 4 The figure shows the combined use of the two methods. Specifically: Verification method 1: Power off or restart the device for testing.

[0040] Perform a write operation on the candidate area, then simulate a power outage or restart the device, read the data again, and compare it with the original written data. If the read data is inconsistent, the candidate area is determined to be a pseudo-expansion segment.

[0041] This is because, after writing specific data to a candidate area on the memory card, immediately performing a power outage or reboot, and then rereading the data in that area after the device is powered back on, if the read result is all 0s, all FFs, a random value, or old data instead of the data just written, it means that the data in that area was not actually written to the flash media, but was only temporarily stored in the controller cache or returned a "write successful" pseudo-response via the firmware. This is essentially a "temporary cache pseudo-write" behavior. This behavior usually occurs in the logically mapped area of ​​a pseudo-expansion card, because there is no real physical space behind it and it cannot accommodate effective storage.

[0042] Verification method 2: address rollback analysis.

[0043] Another verification method involves performing write and read operations on the candidate area and comparing the read data with previously written data from other address blocks. If the read data closely matches the written data from another address block (for example, a match exceeding 90%), address wrapping may be present, where data from the pseudo-expansion area is being written to the actual capacity. The match threshold can be set between 85% and 95%, depending on the required stringency of the test.

[0044] Based on the above method, the present invention also designs a detection system, which includes the following modules: A capacity analysis module, configured to obtain the nominal capacity information of the memory card to be tested, and divide the logical address into a plurality of test address blocks based on the nominal capacity information; A write control module is used to perform distributed small data write operations in each test address block and record the write delay of each write operation; A read verification module is used to perform a read operation on the data of each test address block, and compare the read result with the original written data for consistency, to obtain a readback consistency result; A curve generating module is used to generate a delay behavior curve, wherein the delay behavior curve has a logical address as a horizontal axis and a write delay as a vertical axis, and a readback consistency result is marked on the horizontal axis; an abnormality identification module, configured to identify a local fluctuation abnormal region in the delay behavior curve and detect whether the abnormal region overlaps with a readback consistency failure region; The pseudo expansion determination module is configured to preferentially determine an intersection area between the local fluctuation abnormal area and the readback consistency failure area as a pseudo expansion area.

[0045] These modules work together to realize the complete process from data collection to anomaly determination.

[0046] To illustrate the present invention more intuitively, consider a case: assuming that the nominal capacity of the memory card to be tested is 64GB, the logical address space is divided into 1024 test address blocks, and each block size is approximately 64MB. 10 logical addresses are randomly selected in each address block, 4KB of data is written, the delay is recorded, and the consistency is verified. After generating the delay behavior curve, a sliding window (window width of 10 address blocks) is used to calculate the standard deviation. If the standard deviation exceeds 5ms, it is marked as an abnormal area. The overlap between the abnormal area and the consistency failure area is further checked, and the candidate area is subjected to a power-off test to finally confirm the pseudo-expansion area.

[0047] In summary, the core advantage of the proposed method for detecting fake capacity expansion lies in its combination of write latency and readback consistency. By analyzing the underlying storage response characteristics, it reveals the physical layer differences that make fake capacity expansion cards difficult to disguise. Delay behavior analysis plays a key role in this method.

[0048] Specifically, when a normal memory card completes a data write, the write latency typically exhibits a stable, continuous, and predictable trend. Even if there are local variations, they do not exhibit noticeable sudden changes. However, since the logical addresses of fake expansion cards that exceed the actual capacity do not have corresponding physical storage resources, they often use firmware spoofing, address wrapping, or temporary caching to disguise successful writes.

[0049] Compared to real physical writes, this camouflage process typically introduces a series of additional intermediate processing steps, such as address remapping within the firmware, data wrapping, pseudo-responses for write results, or temporary cached responses. These processes differ significantly from real write operations at the execution level and cannot fully replicate the timing and circuit overhead required for real flash writes. As a result, they are prone to anomalies in write latency, such as sudden increases in latency (due to internal firmware redirection or erase / write conflicts), wild fluctuations in latency (due to switching between different strategies), and even abnormally low latency (such as returning a pseudo-success signal without actually writing).

[0050] Abnormal latency and data consistency failures often occur together because the pseudo-extension area doesn't actually contain physical storage space, making a true storage loop impossible during write and read operations. When data is written to the pseudo-extension area, the controller may employ a "pseudo-write" strategy, either passing the write command directly through the cache as a successful response or wrapping the data back to the front of the actual capacity. Because this process differs from the standard flash write flow, it may omit underlying operations such as write preparation, page programming, and block erase. Consequently, write latency can be abnormally high (due to wrap-around duplication checking, error handling, or firmware intervention) or unreasonably low (such as returning a "write success" signal without actually writing to disk). Subsequently, during a read, the controller attempts to retrieve data from a nonexistent physical address. This often returns a default value (such as all 0s or all FFs) or the contents of a previous data block, making it impossible to restore the original written data and causing consistency failure.

[0051] The present invention jointly models the write delay and consistency comparison results to generate a behavior curve, so that the delay mutation and consistency failure appear in a highly overlapping pattern in the logical address space, thereby achieving high-confidence identification of the pseudo-expansion area.

[0052] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for detecting false expansion of a memory card, characterized in that: The steps include: Obtaining nominal capacity information of the memory card to be tested, and dividing the logical address into a plurality of test address blocks based on the nominal capacity information; Perform distributed small data write operations in each test address block and record the write latency of each write operation; Perform a read operation on the data of each test address block, and compare the read result with the original written data to obtain a readback consistency result; Generate a delay behavior curve, wherein the delay behavior curve has the logical address as the horizontal axis and the write delay as the vertical axis, and the readback consistency result is marked on the horizontal axis; A local fluctuation abnormal area in the delay behavior curve is identified. If a readback consistency failure area overlaps with the local fluctuation abnormal area, an intersection area of ​​the local fluctuation abnormal area and the readback consistency failure area is preferentially determined as a pseudo expansion area.

2. The memory card false expansion detection method according to claim 1, characterized in that: When an area within a sliding window has the following conditions, the area within the sliding window is determined to be a local fluctuation abnormal area: the local fluctuation amplitude of the delay curve within the sliding window is greater than a preset allowable range.

3. The memory card false expansion detection method according to claim 1, characterized in that: The template comparison method is used to identify the local fluctuation abnormal area, which specifically includes the following steps: Establishing a delay behavior template library, wherein the delay behavior template library includes a plurality of delay template curves generated by a normal capacity memory card; The delay behavior curve of the memory card under test is segmented using a sliding window method. Each sliding window corresponds to a local area, and the delay subsequence within the window is extracted as the detection segment. Comparing each detection segment with the template segment at the corresponding position in the delay behavior template library for similarity; If the similarity between any detection segment and the template segment is lower than a preset threshold, the area covered by the corresponding sliding window is marked as a local fluctuation abnormality area.

4. The memory card false expansion detection method according to claim 3, characterized in that: The similarity measurement method includes any one of the following: Euclidean distance, cosine similarity or dynamic time warping distance.

5. The memory card false expansion detection method according to claim 1, characterized in that: The method further includes: determining a union area of ​​the local fluctuation abnormal area and the consistency failure area, after deducting the intersection area, as a candidate area of ​​the pseudo expansion segment.

6. The memory card false expansion detection method according to claim 5, characterized in that: The method further includes: performing a write operation on the candidate area, performing a power-off or device restart operation, and reading original data from the candidate area again. If a consistency failure occurs, the candidate area is determined to be a pseudo-expansion segment.

7. The memory card false expansion detection method according to claim 5, characterized in that: The method further includes: performing write and read operations on the candidate area, and comparing the read data with previously written data of other address blocks, and if the matching degree exceeds a preset threshold, determining that the candidate area is a pseudo expansion segment.

8. A memory card false expansion detection system, characterized in that: include: A capacity analysis module, configured to obtain the nominal capacity information of the memory card to be tested, and divide the logical address into a plurality of test address blocks based on the nominal capacity information; A write control module is used to perform distributed small data write operations in each test address block and record the write delay of each write operation; A read verification module is used to perform a read operation on the data of each test address block, and compare the read result with the original written data for consistency, to obtain a readback consistency result; A curve generating module is used to generate a delay behavior curve, wherein the delay behavior curve has a logical address as a horizontal axis and a write delay as a vertical axis, and a readback consistency result is marked on the horizontal axis; an abnormality identification module, configured to identify a local fluctuation abnormal region in the delay behavior curve and detect whether the abnormal region overlaps with a readback consistency failure region; The pseudo expansion determination module is configured to preferentially determine an intersection area between the local fluctuation abnormal area and the readback consistency failure area as a pseudo expansion area.

9. The memory card false expansion detection system according to claim 8, characterized in that: The abnormality identification module determines that a region within a sliding window is a local fluctuation abnormal region when the following conditions exist in the region within the sliding window: the local fluctuation amplitude of the delay curve within the sliding window is greater than a preset allowable range.

10. The memory card false expansion detection system according to claim 8, characterized in that: The pseudo expansion determination module further determines a union area of ​​the local fluctuation abnormal area and the consistency failure area, after deducting the intersection area, as a candidate area of ​​the pseudo expansion segment.

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