Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate, a scanning line and a driving module, wherein the scanning line and the driving module are arranged on the substrate; at least two transistors in the driving circuit are provided with first grids and second grids; at least part of the second grid electrode is located between the first grid electrode and the substrate; bottom gate via holes of at least two transistors of the driving circuit are arranged along a first direction; the second grid electrode is electrically connected with a connecting part through the bottom grid via hole, and the connecting part is electrically connected with the first grid electrode; or the second grid electrode is electrically connected with the first grid electrode through the bottom grid via hole; the first direction intersects with the second direction, and each scanning line comprises at least one part extending in the second direction. According to the embodiment of the invention, the bottom gate via holes of the at least two transistors of the driving circuit are arranged along the first direction, so that the transverse space occupied by the driving circuit is narrowed, and the realization of a narrow frame is facilitated.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Consumers are increasingly demanding a higher screen-to-body ratio for mobile display devices, which means narrowing the bezel is becoming a major trend. GOA (Gate on Array) circuits are typically designed to be arranged on both sides of the pixel circuit. The cascaded GOA circuits contain numerous capacitors, thin-film transistors, and signal lines. The increased number of GOA control units also occupies a significant amount of space. Therefore, it is necessary to rationally design the placement of components and shared signal routing to reduce the space occupied by the GOA circuits and facilitate the narrowing of the display's bezel.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate, and scan lines and a driving module disposed on the substrate, wherein the driving module comprises a multi-stage driving circuit, and the driving circuit is configured to provide a driving signal to the scan lines;

[0005] At least two transistors in the driving circuit have a first gate and a second gate; at least a portion of the second gate is located between the first gate and the substrate;

[0006] The bottom gate vias of at least two transistors of the driving circuit are arranged along a first direction;

[0007] The second gate is electrically connected to the connecting portion through the bottom gate via, and the connecting portion is electrically connected to the first gate; or the second gate is electrically connected to the first gate through the bottom gate via;

[0008] The first direction intersects with a second direction, and the scan line includes at least a portion extending along the second direction.

[0009] Optionally, an orthographic projection of a bottom gate via of at least one transistor included in the driving circuit on the substrate and an orthographic projection of an electrode of another transistor electrically connected to the transistor on the substrate are arranged along a first direction.

[0010] Optionally, a minimum distance between an orthographic projection of a bottom gate via of at least one transistor included in the driving circuit on the substrate and an orthographic projection of an electrode of another transistor electrically connected to the transistor on the substrate is smaller than a distance threshold.

[0011] Optionally, the driving circuit includes an output circuit, the output circuit being electrically connected to the first output node, the second output node, and the driving signal output terminal, respectively, and configured to generate a driving signal under the control of the potential of the first output node and the potential of the second output node, and provide the driving signal through the driving signal output terminal;

[0012] The length of the active pattern of at least one transistor included in the output circuit along the second direction is smaller than a first length threshold.

[0013] Optionally, the active pattern includes N mutually independent active pattern portions, the active pattern portions extend along the second direction, and N is an integer greater than 1.

[0014] Optionally, the driving circuit includes at least one energy storage circuit, and the energy storage circuit includes a capacitor;

[0015] A length of an orthographic projection of at least one capacitor included in the driving circuit on the substrate along the second direction is smaller than a second length threshold.

[0016] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a first output node setting circuit, a third node control circuit, a first output node control circuit, a control node control circuit, a second output node control circuit, a first energy storage circuit, and an output circuit;

[0017] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0018] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0019] The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node;

[0020] The third node control circuit is electrically connected to the first node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the first node;

[0021] The first output node control circuit is electrically connected to the third node, the second clock signal line, and the first output node, respectively, and is configured to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0022] The control node control circuit is electrically connected to the initial control line, the first voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the first voltage line under the control of the initial control signal provided by the initial control line;

[0023] The second output node control circuit is electrically connected to the second output node and the fourth node respectively, and is used to control the potential of the second output node according to the potential of the fourth node;

[0024] The first energy storage circuit is electrically connected to the second node and the fourth node respectively, and is used to store electrical energy;

[0025] The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

[0026] Optionally, the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor; the first output node setting circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; and the first energy storage circuit includes a first capacitor;

[0027] The control node control circuit includes a fifth transistor, the second output node control circuit includes a sixth transistor; the output circuit includes a seventh transistor and an eighth transistor;

[0028] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node;

[0029] a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node;

[0030] A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node;

[0031] a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node;

[0032] A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node;

[0033] The first gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0034] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0035] A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line;

[0036] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the fourth node.

[0037] Optionally, the orthographic projection of the bottom gate via of the fourth transistor on the substrate, the orthographic projection of the bottom gate via of the seventh transistor on the substrate, the orthographic projection of the bottom gate via of the third transistor on the substrate, the orthographic projection of the bottom gate via of the fifth transistor on the substrate, and the orthographic projection of the bottom gate via of the eighth transistor on the substrate are arranged along a first direction.

[0038] Optionally, an orthographic projection of the bottom gate via of the second transistor on the substrate and an orthographic projection of the second electrode of the first transistor on the substrate are arranged along a first direction.

[0039] Optionally, the control node is directly connected to the second output node; or,

[0040] The driving circuit further includes a first on-off control circuit;

[0041] The first on-off control circuit is electrically connected to the second voltage line, the control node and the second output node respectively, and is used to control the connection or disconnection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line.

[0042] Optionally, the driving circuit further includes a first on-off control circuit; the first on-off control circuit includes a ninth transistor;

[0043] a first gate of the ninth transistor is electrically connected to the second voltage line, a first electrode of the ninth transistor is electrically connected to the control node, and a second electrode of the ninth transistor is electrically connected to the second output node;

[0044] An orthographic projection of the bottom gate via hole of the ninth transistor on the substrate and an orthographic projection of the bottom gate via hole of the sixth transistor on the substrate are arranged along a first direction.

[0045] Optionally, a length of a positive projection of the first capacitor on the substrate along the second direction is less than a second length threshold.

[0046] Optionally, a length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

[0047] Optionally, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first output node control circuit, a first output node setting circuit, a control node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit, and a third energy storage circuit;

[0048] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0049] The second node control circuit is electrically connected to the second node and is used to control the potential of the second node;

[0050] The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node;

[0051] The third node control circuit is electrically connected to the fifth node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the fifth node;

[0052] The first output node control circuit is electrically connected to the third node, the second clock signal line and the first output node respectively, and is used to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0053] The control node control circuit is electrically connected to the input terminal, the first clock signal line, the initial control line, the first voltage line, and the control node, respectively, and is configured to control the connection or disconnection between the control node and the first voltage line under the control of an initial control signal provided by the initial control line, and to control the connection or disconnection between the control node and the input terminal under the control of a first clock signal provided by the first clock signal line;

[0054] The first energy storage circuit is electrically connected to the second node and the second output node respectively, and is used to store electrical energy;

[0055] A first end of the second energy storage circuit is electrically connected to the first node, a second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;

[0056] The third energy storage circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0057] The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

[0058] Optionally, the first node control circuit includes a first transistor and a thirteenth transistor, and the second node control circuit includes a second transistor and a tenth transistor; the first output node set circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; the control node control circuit includes a fifth transistor and an eleventh transistor, and the output circuit includes a seventh transistor and an eighth transistor; and the third node control circuit includes a twelfth transistor;

[0059] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node;

[0060] a first gate of the thirteenth transistor is electrically connected to the control node, a first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and a second electrode of the thirteenth transistor is electrically connected to the first node;

[0061] a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node;

[0062] a first gate of the tenth transistor is electrically connected to the second output node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the second node;

[0063] A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node;

[0064] a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node;

[0065] A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node;

[0066] a first gate of the eleventh transistor being electrically connected to the first clock signal line, a first electrode of the eleventh transistor being electrically connected to the input terminal, and a second electrode of the eleventh transistor being electrically connected to the control node;

[0067] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0068] A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line;

[0069] a first gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the third node;

[0070] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the second output node;

[0071] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the third node;

[0072] The first plate of the third capacitor is electrically connected to the first output node, and the second plate of the third capacitor is electrically connected to the first voltage line.

[0073] Optionally, the orthographic projection of the plate of the second capacitor on the substrate is at least partially arranged around the orthographic projection of the bottom gate via of the eleventh transistor on the substrate.

[0074] Optionally, an orthographic projection of the second electrode of the eleventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate are arranged along a first direction.

[0075] Optionally, an orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate and an orthographic projection of the first electrode of the first transistor on the substrate are arranged along a first direction.

[0076] Optionally, an orthographic projection of the bottom gate via hole of the twelfth transistor on the substrate, an orthographic projection of the bottom gate via hole of the seventh transistor on the substrate, and an orthographic projection of the bottom gate via hole of the fifth transistor on the substrate are arranged along a first direction.

[0077] Optionally, an orthographic projection of the bottom gate via hole of the fourth transistor on the substrate and an orthographic projection of the second electrode of the third transistor on the substrate are arranged along the second direction.

[0078] Optionally, an orthographic projection of the bottom gate via hole of the tenth transistor on the substrate and an orthographic projection of the plate of the first capacitor on the substrate are arranged along the second direction.

[0079] Optionally, a length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

[0080] Optionally, the control node is directly connected to the second output node; the first node is electrically connected to the fifth node; or,

[0081] The driving circuit further includes a first on-off control circuit and a second on-off control circuit;

[0082] The first on-off control circuit is electrically connected to the second voltage line, the control node and the second output node respectively, and is used to control the connection or disconnection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line;

[0083] The second on-off control circuit is electrically connected to the second voltage line, the first node and the fifth node respectively, and is used to control the connection or disconnection between the first node and the fifth node under the control of a second voltage signal provided by the second voltage line.

[0084] Optionally, the driving circuit includes a first output node control circuit, a sixth node control circuit, a second output node control circuit and an output circuit;

[0085] The first output node control circuit is used to control the potential of the first output node;

[0086] The sixth node control circuit is used to control the potential of the sixth node;

[0087] The second output node control circuit is used to control the potential of the second output node according to the potential of the sixth node;

[0088] The output circuit is used to control the supply of a driving signal through the driving signal output terminal based on the potential of the first output node and the potential of the second output node.

[0089] Optionally, the first output node control circuit includes a first transistor and a ninth transistor;

[0090] A first gate of the first transistor is electrically connected to a first clock signal line, a first electrode of the first transistor is electrically connected to a second voltage line, and a second electrode of the first transistor is electrically connected to the first output node;

[0091] a first gate of the ninth transistor is electrically connected to the sixth node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first output node;

[0092] The sixth node control circuit includes an eleventh transistor, a fourteenth transistor, and a fifteenth transistor;

[0093] The first gate of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the input terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node;

[0094] a first gate of the fourteenth transistor is electrically connected to the first output node, a first electrode of the fourteenth transistor is electrically connected to the first voltage line, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

[0095] The first gate of the fifteenth transistor is electrically connected to the second clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the sixth node;

[0096] The second output node control circuit includes a sixteenth transistor;

[0097] A first gate of the sixteenth transistor is electrically connected to the second voltage line, a first electrode of the sixteenth transistor is electrically connected to the sixth node, and a second electrode of the sixteenth transistor is electrically connected to the second output node;

[0098] The output circuit includes a seventh transistor and an eighth transistor;

[0099] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0100] The first gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the driving signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal line.

[0101] Optionally, an orthographic projection of the bottom gate via hole of the eleventh transistor on the substrate, an orthographic projection of the bottom gate via hole of the ninth transistor on the substrate, and an orthographic projection of the bottom gate via hole of the sixteenth transistor on the substrate are arranged along a first direction.

[0102] Optionally, an orthographic projection of the bottom gate via hole of the seventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the eighth transistor on the substrate are arranged along a first direction.

[0103] Optionally, the eleventh transistor in the current stage driving circuit, the first transistor in the current stage driving circuit and the fifteenth transistor in the adjacent previous stage driving circuit share a bottom gate via of the transistor.

[0104] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] FIG1 is a structural diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0106] FIG2 is a circuit diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0107] FIG3 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG2 ;

[0108] 4A and 4B are layout diagrams of at least one embodiment of the driving circuit shown in FIG. 2 ;

[0109] FIG5 is a layout diagram of the light-shielding metal layer in FIG4A;

[0110] FIG6 is a layout diagram of the semiconductor layer in FIG4A;

[0111] FIG7 is a layout diagram of the first gate metal layer in FIG4A ;

[0112] FIG8 is a layout diagram of the second gate metal layer in FIG4A;

[0113] FIG9 is a layout diagram of the first source / drain metal layer in FIG4A ;

[0114] FIG10 is a layout diagram of the second source / drain metal layer in FIG4A ;

[0115] FIG11A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in FIG4A ;

[0116] 11B is a schematic diagram of the superposition of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG. 4A ;

[0117] 11C is a schematic diagram of the superposition of the first source / drain metal layer and the second source / drain metal layer in FIG. 4A ;

[0118] FIG. 11D is a schematic diagram of the superposition of the light-shielding metal layer and the semiconductor layer in FIG. 4A

[0119] FIG12 is a structural diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0120] FIG13 is a circuit diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0121] 14A and 14B are layout diagrams of at least one embodiment of the driving circuit shown in FIG. 13 ;

[0122] FIG15 is a layout diagram of the light-shielding metal layer in FIG14A;

[0123] FIG16 is a layout diagram of the semiconductor layer in FIG14A;

[0124] FIG17 is a layout diagram of the first gate metal layer in FIG14A;

[0125] FIG18 is a layout diagram of the second gate metal layer in FIG14A;

[0126] FIG19 is a layout diagram of the third gate metal layer in FIG14A;

[0127] FIG20 is a layout diagram of the first source / drain metal layer in FIG14A;

[0128] FIG21 is a layout diagram of the second source / drain metal layer in FIG14A;

[0129] FIG22A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in FIG14A ;

[0130] FIG22B is a schematic diagram of the superposition of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG14A;

[0131] FIG22C is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG14A;

[0132] FIG22D is a layout diagram of the light-shielding metal layer and the semiconductor layer in FIG14A;

[0133] FIG23 is a structural diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0134] FIG24 is a circuit diagram of at least one embodiment of a driving circuit in a display substrate according to the present disclosure;

[0135] 25A and 25B are layout diagrams of at least one embodiment of the driving circuit shown in FIG. 24 ;

[0136] FIG26 is a layout diagram of the light-shielding metal layer in FIG25A;

[0137] FIG27 is a layout diagram of the semiconductor layer in FIG25A;

[0138] FIG28 is a layout diagram of the first gate metal layer in FIG25A ;

[0139] FIG29 is a layout diagram of the second gate metal layer in FIG25A;

[0140] FIG30 is a layout diagram of the first source / drain metal layer in FIG25A;

[0141] FIG31 is a layout diagram of the second source / drain metal layer in FIG25A .

[0142] FIG32A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in FIG25A;

[0143] FIG32B is a schematic diagram of the superposition of the first source / drain metal layer and the second source / drain metal layer in FIG25A ;

[0144] FIG32C is a schematic diagram showing the superposition of the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG25A ;

[0145] FIG32D is a schematic diagram showing the superposition of the light-shielding metal layer and the semiconductor layer in FIG25A . DETAILED DESCRIPTION

[0146] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0147] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0148] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0149] The display substrate of the embodiment of the present disclosure includes a substrate, a scan line and a driving module provided on the substrate, wherein the driving module includes a multi-stage driving circuit, and the driving circuit is used to provide a driving signal for the scan line;

[0150] At least two transistors in the driving circuit have a first gate and a second gate; at least a portion of the second gate is located between the first gate and the substrate;

[0151] The bottom gate vias of at least two transistors of the driving circuit are arranged along a first direction;

[0152] The second gate is electrically connected to the connecting portion through the bottom gate via, and the connecting portion is electrically connected to the first gate; or the second gate is electrically connected to the first gate through the bottom gate via;

[0153] The first direction intersects with a second direction, and the scan line includes at least a portion extending along the second direction.

[0154] In related drive circuits, transistors typically have a single-gate design, employing a top-gate solution in which a first gate metal layer is placed above a semiconductor layer. However, with this structure, transistor characteristics are susceptible to deviation. To ensure the stability of transistor characteristics, in at least one embodiment of the present disclosure, a light-shielding metal layer is added to the side of the transistor's semiconductor layer close to the substrate. The light-shielding metal layer includes the transistor's second gate, forming a top-bottom dual-gate design. The newly added second gate needs to be connected to the transistor's first gate via a transfer hole, requiring optimized layout space to reduce the border.

[0155] In at least one embodiment of the present disclosure, bottom gate vias of at least two transistors of the driving circuit are arranged along a first direction to narrow the lateral space occupied by the driving circuit, thereby facilitating a narrow frame.

[0156] During the specific implementation, since the punched connectors take up a large space when the lines jump between layers, the punched adapters should be arranged in a staggered manner, and as many adapter holes as possible should be placed in the same column to facilitate space compression.

[0157] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction, but is not limited thereto.

[0158] In at least one embodiment of the present disclosure, an orthographic projection of a bottom gate via of at least one transistor included in the driving circuit on the substrate and an orthographic projection of an electrode of another transistor electrically connected to the transistor on the substrate are arranged along a first direction.

[0159] Optionally, an electrode of another transistor electrically connected to the transistor may be a first electrode or a second electrode, but is not limited thereto.

[0160] In a specific implementation, the bottom gate via of the transistor can be arranged close to the first electrode and / or second electrode of another transistor electrically connected to the transistor, thereby reducing the length of the transfer hole connection while avoiding the transistor structure, thereby compressing the layout space.

[0161] Optionally, the distance threshold may be greater than or equal to 1 μm and less than or equal to 2 μm, but is not limited thereto.

[0162] In at least one embodiment of the present disclosure, the driving circuit includes an output circuit, the output circuit being electrically connected to a first output node, a second output node, and a driving signal output terminal, respectively, and configured to generate a driving signal under the control of a potential of the first output node and a potential of the second output node, and provide the driving signal through the driving signal output terminal;

[0163] The length of the active pattern of at least one transistor included in the output circuit along the second direction is smaller than a first length threshold.

[0164] In a specific implementation, the driving circuit may include an output circuit, which generates a driving signal under the control of the potential of the first output node and the potential of the second output node. The active pattern of at least one transistor included in the output circuit has a smaller length along the second direction, that is, the width of the active pattern of at least one transistor included in the output circuit along the horizontal direction is narrowed, which is conducive to achieving a narrow frame.

[0165] Optionally, the first length threshold may be greater than or equal to 45 μm and less than or equal to 55 μm, but is not limited thereto.

[0166] In at least one embodiment of the present disclosure, the active pattern includes N mutually independent active pattern portions, the active pattern portions extend along the second direction, and N is an integer greater than 1.

[0167] In at least one embodiment of the present disclosure, the driving circuit includes at least one energy storage circuit, and the energy storage circuit includes a capacitor;

[0168] A length of an orthographic projection of at least one capacitor included in the driving circuit on the substrate along the second direction is smaller than a second length threshold.

[0169] In a specific implementation, the length of the orthographic projection of at least one capacitor in the driving circuit on the substrate along the second direction can be set to be relatively small, which is conducive to achieving a narrow frame.

[0170] Optionally, the second length threshold may be greater than or equal to 25 μm and less than or equal to 36 μm, but is not limited thereto.

[0171] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit, a second node control circuit, a first output node setting circuit, a third node control circuit, a first output node control circuit, a control node control circuit, a second output node control circuit, a first energy storage circuit, and an output circuit;

[0172] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0173] The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node;

[0174] The third node control circuit is electrically connected to the first node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the first node;

[0175] The first output node control circuit is electrically connected to the third node, the second clock signal line and the first output node respectively, and is used to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0176] The control node control circuit is electrically connected to the initial control line, the first voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the first voltage line under the control of the initial control signal provided by the initial control line;

[0177] The second output node control circuit is electrically connected to the second output node and the fourth node respectively, and is used to control the potential of the second output node according to the potential of the fourth node;

[0178] The first energy storage circuit is electrically connected to the second node and the fourth node respectively, and is used to store electrical energy;

[0179] The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

[0180] Optionally, the first voltage line may be a high voltage line, but is not limited thereto.

[0181] Optionally, the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor; the first output node setting circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; and the first energy storage circuit includes a first capacitor;

[0182] The control node control circuit includes a fifth transistor, the second output node control circuit includes a sixth transistor; the output circuit includes a seventh transistor and an eighth transistor;

[0183] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node;

[0184] a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node;

[0185] A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node;

[0186] a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node;

[0187] A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node;

[0188] The first gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0189] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0190] A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line;

[0191] The first electrode plate of the first capacitor is electrically connected to the second node, and the second electrode plate of the first capacitor is electrically connected to the fourth node.

[0192] In at least one embodiment of the present disclosure, the orthographic projection of the bottom gate via of the fourth transistor on the substrate, the orthographic projection of the bottom gate via of the seventh transistor on the substrate, the orthographic projection of the bottom gate via of the third transistor on the substrate, the orthographic projection of the bottom gate via of the fifth transistor on the substrate, and the orthographic projection of the bottom gate via of the eighth transistor on the substrate are arranged along a first direction.

[0193] In at least one embodiment of the present disclosure, the control node is directly connected to the second output node; or,

[0194] The driving circuit further includes a first on-off control circuit;

[0195] The first on-off control circuit is electrically connected to the second voltage line, the control node and the second output node respectively, and is used to control the connection or disconnection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line.

[0196] In a specific implementation, the control node can be directly connected to the second output node; or, the driving circuit also includes a first on-off control circuit; the control node is electrically connected to the second output node through the first on-off control circuit, and the first on-off control circuit controls the connection or disconnection between the control node and the second output node under the control of a second voltage signal.

[0197] Optionally, when the transistor included in the first on-off control circuit is a p-type transistor, the second voltage line may be a low voltage line;

[0198] When the transistor included in the first on-off control circuit is an n-type transistor, the second voltage line may be a high voltage line.

[0199] As shown in FIG1 , at least one embodiment of the driving circuit may include a first node control circuit 11, a second node control circuit 12, a first output node setting circuit 13, a third node control circuit 14, a first output node control circuit 15, a control node control circuit 16, a second output node control circuit 17, a first energy storage circuit 18, an output circuit 19, and a first on-off control circuit 110.

[0200] The first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;

[0201] The second node control circuit 12 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0202] The first output node setting circuit 13 is electrically connected to the control node NC, the first output node N01 and the first voltage line V1 respectively, and is used to control the connection between the first output node N01 and the first voltage line V1 under the control of the potential of the control node NC;

[0203] The third node control circuit 14 is electrically connected to the first node N1 and the third node N3, respectively, and is configured to control the potential of the third node N3 under the control of the potential of the first node N1;

[0204] The first output node control circuit 15 is electrically connected to the third node N3, the second clock signal line CB, and the first output node N01, respectively, and is configured to control the connection or disconnection between the third node N3 and the first output node N01 under the control of the second clock signal provided by the second clock signal line CB;

[0205] The control node control circuit 16 is electrically connected to the initial control line CX, the first voltage line V1 and the control node NC, respectively, and is used to control the connection or disconnection between the control node NC and the first voltage line V1 under the control of the initial control signal provided by the initial control line CX;

[0206] The second output node control circuit 17 is electrically connected to the second output node N02 and the fourth node N4, respectively, and is configured to control the potential of the second output node N02 according to the potential of the fourth node N4;

[0207] The first energy storage circuit 18 is electrically connected to the second node N2 and the fourth node N4 respectively, and is used to store electrical energy;

[0208] The output circuit 19 is electrically connected to the first output node N01, the second output node N02 and the drive signal output terminal OT, respectively, and is used to control the output drive signal under the control of the potential of the first output node N01 and the potential of the second output node N02, and provide the drive signal through the drive signal output terminal OT;

[0209] The first on-off control circuit 110 is electrically connected to the second voltage line V2, the control node NC and the second output node N02 respectively, and is used to control the connection or disconnection between the control node NC and the second output node N02 under the control of the second voltage signal provided by the second voltage line V2.

[0210] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line, but the present invention is not limited thereto.

[0211] At least one embodiment of the driving circuit shown in FIG1 may be a GOA (Gate On Array) circuit for providing a scan signal, a GOA circuit for providing a reset control signal, or a GOA circuit for providing a light emitting control signal.

[0212] Optionally, the driving circuit further includes a first on-off control circuit; the first on-off control circuit includes a ninth transistor;

[0213] a first gate of the ninth transistor is electrically connected to the second voltage line, a first electrode of the ninth transistor is electrically connected to the control node, and a second electrode of the ninth transistor is electrically connected to the second output node;

[0214] An orthographic projection of the bottom gate via hole of the ninth transistor on the substrate and an orthographic projection of the bottom gate via hole of the sixth transistor on the substrate are arranged along a first direction.

[0215] Optionally, the first direction may be a vertical direction, but is not limited thereto.

[0216] As shown in FIG2 , based on at least one embodiment of the driving circuit shown in FIG1 , the first node control circuit may include a first transistor T1, the second node control circuit may include a second transistor T2; the first output node set circuit may include a third transistor T3, the first output node control circuit may include a fourth transistor T4; the first energy storage circuit may include a first capacitor C1;

[0217] The control node control circuit includes a fifth transistor T5, the second output node control circuit includes a sixth transistor T6; the output circuit includes a seventh transistor T7 and an eighth transistor T8;

[0218] The first gate of the first transistor T1 is electrically connected to the first clock signal line CK, the first electrode of the first transistor T1 is electrically connected to the low voltage line VGL, and the second electrode of the first transistor T1 is electrically connected to the first node N1;

[0219] a first gate of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the high voltage line VGH, and a second electrode of the second transistor T2 is electrically connected to the second node N2;

[0220] A first gate of the third transistor T3 is electrically connected to the control node NC, a first electrode of the third transistor T3 is electrically connected to the high voltage line VGH, and a second electrode of the third transistor T3 is electrically connected to the first output node N01;

[0221] A first gate of the fourth transistor T4 is electrically connected to the second clock signal line CB, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, and a second electrode of the fourth transistor T4 is electrically connected to the first output node N01;

[0222] A first gate of the fifth transistor T5 is electrically connected to the initial control line CX, a first electrode of the fifth transistor T5 is electrically connected to the high voltage line VGH, and a second electrode of the fifth transistor T5 is electrically connected to the control node NC;

[0223] The first gate of the sixth transistor T6 and the first electrode of the sixth transistor T6 are electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the second output node N02;

[0224] A first gate of the seventh transistor T7 is electrically connected to the first output node N01, a first electrode of the seventh transistor T7 is electrically connected to the high voltage line VGH, and a second electrode of the seventh transistor T7 is electrically connected to the driving signal output terminal OT;

[0225] A first gate of the eighth transistor T8 is electrically connected to the second output node N02, a first electrode of the eighth transistor T8 is electrically connected to the drive signal output terminal OT, and a second electrode of the eighth transistor T8 is electrically connected to the low voltage line VGL;

[0226] The first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4;

[0227] The first node control circuit further includes a thirteenth transistor T13; the second node control circuit further includes a fourteenth transistor T14; the first output node control circuit further includes a fifteenth transistor T15, a sixteenth transistor T16 and a second capacitor C2;

[0228] The control node control circuit further includes a seventeenth transistor T17;

[0229] The second output node control circuit further includes an eighteenth transistor T18 and a nineteenth transistor T19;

[0230] The first on-off control circuit includes a ninth transistor T9;

[0231] A first gate of the ninth transistor T9 is electrically connected to the low voltage line VGL, a first electrode of the ninth transistor T9 is electrically connected to the control node NC, and a second electrode of the ninth transistor is electrically connected to the second output node N02;

[0232] The driving circuit may further include a third capacitor C3;

[0233] The first gate of T13 is electrically connected to the control node NC, the first electrode of T13 is electrically connected to the first node N1, and the second electrode of T13 is electrically connected to the first clock signal line CK;

[0234] The first gate of T14 is electrically connected to the fourth node N4, the first electrode of T14 is electrically connected to the second node N2, and the second electrode of T14 is electrically connected to the second clock signal line CB;

[0235] The first gate of T16 is electrically connected to the low voltage line VGL, the first electrode of T16 is electrically connected to the first node N1, and the second electrode of T16 is electrically connected to the first gate of T15;

[0236] A first electrode of T15 is electrically connected to the second clock signal line CB, and a second electrode of T15 is electrically connected to the third node N3;

[0237] The first electrode plate of C2 is electrically connected to the first gate of T15, and the second electrode plate of C2 is electrically connected to the third node N3;

[0238] The first gate of T17 is electrically connected to the first clock signal line CK, the first electrode of T17 is electrically connected to the input terminal STV, and the second electrode of T17 is electrically connected to the control node NC;

[0239] The first gate of T18 is electrically connected to the first clock signal line CK, the first electrode of T18 is electrically connected to the input terminal STV, and the second electrode of T18 is electrically connected to the first electrode of T19;

[0240] A first gate electrode of T19 is electrically connected to the low voltage line VGL, and a second electrode of T19 is electrically connected to the fourth node N4;

[0241] The first plate of C3 is electrically connected to the gate of T7 , and the second plate of C3 is electrically connected to the high voltage line VGH.

[0242] In at least one embodiment of the driving circuit shown in FIG. 2 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0243] In at least one embodiment of the driving circuit shown in FIG2 , each transistor is a dual-gate transistor, the first gate of each transistor is a top gate, the second gate of each transistor is a bottom gate, and the first gate of each transistor is electrically connected to the second gate of the transistor.

[0244] FIG. 3 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 2 .

[0245] As shown in FIG3 , when at least one embodiment of the driving circuit shown in FIG2 is in operation,

[0246] During the first time period t1, STV provides a high voltage signal, CK provides a low voltage signal, T17 and T18 are turned on, the potential of NC is high, T13 is turned off, the gate voltage of T6 is high, T14 and T6 are turned off, T1 is turned on, the potential of N1 is low, so T3 and T8 are turned off, and T2 and T15 are turned on. CB provides a high voltage signal, and the potential of N3 is high at this time, so T4 is turned off. Since the voltage across C3 does not change suddenly, the potential of N01 remains at the high level of the previous frame. T7 is turned off, and the potential of the drive signal output by OT remains at the low level of the previous frame.

[0247] In the second time period t2, STV and CK provide high voltage signals, CB provides a low voltage signal, T17, T13, and T1 are turned off, the potential of NC remains at a high voltage, the potential of N1 remains at a low voltage, T15 is turned on, the potential of N3 changes from a high voltage to a low voltage, T4 is turned on, the potential of N01 is a low voltage, T7 is turned on and outputs a high level; T17, T14, T6, T3, and T8 are turned off, and OT outputs a high voltage signal;

[0248] In the third time period t3, STV and CB output high voltage signals, CK provides a low voltage, T17 and T18 are turned on, the potential of NC is high voltage, T13 is turned off, the potential of N4 is high voltage, T14 and T6 are turned off, T1 is turned on, the potential of N1 is low voltage, T15 is turned on, the potential of N3 changes from the low voltage of the previous time period to high voltage; T4 is turned off, the potential of N01 remains low voltage, T7 is turned on and outputs a high level; T3 and T8 are turned off, and OT outputs a high voltage signal;

[0249] In the fourth time period t4, STV and CK provide a high voltage, CB provides a low voltage signal, T17, T18 and T1 are turned off, the potentials of NC and N4 are high, T14 and T6 are turned off, T13 is turned off, the potential of N1 remains at a low voltage, T15 is turned on, the potential of N3 jumps to a low level, T4 is turned on, the potential of N01 is a low voltage, T7 is turned on and outputs a high level, T3 and T8 are turned off, and OT outputs a high voltage signal; to cooperate with the 3Pulse output of the IC (integrated circuit) signal, the potential of the input signal provided by STV during this period can be changed to a low level without affecting the overall GOA (Gate On Array, a gate drive circuit provided on the array substrate) function;

[0250] In the fifth time period t5, STV and CK provide low voltage signals, CB provides a high voltage signal, T17 and T18 are turned on, the potentials of NC and N4 become low voltages, T13 and T1 are turned on, the potential of N1 is low voltage, T2 and T15 are turned on, the potential of N2 is high voltage, the potential of N3 becomes high voltage, T4 is turned off, T3 is turned on, the potential of N01 becomes high level, and T7 is turned off; due to the dynamic changes in the potentials of N02 and N4, the potential of N4 is directly affected by C3, the potential drop rate of N02 is greater than the potential drop rate of N4, T6 is turned off, T8 is fully turned on, and OT outputs a low voltage signal;

[0251] In the sixth time period t6, STV and CB provide low voltage signals, CK provides a high voltage signal, T17, T18, and T1 are turned off, the potential of NC and the potential of N4 are maintained at a low level, T13 is turned on, the potential of N1 and the gate voltage of T15 are high, T2 and T15 are turned off, the potential of N3 becomes high due to the influence of C2, T4 and T3 are turned on, the potential of N01 is high, and T7 is turned off; since the potential of N4 is low voltage, T14 is turned on, the potential of N2 becomes low voltage, the potential of N4 decreases due to the influence of C1, T6 is turned on, maintaining the low voltage state of N02, ensuring that T8 is fully turned on, and OT outputs a low voltage signal;

[0252] In the seventh time period t7, STV and CK provide low voltage signals, CB provides a high voltage signal, T17, T18, T13 and T1 are turned on, the potentials of NC, N1 and N4 are low, T14 and T2 are turned on, the potential of N2 becomes high, the potential of N4 is pulled high under the influence of C1, T6 is turned off; T4 is turned off, T3 is turned on, the potential of N01 is high, T7 is turned off; the potential of NC is pulled low, T9 is turned off, the potential of N02 remains at the low level of the previous frame, T8 is fully turned on, and OT outputs a low voltage signal;

[0253] After the sixth time period t7, the seventh time period t7 and the eighth time period t8 cycle, T3 is continuously turned on, T7 is turned off, T18 and T19 periodically charge C1, T9 and T6 remain turned off, the potential of NO2 remains at a low level, T8 is continuously fully turned on and outputs a low level until the next frame of STV signal pulse enters, and the operating state of this stage of the driving circuit returns to t1 again.

[0254] Figures 4A and 4B are layout diagrams of at least one embodiment of the driving circuit shown in Figure 2. Figure 5 is a layout diagram of the light-shielding metal layer in Figure 4A, Figure 6 is a layout diagram of the semiconductor layer in Figure 4A, Figure 7 is a layout diagram of the first gate metal layer in Figure 4A, Figure 8 is a layout diagram of the second gate metal layer in Figure 4A, Figure 9 is a layout diagram of the first source / drain metal layer in Figure 4A, and Figure 10 is a layout diagram of the second source / drain metal layer in Figure 4A.

[0255] In FIG. 4A to FIG. 32D , the direction labeled Y may be the first direction, and the direction labeled X may be the second direction.

[0256] In FIG4A , HG4 is the bottom gate via of the fourth transistor, HG7 is the bottom gate via of the seventh transistor, HG3 is the bottom gate via of the third transistor, HG5 is the bottom gate via of the fifth transistor, and HG8 is the bottom gate via of the eighth transistor;

[0257] HG4, HG7, HG3, HG5 and HG8 are arranged in a vertical direction to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0258] In specific implementation, HG4, HG7, HG3, HG5 and HG8 are changed from the original left-right tooth arrangement to a vertical arrangement, which utilizes the vertical gaps of the original structure and narrows the space occupied by the driving circuit in the horizontal direction.

[0259] In FIG4A , the bottom gate via hole labeled HG9 is the ninth transistor T9 , and the bottom gate via hole labeled HG6 is the sixth transistor T6 ;

[0260] HG9 and HG6 are arranged in a vertical direction to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0261] In a specific implementation, the bottom gate via HG9 of the ninth transistor T9 and the bottom gate via HG6 of the sixth transistor T6 above C1 are arranged vertically instead of being staggered left and right, thereby reducing the space occupied by the driving circuit in the horizontal direction.

[0262] In at least one embodiment of the present disclosure, an orthographic projection of the bottom gate via of the second transistor on the substrate and an orthographic projection of the second electrode of the first transistor on the substrate are arranged along a first direction.

[0263] As shown in FIG4A , the bottom gate via hole labeled HG2 is the second transistor, and in FIG6 , the second electrode of the first transistor T1 is labeled D1 ;

[0264] As shown in FIG. 4A to FIG. 10 , the orthographic projection of HG2 on the substrate and the orthographic projection of D1 on the substrate are arranged in a vertical direction, and the first gate G2 of the second transistor T2 and the second gate GD2 of the second transistor are electrically connected to the second electrode D1 of the first transistor T1 .

[0265] In specific implementation, the bottom gate via of T2 is moved up to the gap above the second electrode D1 of T1, compressing the horizontal space on the left side of T2, reducing the length of the transfer hole connection while avoiding the transistor structure, thereby compressing the layout space.

[0266] In at least one embodiment of the present disclosure, a length of an orthographic projection of the first capacitor on the substrate along the second direction is less than a second length threshold.

[0267] In a specific implementation, the length of the orthographic projection of the first capacitor on the substrate along the second direction is set to be smaller, that is, the length of the first plate of the first capacitor along the second direction is set to be smaller, and the length of the second plate of the first capacitor along the second direction is set to be smaller, so as to narrow the lateral space occupied by the first capacitor.

[0268] In FIG4B , the first capacitor is labeled C1 , in FIG7 , the first plate of C1 is labeled C1a , and in FIG8 , the second plate of C1 is labeled C1b ;

[0269] The horizontal lengths of C1a and C1b are set to be smaller, and the shape of C1 is changed to increase its vertical height and narrow its width, which is conducive to the close arrangement of devices in the horizontal direction.

[0270] Optionally, a length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

[0271] As shown in FIG6 , the active pattern labeled A8 is the eighth transistor T8 . The length of A8 in the horizontal direction is set to be relatively small, thereby narrowing the space occupied by T8 in the horizontal direction.

[0272] As shown in FIG7 , G81 is the first gate pattern included in the first gate of T8, G82 is the second gate pattern included in the first gate of T8, G83 is the third gate pattern included in the first gate of T8, G84 is the fourth gate pattern included in the first gate of T8, and G85 is the fifth gate pattern included in the first gate of T8;

[0273] By increasing the number of gate patterns included in the gate of T8, it is possible to reduce the horizontal space occupied by the active pattern A8 of T8 while ensuring that the channel width of T8 remains unchanged. For example, the horizontal width of the active pattern of T8 can be reduced from 43μm to 34.4μm, narrowing the horizontal space occupied by T8.

[0274] In Figure 4B, the line labeled STV0 is the starting voltage line, the line labeled VGL1 is the first low voltage line, the line labeled CB is the second clock signal line, the line labeled CK is the first clock signal line, the line labeled VGH1 is the first high voltage line, the line labeled CX is the initial control line, the line labeled VGH2 is the second high voltage line, the line labeled VGH3 is the third high voltage line, and the line labeled VGL2 is the second low voltage line.

[0275] In Figure 5, the second gate of T2 is labeled GD2, the second gate of T3 is labeled GD3, the second gate of T4 is labeled GD4, the second gate of T5 is labeled GD5, the second gate of T5 is labeled GD6, the second gate of T6 is labeled GD7, the second gate of T7 is labeled GD8, and the second gate of T8 is labeled GD9.

[0276] In FIG. 6 , the active pattern labeled A7 is T7 , and the active pattern labeled A8 is T8 .

[0277] In FIG7 , C1a is the first electrode plate of C1 , C2a is the first electrode plate of C2 , and C3a is the first electrode plate of C3 .

[0278] In FIG8 , C1b is the second electrode plate of C1 , C2b is the second electrode plate of C2 , and C3b is the second electrode plate of C3 .

[0279] In FIG9 , S7 is the first electrode of T7 , and D7 is the second electrode of T7 ; S8 is the first electrode of T8 , and D8 is the second electrode of T8 .

[0280] Figure 11A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in Figure 4A, Figure 11B is a schematic diagram of the superposition of the first gate metal layer, the second gate metal layer and the first source and drain metal layer in Figure 4A, Figure 11C is a schematic diagram of the superposition of the first source and drain metal layer and the second source and drain metal layer in Figure 4A, and Figure 11D is a schematic diagram of the superposition of the light-shielding metal layer and the semiconductor layer in Figure 4A.

[0281] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first output node control circuit, a first output node set circuit, a control node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit, and a third energy storage circuit;

[0282] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0283] The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node;

[0284] The third node control circuit is electrically connected to the fifth node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the fifth node;

[0285] The first output node control circuit is electrically connected to the third node, the second clock signal line and the first output node respectively, and is used to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line;

[0286] The control node control circuit is electrically connected to the input terminal, the first clock signal line, the initial control line, the first voltage line, and the control node, respectively, and is configured to control the connection or disconnection between the control node and the first voltage line under the control of an initial control signal provided by the initial control line, and to control the connection or disconnection between the control node and the input terminal under the control of a first clock signal provided by the first clock signal line;

[0287] The first energy storage circuit is electrically connected to the second node and the second output node respectively, and is used to store electrical energy;

[0288] A first end of the second energy storage circuit is electrically connected to the first node, a second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;

[0289] The third energy storage circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0290] The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

[0291] Optionally, the first node may be directly electrically connected to the fifth node, and the control node may be directly electrically connected to the second output node, but the present invention is not limited thereto.

[0292] In a specific implementation, at least one embodiment of the driving circuit may further include a first on-off control circuit and a second on-off control circuit;

[0293] The first on-off control circuit is electrically connected to the second voltage line, the control node, and the second output node, respectively, and is configured to control the connection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line;

[0294] The second on-off control circuit is electrically connected to the second voltage line, the first node and the fifth node respectively, and is used to control the connection between the first node and the fifth node under the control of the second voltage signal provided by the second voltage line.

[0295] As shown in FIG12 , at least one embodiment of the driving circuit includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 14, a first output node control circuit 15, a first output node setting circuit 13, a control node control circuit 16, an output circuit 19, a first energy storage circuit 18, a second energy storage circuit 22, a third energy storage circuit 23, a first on-off control circuit 110, and a second on-off control circuit 111.

[0296] The first node control circuit 11 is electrically connected to the first node N1 and is used to control the potential of the first node N1;

[0297] The second node control circuit 12 is electrically connected to the second node N2 and is used to control the potential of the second node N2;

[0298] The first output node setting circuit 13 is electrically connected to the control node NC, the first output node N01 and the first voltage line V1 respectively, and is used to control the connection between the first output node N01 and the first voltage line V1 under the control of the potential of the control node NC;

[0299] The third node control circuit 14 is electrically connected to the fifth node N5 and the third node N3, respectively, and is configured to control the potential of the third node N3 under the control of the potential of the fifth node N5;

[0300] The first output node control circuit 15 is electrically connected to the third node N3, the second clock signal line CB, and the first output node N01, respectively, and is configured to control the connection or disconnection between the third node N3 and the first output node N01 under the control of the second clock signal provided by the second clock signal line CB;

[0301] The control node control circuit 16 is electrically connected to the input terminal STV, the first clock signal line CK, the initial control line CX, the first voltage line V1, and the control node NC, respectively, and is configured to control the connection or disconnection between the control node NC and the first voltage line V1 under the control of an initial control signal provided by the initial control line CX, and to control the connection or disconnection between the control node NC and the input terminal STV under the control of a first clock signal provided by the first clock signal line CK;

[0302] The first energy storage circuit 18 is electrically connected to the second node N2 and the second output node N02, respectively, for storing electrical energy;

[0303] A first end of the second energy storage circuit 22 is electrically connected to the fifth node N5, a second end of the second energy storage circuit 22 is electrically connected to the third node N3, and the second energy storage circuit 22 is used to store electrical energy;

[0304] The third energy storage circuit 23 is electrically connected to the first output node N01 and is used to maintain the potential of the first output node N01;

[0305] The output circuit 19 is electrically connected to the first output node N01, the second output node N02 and the drive signal output terminal OT, respectively, and is used to control the output drive signal under the control of the potential of the first output node N01 and the potential of the second output node N02, and provide the drive signal through the drive signal output terminal OT;

[0306] The first on-off control circuit 110 is electrically connected to the second voltage line V2, the control node NC, and the second output node N02, respectively, and is configured to control the connection between the control node NC and the second output node N02 under the control of a second voltage signal provided by the second voltage line V2;

[0307] The second on-off control circuit 111 is electrically connected to the second voltage line V2, the first node N1 and the fifth node N5 respectively, and is used to control the connection between the first node N1 and the fifth node N5 under the control of the second voltage signal provided by the second voltage line V2.

[0308] Optionally, the first node control circuit includes a first transistor and a thirteenth transistor, and the second node control circuit includes a second transistor and a tenth transistor; the first output node set circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; the control node control circuit includes a fifth transistor and an eleventh transistor, and the output circuit includes a seventh transistor and an eighth transistor; and the third node control circuit includes a twelfth transistor;

[0309] The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node;

[0310] a first gate of the thirteenth transistor is electrically connected to the control node, a first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and a second electrode of the thirteenth transistor is electrically connected to the first node;

[0311] a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node;

[0312] a first gate of the tenth transistor is electrically connected to the second output node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the second node;

[0313] A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node;

[0314] a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node;

[0315] A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node;

[0316] a first gate of the eleventh transistor being electrically connected to the first clock signal line, a first electrode of the eleventh transistor being electrically connected to the input terminal, and a second electrode of the eleventh transistor being electrically connected to the control node;

[0317] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0318] A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line;

[0319] a first gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the third node;

[0320] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the second output node;

[0321] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the third node;

[0322] The first plate of the third capacitor is electrically connected to the first output node, and the second plate of the third capacitor is electrically connected to the first voltage line.

[0323] As shown in FIG13 , based on at least one embodiment of the driving circuit shown in FIG12 , the first node control circuit includes a first transistor T1 and a thirteenth transistor T13, the second node control circuit includes a second transistor T2 and a tenth transistor T10; the first output node set circuit includes a third transistor T3, and the first output node control circuit includes a fourth transistor T4; the first energy storage circuit includes a first capacitor C1; the second energy storage circuit includes a second capacitor C2, and the third energy storage circuit includes a third capacitor C3; the control node control circuit includes a fifth transistor T5 and an eleventh transistor T11, the output circuit includes a seventh transistor T7 and an eighth transistor T8; and the third node control circuit includes a twelfth transistor T12.

[0324] The first gate of the first transistor T1 is electrically connected to the first clock signal line CK, the first electrode of the first transistor T1 is electrically connected to the low voltage line VGL, and the second electrode of the first transistor T1 is electrically connected to the first node N1;

[0325] A first gate of the thirteenth transistor T13 is electrically connected to the control node NC, a first electrode of the thirteenth transistor T13 is electrically connected to the first clock signal line CK, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1;

[0326] a first gate of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the high voltage line VGH, and a second electrode of the second transistor T2 is electrically connected to the second node N2;

[0327] A first gate of the tenth transistor T10 is electrically connected to the second output node N02, a first electrode of the tenth transistor T10 is electrically connected to the second clock signal line CB, and a second electrode of the tenth transistor T10 is electrically connected to the second node N2;

[0328] A first gate of the third transistor T3 is electrically connected to the control node NC, a first electrode of the third transistor T3 is electrically connected to the high voltage line VGH, and a second electrode of the third transistor T3 is electrically connected to the first output node N01;

[0329] A first gate of the fourth transistor T4 is electrically connected to the second clock signal line CB, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, and a second electrode of the fourth transistor T4 is electrically connected to the first output node N01;

[0330] A first gate of the fifth transistor T5 is electrically connected to the initial control line CX, a first electrode of the fifth transistor T5 is electrically connected to the high voltage line VGH, and a second electrode of the fifth transistor T5 is electrically connected to the control node NC;

[0331] a first gate of the eleventh transistor T11 electrically connected to the first clock signal line CK, a first electrode of the eleventh transistor T11 electrically connected to the input terminal STV, and a second electrode of the eleventh transistor T11 electrically connected to the control node NC;

[0332] A first gate of the seventh transistor T7 is electrically connected to the first output node N01, a first electrode of the seventh transistor T7 is electrically connected to the high voltage line VGH, and a second electrode of the seventh transistor T7 is electrically connected to the driving signal output terminal OT;

[0333] A first gate of the eighth transistor T8 is electrically connected to the second output node N02, a first electrode of the eighth transistor T8 is electrically connected to the drive signal output terminal OT, and a second electrode of the eighth transistor T8 is electrically connected to the low voltage line VGL;

[0334] The first gate of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal line CB, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3;

[0335] The first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the second output node N02;

[0336] The first plate of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate of the second capacitor C2 is electrically connected to the third node N3;

[0337] The first plate of the third capacitor C3 is electrically connected to the first output node N01, and the second plate of the third capacitor C3 is electrically connected to the high voltage line VGH;

[0338] The first on-off control circuit includes a ninth transistor T9, and the second on-off control circuit includes a sixteenth transistor T16;

[0339] A first gate of the ninth transistor T9 is electrically connected to the low voltage line VGL, a first electrode of the ninth transistor T9 is electrically connected to the control node NC, and a second electrode of the ninth transistor T9 is electrically connected to the second output node N02;

[0340] A first gate of the sixteenth transistor T16 is electrically connected to the low voltage line VGL, a first electrode of the sixteenth transistor T16 is electrically connected to the first node N1, and a second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5.

[0341] In at least one embodiment of the driving circuit shown in FIG. 13 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0342] In at least one embodiment of the present disclosure, the orthographic projection of the plate of the second capacitor on the substrate is at least partially arranged around the orthographic projection of the bottom gate via of the eleventh transistor on the substrate.

[0343] Optionally, the plates of the second capacitor include a first plate of the second capacitor and a second plate of the second capacitor.

[0344] In a specific implementation, the shape of the electrode plate of the second capacitor can be changed, stretched vertically and surrounding the bottom gate via of the eleventh transistor, and the orthographic projection of the electrode plate of the second capacitor on the substrate is set to at least partially surround the orthographic projection of the bottom gate via of the eleventh transistor on the substrate, so as to reduce the width of the driving circuit in the horizontal direction.

[0345] Figures 14A and 14B are layout diagrams of at least one embodiment of the driving circuit shown in Figure 13, Figure 15 is a layout diagram of the light-shielding metal layer in Figure 14A, Figure 16 is a layout diagram of the semiconductor layer in Figure 14A, Figure 17 is a layout diagram of the first gate metal layer in Figure 14A, Figure 18 is a layout diagram of the second gate metal layer in Figure 14A, Figure 19 is a layout diagram of the third gate metal layer in Figure 14A, Figure 20 is a layout diagram of the first source-drain metal layer in Figure 14A, and Figure 21 is a layout diagram of the second source-drain metal layer in Figure 14A.

[0346] Figure 22A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in Figure 14A, Figure 22B is a schematic diagram of the superposition of the first gate metal layer, the second gate metal layer and the first source and drain metal layer in Figure 14A, Figure 22C is a layout diagram of the first source and drain metal layer and the second source and drain metal layer in Figure 14A, and Figure 22D is a layout diagram of the shading metal layer and the semiconductor layer in Figure 14A.

[0347] As shown in FIG17 , C2a is the first plate of the second capacitor C2 , and as shown in FIG18 , C2b is the second plate of the second capacitor C2 . In FIG14A , HG11 is the bottom gate via of the eleventh transistor T11 .

[0348] In at least one embodiment of the present disclosure, an orthographic projection of the second electrode of the eleventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate are arranged along a first direction.

[0349] In FIG14A , HG13 is the bottom gate via of the thirteenth transistor T13. In FIG20 , D11 is the second electrode of the eleventh transistor T11. As shown in FIG17 , G13 is the first gate of T13. As shown in FIG14A to FIG21 , the first gate G13 of the thirteenth transistor T13 is electrically connected to the second electrode of the eleventh transistor T11.

[0350] As shown in FIG. 14A to FIG. 21 , D11 and HG13 are arranged in the vertical direction to reduce the lateral space occupied by the driving circuit and reduce the length of the transfer hole connection while avoiding the transistor structure, thereby compressing the layout space.

[0351] In at least one embodiment of the present disclosure, an orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate and an orthographic projection of the first electrode of the first transistor on the substrate are arranged along a first direction.

[0352] In a specific implementation, the orthographic projection of the bottom gate via of the thirteenth transistor on the substrate and the orthographic projection of the first electrode of the first transistor on the substrate are arranged along a first direction to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0353] As shown in FIG14A , the bottom gate via hole labeled HG13 is the thirteenth transistor T13 , and as shown in FIG16 , the first electrode of the first transistor labeled S1 is the first electrode.

[0354] The orthographic projection of HG13 on the substrate and the orthographic projection of S1 on the substrate are arranged in a vertical direction to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0355] In at least one embodiment of the present disclosure, the orthographic projection of the bottom gate via of the twelfth transistor on the substrate, the orthographic projection of the bottom gate via of the seventh transistor on the substrate, and the orthographic projection of the bottom gate via of the fifth transistor on the substrate are arranged along a first direction.

[0356] In a specific implementation, the orthographic projection of the bottom gate via of the twelfth transistor on the substrate, the orthographic projection of the bottom gate via of the seventh transistor on the substrate, and the orthographic projection of the bottom gate via of the fifth transistor on the substrate are arranged to be arranged along a first direction to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0357] As shown in FIG14A , the bottom gate via hole labeled HG12 is the bottom gate via hole of the twelfth transistor T12 , the bottom gate via hole labeled HG7 is the bottom gate via hole of the seventh transistor T7 , and the bottom gate via hole labeled HG5 is the bottom gate via hole of the fifth transistor T5 ;

[0358] HG12, HG7, and HG5 are arranged vertically to reduce the horizontal space occupied by the driving circuit, thus facilitating the realization of a narrow frame.

[0359] In at least one embodiment of the present disclosure, an orthographic projection of the bottom gate via of the fourth transistor on the substrate and an orthographic projection of the second electrode of the third transistor on the substrate are arranged along the second direction.

[0360] In a specific implementation, the bottom gate via of the fourth transistor is inserted into the space on the left side of the third transistor, which can compress the horizontal space and facilitate the realization of a narrow frame.

[0361] As shown in FIG14A , the bottom gate via hole labeled HG4 is the fourth transistor, and as shown in FIG16 , the second electrode of the third transistor T3 is labeled D3 ;

[0362] As shown in FIG. 14A to FIG. 21 , HG4 and D3 are arranged in the horizontal direction, and HG4 is set in the space on the left side of D3 to compress the horizontal space.

[0363] In at least one embodiment of the present disclosure, an orthographic projection of the bottom gate via of the tenth transistor on the substrate and an orthographic projection of the plate of the first capacitor on the substrate are arranged along the second direction.

[0364] Optionally, the plates of the first capacitor include a first plate of the first capacitor and a second plate of the first capacitor.

[0365] In a specific implementation, the shape of the first capacitor can be stretched horizontally, and the bottom gate via of the tenth transistor can be set on the left side of the first capacitor, which can reduce the horizontal space occupied by the bottom gate via on the left side of the eighth transistor.

[0366] As shown in FIG14A , HG10 is the bottom gate via of the tenth transistor T10 , and C1 is the first capacitor.

[0367] As shown in FIG17 , the first plate of the first capacitor C1 is labeled C1a, and as shown in FIG18 , the first plate of the first capacitor C1 is labeled C1b.

[0368] is the second plate of the first capacitor C1.

[0369] As shown in FIG. 14A to FIG. 21 , the orthographic projection of HG10 on the substrate and the orthographic projection of C1a on the substrate are arranged in the horizontal direction.

[0370] Optionally, a length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

[0371] In FIG16 , the active pattern labeled A8 is the eighth transistor T8;

[0372] During specific implementation, the length of the active pattern A8 of the eighth transistor T8 in the horizontal direction may be set to be relatively small, so as to narrow the lateral space occupied by the driving circuit.

[0373] In FIG14B , VGL1 is a first low voltage line, CK is a first clock signal line, CB is a second clock signal line, CX is an initial control line, VGH is a high voltage line, and VGL2 is a second low voltage line.

[0374] In Figure 15, the second gate of T4 is labeled GD4, the second gate of T5 is labeled GD5, the second gate of T7 is labeled GD7, the second gate of T7 is labeled GD10, the second gate of T10 is labeled GD11, the second gate of T11 is labeled GD12, and the second gate of T12 is labeled GD13.

[0375] In FIG. 16 , the active pattern labeled A7 is T7 , and the active pattern labeled A8 is T8 .

[0376] In at least one embodiment of the present disclosure, the driving circuit includes a first output node control circuit, a sixth node control circuit, a second output node control circuit, and an output circuit;

[0377] The first output node control circuit is used to control the potential of the first output node;

[0378] The sixth node control circuit is used to control the potential of the sixth node;

[0379] The second output node control circuit is used to control the potential of the second output node according to the potential of the sixth node;

[0380] The output circuit is used to control the supply of a driving signal through the driving signal output terminal based on the potential of the first output node and the potential of the second output node.

[0381] In a specific implementation, the driving circuit may include a first output node control circuit, a sixth node control circuit, a second output node control circuit and an output circuit; the first output node control circuit controls the potential of the first output node; the sixth node control circuit controls the potential of the sixth node; the second output node control circuit controls the potential of the second output node according to the potential of the sixth node; the output circuit controls the provision of a driving signal through the driving signal output terminal at the potential of the first output node and the potential of the second output node.

[0382] As shown in FIG23 , at least one embodiment of the driving circuit includes a first output node control circuit 15 , a sixth node control circuit 31 , a second output node control circuit 17 , and an output circuit 19 ;

[0383] The first output node control circuit 15 is electrically connected to the first output node N01 and is used to control the potential of the first output node N01;

[0384] The sixth node control circuit 31 is electrically connected to the sixth node N6 and is used to control the potential of the sixth node N6;

[0385] The second output node control circuit is electrically connected to the sixth node N6 and the second output node N02, respectively, and is configured to control the potential of the second output node N02 according to the potential of the sixth node N6;

[0386] The output circuit 19 is electrically connected to the first output node N01, the second output node N02 and the drive signal output terminal OT respectively, and is used to control the provision of a drive signal through the drive signal output terminal OT based on the potential of the first output node N01 and the potential of the second output node N02.

[0387] Optionally, the first output node control circuit includes a first transistor and a ninth transistor;

[0388] A first gate of the first transistor is electrically connected to a first clock signal line, a first electrode of the first transistor is electrically connected to a second voltage line, and a second electrode of the first transistor is electrically connected to the first output node;

[0389] a first gate of the ninth transistor is electrically connected to the sixth node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first output node;

[0390] The sixth node control circuit includes an eleventh transistor, a fourteenth transistor, and a fifteenth transistor;

[0391] The first gate of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the input terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node;

[0392] a first gate of the fourteenth transistor is electrically connected to the first output node, a first electrode of the fourteenth transistor is electrically connected to the first voltage line, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

[0393] The first gate of the fifteenth transistor is electrically connected to the second clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the sixth node;

[0394] The second output node control circuit includes a sixteenth transistor;

[0395] A first gate of the sixteenth transistor is electrically connected to the second voltage line, a first electrode of the sixteenth transistor is electrically connected to the sixth node, and a second electrode of the sixteenth transistor is electrically connected to the second output node;

[0396] The output circuit includes a seventh transistor and an eighth transistor;

[0397] A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal;

[0398] The first gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the driving signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal line.

[0399] As shown in FIG24 , based on at least one embodiment of the driving circuit shown in FIG23 , the first output node control circuit includes a first transistor T1 and a ninth transistor T9 ;

[0400] The first gate of the first transistor T1 is electrically connected to the first clock signal line CK, the first electrode of the first transistor T1 is electrically connected to the low voltage line VGL, and the second electrode of the first transistor T1 is electrically connected to the first output node N01;

[0401] A first gate of the ninth transistor T9 is electrically connected to the sixth node N6, a first electrode of the ninth transistor T9 is electrically connected to the first clock signal line CK, and a second electrode of the ninth transistor T9 is electrically connected to the first output node N01;

[0402] The sixth node control circuit includes an eleventh transistor T11, a fourteenth transistor T14 and a fifteenth transistor T15;

[0403] a first gate of the eleventh transistor T11 electrically connected to the first clock signal line CK, a first electrode of the eleventh transistor T11 electrically connected to the input terminal STV, and a second electrode of the eleventh transistor T11 electrically connected to the sixth node N6;

[0404] A first gate of the fourteenth transistor T14 is electrically connected to the first output node N01, a first electrode of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and a second electrode of the fourteenth transistor T14 is electrically connected to the first electrode of the fifteenth transistor T15;

[0405] A first gate of the fifteenth transistor T15 is electrically connected to the second clock signal line CB, and a second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6;

[0406] The second output node control circuit includes a sixteenth transistor T16;

[0407] A first gate of the sixteenth transistor T16 is electrically connected to the low voltage line VGL, a first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and a second electrode of the sixteenth transistor T16 is electrically connected to the second output node N02;

[0408] The output circuit includes a seventh transistor T7 and an eighth transistor T8;

[0409] A first gate of the seventh transistor T7 is electrically connected to the first output node N01, a first electrode of the seventh transistor T7 is electrically connected to the high voltage line VGH, and a second electrode of the seventh transistor T7 is electrically connected to the driving signal output terminal OT;

[0410] A first gate of the eighth transistor T8 is electrically connected to the second output node N02, a first electrode of the eighth transistor T8 is electrically connected to the drive signal output terminal OT, and a second electrode of the eighth transistor T8 is electrically connected to the second clock signal line CB;

[0411] The driving circuit further includes a first capacitor C1 and a second capacitor C2;

[0412] The first plate of the first capacitor C1 is electrically connected to the first output node N01, and the second plate of the first capacitor C1 is electrically connected to the high voltage line VGH;

[0413] The first plate of the second capacitor C2 is electrically connected to the second output node N02 , and the second plate of the second capacitor C2 is electrically connected to the driving signal output terminal OT.

[0414] In at least one embodiment of the driving circuit shown in FIG. 24 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0415] In at least one embodiment of the present disclosure, the orthographic projection of the bottom gate via of the eleventh transistor on the substrate, the orthographic projection of the bottom gate via of the ninth transistor on the substrate, and the orthographic projection of the bottom gate via of the sixteenth transistor on the substrate are arranged along a first direction.

[0416] In a specific implementation, the orthographic projection of the bottom gate via of the eleventh transistor on the substrate, the orthographic projection of the bottom gate via of the ninth transistor on the substrate, and the orthographic projection of the bottom gate via of the sixteenth transistor on the substrate can be arranged along the first direction to narrow the lateral space occupied by the driving circuit, for example, to achieve a narrow frame.

[0417] Figures 25A and 25B are layout diagrams of at least one embodiment of the driving circuit shown in Figure 24, Figure 26 is a layout diagram of the light-shielding metal layer in Figure 25A, Figure 27 is a layout diagram of the semiconductor layer in Figure 25A, Figure 28 is a layout diagram of the first gate metal layer in Figure 25A, Figure 29 is a layout diagram of the second gate metal layer in Figure 25A, Figure 30 is a layout diagram of the first source-drain metal layer in Figure 25A, and Figure 31 is a layout diagram of the second source-drain metal layer in Figure 25A.

[0418] Figure 32A is a schematic diagram of the superposition of the semiconductor layer and the first gate metal layer in Figure 25A, Figure 32B is a schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer in Figure 25A, Figure 32C is a schematic diagram of the superposition of the first gate metal layer, the second gate metal layer and the first source-drain metal layer in Figure 25A; Figure 32D is a schematic diagram of the superposition of the light-shielding metal layer and the semiconductor layer in Figure 25A.

[0419] In FIG25A , the bottom gate via hole labeled HG11 is the eleventh transistor T11, the bottom gate via hole labeled HG9 is the ninth transistor T9, and the bottom gate via hole labeled HG16 is the sixteenth transistor T16;

[0420] HG11 , HG9 , and HG16 are arranged in a vertical direction to narrow the horizontal space occupied by the driving circuit, for example, to achieve a narrow frame.

[0421] In at least one embodiment of the present disclosure, an orthographic projection of the bottom gate via hole of the seventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the eighth transistor on the substrate are arranged along a first direction.

[0422] In a specific implementation, the orthographic projection of the bottom gate via of the seventh transistor on the substrate and the orthographic projection of the bottom gate via of the eighth transistor on the substrate are arranged along the first direction to narrow the lateral space occupied by the driving circuit, for example, to achieve a narrow frame.

[0423] In FIG. 25A , the bottom gate via hole labeled HG7 is the bottom gate via hole of the seventh transistor T7 , and the bottom gate via hole labeled HG8 is the bottom gate via hole of the eighth transistor T8 . HG7 and HG8 are arranged in a vertical direction.

[0424] In at least one embodiment of the present disclosure, the eleventh transistor in the current stage driver circuit, the first transistor in the current stage driver circuit, and the fifteenth transistor in the adjacent previous stage driver circuit share a bottom gate via of the transistor.

[0425] In a specific implementation, two transistors in a current-stage driving circuit and one transistor in an adjacent previous-stage driving circuit share a bottom-gate via, thereby reducing the number of bottom-gate vias used and thereby achieving the goal of reducing space.

[0426] In FIG25B , VGL is a low voltage line, CB is a second clock signal line, CK is a first clock signal line, STV is a starting voltage line, and VGH is a high voltage line.

[0427] In FIG26 , GD7 is the second gate of T7 , GD8 is the second gate of T8 , GD9 is the second gate of T9 , GD11 is the second gate of T11 , and GD16 is the second gate of T16 .

[0428] In FIG27 , the active pattern labeled A7 is T7 , and the active pattern labeled A8 is T8 .

[0429] In Figure 28, C1a is the first electrode plate of C1, C2a is the first electrode plate of C2, in Figure 29, C1b is the second electrode plate of C1, C2b is the second electrode plate of C2. In Figure 30, S7 is the first electrode of T7.

[0430] In FIG31 , VGL is a low voltage line, CB is a second clock signal line, CK is a first clock signal line, STV is a starting voltage line, and VGH is a high voltage line.

[0431] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0432] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate comprising a substrate, a scanning line and a driving module disposed on the substrate, wherein the driving module comprises a multi-stage driving circuit for providing a driving signal to the scanning line; At least two transistors in the driving circuit have a first gate and a second gate; at least a portion of the second gate is located between the first gate and the substrate; The bottom gate vias of at least two transistors of the driving circuit are arranged along a first direction; The second gate is electrically connected to the connecting portion through the bottom gate via, and the connecting portion is electrically connected to the first gate; or the second gate is electrically connected to the first gate through the bottom gate via; The first direction intersects with a second direction, and the scan line includes at least a portion extending along the second direction.

2. The display substrate according to claim 1, wherein: An orthographic projection of a bottom gate via hole of at least one transistor included in the driving circuit on the substrate and an orthographic projection of an electrode of another transistor electrically connected to the transistor on the substrate are arranged along a first direction.

3. The display substrate according to claim 1, wherein: A minimum distance between an orthographic projection of a bottom gate via of at least one transistor included in the driving circuit on the substrate and an orthographic projection of an electrode of another transistor electrically connected to the transistor on the substrate is smaller than a distance threshold.

4. The display substrate according to claim 1, wherein: The driving circuit includes an output circuit, the output circuit being electrically connected to a first output node, a second output node, and a driving signal output terminal, respectively, and configured to generate a driving signal under the control of a potential of the first output node and a potential of the second output node, and provide the driving signal through the driving signal output terminal; The length of the active pattern of at least one transistor included in the output circuit along the second direction is smaller than a first length threshold.

5. The display substrate according to claim 4, wherein: The active pattern includes N mutually independent active pattern portions, and the active pattern portions extend along the second direction, where N is an integer greater than 1.

6. The display substrate according to claim 1, wherein: The driving circuit includes at least one energy storage circuit, and the energy storage circuit includes a capacitor; A length of an orthographic projection of at least one capacitor included in the driving circuit on the substrate along the second direction is smaller than a second length threshold.

7. The display substrate according to any one of claims 1 to 6, wherein: The driving circuit includes a first node control circuit, a second node control circuit, a first output node setting circuit, a third node control circuit, a first output node control circuit, a control node control circuit, a second output node control circuit, a first energy storage circuit and an output circuit; The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node; The third node control circuit is electrically connected to the first node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the first node; The first output node control circuit is electrically connected to the third node, the second clock signal line, and the first output node, respectively, and is configured to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line; The control node control circuit is electrically connected to the initial control line, the first voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the first voltage line under the control of the initial control signal provided by the initial control line; The second output node control circuit is electrically connected to the second output node and the fourth node respectively, and is used to control the potential of the second output node according to the potential of the fourth node; The first energy storage circuit is electrically connected to the second node and the fourth node respectively, and is used to store electrical energy; The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

8. The display substrate according to claim 7, wherein: The first node control circuit includes a first transistor, and the second node control circuit includes a second transistor; the first output node set circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; the first energy storage circuit includes a first capacitor; The control node control circuit includes a fifth transistor, the second output node control circuit includes a sixth transistor; the output circuit includes a seventh transistor and an eighth transistor; The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node; a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node; A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node; a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node; A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node; The first gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the second output node; A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal; A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the fourth node.

9. The display substrate according to claim 7, wherein: The orthographic projection of the bottom gate via of the fourth transistor on the substrate, the orthographic projection of the bottom gate via of the seventh transistor on the substrate, the orthographic projection of the bottom gate via of the third transistor on the substrate, the orthographic projection of the bottom gate via of the fifth transistor on the substrate, and the orthographic projection of the bottom gate via of the eighth transistor on the substrate are arranged along a first direction.

10. The display substrate according to claim 7, wherein: An orthographic projection of the bottom gate via hole of the second transistor on the substrate and an orthographic projection of the second electrode of the first transistor on the substrate are arranged along a first direction.

11. The display substrate according to claim 7, wherein: The control node is directly connected to the second output node; or, The driving circuit further includes a first on-off control circuit; The first on-off control circuit is electrically connected to the second voltage line, the control node and the second output node respectively, and is used to control the connection or disconnection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line.

12. The display substrate according to claim 11, wherein: The driving circuit further includes a first on-off control circuit; the first on-off control circuit includes a ninth transistor; a first gate of the ninth transistor is electrically connected to the second voltage line, a first electrode of the ninth transistor is electrically connected to the control node, and a second electrode of the ninth transistor is electrically connected to the second output node; An orthographic projection of the bottom gate via hole of the ninth transistor on the substrate and an orthographic projection of the bottom gate via hole of the sixth transistor on the substrate are arranged along a first direction.

13. The display substrate according to claim 8, wherein: A length of an orthographic projection of the first capacitor on the substrate along the second direction is less than a second length threshold.

14. The display substrate according to claim 8, wherein: A length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

15. The display substrate according to any one of claims 1 to 6, wherein: The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first output node control circuit, a first output node setting circuit, a control node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit and a third energy storage circuit; The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The first output node setting circuit is electrically connected to the control node, the first output node and the first voltage line respectively, and is used to control the connection between the first output node and the first voltage line under the control of the potential of the control node; The third node control circuit is electrically connected to the fifth node and the third node respectively, and is used to control the potential of the third node under the control of the potential of the fifth node; The first output node control circuit is respectively connected to the third node, the second clock signal line and the first output node The third node is electrically connected to the first output node, and is used to control the connection or disconnection between the third node and the first output node under the control of the second clock signal provided by the second clock signal line; The control node control circuit is electrically connected to the input terminal, the first clock signal line, the initial control line, the first voltage line, and the control node, respectively, and is configured to control the connection or disconnection between the control node and the first voltage line under the control of an initial control signal provided by the initial control line, and to control the connection or disconnection between the control node and the input terminal under the control of a first clock signal provided by the first clock signal line; The first energy storage circuit is electrically connected to the second node and the second output node respectively, and is used to store electrical energy; A first end of the second energy storage circuit is electrically connected to the first node, a second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy; The third energy storage circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node and the drive signal output terminal respectively, and is used to control the output drive signal under the control of the potential of the first output node and the potential of the second output node, and provide the drive signal through the drive signal output terminal.

16. The display substrate according to claim 15, wherein: The first node control circuit includes a first transistor and a thirteenth transistor, and the second node control circuit includes a second transistor and a tenth transistor; the first output node set circuit includes a third transistor, and the first output node control circuit includes a fourth transistor; the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; the control node control circuit includes a fifth transistor and an eleventh transistor, and the output circuit includes a seventh transistor and an eighth transistor; and the third node control circuit includes a twelfth transistor; The first gate of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node; a first gate of the thirteenth transistor is electrically connected to the control node, a first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and a second electrode of the thirteenth transistor is electrically connected to the first node; a first gate of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to a first voltage line, and a second electrode of the second transistor is electrically connected to the second node; a first gate of the tenth transistor is electrically connected to the second output node, a first electrode of the tenth transistor is electrically connected to the second clock signal line, and a second electrode of the tenth transistor is electrically connected to the second node; A first gate of the third transistor is electrically connected to the control node, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the first output node; a first gate of the fourth transistor is electrically connected to the second clock signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first output node; A first gate of the fifth transistor is electrically connected to the initial control line, a first electrode of the fifth transistor is electrically connected to the first voltage line, and a second electrode of the fifth transistor is electrically connected to the control node; a first gate of the eleventh transistor being electrically connected to the first clock signal line, a first electrode of the eleventh transistor being electrically connected to the input terminal, and a second electrode of the eleventh transistor being electrically connected to the control node; A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal; A first gate of the eighth transistor is electrically connected to the second output node, a first electrode of the eighth transistor is electrically connected to the drive signal output terminal, and a second electrode of the eighth transistor is electrically connected to the second voltage line; a first gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the second clock signal line, and a second electrode of the twelfth transistor is electrically connected to the third node; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the second output node; The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the third node; The first plate of the third capacitor is electrically connected to the first output node, and the second plate of the third capacitor is electrically connected to the first voltage line.

17. The display substrate according to claim 16, wherein: The orthographic projection of the electrode plate of the second capacitor on the substrate is at least partially arranged around the orthographic projection of the bottom gate via hole of the eleventh transistor on the substrate.

18. The display substrate according to claim 16, wherein: An orthographic projection of the second electrode of the eleventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate are arranged along a first direction.

19. The display substrate according to claim 18, wherein: An orthographic projection of the bottom gate via hole of the thirteenth transistor on the substrate and an orthographic projection of the first electrode of the first transistor on the substrate are arranged along a first direction.

20. The display substrate according to claim 16, wherein An orthographic projection of the bottom gate via hole of the twelfth transistor on the substrate, an orthographic projection of the bottom gate via hole of the seventh transistor on the substrate, and an orthographic projection of the bottom gate via hole of the fifth transistor on the substrate are arranged along a first direction.

21. The display substrate according to claim 16, wherein An orthographic projection of the bottom gate via hole of the fourth transistor on the substrate and an orthographic projection of the second electrode of the third transistor on the substrate are arranged along a second direction.

22. The display substrate according to claim 16, wherein: An orthographic projection of the bottom gate via hole of the tenth transistor on the substrate and an orthographic projection of the plate of the first capacitor on the substrate are arranged along the second direction.

23. The display substrate according to claim 16, wherein: A length of the active pattern of the eighth transistor along the second direction is less than a first length threshold.

24. The display substrate according to claim 16, wherein: The control node is directly connected to the second output node; the first node is electrically connected to the fifth node; or, The driving circuit further includes a first on-off control circuit and a second on-off control circuit; The first on-off control circuit is electrically connected to the second voltage line, the control node and the second output node respectively, and is used to control the connection or disconnection between the control node and the second output node under the control of a second voltage signal provided by the second voltage line; The second on-off control circuit is electrically connected to the second voltage line, the first node and the fifth node respectively, and is used to control the first node and the fifth node under the control of the second voltage signal provided by the second voltage line. The room is connected or disconnected.

25. The display substrate according to any one of claims 1 to 6, wherein: The driving circuit includes a first output node control circuit, a sixth node control circuit, a second output node control circuit and an output circuit; The first output node control circuit is used to control the potential of the first output node; The sixth node control circuit is used to control the potential of the sixth node; The second output node control circuit is used to control the potential of the second output node according to the potential of the sixth node; The output circuit is used to control the supply of a driving signal through the driving signal output terminal based on the potential of the first output node and the potential of the second output node.

26. The display substrate according to claim 25, wherein: The first output node control circuit includes a first transistor and a ninth transistor; A first gate of the first transistor is electrically connected to a first clock signal line, a first electrode of the first transistor is electrically connected to a second voltage line, and a second electrode of the first transistor is electrically connected to the first output node; a first gate of the ninth transistor is electrically connected to the sixth node, a first electrode of the ninth transistor is electrically connected to the first clock signal line, and a second electrode of the ninth transistor is electrically connected to the first output node; The sixth node control circuit includes an eleventh transistor, a fourteenth transistor and a fifteenth transistor; The first gate of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the input terminal, and the second electrode of the eleventh transistor is electrically connected to the sixth node; a first gate of the fourteenth transistor is electrically connected to the first output node, a first electrode of the fourteenth transistor is electrically connected to the first voltage line, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor; The first gate of the fifteenth transistor is electrically connected to the second clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the sixth node; The second output node control circuit includes a sixteenth transistor; A first gate of the sixteenth transistor is electrically connected to the second voltage line, a first electrode of the sixteenth transistor is electrically connected to the sixth node, and a second electrode of the sixteenth transistor is electrically connected to the second output node; The output circuit includes a seventh transistor and an eighth transistor; A first gate of the seventh transistor is electrically connected to the first output node, a first electrode of the seventh transistor is electrically connected to the first voltage line, and a second electrode of the seventh transistor is electrically connected to the drive signal output terminal; The first gate of the eighth transistor is electrically connected to the second output node, the first electrode of the eighth transistor is electrically connected to the driving signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal line.

27. The display substrate according to claim 26, wherein: An orthographic projection of the bottom gate via hole of the eleventh transistor on the substrate, an orthographic projection of the bottom gate via hole of the ninth transistor on the substrate, and an orthographic projection of the bottom gate via hole of the sixteenth transistor on the substrate are arranged along a first direction.

28. The display substrate according to claim 26, wherein: An orthographic projection of the bottom gate via hole of the seventh transistor on the substrate and an orthographic projection of the bottom gate via hole of the eighth transistor on the substrate are arranged along a first direction.

29. The display substrate according to claim 26, wherein: The eleventh transistor in the current stage driving circuit, the first transistor in the current stage driving circuit and the fifteenth transistor in the adjacent previous stage driving circuit share the bottom gate via of the transistor.

30. A display device comprising the display substrate according to any one of claims 1 to 29.

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