Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of sub-pixels in at least one area; wherein the light emitting area of each sub-pixel in the plurality of sub-pixels has a first end and a second end, and the second end is located at one side, far away from the same reference area of the plurality of sub-pixels in the area, of the first end. The plurality of sub-pixels substantially point to the same reference area in the direction from the second ends to the first ends of the plurality of sub-pixels. In the region, the number of pixels per inch (PPI) is substantially the same according to a distance from the same reference region. In the region, the plurality of sub-pixels includes a first sub-pixel of a first orientation and a second sub-pixel of a second orientation. The first orientation and the second orientation are substantially opposite to each other.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal display panels have been widely used. Typically, a liquid crystal display panel includes an opposing substrate and an array substrate facing each other. Thin-film transistors, gate lines, data lines, pixel electrodes, common electrodes, and common electrode signal lines are arranged on the array substrate and the opposing substrate. Liquid crystal material is injected between the two substrates to form a liquid crystal layer. A common problem associated with liquid crystal display panels is light leakage. To prevent light leakage, a black matrix is ​​provided on the opposing substrate. Liquid crystal display panels with a larger black matrix can better prevent light leakage. However, the use of a black matrix with a larger area reduces the aperture ratio of the liquid crystal display device.

[0003] Organic light-emitting diode (OLED) displays are driven by a drive current that needs to be kept constant to control light emission. The OLED display panel includes a plurality of pixel units configured with pixel drive circuits arranged in multiple rows and columns. Each pixel drive circuit includes a drive transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the drive transistor is turned on, and the data voltage is applied from the data line to the drive transistor via the switching transistor, so that the drive transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0004] In one aspect, the present disclosure provides an array substrate comprising a plurality of sub-pixels in at least one region; wherein the light-emitting region of each of the plurality of sub-pixels has a first end and a second end, the second end being located on a side of the first end away from a same reference region with respect to the plurality of sub-pixels in the region; the directions from the second ends to the first ends of the plurality of sub-pixels respectively substantially point to the same reference region; and in the region, the number of pixels per inch (PPI) is substantially the same according to the distance from the same reference region; wherein, in the region, the plurality of sub-pixels include first sub-pixels of a first orientation and second sub-pixels of a second orientation; the width of the first light-emitting region of each first sub-pixel in the first sub-pixels increases from the first end to the second end; the width of the second light-emitting region of each second sub-pixel in the second sub-pixels decreases from the first end to the second end; and the first orientation and the second orientation are substantially opposite to each other.

[0005] Optionally, the array substrate includes N parts arranged in sequence in the area, where N is an integer greater than 2; wherein the (n+1)th part is located on the side of the nth part away from the same reference area, 1≤n≤(N-1); and the sub-pixels in the nth part directly adjacent to the (n+1)th part and the sub-pixels in the (n+1)th part directly adjacent to the nth part have different orientations, wherein the wider end of the light-emitting area of ​​the sub-pixel in the nth part directly adjacent to the (n+1)th part is directly adjacent to the wider end of the light-emitting area of ​​the sub-pixel in the (n+1)th part directly adjacent to the nth part.

[0006] Optionally, a plurality of adjacent sub-pixels in each of the N parts constitutes one pixel.

[0007] Optionally, each of the N parts includes one or more sub-pixel arcs; the array substrate includes X sub-pixel arcs that at least partially surround the same reference area, where X is an integer greater than 2; and sub-pixels from any two directly adjacent sub-pixel arcs have different orientations.

[0008] Optionally, the first part of the N parts includes one sub-pixel arc, the nth part includes two sub-pixel arcs, and the Nth part includes two sub-pixel arcs, and X=2(N-1)+1.

[0009] Optionally, the first part of the N parts includes a sub-pixel arc, and adjacent sub-pixels along the sub-pixel arc have the same orientation.

[0010] Optionally, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth part is greater than the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the (n+1)th part.

[0011] Optionally, a ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth portion is in the range of (n-0.5):(n-1) to (n+0.5):(n-1).

[0012] Optionally, the sub-pixels in the nth part that are directly adjacent to the (n+1)th part have the first orientation; and the sub-pixels in the (n+1)th part that are directly adjacent to the nth part have the second orientation.

[0013] Optionally, at least the m-th part among the N parts includes a first sub-part and a second sub-part, the second sub-part being located on a side of the first sub-part away from the same reference region, 1 < m < (N - 1); and the sub-pixels of the first sub-part and the sub-pixels of the second sub-part have different orientations.

[0014] Optionally, the sub-pixels of the first sub-part have the second orientation; and the sub-pixels of the second sub-part have the first orientation.

[0015] Optionally, the number of sub-pixels in the n-th part is S × I × (2n - 1); S represents the number of sub-pixels in each pixel; and I represents the number of sub-pixels in the first part among the N parts divided by S, the first part being the part closest to the same reference region among the N parts.

[0016] Optionally, the array substrate includes at least N gate lines and at least (J × N) data lines; wherein, each of the (N - 1) gate lines among the N gate lines is located between two adjacent parts among the N parts; and J represents the number of sub-pixels in the first part among the N parts, the first part being the part closest to the same reference region among the N parts.

[0017] Optionally, the array substrate includes (2N - 1) gate lines and (J × N) data lines.

[0018] Optionally, the first gate line among the (2N - 1) gate lines is configured to provide a gate driving signal to the sub-pixels in the first part; and each of the second part to the N-th part among the N parts is configured to receive a gate driving signal from two gate lines.

[0019] Optionally, the (J × N) data lines include J groups of data lines, each group among the J groups of data lines including N data lines; and the n-th data line in each group is configured to provide a data signal to one or more sub-pixels in the n-th part among the N parts, 1 ≤ n ≤ N.

[0020] Optionally, the N-th data line among the N data lines in each group is configured to provide a data signal to a row of sub-pixels in each of the N parts; the first data line among the N data lines in each group is configured to provide a data signal to two sub-pixels in the N-th part among the N parts; and the n'-th data line among the N data lines in each group is configured to provide a data signal to two rows of sub-pixels in each of the n'-th parts among the N parts, 1 < n' < N.

[0021] Optionally, each group in the J groups of data lines includes N data lines; in the j'th group in the J groups of data lines, 1<j'<J, two sub-pixels in the same part have the same orientation, wherein at least 40% of the slender side of each sub-pixel is directly adjacent to the N data line; and in the j'th group in the J groups of data lines, 1<j'<J, two sub-pixels in the same part have the same orientation, wherein at least 40% of the slender side of each sub-pixel is directly adjacent to the n"th data line in the N data lines.

[0022] Optionally, the array substrate includes N gate lines and (J×(2N-1)) data lines.

[0023] Optionally, each gate line is configured to provide a gate driving signal to the two adjacent portions among the N portions.

[0024] Optionally, the (J×(2N-1)) data lines include I groups of data lines, each group of the I groups of data lines includes (2N-1) data lines; the (2n'-1)th data line in each group is configured to provide data signals to one or more sub-pixels in n' parts of the N parts, 1<n'<N; and the 2n'th data line in each group is configured to provide data signals to one or more sub-pixels in n' parts of the N parts.

[0025] Optionally, the first data line in each group is configured to provide data signals to a row of sub-pixels in the N parts respectively; the (2n'-1)th data line in each group is configured to provide data signals to a row of first sub-pixels in n' parts in the N parts respectively, 1<n'<N; and the 2n'th data line in each group is configured to provide data signals to a row of second sub-pixels in n' parts in the N parts respectively.

[0026] Optionally, the array substrate includes: M gate lines, the M gate lines are arranged as M partial circles surrounding the same reference area; and (M-1) connecting lines; wherein the (M-1) connecting lines and the M gate lines are located in different layers; the i-th connecting line among the (M-1) connecting lines electrically connects the (i+1)-th gate line to the gate driving circuit on the array substrate, 1≤i≤(M-1); and the i-th connecting line crosses the i gate lines.

[0027] Optionally, the (M-1) connection lines and the at least (J×N) data lines are located in the same layer.

[0028] Optionally, areas of the sub-pixels in the region are substantially the same.

[0029] Optionally, the number of sub-pixels in the N parts increases with increasing distance from the same reference area.

[0030] Optionally, the width of the same reference area is less than twice the maximum length of each sub-pixel.

[0031] In another aspect, the present disclosure provides a display device including an array substrate described herein or manufactured by the method described herein and one or more integrated circuits connected to the array substrate.

[0032] Optionally, the display device has a circular shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings are examples for illustration purposes only and are not intended to limit the scope of the invention, in accordance with various disclosed embodiments.

[0034] Figure 1 is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 2 is a schematic diagram illustrating the structure of the shape of each sub-pixel in some embodiments of the present disclosure.

[0036] Figure 3 is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 4A is a schematic diagram illustrating the arrangement of pixels in an array substrate according to some embodiments of the present disclosure.

[0038] Figure 4B N parts of an array substrate according to some embodiments of the present disclosure are shown.

[0039] Figure 5 Schematic diagram illustrating sub-pixels with different orientations in an array substrate according to some embodiments of the present disclosure.

[0040] Figure 6A is a schematic diagram illustrating the structure of a region in an array substrate according to some embodiments of the present disclosure.

[0041] Figure 6B is a schematic diagram illustrating sub-pixel arcs in an array substrate according to some embodiments of the present disclosure.

[0042] Figure 7 Schematic diagram illustrating the orientation of sub-pixels in different portions of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 8The orientation of sub-pixels in a sub-portion of a single portion of an array substrate according to some embodiments of the present disclosure is shown.

[0044] Figure 9A The layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure is shown.

[0045] Figure 9B Show Figure 9A The layout of the data lines in the array substrate is shown in FIG.

[0046] Figure 9C Multiple rows of sub-pixels connected to respective groups of data lines in an array substrate according to some embodiments of the present disclosure are shown.

[0047] Figure 9D Schematic diagram illustrating sub-pixels in an array substrate according to some embodiments of the present disclosure.

[0048] Figure 9E Schematic diagram illustrating sub-pixels in an array substrate according to some embodiments of the present disclosure.

[0049] Figure 9F A row of sub-pixels rN is shown according to some embodiments of the present disclosure.

[0050] Figure 9G A row of sub-pixels rn'1 in one of n' sections out of N sections is shown.

[0051] Figure 9H A row of sub-pixels rn'1 in one of n' sections out of N sections is shown.

[0052] Figure 9I The layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure is shown.

[0053] Figure 10A The layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure is shown.

[0054] Figure 10B Show Figure 10A The layout of the data lines in the array substrate is shown in FIG.

[0055] Figure 10C Multiple rows of sub-pixels connected to respective groups of data lines in an array substrate according to some embodiments of the present disclosure are shown.

[0056] Figure 10D A row of sub-pixels r(2N-1) is shown according to some embodiments of the present disclosure.

[0057] Figure 10E A row of sub-pixels rspl in one of n' sections out of N sections is shown.

[0058] Figure 10F A row of sub-pixels rsp2 in one of n' sections out of N sections is shown.

[0059] Figure 11A The diagram shows the layout of signal lines in an array substrate according to some embodiments of the present disclosure.

[0060] Figure 11B The diagram shows the layout of gate lines in an array substrate according to some embodiments of the present disclosure.

[0061] Figure 11C The diagram shows the layout of data lines in an array substrate according to some embodiments of the present disclosure.

[0062] Figure 12 It is along Figure 11A Cross-sectional view along line AA'.

[0063] Figure 13 Several defects along the curved edges in prior art display panels are shown.

[0064] Figure 14 is a structural diagram illustrating a liquid crystal display device according to some embodiments of the present disclosure.

[0065] Figure 15 The detailed structure of the display area of ​​the light emitting diode display device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0066] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0067] The present disclosure, in particular, provides an array substrate and a display device that substantially overcome one or more problems caused by limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of sub-pixels in at least one region. Optionally, the light-emitting region of each of the plurality of sub-pixels has a first end and a second end, with the second end located on a side of the first end away from a common reference region for the plurality of sub-pixels in the region. Optionally, directions from the second ends to the first ends of the plurality of sub-pixels are substantially directed toward the common reference region. Optionally, in the region, the number of pixels per inch (PPI) is substantially the same based on the distance from the common reference region. Optionally, in the region, the plurality of sub-pixels include first sub-pixels in a first orientation and second sub-pixels in a second orientation. Optionally, the width of the first light-emitting region of each of the first sub-pixels increases from the first end to the second end. Optionally, the width of the second light-emitting region of each of the second sub-pixels decreases from the first end to the second end. Optionally, the first orientation and the second orientation are substantially opposite to each other.

[0068] Figure 1 Schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 1 The array substrate includes a plurality of sub-pixels sp. The plurality of sub-pixels sp are arranged around the same reference region RR. Figure 1 An array substrate is shown, wherein a plurality of sub-pixels sp are arranged in a plurality of rings, each ring surrounding the same reference region RR. In a specific example, the plurality of rings surround the same reference center, for example, the plurality of rings are concentric.

[0069] Each sub-pixel in the plurality of sub-pixels sp can have various suitable shapes. Examples of suitable shapes include rectangles, squares, triangles, polygons, and irregular shapes. In one example, each sub-pixel has an elongated shape, the width of which increases or decreases along the extension direction or length direction of the elongated shape. In one example, the width at one end of the elongated shape is substantially zero. As used herein, the term "sub-pixel" refers to a portion of a pixel that can be independently addressed to emit a specific color (e.g., red, green, blue, or white).

[0070] Figure 2 Schematic diagram showing the structure of the shape of corresponding sub-pixels in some embodiments of the present disclosure. Figure 2 The light emitting region of each of the plurality of sub-pixels sp has a first end E1 and a second end E2. The second end E2 is located on a side of the first end E1 away from the same reference region RR of the plurality of sub-pixels sp in at least one region of the array substrate.

[0071] Reference Figure 1 and Figure 2 , the multiple sub-pixels sp can be oriented in various directions. However, the direction from the second end to the first end of the light-emitting region of the multiple sub-pixels sp substantially points to the same reference region RR. As used herein, the term "substantially points to or substantially points to" means that the extension direction of the line connecting the midpoint of the light-emitting region of each sub-pixel on the side of the second end and the midpoint of the light-emitting region of the sub-pixel on the side of the first end intersects the same reference region RR.

[0072] The same reference region RR may have various suitable shapes. Examples of suitable shapes of the same reference region RR include a circle, a square, a rectangle, an ellipse, a triangle, a polygon, and an irregular shape. The same reference region RR may have various suitable sizes. In some embodiments, the width of the same reference region RR is less than ten times the maximum length of each sub-pixel, for example, less than nine times the maximum length of each sub-pixel, less than eight times the maximum length of each sub-pixel, less than seven times the maximum length of each sub-pixel, less than six times the maximum length of each sub-pixel, less than five times the maximum length of each sub-pixel, less than four times the maximum length of each sub-pixel, less than three times the maximum length of each sub-pixel, less than two times the maximum length of each sub-pixel, or less than the maximum length of each sub-pixel.

[0073] In some embodiments, the plurality of sub-pixels sp arranged above are limited to one area of ​​the array substrate. Figure 3 Schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 3 In some embodiments, the array substrate includes a plurality of sub-pixels sp in the corner region CR. The same reference region RR with respect to the plurality of sub-pixels sp in the corner region CR is a region adjacent to the corner of the array substrate.

[0074] In another example, referring to Figure 3 The array substrate includes a plurality of sub-pixels sp surrounding a window region WR in the array substrate. The window region WR may be an area for mounting components such as a camera or a fingerprint sensor below the light emitting element. The same reference region may be the window region WR.

[0075] The array substrate can have various suitable shapes. Figure 1 In one example shown, the array substrate has a circular shape. Examples of suitable shapes of the array substrate also include square, rectangle, ellipse, triangle, polygon, and irregular shapes.

[0076] Reference Figure 1 In some embodiments, the array substrate further includes a black matrix in the inter-subpixel region of the array substrate.

[0077] Figure 4A Schematic diagram showing the arrangement of pixels in an array substrate according to some embodiments of the present disclosure. Figure 4A The array substrate includes a plurality of pixels pxl, and each pixel includes one or more sub-pixels. Figure 4A An example is shown in which a single pixel includes three sub-pixels of different colors, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The pixel arrangement may be different in different parts of the array substrate.

[0078] Figure 4B N parts of an array substrate according to some embodiments of the present disclosure are shown. Figure 4B Describes the Figure 4A The array substrate described in corresponds to the portion of the array substrate. Figure 4A and Figure 4B In some embodiments, the array substrate includes N portions (P1, ..., Pn, ..., PN) sequentially arranged in a region, where N is an integer greater than 2. The first portion P1 surrounds the same reference region RR, the second portion surrounds the first portion P1, the nth portion Pn surrounds the (n-1)th portion, and the Nth portion PN surrounds the (N-1)th portion.

[0079] In some embodiments, reference Figure 4A , in this region, the number of sub-pixels per unit area is substantially the same depending on the distance from the same reference region RR. For example, in this region, the number of pixels per inch (PPI) is substantially the same depending on the distance from the same reference region RR. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), for example, not exceeding 8% of the base value, not exceeding 6% of the base value, not exceeding 4% of the base value, not exceeding 2% of the base value, not exceeding 1% of the base value, not exceeding 0.5% of the base value, not exceeding 0.1% of the base value, not exceeding 0.05% of the base value, or not exceeding 0.01% of the base value. In some embodiments, the area of ​​each sub-pixel in the region is substantially the same. In some embodiments, the number of sub-pixels in the N portions increases as the distance from the same reference region RR increases.

[0080] Figure 5 Schematic diagram showing sub-pixels with different orientations in an array substrate according to some embodiments of the present disclosure. Figure 1 、 Figure 2 and Figure 5In some embodiments, the plurality of sub-pixels sp include a first sub-pixel sp1 in a first orientation O1 and a second sub-pixel in a second orientation O2. The width of the light-emitting area of ​​each first sub-pixel in the first sub-pixel sp1 increases from the first end E1 to the second end E2. The width of the light-emitting area of ​​each second sub-pixel in the second sub-pixel sp2 decreases from the first end E1 to the second end E2. In one example, the first orientation O1 and the second orientation O2 are arranged substantially opposite to each other. As used herein, the term "substantially opposite to each other" means that the offset angle between the two orientations is in the range of 70 degrees to 110 degrees, for example, 70 degrees to 75 degrees, 75 degrees to 80 degrees, 80 degrees to 85 degrees, 85 degrees to 90 degrees, 90 degrees to 95 degrees, 95 degrees to 100 degrees, 100 degrees to 105 degrees, or 105 degrees to 110 degrees.

[0081] Figure 6A Schematic diagram showing the structure of a region in an array substrate according to some embodiments of the present disclosure. Figure 6A , the array substrate includes a plurality of pixels (such as Figure 6A pxl1, pxl2, pxl3, pxl4 and pxl5) shown in the figure, each pixel includes one or more sub-pixels. Figure 6A An example is shown in which a single pixel includes four sub-pixels of different colors, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Alternatively, a plurality of adjacent sub-pixels in each of the N parts constitute a pixel.

[0082] Reference Figure 4B and Figure 6A , N portions (P1, ..., Pn, ..., PN) are sequentially arranged in the region. In some embodiments, the (n+1)th portion P(n+1) is located on a side of the nth portion Pn away from the same reference region, 1≤n≤(N-1). In some embodiments, the subpixel in the nth portion Pn that is directly adjacent to the (n+1)th portion P(n+1) and the subpixel in the (n+1)th portion P(n+1) that is directly adjacent to the nth portion Pn have different orientations, wherein the wider end of the light-emitting region of the subpixel in the nth portion that is directly adjacent to the (n+1)th portion is directly adjacent to the wider end of the light-emitting region of the subpixel in the (n+1)th portion that is directly adjacent to the nth portion.

[0083] Alternatively, in some embodiments, the sub-pixel in the nth part Pn that is directly adjacent to the (n+1)th part P(n+1) and the sub-pixel in the (n+1)th part P(n+1) that is directly adjacent to the nth part Pn have different orientations, wherein the narrower end of the light-emitting area of ​​the sub-pixel in the nth part that is directly adjacent to the (n+1)th part is directly adjacent to the narrower end of the light-emitting area of ​​the sub-pixel in the (n+1)th part that is directly adjacent to the nth part.

[0084] In some embodiments, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth portion is greater than the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the (n+1)th portion. Optionally, the first portion includes only a plurality of sub-pixels having the first orientation. Optionally, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the second portion is in the range of 1.5:1 to 2.5:1, for example, 2:1. Optionally, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the third portion is in the range of 2.5:2 to 3.5:2, for example, 3:2. Optionally, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth portion is in the range of (n-0.5):(n-1) to (n+0.5):(n-1), for example, n:(n-1). Optionally, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the (n+1)th part is in the range of (n+1-0.5):n to (n+1+0.5):n, for example, (n+1):n.

[0085] Figure 7 1 shows the orientation of sub-pixels in different parts of the array substrate according to some embodiments of the present disclosure. For illustration purposes, Figure 7 Only a few sub-pixels selected from the nth part Pn and the (n+1)th part P(n+1) are shown. Figure 4A 、 Figure 4B and Figure 7 , the nth portion Pn includes two circles of pixels. In the nth portion Pn, a circle of pixels directly adjacent to the (n+1)th portion P(n+1) is the first subpixel sp1 of the first alignment O1, and a circle of pixels not directly adjacent to the (n+1)th portion P(n+1) (for example, the subpixel adjacent to the (n-1)th portion) is the second subpixel sp2 of the second alignment O2. The (n+1)th portion P(n+1) also includes two circles of pixels. In the (n+1)th portion P(n+1), a circle of pixels directly adjacent to the nth portion Pn is the second subpixel sp2 of the second alignment O2, and a circle of pixels not directly adjacent to the nth portion Pn (for example, the subpixel adjacent to the (n+2)th portion) is the first subpixel sp1 of the first alignment O1. The subpixels in the nth portion Pn that are directly adjacent to the (n+1)th portion P(n+1) and the subpixels in the (n+1)th portion P(n+1) that are directly adjacent to the nth portion Pn have different orientations, such as substantially opposite orientations.

[0086] Figure 8Shows the orientation of sub-pixels in a sub-part of a single part of an array substrate according to some embodiments of the present disclosure. For illustrative purposes, Figure 8 only a few selected sub-pixels in the m-th part Pm are shown. Referring to Figure 8 , at least the m-th part Pm of the N parts includes a first sub-part 1Sp and a second sub-part 2Sp. Optionally, 1 < m < (N - 1). Optionally, 1 < m ≤ (N - 1). Optionally, 1 ≤ m ≤ (N - 1). The second sub-part 2Sp is located on a side of the first sub-part 1Sp away from the same reference region RR.

[0087] In some embodiments, the sub-pixels of the first sub-part 1Sp and the sub-pixels of the second sub-part 2Sp have different orientations. Referring to Figure 8 , the sub-pixels of the first sub-part 1Sp are second sub-pixels sp2 of the second orientation O2; the sub-pixels of the second sub-part 2Sp are first sub-pixels sp1 of the first orientation O1.

[0088] In some embodiments, referring to Figure 6A , the N parts are respectively arranged along N arcs. The N arcs at least partially surround the same reference region RR. As used herein, the term "arc" is not limited to a part of a true circle, but can be a part of an ellipse, can be U-shaped, can be C-shaped, can be a part of a hyperbola, can be a part of a sine curve, or can be interpreted as including a series of straight line segments connected end to end, an angular pattern, so as to form a generally angular arc and a smooth curve shape.

[0089] In some embodiments, referring to Figure 4A and Figure 4B , the N arcs are respectively N circles. The same reference region RR is the same central region with respect to the N circles, and the N parts are arranged along the same central region. The N circles substantially surround the same central region.

[0090] In some embodiments, the number of sub-pixels in the n-th part is S × I × (2n - 1), where S represents the number of sub-pixels in each pixel; I represents the number of sub-pixels in the first part of the N parts divided by S, and the first part is the part closest to the same reference region among the N parts.

[0091] Referring to Figure 6A , in one example, each pixel includes four sub-pixels, for example S = 4. The first part P1 of the N parts includes four sub-pixels, for example I = 4 / 4. The number of sub-pixels in the n-th part is 4 × 4 / 4 × (2n - 1). For example, the first part P1 includes 4 sub-pixels, the second part includes 12 sub-pixels, and the third part includes 20 sub-pixels.

[0092] Referring to Figure 4A and Figure 4B , each pixel includes three sub-pixels, for example, S=3. The first portion P1 of the N portions includes 24 sub-pixels, for example, I=24 / 3. The number of sub-pixels in the nth portion is 3×24 / 3×(2n-1). For example, the first portion P1 includes 24 sub-pixels, the second portion includes 72 sub-pixels, and the third portion includes 120 sub-pixels.

[0093] In some embodiments, each of the N portions includes one or more sub-pixel arcs, such as Figure 1 、 Figure 4A and Figure 6A As shown. Each of the N parts includes one or more sub-pixel arcs. Optionally, each of the N parts includes y sub-pixel arcs, where y is an integer greater than or equal to 1. For example, the first part includes one sub-pixel arc, the nth part Pn includes two sub-pixel arcs, and the Nth part includes two sub-pixel arcs, as shown. Figure 6A As shown. The array substrate includes X sub-pixel arcs at least partially surrounding the same reference region RR. Optionally, sub-pixels from any two directly adjacent sub-pixel arcs have different orientations. The X sub-pixel arcs have alternating orientations.

[0094] In some embodiments, the first portion of the N portions includes an arc of sub-pixels, and adjacent sub-pixels along the arc of sub-pixels have the same orientation. Figure 6A In one example, the first portion of the N portions includes only one sub-pixel arc. The first portion includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel that are adjacent to each other. The red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels in the first portion constitute a pixel.

[0095] Figure 6B Schematic diagram showing a sub-pixel arc in an array substrate according to some embodiments of the present disclosure. Figure 6B, in which area the array substrate includes X sub-pixel arcs (e.g., A1, ..., Ax, A(x+1), ..., A(X-1), AX) that at least partially surround the same reference region RR. In some embodiments, any two adjacent sub-pixels in the same arc have the same orientation. Optionally, the sub-pixels from any two directly adjacent sub-pixel arcs have different orientations. For example, the sub-pixels in Ax and the sub-pixels in A(x+1) have different orientations. The X sub-pixel arcs have alternating orientations. As used herein, the term "arc" refers to an arc of any appropriate shape, such as a double arc. In one example, in the case of a sub-pixel arc, the arc may refer to a virtual line that intersects the wider end of the light-emitting area of ​​the sub-pixel. In another example, the arc may refer to a virtual line that intersects the narrower end of the light-emitting area of ​​the sub-pixel. In another example, the arc may refer to a virtual line that intersects the center of the light-emitting area of ​​the sub-pixel.

[0096] In some embodiments, the array substrate further includes a plurality of thin film transistors, a plurality of gate lines configured to provide gate driving signals to the plurality of thin film transistors, and a plurality of data lines configured to provide data signals to the plurality of thin film transistors.

[0097] In some embodiments, the array substrate includes at least N gate lines and at least (J×N) data lines. Each of (N-1) of the N gate lines is located between two adjacent sections of the N sections. J represents the number of sub-pixels in section 1 of the N sections, where section 1 is the section of the N sections closest to the same reference region.

[0098] Figure 9A Schematic diagram showing the layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure. Figure 9A In some embodiments, the array substrate includes N sections (P1 to PN). In some embodiments, the array substrate includes (2N-1) gate lines GL and (J×N) data lines DL. J represents the number of sub-pixels in section 1 of the N sections.

[0099] In some embodiments, the first gate line GL1 of the (2N-1) gate lines GL is configured to provide a gate driving signal to the sub-pixels in the first portion P1. Each of the second portion P2 to the Nth portion PN of the N portions is configured to receive gate driving signals from two gate lines. Figure 9A , the second part P2 is configured to receive gate driving signals from gate lines GL2 and GL3; the Nth part PN is configured to receive gate driving signals from gate lines GL(2N-2) and GL(2N-1).

[0100] In some embodiments, the (J×N) data lines include J groups of data lines, and each group of the J groups of data lines includes N data lines. Figure 9B Show Figure 9A The layout of the data lines in the array substrate is shown in FIG. Figure 9A and Figure 9B In one example, the number of sub-pixels in the first section P1 of the N sections is 3, e.g., J=3. The (J×N) data lines include three groups of data lines, e.g., set1, set2, and set3. Each of the J groups of data lines includes N data lines. For example, the first group of data lines set1 includes N data lines DL1, DL2, ..., DLN.

[0101] In some embodiments, the nth data line in each group is configured to provide data signals to one or more sub-pixels in n of the N sections, 1≤n≤N. Figure 9A and Figure 9B The first data line DL1 is configured to provide data signals to one or more sub-pixels in a single section (PN) among the N sections. The second data line DL2 is configured to provide data signals to one or more sub-pixels in two sections (PN and P(N-1)) among the N sections. The Nth data line DLN is configured to provide data signals to one or more sub-pixels in N sections (P1 to PN) among the N sections.

[0102] Figure 9C 1 shows a plurality of rows of sub-pixels connected to a corresponding set of data lines in an array substrate according to some embodiments of the present disclosure. Figures 9A to 9C The Nth data line DLN of the N data lines in each group (e.g., set1) is configured to provide data signals to a row of sub-pixels rN in the N sections. The first data line of the N data lines in each group is configured to provide data signals to two sub-pixels in the N section of the N sections (e.g., Figure 9C The n'th data line of the N data lines in each group is configured to respectively supply data signals to two rows of sub-pixels in n'th sections of the N sections (eg, Figure 9C rn'1 and rn'2 in each group) provide data signals, where 1<n'<N. For example, when n'=2, the second data line DL2 of the N data lines in each group is configured to respectively supply data signals to two rows of sub-pixels in two of the N sections (for example, Figure 9C PN and P(N-1)) in provide data signals. Figure 9F A row of sub-pixels rN is shown according to some embodiments of the present disclosure. Figure 9G A row of sub-pixels rn'1 in one of n' sections out of N sections is shown. Figure 9HA row of sub-pixels rn'1 in one of n' sections out of N sections is shown. As used herein, the term "a row of sub-pixels" refers to a plurality of sub-pixels having substantially the same orientation and coupled to the same data line.

[0103] Reference Figure 9A and Figure 9B , in the j'th group among the J groups of data lines, 1<j'<J, two sub-pixels in the same portion have the same orientation (e.g., the first orientation), wherein at least 40% (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) of the elongated side of each sub-pixel is directly adjacent to the N-th data line DLN. Optionally, in the j'th group among the J groups of data lines, 1<j'<J, two sub-pixels in the same portion have the same orientation (e.g., the first orientation), wherein at least 40% (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) of the elongated side of each sub-pixel is directly adjacent to the n"th data line among the N data lines, 1≤n" <N。

[0104] Reference Figure 9CIn some embodiments, the first subpixel sp1 in the Ax arc and the second subpixel sp2 in the A(x+1) arc have different shapes, and the Ax arc and the A(x+1) arc are directly adjacent to each other. In some embodiments, the wider end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc and the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc are adjacent to each other. For example, the narrower end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc is located on the side of the first subpixel in the first subpixel sp1 in the Ax arc away from the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc; and the narrower end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc is located on the side of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc away from the wider end of the light-emitting area of ​​each first subpixel in the Ax arc. Each of the second subpixels sp2 in the A(x+1) arc is located on a side of each of the first subpixels sp1 in the Ax arc that is away from the same reference region RR. In some embodiments, the wider end of the light-emitting region of each of the first subpixels sp1 in the Ax arc has a convex shape that protrudes toward the wider end of the light-emitting region of each of the second subpixels sp2 in the A(x+1) arc. In some embodiments, the wider end of the light-emitting region of each of the second subpixels sp2 in the A(x+1) arc has a concave shape that is recessed from the wider end of the light-emitting region of each of the first subpixels sp1 in the Ax arc.

[0105] Figure 9D FIG. 4 shows a sub-pixel in an array substrate according to some embodiments of the present disclosure. Figure 9DIn some embodiments, the first subpixel sp1 in the Ax arc and the second subpixel sp2 in the A(x+1) arc may have the same or different shapes, and the Ax arc and the A(x+1) arc are directly adjacent to each other. In some embodiments, the wider end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc and the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc are adjacent to each other. For example, the narrower end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc is located on the side of the first subpixel in the first subpixel sp1 in the Ax arc away from the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc; and the narrower end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc is located on the side of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc away from the wider end of the light-emitting area of ​​each first subpixel in the Ax arc. Each second subpixel in the second subpixel sp2 in the A(x+1) arc is located on a side of each first subpixel in the first subpixel sp1 in the Ax arc that is away from the same reference region RR. In some embodiments, the wider end of the light-emitting region of each first subpixel in the first subpixel sp1 in the Ax arc has a convex shape that protrudes toward the wider end of the light-emitting region of each second subpixel in the second subpixel sp2 in the A(x+1) arc. In some embodiments, the wider end of the light-emitting region of each second subpixel in the second subpixel sp2 in the A(x+1) arc has a convex shape that protrudes toward the wider end of the light-emitting region of each first subpixel in the first subpixel sp1 in the Ax arc.

[0106] Figure 9E FIG. 4 shows a sub-pixel in an array substrate according to some embodiments of the present disclosure. Figure 9EIn some embodiments, the first subpixel sp1 in the Ax arc and the second subpixel sp2 in the A(x+1) arc may have the same or different shapes, and the Ax arc and the A(x+1) arc are directly adjacent to each other. In some embodiments, the wider end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc and the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc are adjacent to each other. For example, the narrower end of the light-emitting area of ​​each first subpixel in the first subpixel sp1 in the Ax arc is located on the side of the first subpixel in the first subpixel sp1 in the Ax arc away from the wider end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc; and the narrower end of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc is located on the side of the light-emitting area of ​​each second subpixel in the second subpixel sp2 in the A(x+1) arc away from the wider end of the light-emitting area of ​​each first subpixel in the Ax arc. Each second subpixel in the second subpixel sp2 in the A(x+1) arc is located on a side of each first subpixel in the first subpixel sp1 in the Ax arc that is away from the same reference region RR. In some embodiments, the wider end of the light-emitting region of each first subpixel in the first subpixel sp1 in the Ax arc has a concave shape that is recessed from the wider end of the light-emitting region of each second subpixel in the second subpixel sp2 in the A(x+1) arc. In some embodiments, the wider end of the light-emitting region of each second subpixel in the second subpixel sp2 in the A(x+1) arc has a concave shape that is recessed from the wider end of the light-emitting region of each first subpixel in the first subpixel sp1 in the Ax arc.

[0107] The sub-pixels in the array substrate according to the present disclosure may have various appropriate shapes.

[0108] refer to Figure 9AIn some embodiments, at least some of the gate lines (e.g., GL2, GL(2N-2)) intersect with the sub-pixel areas of one or more sub-pixel arcs; and at least some of the gate lines (e.g., GL1, GL3, GL(2N-1)) intersect with the inter-sub-pixel area of ​​the array substrate. As used herein, the sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in a liquid crystal display, or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel. Optionally, the pixel may include a plurality of separate light-emitting areas corresponding to a plurality of sub-pixels in the pixel. Optionally, the sub-pixel area is the light-emitting area of ​​a red sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​a green sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​a blue sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​a white sub-pixel. As used herein, the inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in a liquid crystal display, or the area corresponding to the pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-subpixel region is a region between two adjacent sub-pixel regions in two adjacent pixels. Optionally, the inter-subpixel region is a region between a sub-pixel region of a red sub-pixel and a sub-pixel region of an adjacent green sub-pixel. Optionally, the inter-subpixel region is a region between a sub-pixel region of a red sub-pixel and a sub-pixel region of an adjacent blue sub-pixel. Optionally, the inter-subpixel region is a region between a sub-pixel region of a green sub-pixel and a sub-pixel region of an adjacent blue sub-pixel.

[0109] Figure 9I Schematic diagram showing the layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure. Figure 9I , all gate lines are arranged in the inter-sub-pixel region of the array substrate. Optionally, two adjacent gate lines are arranged in the same inter-sub-pixel region. For example, GL1 and GL2 are arranged in the same inter-sub-pixel region. By having this structure, Figure 9A Compared with the array substrate shown in FIG. 1 , the aperture ratio of the array substrate can be improved.

[0110] Figure 10A Schematic diagram showing the layout of gate lines and data lines in an array substrate according to some embodiments of the present disclosure. Figure 10A In some embodiments, the array substrate includes N sections (P1 to PN). In some embodiments, the array substrate includes N gate lines and (J×(2N-1)) data lines. J represents the number of sub-pixels in section 1 of the N sections. Figure 10AAs shown, in some embodiments, each of the (N - 1) gate lines among the N gate lines is located between two adjacent ones of the N portions. For example, the first gate line GL1 is located between the first portion P1 and the second portion P2; the second gate line GL2 is located between the second portion P2 and the third portion P3. Each gate line is configured to provide a gate driving signal to two adjacent ones of the N portions. For example, the first gate line GL1 is configured to provide a gate driving signal to the first portion P1 and the second portion P2; the second gate line is configured to provide a gate driving signal to the second portion P2 and the third portion P3.

[0111] In some embodiments, the (J×(2N - 1)) data lines include J groups of data lines, and each group among the J groups of data lines includes (2N - 1) data lines. Figure 10B Shown Figure 10A is the layout of the data lines in the array substrate shown in. Refer to Figure 10A and Figure 10B , in one example, the number of sub-pixels in the first portion P1 among the N portions is 3, for example J = 3. The (J×(2N - 1)) data lines include three groups of data lines, for example, set1, set2, and set3. Each group among the J groups of data lines includes (2N - 1) data lines. For example, the first group of data lines set1 includes (2N - 1) data lines, DL1, DL2,......, DL(2n’ - 1), DL2n’,......, DLN.

[0112] In some embodiments, the (2n’ - 1)th data line in each group is configured to provide a data signal to one or more sub-pixels in n’ of the N portions, 1 < n’ < N. In Figure 10A and Figure 10B depicted in, N = 3, n’ = 2; the 3rd data line in each group is configured to provide a data signal to one or more sub-pixels in two of the N portions (P2 and P3). In another example, N = 3, n’ = 1; the first data line DL1 in each group is configured to provide a data signal to one or more sub-pixels in one of the N portions (P3). [[ID=第十九]]

[0113] In some embodiments, the 2n’th data line in each group is configured to provide a data signal to one or more sub-pixels in n’ of the N portions. In Figure 10A and Figure 10BIn one example depicted in FIG, N=3, n'=2; the fourth data line in each group is configured to provide data signals to one or more sub-pixels in two of the N sections (P2 and P3). In another example, N=3, n'=1; the second data line DL2 in each group is configured to provide data signals to one or more sub-pixels in one of the N sections (P3).

[0114] Figure 10C 1 shows a plurality of rows of sub-pixels connected to a corresponding set of data lines in an array substrate according to some embodiments of the present disclosure. FIG. 10A to FIG. 10C , the (2N-1)th data line in each group (for example, set1) is configured to provide data signals to a row of sub-pixels r(2N-1) in the N parts, respectively. The (2n'-1)th data line DL(2n'-1) in each group is configured to provide data signals to a row of first sub-pixels rsp1 in n' parts in the N parts, respectively. For example, when n'=2, the 3rd data line in each group is configured to provide data signals to a row of first sub-pixels rsp1 in two parts (P2 and P3) in the N parts, respectively. The 2n'th data line DL2n' in each group is configured to provide data signals to a row of second sub-pixels rsp2 in n' parts in the N parts, respectively. For example, when n'=2, the fourth data line in each group is configured to provide data signals to a row of second sub-pixels rsp2 in two parts (P2 and P3) in the N parts, respectively. Figure 10D A row of sub-pixels r(2N-1) is shown according to some embodiments of the present disclosure. Figure 10E A row of sub-pixels rspl in one of n' sections out of N sections is shown. Figure 10F A row of sub-pixels rsp2 in one of n' sections out of N sections is shown.

[0115] Figure 11A The diagram shows the layout of signal lines in an array substrate according to some embodiments of the present disclosure. Figure 11B The diagram shows the layout of gate lines in an array substrate according to some embodiments of the present disclosure. Figure 11C The diagram shows the layout of data lines in an array substrate according to some embodiments of the present disclosure. Figures 11A to 11C The layout of the signal lines shown can be applied to, for example, Figure 1 、 Figure 6A 、 Figure 9A or Figure 10A The array substrate shown. Figures 11A to 11C In some embodiments, the array substrate includes a plurality of data lines DL, a plurality of gate lines GL, one or more on-array-substrate gate driving circuits GOA configured to provide gate driving signals to the plurality of gate lines, and a plurality of connection lines CL.

[0116] In some embodiments, the array substrate includes M gate lines (e.g., GL1, GL2, GL3, GL4, and GL5), which are arranged as M partial circles surrounding the same reference area; and (M-1) connecting lines (e.g., CL1, CL2, CL3, and CL4). The (M-1) connecting lines are located on a different layer from the M gate lines.

[0117] In some embodiments, the i-th connection line among the (M-1) connection lines electrically connects the (i+1)-th gate line to the gate drive circuit on the array substrate, where 1≤i≤(M-1). For example, CL1 electrically connects GL2 to the gate drive circuit on the array substrate; CL2 electrically connects GL3 to the gate drive circuit on the array substrate; CL3 electrically connects GL4 to the gate drive circuit on the array substrate; and CL4 electrically connects GL5 to the gate drive circuit on the array substrate.

[0118] In some embodiments, the i-th connection line intersects i gate lines. For example, CL1 intersects one gate line (GL1); CL2 intersects two gate lines (GL1 and GL2); CL3 intersects three gate lines (GL1, GL2, GL3); and CL4 intersects four gate lines (GL1, GL2, GL3, and GL4).

[0119] Figure 12 It is along Figure 11A Cross-sectional view of line A-A' in FIG. Figure 11A and Figure 12 In some embodiments, the plurality of connection lines CL and the plurality of data lines DL are located in the same layer.

[0120] The array substrate according to the present disclosure is particularly advantageous for manufacturing display panels with curved edges (e.g., circular display panels). In related display panels, subpixels are typically fabricated to have rectangular shapes. When forming the curved edges of related display panels, subpixels adjacent to the curved edges must be cut. Segmenting rectangular subpixels along the curved edges often results in subpixels of different colors (e.g., red subpixels, green subpixels, and blue subpixels) having significantly different areas, or even results in the loss of subpixels of one or more colors along the curved edges. When a black matrix with curved edges is used along the curved edges, display panels of the related art are prone to rainbow pattern defects. To eliminate the rainbow pattern defects, a black matrix can be applied to the segmented subpixels along the curved edges. However, this embodiment results in jagged edge defects in display panels of the related art. Therefore, in display panels of the related art, it is difficult to simultaneously eliminate both rainbow pattern defects and jagged edge defects. Alternatively, subpixels along the curved edges of display panels of the related art can be fabricated to have smaller sizes. However, this embodiment still cannot completely eliminate both rainbow pattern defects and jagged edge defects. Furthermore, making the sub-pixels along the curved edges smaller may result in "local dotted lines along the edges," which adversely affects the display quality.

[0121] Figure 13 Several defects along the curved edges in the display panel of the related art are shown. The array substrate according to the present disclosure effectively avoids these defects.

[0122] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS devices, and the like. Optionally, the display device is a liquid crystal display device. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a miniature light-emitting diode display device.

[0123] The display device can have various suitable shapes. Examples of suitable shapes for the display device include circular, square, rectangular, elliptical, triangular, polygonal, and irregular shapes.

[0124] In some embodiments, the display device is a liquid crystal display device. Figure 14 1 is a diagram showing the structure of a liquid crystal display device according to some embodiments of the present disclosure. Figure 14In some embodiments, a liquid crystal display device includes a liquid crystal display panel 0 and a backlight module 4. In some embodiments, the liquid crystal display panel 0 includes an array substrate 1, an opposing substrate 2, and a liquid crystal layer 3 located between the array substrate 1 and the opposing substrate 2. The liquid crystal layer 3 includes liquid crystal molecules 30 configured to switch between a light-transmitting state and a light-shielding state. In some embodiments, the opposing substrate 2 includes a base substrate 20, a black matrix layer 22, and a color filter layer 21 on the base substrate 20. The array substrate 1 includes a base substrate 12 and a thin-film transistor substrate 11 on the base substrate 12.

[0125] The display device according to the present disclosure is not limited to a liquid crystal display device, but can be a display device of various appropriate types. In some embodiments, the display device is a light emitting diode display device. Figure 15 Detailed structure of the display area of ​​the light emitting diode display device according to some embodiments of the present disclosure is shown. Figure 15In some embodiments, the display device includes in the display area: a base substrate BS (for example, a flexible base substrate); an active layer ACT of each thin film transistor in a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI, which is located on a side of the active layer ACT away from the base substrate BS; a gate G and a first capacitor electrode Ce1 (both part of the first gate metal layer), which are located on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN, which is located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of the second gate metal layer), which is located on a side of the insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD, which is located on a side of the second capacitor electrode Ce2 away from the gate The gate insulating layer GI includes a source electrode S and a drain electrode D (part of the first SD metal layer), which are located on a side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX, which is located on a side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1, which is located on a side of the passivation layer PVX away from the interlayer dielectric layer ILD; a second planarization layer PLN2, which is located on a side of the first planarization layer PLN1 away from the passivation layer PVX; a relay electrode RE (part of the second SD metal layer), which is located on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; a pixel defining layer PDL, which defines a sub-pixel opening and is located on a side of the second planarization layer PLN2 away from the substrate BS; and a light-emitting element LE in the sub-pixel opening. The light-emitting element LE includes an anode AD, which is located on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL, which is located on a side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD, which is located on a side of the light-emitting layer EL away from the anode AD. The display device further includes an encapsulation layer EN in the display area, which encapsulates the light emitting element LE and is located on a side of the cathode layer CD away from the base substrate BS.

[0126] In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1, which is located on the side of the cathode layer CD away from the substrate BS; a first organic encapsulation sublayer IJP1, which is located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; a second inorganic encapsulation sublayer CVD2, which is located on the side of the first organic encapsulation sublayer IJP1 away from the substrate BS; the second inorganic encapsulation sublayer CVD2 is located on the side of the first organic encapsulation sublayer IJP1 away from the substrate BS; the second organic encapsulation sublayer IJP2 is located on the side of the second inorganic encapsulation sublayer CVD2 away from the substrate BS; and a third inorganic encapsulation sublayer CVD3, which is located on the side of the second organic encapsulation sublayer IJP2 away from the substrate BS.

[0127] The array substrate also includes a buffer layer BUF in the display area, which is located on the side of the encapsulation layer EN away from the base substrate BS; a first touch electrode layer TE1, which is located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulation layer TI, which is located on the side of the first touch electrode layer TE1 away from the buffer layer BUF; a second touch electrode layer TE2, which is located on the side of the touch insulation layer TI away from the buffer layer BUF; and an outer coating layer OC, which is located on the side of the second touch electrode layer TE2 away from the touch insulation layer TI.

[0128] refer to Figure 15 The display device includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SLL1, and a second signal line layer SLL2. The display device also includes an insulating layer IN between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD located between the second conductive layer Gate2 and the first signal line layer SLL1; and at least one passivation layer PVX or a planarization layer PLN located between the first signal line layer SLL1 and the second signal line layer SLL2.

[0129] In another aspect, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of sub-pixels in at least one region. Optionally, the light-emitting region of each of the plurality of sub-pixels is formed to have a first end and a second end, the second end being located on a side of the first end away from a common reference region relative to the plurality of sub-pixels in the region; and the direction from the second end to the first end of each of the plurality of sub-pixels is substantially directed toward the common reference region. Optionally, in the region, the number of pixels per inch (PPI) is substantially the same depending on the distance from the common reference region. Optionally, in the region, forming the plurality of sub-pixels includes forming first sub-pixels in a first orientation and forming second sub-pixels in a second orientation. Optionally, the width of the first light-emitting region of each of the first sub-pixels increases from the first end to the second end. Optionally, the width of the second light-emitting region of each of the second sub-pixels decreases from the first end to the second end. Optionally, the first orientation and the second orientation are substantially opposite to each other.

[0130] Various suitable conductive materials and various suitable manufacturing methods can be used to make gate line, data line and connecting line.For example, conductive material can be deposited on substrate and patterned by plasma enhanced chemical vapor deposition (PECVD) process.The example of suitable conductive material for making gate line, data line and connecting line includes but is not limited to aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy etc.

[0131] In some embodiments, the method includes forming N parts arranged in sequence in the region, where N is an integer greater than 2. Optionally, the (n+1)th part is formed to be located on a side of the nth part away from the same reference region, 1≤n≤(N-1). Optionally, the sub-pixels in the nth part that are directly adjacent to the (n+1)th part and the sub-pixels in the (n+1)th part that are directly adjacent to the nth part are formed to have different orientations, wherein the wider end of the light-emitting area of ​​the sub-pixel in the nth part that is directly adjacent to the (n+1)th part is directly adjacent to the wider end of the light-emitting area of ​​the sub-pixel in the (n+1)th part that is directly adjacent to the nth part.

[0132] In some embodiments, a plurality of adjacent sub-pixels in each of the N portions constitute a pixel.

[0133] In some embodiments, the N portions are arranged along N arcs, respectively. Optionally, the N arcs are formed to at least partially surround the same reference region.

[0134] In some embodiments, the N arcs are respectively N circles. Optionally, the same reference area is the same central area about the N circles, and the N parts are respectively arranged along the N circles. Optionally, the N circles substantially surround the same central area.

[0135] In some embodiments, forming each of the N portions includes forming one or more sub-pixel arcs. Alternatively, forming the array substrate includes forming X sub-pixel arcs that at least partially surround the same reference region, where X is an integer greater than 2. Alternatively, sub-pixels from any two directly adjacent sub-pixel arcs are formed to have different orientations.

[0136] In some embodiments, the first of the N portions is formed to include one sub-pixel arc, the nth portion is formed to include two sub-pixel arcs, and the Nth portion is formed to include two sub-pixel arcs, and X=2(N-1)+1.

[0137] In some embodiments, the first portion of the N portions is formed to include a sub-pixel arc. Optionally, adjacent sub-pixels along a sub-pixel arc have the same orientation.

[0138] In some embodiments, the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth portion is greater than the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the (n+1)th portion.

[0139] In some embodiments, the ratio of the number of sub-pixels having a first orientation to the number of sub-pixels having a second orientation in the n-th portion is in the range of (n - 0.5):(n - 1) to (n + 0.5):(n - 1), e.g., n:(n - 1).

[0140] In some embodiments, the sub-pixels in the n-th portion that are directly adjacent to the (n + 1)-th portion are formed to have the first orientation; and the sub-pixels in the (n + 1)-th portion that are directly adjacent to the n-th portion are formed to have the second orientation.

[0141] In some embodiments, forming at least the m-th portion among the N portions includes forming a first sub-portion and a second sub-portion, the second sub-portion being located on a side of the first sub-portion away from the same reference region, where 1 < m < (N - 1). Optionally, the sub-pixels of the first sub-portion and the sub-pixels of the second sub-portion have different orientations.

[0142] In some embodiments, the sub-pixels of the first sub-portion are formed to have the second orientation. Optionally, the sub-pixels of the second sub-portion are formed to have the first orientation.

[0143] In some embodiments, the number of sub-pixels formed in the n-th portion is S×I×(2n - 1); S represents the number of sub-pixels in each pixel; and I represents the number of sub-pixels in the first portion among the N portions divided by S, the first portion being the portion closest to the same reference region among the N portions.

[0144] In some embodiments, the method includes forming at least N gate lines and at least (J×N) data lines. Optionally, each of the (N - 1) gate lines among the N gate lines is formed to be located between two adjacent portions among the N portions. Optionally, J represents the number of sub-pixels in the first portion among the N portions, the first portion being the portion closest to the same reference region among the N portions.

[0145] In some embodiments, the method includes forming (2N - 1) gate lines and (J×N) data lines.

[0146] In some embodiments, the first gate line among the (2N - 1) gate lines is configured to provide a gate driving signal to the sub-pixels in the first portion. Optionally, each of the second to N-th portions among the N portions is configured to receive a gate driving signal from two gate lines.

[0147] In some embodiments, forming (J×N) data lines includes forming J groups of data lines, each group of the J groups of data lines including N data lines. Optionally, the nth data line in each group is configured to provide a data signal to one or more sub-pixels in n of the N sections, 1≤n≤N.

[0148] In some embodiments, the Nth data line of the N data lines in each group is configured to provide data signals to a row of sub-pixels in the N sections. Alternatively, the first data line of the N data lines in each group is configured to provide data signals to two sub-pixels in the N section of the N sections. Alternatively, the n'th data line of the N data lines in each group is configured to provide data signals to two rows of sub-pixels in the n' section of the N sections. <n’<N。

[0149] In some embodiments, each of the J groups of data lines includes N data lines. Optionally, in the j'th group of the J groups of data lines, 1<j'<J, two sub-pixels in the same portion have the same orientation, wherein at least 40% of the elongated side of each sub-pixel is directly adjacent to the Nth data line. Optionally, in the j'th group of the J groups of data lines, 1<j'<J, two sub-pixels in the same portion have the same orientation, wherein at least 40% of the elongated side of each sub-pixel is directly adjacent to the n"th data line of the N data lines.

[0150] In some embodiments, the method includes forming N gate lines and (J×(2N−1)) data lines.

[0151] In some embodiments, each gate line is configured to provide a gate driving signal to the two adjacent portions among the N portions.

[0152] In some embodiments, forming (J×(2N-1)) data lines includes forming I groups of data lines, each group of the I groups of data lines including (2N-1) data lines. Optionally, the (2n'-1)th data line in each group is configured to provide a data signal to one or more sub-pixels in n' of the N sections, 1<n'<N. Optionally, the 2n'th data line in each group is configured to provide a data signal to one or more sub-pixels in n' of the N sections.

[0153] In some embodiments, the first data line in each group is configured to provide data signals to a row of sub-pixels in the N sections. Alternatively, the (2n'-1)th data line in each group is configured to provide data signals to a row of first sub-pixels in n' sections of the N sections, where 1<n'<N. Alternatively, the 2n'th data line in each group is configured to provide data signals to a row of second sub-pixels in n' sections of the N sections.

[0154] In some embodiments, the method includes forming M gate lines, the M gate lines being arranged as M partial circles surrounding the same reference area; and forming (M-1) connecting lines. Optionally, the (M-1) connecting lines are located in different layers from the M gate lines. Optionally, the i-th connecting line among the (M-1) connecting lines electrically connects the (i+1)-th gate line to the gate drive circuit on the array substrate, 1≤i≤(M-1). Optionally, the i-th connecting line intersects the i-th gate line.

[0155] In some embodiments, the (M-1) connection lines are formed to be located at the same layer as the at least (J×N) data lines.

[0156] In some embodiments, areas of the sub-pixels in the region are substantially the same.

[0157] In some embodiments, the number of sub-pixels in the N parts increases with increasing distance from the same reference area.

[0158] In some embodiments, the width of the same reference region is less than twice the maximum length of each sub-pixel.

[0159] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to specific embodiments, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate comprising a plurality of sub-pixels in at least one region; The light emitting region of each of the plurality of sub-pixels has a first end and a second end, the second end being located on a side of the first end away from a same reference region with respect to the plurality of sub-pixels in the region; The directions from the second ends to the first ends of the plurality of sub-pixels respectively substantially point to the same reference area; as well as In the regions, the number of pixels per inch (PPI) is substantially the same depending on the distance from the same reference region; Wherein, in the region, the plurality of sub-pixels include a first sub-pixel in a first orientation and a second sub-pixel in a second orientation; The width of the first light emitting region of each of the first sub-pixels increases from the first end to the second end; the width of the second light emitting region of each of the second sub-pixels decreases from the first end to the second end; and The first orientation and the second orientation are substantially opposite to each other.

2. The array substrate according to claim 1, comprising N parts sequentially arranged in the region, where N is an integer greater than 2; in, The (n+1)th portion is located on the side of the nth portion away from the same reference region, 1≤n≤(N-1); and The sub-pixel in the nth part that is directly adjacent to the (n+1)th part and the sub-pixel in the (n+1)th part that is directly adjacent to the nth part have different orientations, wherein the wider end of the light-emitting area of ​​the sub-pixel in the nth part that is directly adjacent to the (n+1)th part is directly adjacent to the wider end of the light-emitting area of ​​the sub-pixel in the (n+1)th part that is directly adjacent to the nth part.

3. The array substrate according to claim 2, wherein: A plurality of adjacent sub-pixels in each of the N parts constitutes one pixel.

4. The array substrate according to claim 2, wherein: Each of the N portions includes one or more sub-pixel arcs; The array substrate includes X sub-pixel arcs at least partially surrounding the same reference area, where X is an integer greater than 2; as well as Sub-pixels from any two directly adjacent arcs of sub-pixels have different orientations.

5. The array substrate according to claim 4, wherein: The first portion of the N portions includes one sub-pixel arc, the nth portion includes two sub-pixel arcs, and the Nth portion includes two sub-pixel arcs, and X=2(N-1)+1.

6. The array substrate according to claim 4, wherein: The first portion of the N portions includes a sub-pixel arc, and adjacent sub-pixels along the sub-pixel arc have the same orientation.

7. The array substrate according to any one of claims 2 to 6, wherein: The ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the nth part is greater than the ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the (n+1)th part.

8. The array substrate according to claim 7, wherein: A ratio of the number of sub-pixels having the first orientation to the number of sub-pixels having the second orientation in the n-th portion is in the range of (n-0.5):(n-1) to (n+0.5):(n-1).

9. The array substrate according to any one of claims 2 to 8, wherein: The sub-pixels in the nth portion that are directly adjacent to the (n+1)th portion have the first orientation; and The sub-pixels in the (n+1)th portion that are directly adjacent to the nth portion have a second orientation.

10. The array substrate according to any one of claims 2 to 9, wherein: At least the m-th part among the N parts includes a first sub-part and a second sub-part, and the second sub-part is located on a side of the first sub-part away from the same reference area, where 1 < m < (N - 1); and The sub-pixels of the first sub-part and the sub-pixels of the second sub-part have different orientations.

11. The array substrate according to claim 10, wherein: The sub-pixels of the first sub-part have the second orientation; and The sub-pixels of the second sub-part have the first orientation.

12. The array substrate according to any one of claims 2 to 11, wherein: The number of sub-pixels in the n-th part is S×I×(2n - 1); S represents the number of sub-pixels in each pixel; And I represents the number of sub-pixels in the first part among the N parts divided by S, and the first part is the part closest to the same reference area among the N parts.

13. The array substrate according to any one of claims 2 to 12, comprising at least N gate lines and at least (J×N) data lines; in, Each of the (N - 1) gate lines among the N gate lines is located between two adjacent parts among the N parts; And J represents the number of sub-pixels in the first part among the N parts, and the first part is the part closest to the same reference area among the N parts.

14. The array substrate according to claim 13, comprising (2N - 1) gate lines and (J×N) data lines.

15. The array substrate according to claim 14, wherein: The first gate line among the (2N - 1) gate lines is configured to provide a gate driving signal to the sub-pixels in the first part; And Each of the second part to the N-th part among the N parts is configured to receive a gate driving signal from two gate lines.

16. The array substrate according to claim 14, wherein: The (J×N) data lines include J groups of data lines, and each group among the J groups of data lines includes N data lines; and The n-th data line in each group is configured to provide a data signal to one or more sub-pixels in the n-th part among the N parts, where 1 ≤ n ≤ N.

17. The array substrate according to claim 16, wherein: The N-th data line among the N data lines in each group is configured to provide a data signal to a row of sub-pixels in each of the N parts respectively; The first data line among the N data lines in each group is configured to provide a data signal to two sub-pixels in the N-th part among the N parts; And The n'-th data line among the N data lines in each group is configured to provide a data signal to two rows of sub-pixels in each of the n'-th parts among the N parts respectively, where 1 < n' < N.

18. The array substrate according to claim 14, wherein: Each of the J groups of data lines includes N data lines; In the j'-th group among the J groups of data lines, where 1 < j' < J, two sub-pixels in the same part have the same orientation, and at least 40% of the long side of each sub-pixel is directly adjacent to the N-th data line; And In the j'-th group among the J groups of data lines, where 1 < j' < J, two sub-pixels in the same part have the same orientation, and at least 40% of the long side of each sub-pixel is directly adjacent to the n''-th data line among the N data lines.

19. The array substrate according to claim 13, comprising N gate lines and (J×(2N - 1)) data lines.

20. The array substrate according to claim 19, wherein: Each gate line is configured to provide a gate driving signal to the two adjacent sections among the N sections.

21. The array substrate according to claim 19, wherein: The (J×(2N-1)) data lines include I groups of data lines, and each group of the I groups of data lines includes (2N-1) data lines; The (2n′-1)th data line in each group is configured to provide a data signal to one or more sub-pixels in n′ sections of the N sections, 1<n′<N; as well as The 2n′-th data line in each of the groups is configured to provide a data signal to one or more sub-pixels in n′ sections among the N sections.

22. The array substrate according to claim 21, wherein: The first data lines in each group are configured to provide data signals to a row of sub-pixels in the N parts respectively; The (2n′-1)th data line in each group is configured to provide data signals to a row of first sub-pixels in n′ sections of the N sections, respectively, where 1<n′<N; as well as The 2n′-th data lines in each group are configured to provide data signals to a row of second sub-pixels in n′ sections of the N sections, respectively.

23. The array substrate according to any one of claims 13 to 22, comprising: M grid lines, the M grid lines being arranged as M partial circles surrounding the same reference area; as well as (M-1) connecting lines; Wherein, the (M-1) connecting lines and the M gate lines are located in different layers; The i-th connecting line among the (M-1) connecting lines electrically connects the (i+1)-th gate line to the gate driving circuit on the array substrate, 1≤i≤(M-1); and The i-th connecting line crosses i gate lines.

24. The array substrate according to claim 23, wherein: The (M-1) connection lines and the at least (J×N) data lines are located in the same layer.

25. The array substrate according to any one of claims 1 to 24, wherein: The areas of the sub-pixels in the region are substantially the same.

26. The array substrate according to any one of claims 2 to 25, wherein: The number of sub-pixels in the N parts increases as the distance from the same reference area increases.

27. The array substrate according to any one of claims 1 to 26, wherein: The width of the same reference area is less than twice the maximum length of each sub-pixel.

28. A display device comprising the array substrate according to any one of claims 1 to 27 and one or more integrated circuits connected to the array substrate.

29. The display device according to claim 28, wherein The display device has a circular shape.

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