Multistage clamping test device and test system

Abstract

The invention provides a multi-stage clamping test device and test system, the test device comprises a multi-stage clamping circuit, a test board and a connecting device, and the test board comprises a control circuit and a plurality of relays; the control circuit is used for controlling the plurality of relays to be switched on and off so as to switch a test loop of the test device; and each stage of clamping circuit is used for clamping the voltage of the position where each stage of clamping circuit is located so as to reduce the influence generated by parasitic inductance in the test loop. By adopting the test device, clamping can be performed at different positions in the test device through the multi-stage clamping circuit, so that the influence generated by parasitic inductance in a test loop is reduced, the overvoltage generated by the to-be-tested module in the switching process is reduced, the maximum switching speed of the to-be-tested module is improved, the test efficiency is improved, and meanwhile, the test efficiency is improved. The size of each stage of clamping circuit can be reduced by clamping through the multi-stage clamping circuit, the integration degree is improved, the cost is low, and the applicability is high.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a multi-stage clamping test device and a test system. Background Art

[0002] In the field of power electronics technology, a test device is usually used to test a module to be tested consisting of a power semiconductor chip. The test device connects the module to be tested to a test board through a connecting device, and connects the power supply through the test board. Among them, the module to be tested usually includes multiple components to be tested, and the test device usually needs to establish an electrical connection between different components to be tested in the module to be tested and the power supply, or to form different test loops. The test board usually includes a control circuit and multiple relays. The control circuit can switch the test loop by controlling the on and off of the relays. Since the parasitic inductance in the test loop is greater than the parasitic inductance of the module to be tested in a normal working environment, it will not only affect the test results of the module to be tested, but also limit the maximum switching speed of the module to be tested. In other words, it will limit the pull-off test capability of the test device. In the prior art, a decoupling capacitor is usually used between the test board and the power supply to clamp the test loop to decouple the parasitic inductance generated by the front-end circuit of the decoupling capacitor, or to reduce the influence of the parasitic inductance generated by the front-end circuit of the decoupling capacitor on the back-end circuit. However, to ensure that the decoupling capacitors can effectively decouple the parasitic inductance generated by the front-end circuitry, larger capacitance values ​​are typically required, reducing the device's integration density. When a circuit breaker is placed between the power supply and the test board, excessively large decoupling capacitance can weaken the circuit breaker's ability to protect the test device from overcurrent and short-circuit conditions, reducing its reliability and safety. Furthermore, decoupling capacitors lack the ability to decouple parasitic inductance introduced by components such as the test board in the back-end circuitry, making them less suitable for use. Summary of the Invention

[0003] The present application provides a multi-stage clamping test device and test system, which can sense the current size in the bus through a coupling device. When the current in the bus is too large, the electrical connection between the energy storage circuit and the ignition disconnect module is turned on, so that an ignition current is generated in the ignition circuit to cause the gunpowder explosion to drive the cutting component to move and cut off the disconnecting section on the bus, thereby disconnecting the electrical connection between the power supply and the load. It has high reliability, simple structure, low cost and strong applicability.

[0004] In a first aspect, the present application provides a multi-stage clamping test device, which may include a multi-stage clamping circuit, a test board and a connecting device. Here, the connecting device can be used to connect the test board and the module to be tested, the module to be tested has multiple components to be tested, the test board can be used to connect the power supply through a circuit breaker, the first-stage clamping circuit in the multi-stage clamping circuit can be used to connect between the circuit breaker and the test board, the second-stage clamping circuit in the multi-stage clamping circuit can be used to connect between the test board and the connecting device, and the test board may include a control circuit and multiple relays. The control circuit here can be used to control the multiple relays to be turned on and off to switch the test circuit of the test device, and the test circuit is a circuit formed by establishing electrical connections between different components to be tested in the multiple components to be tested and the power supply. The clamping circuits of each level in the multi-stage clamping circuit here are respectively used to clamp the voltage at the location of the clamping circuit of each level to reduce the influence of parasitic inductance in the test circuit.

[0005] In the present application, the test device can test the module to be tested to verify the performance of the module to be tested. The module to be tested can be a semiconductor chip such as a power semiconductor chip or an inherited circuit. Here, the test device can connect the module to be tested to the test board through a connecting device, and connect the power supply through the test board. The module to be tested usually includes a plurality of components to be tested, and the test device usually needs to establish an electrical connection between different components to be tested in the module to be tested and the power supply, or form different test loops. The test board usually includes a control circuit and a plurality of relays, and the control circuit can switch the test loop by controlling the on and off of the relays. It can be understood that due to the introduction of relays in the test loop, the parasitic inductance in the test loop is greater than the parasitic inductance of the module to be tested in a normal working environment. The larger parasitic inductance will not only affect the test results of the module to be tested, but also limit the maximum switching speed of the module to be tested. In other words, it will limit the pull-off test capability of the test device. Here, the test device may include a multi-stage clamping circuit, wherein the first stage clamping circuit in the multi-stage clamping circuit can be used to connect between the circuit breaker and the test board, and the second stage clamping circuit in the multi-stage clamping circuit can be used to connect between the test board and the connection device. When the control circuit controls each relay to switch on and off to switch different test circuits, or when the control circuit controls each to-be-tested component in the to-be-tested module to switch on and off, each stage clamping circuit can decouple the parasitic inductance generated by the to-be-tested module and part of the circuit in the test circuit from the to-be-tested module, thereby reducing the overvoltage generated by the parasitic inductance during the switching process, while increasing the maximum switching speed of each to-be-tested component, with a simple structure and high reliability. Here, the clamping circuits at different positions correspond to different front-end circuits and back-end circuits, respectively. The front-end circuit corresponding to a certain stage clamping circuit refers to the circuit composed of devices between the location of the clamping circuit in the test circuit and the power supply (including the power supply), and correspondingly, the back-end circuit corresponding to this clamping circuit refers to the circuit between the location of the clamping circuit in the test circuit and the to-be-tested module (including the to-be-tested module). It can be understood that each stage of the circuit can decouple the parasitic inductance generated by its corresponding front-end circuit from its corresponding back-end circuit, reducing the impact of the parasitic inductance generated by the front-end circuit on the back-end circuit. In addition, each stage of the multi-stage clamping circuit can include a capacitor. Compared to a single decoupling capacitor, the capacitor in each stage of the clamping circuit can adopt a smaller capacitance value, reducing the size of each stage of the clamping circuit, improving the system integration and applicability, and reducing design costs.

[0006] By adopting the present application, clamping can be performed at different positions in the test device through a multi-stage clamping circuit to reduce the influence of parasitic inductance in the test loop, reduce the overvoltage generated by the module to be tested during the switching process, increase the maximum switching speed of the module to be tested, and improve the test efficiency. At the same time, clamping through a multi-stage clamping circuit can reduce the volume of the clamping circuit at each level, improve the integration, low cost, and strong applicability.

[0007] In combination with the first aspect, in a first possible implementation, the test device further includes a busbar, which is connected between the circuit breaker and the test board, and a first-stage clamping circuit is used to connect between the busbar and the test board. Here, the busbar can be used as a connector to connect the circuit breaker and the test board, and the clamping circuits at each level can decouple part of the parasitic inductance in the test loop from the module to be tested. In other words, the first-stage clamping circuit here can decouple the parasitic inductance generated by the power supply, circuit breaker and busbar in the front-end circuit from the module to be tested, reducing the impact of the parasitic inductance generated by the power supply, circuit breaker and busbar on the module to be tested, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The second-stage clamping circuit here can decouple the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board in the front-end circuit from the module to be tested, reducing the impact of the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board on the module to be tested. In other words, it reduces the overvoltage generated by this parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, improving test efficiency and accuracy. In addition, each level of the clamping circuit in the multi-stage clamping circuit can include capacitors. Compared with a single decoupling capacitor, the capacitors in each level of the clamping circuit can use smaller capacitance, reducing the size of each level of the clamping circuit, improving the system's integration and applicability, and reducing design costs.

[0008] In conjunction with the first aspect, in a second possible embodiment, the testing device further includes a busbar, the busbar being connected between the circuit breaker and the test board, and a first-stage clamping circuit being connected between the circuit breaker and the busbar. Here, the busbar can serve as a connector to connect the circuit breaker and the test board, and each stage of the clamping circuit can decouple the front-end circuit from the module to be tested. That is, the first-stage clamping circuit here can decouple the parasitic inductance generated by the power supply and circuit breaker in the front-end circuit from the module to be tested, reducing the impact of the parasitic inductance generated by the power supply and circuit breaker on the module to be tested, that is, reducing the overvoltage generated by this parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The second-stage clamping circuit here can decouple the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board in the front-end circuit from the module to be tested, reducing the impact of the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board on the module to be tested, that is, reducing the overvoltage generated by this parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, thereby improving test efficiency and accuracy. In addition, each level of the multi-level clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of the clamping circuit can adopt a smaller capacitance value, which reduces the volume of the clamping circuit at each level, improves the integration and applicability of the system, and reduces the design cost.

[0009] In conjunction with the first aspect, in a third possible embodiment, the test device further includes a busbar, the multi-stage clamping circuit includes a three-stage clamping circuit, the first-stage clamping circuit in the multi-stage clamping circuit is used to connect between the busbar and the test board, the second-stage clamping circuit in the multi-stage clamping circuit is used to connect between the test board and the connection device, and the third-stage clamping circuit in the multi-stage clamping circuit is used to connect between the circuit breaker and the busbar. Here, the busbar can serve as a connector to connect the circuit breaker and the test board, and each stage of the clamping circuit can decouple the front-end circuit from the module to be tested. In other words, the first-stage clamping circuit here can decouple the parasitic inductance generated by the power supply, circuit breaker, and busbar in the front-end circuit from the module to be tested, reducing the impact of the parasitic inductance generated by the power supply, circuit breaker, and busbar on the module to be tested, that is, reducing the overvoltage generated by this parasitic inductance during the switching process, while simultaneously increasing the maximum switching speed of each component to be tested. The third-stage clamping circuit here can decouple the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board in the front-end circuit from the connectors and modules to be tested in the back-end circuit, reducing the impact of the parasitic inductance generated by the power supply, circuit breaker, busbar, and test board on the modules to be tested, that is, reducing the overvoltage generated by this parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The first-stage clamping circuit here can decouple the parasitic inductance generated by the power supply and circuit breaker in the front-end circuit from the test board, connectors, and modules to be tested in the back-end circuit, reducing the impact of the parasitic inductance generated by the power supply and circuit breaker on the modules to be tested, that is, reducing the overvoltage generated by this parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, improving test efficiency and accuracy. In addition, each level of the clamping circuit in the multi-stage clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of the clamping circuit can use a smaller capacitance value, reducing the volume of each level of the clamping circuit, improving the system's integration and applicability, and reducing design costs.

[0010] In combination with the first aspect or any possible implementation manner of the first aspect, in a fourth possible implementation manner, the first-stage clamping circuit and the third-stage clamping circuit in the multi-stage clamping circuit include at least one of a decoupling capacitor, an RC clamping circuit or an RC second-order clamping circuit, which has a simple structure, low design cost and strong applicability.

[0011] In combination with the first aspect or any possible implementation manner of the first aspect, in a fifth possible implementation manner, the second-stage clamping circuit in the multi-stage clamping circuit includes at least one of an RCD clamping circuit, an LCD clamping circuit or an active clamping circuit. The second-stage clamping circuit can decouple the parasitic inductance generated by the front-end circuit from the module to be tested, while also decoupling the parasitic inductance generated by the test board and the connecting device from the module to be tested, thereby reducing the impact of the parasitic inductance generated by the test board and the connecting device on the module to be tested, further improving the maximum switching speed of each component to be tested, and improving the test efficiency and accuracy.

[0012] In combination with the first aspect or any possible implementation manner of the first aspect, in a sixth possible implementation manner, the test device further includes a circuit breaker, and the test board is connected to the power supply via the circuit breaker, or the test board is connected to the power supply via a busbar and a circuit breaker. Here, the circuit breaker can disconnect the electrical connection between the module to be tested and the power supply when the current or voltage in the test circuit is too high, thereby ensuring the safety of the test device, simplifying the structure, and improving applicability.

[0013] In combination with the first aspect or any possible implementation manner of the first aspect, in a seventh possible implementation manner, the test device further includes a bus capacitor connected between the circuit breaker and the power supply. Here, the power supply can charge the bus capacitor, and after being charged, the bus capacitor can quickly provide power to the test circuit, thereby ensuring power supply efficiency of the test device, having a simple structure, and high applicability.

[0014] In combination with the seventh possible implementation of the first aspect, in an eighth possible implementation, the test board also includes a load inductor, which can prevent the test board from generating excessive current due to too small a load or no load, thereby improving the safety of the test device.

[0015] In a second aspect, the present application provides a multi-stage clamping test system, which may include a power supply and the multi-stage clamping test device in the first aspect or any possible implementation of the first aspect.

[0016] In the present application, the test system can test the module to be tested to verify the performance of the module to be tested. The module to be tested can be a semiconductor chip such as a power semiconductor chip or an inherited circuit. Here, the test device can connect the module to be tested to the test board through a connecting device, and connect the power supply through the test board. The module to be tested usually includes multiple components to be tested, and the test device usually needs to establish electrical connections between different components to be tested in the module to be tested and the power supply, or form different test loops. The test board usually includes a control circuit and multiple relays, and the control circuit can switch the test loop by controlling the on and off of the relays. It can be understood that due to the introduction of relays in the test loop, the parasitic inductance in the test loop is greater than the parasitic inductance of the module to be tested in a normal working environment. The larger parasitic inductance will not only affect the test results of the module to be tested, but will also limit the maximum switching speed of the module to be tested. In other words, it will limit the pull-off test capability of the test device. Here, the test device may include a multi-stage clamping circuit, wherein the first stage clamping circuit in the multi-stage clamping circuit can be used to connect between the circuit breaker and the test board, and the second stage clamping circuit in the multi-stage clamping circuit can be used to connect between the test board and the connection device. When the control circuit controls each relay to switch on and off to switch different test circuits, or when the control circuit controls each to-be-tested component in the to-be-tested module to switch on and off, each stage clamping circuit can decouple the parasitic inductance generated by the to-be-tested module and part of the circuit in the test circuit from the to-be-tested module, thereby reducing the overvoltage generated by the parasitic inductance during the switching process, while increasing the maximum switching speed of each to-be-tested component, with a simple structure and high reliability. Here, the clamping circuits at different positions correspond to different front-end circuits and back-end circuits, respectively. The front-end circuit corresponding to a certain stage clamping circuit refers to the circuit composed of devices between the location of the clamping circuit in the test circuit and the power supply (including the power supply), and correspondingly, the back-end circuit corresponding to this clamping circuit refers to the circuit between the location of the clamping circuit in the test circuit and the to-be-tested module (including the to-be-tested module). It can be understood that each stage of the circuit can decouple the parasitic inductance generated by its corresponding front-end circuit from its corresponding back-end circuit, reducing the impact of the parasitic inductance generated by the front-end circuit on the back-end circuit. In addition, each stage of the multi-stage clamping circuit can include a capacitor. Compared to a single decoupling capacitor, the capacitor in each stage of the clamping circuit can adopt a smaller capacitance value, reducing the size of each stage of the clamping circuit, improving the system integration and applicability, and reducing design costs.

[0017] By adopting the present application, clamping can be performed at different positions in the test device through a multi-stage clamping circuit to reduce the influence of parasitic inductance in the test loop, reduce the overvoltage generated by the module to be tested during the switching process, increase the maximum switching speed of the module to be tested, and improve the test efficiency. At the same time, clamping through a multi-stage clamping circuit can reduce the volume of the clamping circuit at each level, improve the integration, low cost, and strong applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of an application scenario of a multi-stage clamping test device provided in an embodiment of the present application;

[0019] Figure 2 1 is a structural diagram of a multi-stage clamping test device provided in an embodiment of the present application;

[0020] Figure 3 is another structural schematic diagram of the multi-stage clamping test device provided in an embodiment of the present application;

[0021] Figure 4 is another structural schematic diagram of the multi-stage clamping test device provided in an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of the structure of the test circuit provided in an embodiment of the present application;

[0023] Figure 6 1 is an equivalent schematic diagram of a test circuit provided in an embodiment of the present application;

[0024] Figure 7 is another equivalent schematic diagram of the test loop provided in an embodiment of the present application;

[0025] Figure 8 is another equivalent schematic diagram of the test loop provided in an embodiment of the present application;

[0026] Figure 9 is another structural diagram of the test circuit provided in an embodiment of the present application;

[0027] Figure 10 is another structural schematic diagram of the multi-stage clamping test device provided in an embodiment of the present application;

[0028] Figure 11 is another structural schematic diagram of the multi-stage clamping test device provided in an embodiment of the present application;

[0029] Figure 12 Schematic diagram of the structure of the multi-stage clamping test system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The multi-stage clamping test device provided in the present application can be applicable to the testing field of functional modules, such as testing power conversion modules in photovoltaic power generation, testing power supply modules in new energy vehicles, and other testing fields. The specific application can be determined according to the actual application scenario and is not limited here. The multi-stage clamping test device provided in the present application can be applicable to different application environments such as laboratories, factory production workshops, equipment manufacturers, etc. At the same time, it can test chips used in different scenarios such as large-scale photovoltaic power stations, industrial and commercial photovoltaic power supply, household energy storage power supply, pure energy storage power supply, new energy vehicle power supply, etc., and is not limited here. The chip here can be a functional chip with multiple modules to be tested, such as a power chip. The power chip here can be a chip with power conversion function such as a half-bridge circuit, an NPC circuit, and a three-level circuit. The following will take the detection of a T-type three-level module as an example of the application scenario of the multi-stage clamping test device for explanation, and will not be repeated below.

[0031] See Figure 1 , Figure 1 Schematic diagram of the application scenario of the multi-stage clamping test device provided in the embodiment of the present application. The test device 1 provided in the present application is suitable for testing systems such as Figure 1 As shown, the test device 1 may include a multi-stage clamping circuit (e.g., a first-stage clamping circuit 11a and a second-stage clamping circuit 11b), a test board 4, and a connecting device 5. Here, the connecting device 5 can be used to connect the test board 4 and a module to be tested 6, where the module to be tested 6 has multiple components to be tested. The test board 4 can be used to connect to the power supply 2 through the circuit breaker 3. The first-stage clamping circuit 11a in the multi-stage clamping circuit can be used to connect between the circuit breaker 3 and the test board 4. The second-stage clamping circuit 11b in the multi-stage clamping circuit can be used to connect between the test board 4 and the connecting device 5. The test board 4 may include a control circuit and multiple relays, such as relays 42a to 42n.

[0032] It is understood that the test device 1 can test the module to be tested 6 to verify the performance of the module to be tested 6. The module to be tested 6 can be a semiconductor chip such as a power semiconductor chip or an inherited circuit. Here, the test device 1 can connect the module to be tested 6 to the test board 4 through the connecting device 5, and connect to the power supply 2 through the test board 4. The module to be tested 6 usually includes multiple components to be tested, and the test device 1 usually needs to establish electrical connections between different components to be tested in the module to be tested 6 and the power supply 2, or form different test loops. The test board 4 usually includes a control circuit and multiple relays, and the control circuit can switch the test loop by controlling the on and off of the relays. It is understood that due to the introduction of relays in the test loop, the parasitic inductance in the test loop is greater than the parasitic inductance of the module to be tested 6 in a normal working environment. The larger parasitic inductance will not only affect the test results of the module to be tested 6, but will also limit the maximum switching speed of the module to be tested 6. In other words, it will limit the pull-off test capability of the test device 1.

[0033] Here, the test device 1 may include a multi-stage clamping circuit. The first-stage clamping circuit 11a of the multi-stage clamping circuit may be connected between the circuit breaker 3 and the test board 4, and the second-stage clamping circuit 11b of the multi-stage clamping circuit may be connected between the test board 4 and the connector 5. The control circuit may be used to control the on / off switching of multiple relays to switch the test circuit of the test device 1. The test circuit is a circuit formed by establishing an electrical connection between different components under test among the multiple components under test and the power supply 2. Each clamping circuit in the multi-stage clamping circuit is used to clamp the voltage at the location of each clamping circuit to reduce the impact of parasitic inductance in the test circuit. In other words, when the control circuit controls the on / off switching of each relay to switch different test circuits, or when the control circuit controls the on / off switching of each component under test in the module under test, each clamping circuit can decouple the parasitic inductance generated by the module under test 6 and a portion of the circuit in the test circuit from the module under test 6, thereby reducing the overvoltage generated by the parasitic inductance during the switching process and simultaneously increasing the maximum switching speed of each component under test. The structure is simple and the reliability is high. Here, the clamping circuits at different positions correspond to different front-end circuits and back-end circuits. The front-end circuit corresponding to a certain level of clamping circuit refers to the circuit composed of devices between the location of the clamping circuit and the power supply 2 (including the power supply 2) in the test loop. Correspondingly, the back-end circuit corresponding to this clamping circuit refers to the circuit between the location of the clamping circuit at this level and the module to be tested 6 (including the module to be tested 6) in the test loop. It can be understood that each level of circuit can decouple the parasitic inductance generated by its corresponding front-end circuit from its corresponding back-end circuit, reducing the impact of the parasitic inductance generated by the front-end circuit on the back-end circuit. In addition, each level of clamping circuit in the multi-level clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of clamping circuit can adopt a smaller capacitance value, reducing the volume of each level of clamping circuit, improving the integration and applicability of the system, and reducing the design cost.

[0034] By adopting the present application, clamping can be performed at different positions in the test device 1 through a multi-stage clamping circuit to reduce the influence of parasitic inductance in the test loop, reduce the overvoltage generated by the module to be tested 6 during the switching process, increase the maximum switching speed of the module to be tested 6, and improve the test efficiency. At the same time, clamping through a multi-stage clamping circuit can reduce the volume of the clamping circuit at each level, improve the integration, low cost, and strong applicability.

[0035] Please combine Figure 2 , Figure 2 Schematic diagram of a multi-stage clamping test device provided in an embodiment of the present application. Figure 2As shown, the test device 1 also includes a busbar 12, which is connected between the circuit breaker 3 and the test board 4, and a first-stage clamping circuit 11a is used to connect between the busbar 12 and the test board 4. Here, the busbar 12 can serve as a connector to connect the circuit breaker 3 and the test board 4, and each stage of the clamping circuit can decouple part of the parasitic inductance in the test loop from the module to be tested 6. In other words, the first-stage clamping circuit 11a here can decouple the parasitic inductance generated by the power supply 2, circuit breaker 3, and busbar 12 in the front-end circuit from the module to be tested 6, reducing the impact of the parasitic inductance generated by the power supply 2, circuit breaker 3, and busbar 12 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while improving the maximum switching speed of each component to be tested. The second-stage clamping circuit 11b here can decouple the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 in the front-end circuit from the module to be tested 6, reducing the impact of the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, improving the test efficiency and accuracy. In addition, each level of the clamping circuit in the multi-stage clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of the clamping circuit can adopt a smaller capacitance value, reducing the volume of each level of the clamping circuit, improving the integration and applicability of the system, and reducing the design cost.

[0036] In some feasible implementations, the first-stage clamping circuit can also be arranged at other locations. Figure 3 , Figure 3 FIG. 1 is another structural diagram of the multi-stage clamping test device provided in an embodiment of the present application. Figure 3As shown, the busbar 12 can also be connected between the circuit breaker 3 and the test board 4, and the first-stage clamping circuit 11a is used to connect between the circuit breaker 3 and the busbar 12. Here, the busbar 12 can serve as a connector to connect the circuit breaker 3 and the test board 4. The clamping circuits at each stage can decouple the front-end circuit from the module to be tested 6. In other words, the first-stage clamping circuit 11a here can decouple the parasitic inductance generated by the power supply 2 and the circuit breaker 3 in the front-end circuit from the module to be tested 6, reducing the impact of the parasitic inductance generated by the power supply 2 and the circuit breaker 3 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The second-stage clamping circuit 11b here can decouple the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 in the front-end circuit from the module to be tested 6, reducing the impact of the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, improving the test efficiency and accuracy. In addition, each level of the clamping circuit in the multi-stage clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of the clamping circuit can adopt a smaller capacitance value, reducing the volume of each level of the clamping circuit, improving the integration and applicability of the system, and reducing the design cost.

[0037] In some feasible implementations, the multi-stage clamping circuit may further include a third-stage clamping circuit 11c. Figure 4 , Figure 4 FIG. 1 is another structural diagram of the multi-stage clamping test device provided in an embodiment of the present application. Figure 4As shown, the test device 1 also includes a busbar 12, and a multi-stage clamping circuit including three stages. The first-stage clamping circuit 11a of the multi-stage clamping circuit is used to connect between the busbar 12 and the test board 4, the second-stage clamping circuit 11b of the multi-stage clamping circuit is used to connect between the test board 4 and the connector 5, and the third-stage clamping circuit 11c of the multi-stage clamping circuit is used to connect between the circuit breaker 3 and the busbar 12. Here, the busbar 12 can serve as a connector to connect the circuit breaker 3 and the test board 4. Each stage of the clamping circuit can decouple the front-end circuit from the module under test 6. In other words, the first-stage clamping circuit 11a here can decouple the parasitic inductance generated by the power supply 2, circuit breaker 3, and busbar 12 in the front-end circuit from the module under test 6, reducing the impact of the parasitic inductance generated by the power supply 2, circuit breaker 3, and busbar 12 on the module under test 6. In other words, it can reduce the overvoltage generated by this parasitic inductance during the switching process, while also improving the maximum switching speed of each component under test. The third-stage clamping circuit 11c here can decouple the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 in the front-end circuit from the connector 5 and the module to be tested 6 in the back-end circuit, reducing the impact of the parasitic inductance generated by the power supply 2, circuit breaker 3, busbar 12 and test board 4 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The first-stage clamping circuit 11a here can decouple the parasitic inductance generated by the power supply 2 and circuit breaker 3 in the front-end circuit from the test board 4, connector 5 and module to be tested 6 in the back-end circuit, reducing the impact of the parasitic inductance generated by the power supply 2 and circuit breaker 3 on the module to be tested 6, that is, reducing the overvoltage generated by this part of the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested, thereby improving test efficiency and accuracy. In addition, each level of the multi-level clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of the clamping circuit can adopt a smaller capacitance value, which reduces the volume of the clamping circuit at each level, improves the integration and applicability of the system, and reduces the design cost.

[0038] It will be appreciated that the present application does not limit the specific locations of the various clamping circuits or the division of their internal functional circuits. The first-stage clamping circuit 11a and the third-stage clamping circuit 11c of the multi-stage clamping circuit include at least one of a decoupling capacitor, an RC clamping circuit, or a second-stage RC clamping circuit, resulting in a simple structure, low design cost, and strong applicability. The first-stage clamping circuit 11a and the third-stage clamping circuit 11c herein can be any clamping circuit not connected between the test board 4 and the connector 5, and will not be further described below.

[0039] It can also be understood that the second-stage clamping circuit 11b in the multi-stage clamping circuit includes at least one of an RCD clamping circuit, an LCD clamping circuit, or an active clamping circuit. The second-stage clamping circuit 11b can decouple the parasitic inductance generated by the front-end circuit from the module under test 6, while also decoupling the parasitic inductance generated by the test board 4 and the connector 5 from the module under test 6, thereby reducing the impact of the parasitic inductance generated by the test board 4 and the connector 5 on the module under test 6, further improving the maximum switching speed of each component under test, and improving test efficiency and accuracy. The second-stage clamping circuit 11b here can refer to any clamping circuit connected between the test board 4 and the connector 5, and will not be further described below.

[0040] In some feasible implementations, the test board 4 further includes a load inductor, which can prevent the test board 4 from generating excessive current due to too small a load or no load, thereby improving the safety of the test device 1 .

[0041] Here, we take the T-type three-level module as an example and the RCD clamp circuit as the second-stage clamp circuit to explain the working principle of the test device 1 in detail. Figure 5 , Figure 5 This is a schematic diagram of the structure of the test circuit provided in the embodiment of the present application. Figure 5 As shown, the test board 4 may include a load inductor L0 and multiple relays, namely relay S1, relay S2, relay S3, relay S4, relay S5, and relay S6. At the same time, one second-stage clamping circuit 11b may be an RCD clamping circuit, including a resistor R1, a capacitor C1, and a diode D1, and another second-stage clamping circuit 11b may also be an RCD clamping circuit, including a resistor R2, a capacitor C2, and a diode D2. The front-end circuit corresponding to the second-stage clamping circuit 11b is equivalently represented by a capacitor Cdep, and the module to be tested includes multiple components to be tested, namely switch tubes T1, switch tube T2, switch tube T3, and switch tube T4, as well as diodes D1, diode D2, diode D3, and diode D4. Here, the control circuit 41 can control the multiple relays to be turned on and off to switch the test circuit of the test device 1, and then test different components to be tested in the module to be tested. Here, the test circuit is a circuit formed by establishing an electrical connection between different components to be tested among the multiple components to be tested and the power supply 2. At the same time, the second-stage clamping circuit can clamp the voltage at its location during the test process to reduce the impact of parasitic inductance in the test loop.

[0042] Specifically, when the test device 1 tests the switch tube T1 or the diode D4, the relays S1, S2 and S6 can be closed, and the relays S3, S4 and S5 can be opened. At the same time, a positive drive signal is continuously output to the switch tube T3 and a negative drive signal is output to the switch tube T4. Figure 6 , Figure 6 This is an equivalent schematic diagram of the test circuit provided in the embodiment of the present application. Figure 6 As shown, before starting dynamic testing on switch T1, capacitor Cdep can be charged to capacitor C1 through resistor R1 until the voltage across capacitor C1 reaches the target voltage, which can be the bus voltage. When switch T1 is turned on, a voltage spike appears across diode D4. Once the voltage across diode D4 exceeds the target voltage, diode D1 conducts, directly connecting capacitor C1 to diode D4 and significantly suppressing the voltage spike. When switch T1 transitions from on to off, capacitor C1 releases the absorbed turn-off overvoltage to the front-end circuit through resistor R1.

[0043] Specifically, when the test device 1 tests the switch tube T4 or the diode D5, the relays S1, S2 and S5 can be closed, and the relays S3, S4 and S6 can be opened. At the same time, a positive drive signal is continuously output to the switch tube T3 and a negative drive signal is output to the switch tube T1. Figure 7 , Figure 7 This is another equivalent schematic diagram of the test circuit provided in the embodiment of the present application. Figure 7 As shown, before starting the dynamic test on switch T4, capacitor Cdep can be charged to capacitor C1 through resistor R1 until the voltage across capacitor C1 reaches the target voltage, which can be the bus voltage. When switch T4 is turned on, a voltage spike appears across diode D5. Once the voltage across diode D5 exceeds the target voltage, diode D4 conducts, connecting capacitor C1 to diode D5 through resistor R1. The energy at diode D5 flows through resistor R1 to capacitor C1, charging capacitor C1 and significantly suppressing the voltage spike. When switch T4 transitions from on to off, capacitor C1 releases the absorbed turn-off overvoltage to the front-end circuit through resistor R1.

[0044] Specifically, when the test device 1 tests the switch tube T2 or the diode D3, the relays S3, S4 and S5 can be closed, and the relays S1, S2 and S6 can be opened. At the same time, a positive drive signal is continuously output to the switch tube T4, and a negative drive signal is output to the switch tube T3. Figure 8 , Figure 8 This is another equivalent schematic diagram of the test circuit provided in the embodiment of the present application. Figure 8As shown, before starting the dynamic test on switch T2, capacitor Cdep can be charged to capacitor C2 through resistor R2 until the voltage across capacitor C2 reaches the target voltage, which can be the bus voltage. When switch T2 is turned on, a voltage spike appears across diode D3. Once the voltage across diode D3 exceeds the target voltage, diode D2 conducts, directly connecting capacitor C2 across diode D3 and significantly suppressing the voltage spike. When switch T2 transitions from on to off, capacitor C2 releases the absorbed turn-off overvoltage to the front-end circuit through resistor R2.

[0045] Specifically, when the test device 1 tests the switch tube T3 or the diode D6, the relays S3, S4 and S6 can be closed, and the relays S1, S2 and S5 can be opened. At the same time, a positive drive signal is continuously output to the switch tube T4, and a negative drive signal is output to the switch tube T2. Figure 9 , Figure 9 This is another equivalent schematic diagram of the test circuit provided in the embodiment of the present application. Figure 9 As shown, before starting the dynamic test on switch T3, capacitor Cdep can be charged to capacitor C2 through switch T4 and resistor R2 until the voltage across capacitor C2 reaches the target voltage, which can be the bus voltage. When switch T3 is turned on, a voltage spike appears across diode D6. Once the voltage across diode D6 exceeds the target voltage, diode D3 conducts, connecting capacitor C2 to diode D6 via resistor R2. The energy at diode D6 flows through diode D3 to capacitor C2, significantly suppressing the voltage spike. When switch T3 transitions from on to off, capacitor C2 releases the absorbed turn-off overvoltage to the front-end circuit through switch T4 and resistor R2.

[0046] It can be understood that this application only uses the T-type three-level as an example to introduce the working process of the test device. In actual applications, the test device provided by this application can also test other types of modules to be tested, which is not limited here.

[0047] In some feasible implementations, the testing device 1 further includes a circuit breaker. Figure 10 , Figure 10 This is another structural diagram of the multi-stage clamping test device provided in the embodiment of the present application. Figure 10 As shown, the test device 1 further includes a circuit breaker 3, through which the test board 4 is connected to the power supply 2, or alternatively, the test board 4 is connected to the power supply 2 via the busbar 12 and the circuit breaker 3. Here, the circuit breaker 3 can disconnect the electrical connection between the module under test 6 and the power supply 2 when the current or voltage in the test circuit is too high, thereby ensuring the safety of the test device 1, with a simple structure and high applicability.

[0048] In some feasible implementations, the testing device 1 further includes a bus capacitor. Figure 11 , Figure 11 This is another structural diagram of the multi-stage clamping test device provided in the embodiment of the present application. Figure 11 As shown, the test device 1 also includes a bus capacitor, which is used to connect between the circuit breaker 3 and the power supply 2. Here, the power supply 2 can charge the bus capacitor, and after the bus capacitor is charged, it can quickly provide power to the test circuit, ensuring the power supply efficiency of the test device 1. It has a simple structure and high applicability.

[0049] The present application also provides a test system, the test system may include a power supply and Figures 1-11 For details, please refer to the multi-stage clamping test device of any feasible embodiment. Figure 12 , Figure 12 Schematic diagram of the structure of the multi-stage clamping test system provided in the embodiment of the present application. Figure 12 As shown, the test system 1000 may include a power supply 2 and a test device 1 , wherein the test device 1 includes a multi-stage clamping circuit, a test board 4 and a connection device 5 .

[0050] In the present application, the test system 1000 can test the module to be tested 6 to verify the performance of the module to be tested 6. The module to be tested 6 can be a semiconductor chip such as a power semiconductor chip or an inherited circuit. Here, the test device 1 can connect the module to be tested 6 to the test board 4 through the connecting device 5, and connect to the power supply 2 through the test board 4. The module to be tested 6 usually includes multiple components to be tested, and the test device 1 usually needs to establish electrical connections between different components to be tested in the module to be tested 6 and the power supply 2, or form different test loops. The test board 4 usually includes a control circuit and multiple relays, and the control circuit can switch the test loop by controlling the on and off of the relays. It can be understood that due to the introduction of relays in the test loop, the parasitic inductance in the test loop is greater than the parasitic inductance of the module to be tested 6 in a normal working environment. The larger parasitic inductance will not only affect the test results of the module to be tested 6, but will also limit the maximum switching speed of the module to be tested 6. In other words, it will limit the pull-off test capability of the test device 1. Here, the test device 1 may include a multi-stage clamping circuit. The first-stage clamping circuit 11a of the multi-stage clamping circuit may be used to connect between the circuit breaker 3 and the test board 4, and the second-stage clamping circuit 11b of the multi-stage clamping circuit may be used to connect between the test board 4 and the connector 5. When the control circuit controls the relays to switch on and off to switch different test loops, or when the control circuit controls the individual components to be tested in the module to be tested to switch on and off, the clamping circuits at each stage can decouple the parasitic inductance generated by the module to be tested 6 and part of the circuit in the test loop from the module to be tested 6, thereby reducing the overvoltage generated by the parasitic inductance during the switching process, while increasing the maximum switching speed of each component to be tested. The structure is simple and the reliability is high. Here, the clamping circuits at different positions correspond to different front-end circuits and back-end circuits. The front-end circuit corresponding to a certain level of clamping circuit refers to the circuit composed of devices between the location of the clamping circuit and the power supply 2 (including the power supply 2) in the test loop. Correspondingly, the back-end circuit corresponding to this clamping circuit refers to the circuit between the location of the clamping circuit at this level and the module to be tested 6 (including the module to be tested 6) in the test loop. It can be understood that each level of circuit can decouple the parasitic inductance generated by its corresponding front-end circuit from its corresponding back-end circuit, reducing the impact of the parasitic inductance generated by the front-end circuit on the back-end circuit. In addition, each level of clamping circuit in the multi-level clamping circuit can include a capacitor. Compared with a single decoupling capacitor, the capacitor in each level of clamping circuit can adopt a smaller capacitance value, reducing the volume of each level of clamping circuit, improving the integration and applicability of the system, and reducing the design cost.

[0051] By adopting the present application, clamping can be performed at different positions in the test device 1 through a multi-stage clamping circuit to reduce the influence of parasitic inductance in the test loop, reduce the overvoltage generated by the module to be tested 6 during the switching process, increase the maximum switching speed of the module to be tested 6, and improve the test efficiency. At the same time, clamping through a multi-stage clamping circuit can reduce the volume of the clamping circuit at each level, improve the integration, low cost, and strong applicability.

[0052] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A multi-stage clamping test device, characterized in that: The test device includes a multi-stage clamping circuit, a test board, and a connecting device, wherein the connecting device is used to connect the test board and a module to be tested, wherein the module to be tested has multiple components to be tested, and the test board is used to connect to a power supply through a circuit breaker. A first-stage clamping circuit in the multi-stage clamping circuit is used to connect between the circuit breaker and the test board, and a second-stage clamping circuit in the multi-stage clamping circuit is used to connect between the test board and the connecting device. The test board includes a control circuit and multiple relays. The control circuit is used to control the multiple relays to be turned on and off to switch the test circuit of the test device, and the test circuit is a circuit formed by establishing electrical connections between different components to be tested among the multiple components to be tested and the power supply; Each level of the clamping circuit in the multi-level clamping circuit is used to clamp the voltage at the location of each level of the clamping circuit, so as to reduce the influence of the parasitic inductance in the test loop.

2. The multi-stage clamping test device according to claim 1, characterized in that: The testing device further includes a busbar connected between the circuit breaker and the testing board, and the first-stage clamping circuit is used to be connected between the busbar and the testing board.

3. The multi-stage clamping test device according to claim 1, characterized in that: The testing device further includes a busbar connected between the circuit breaker and the testing board, and the first-stage clamping circuit is used to be connected between the circuit breaker and the busbar.

4. The multi-stage clamping test device according to claim 1, characterized in that: The testing device also includes a busbar, and the multi-stage clamping circuit includes a three-stage clamping circuit. The first-stage clamping circuit in the multi-stage clamping circuit is used to connect between the busbar and the test board, the second-stage clamping circuit in the multi-stage clamping circuit is used to connect between the test board and the connecting device, and the third-stage clamping circuit in the multi-stage clamping circuit is used to connect between the circuit breaker and the busbar.

5. The multi-stage clamping test device according to any one of claims 1 to 4, characterized in that: The first-stage clamping circuit and the third-stage clamping circuit in the multi-stage clamping circuit include at least one of a decoupling capacitor, an RC clamping circuit or an RC second-stage clamping circuit.

6. The multi-stage clamping test device according to any one of claims 1 to 5, characterized in that: The second-stage clamping circuit in the multi-stage clamping circuit includes at least one of an RCD clamping circuit, an LCD clamping circuit or an active clamping circuit.

7. The multi-stage clamping test device according to any one of claims 1 to 6, characterized in that: The testing device further includes a circuit breaker, and the testing board is connected to the power supply via the circuit breaker, or the testing board is connected to the power supply via the busbar and the circuit breaker.

8. The multi-stage clamping test device according to any one of claims 1 to 7, characterized in that: The testing device further includes a bus capacitor, which is used to be connected between the circuit breaker and the power supply.

9. The multi-stage clamping test device according to any one of claims 1 to 8, characterized in that: The test board further includes a load inductor.

10. A multi-stage clamping test system, characterized in that: The test system comprises a power supply and the multi-stage clamping test device according to any one of claims 1 to 9.

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