LVDS (Low Voltage Differential Signaling) communication method, line card, electronic equipment and device

Abstract

The embodiment of the invention provides an LVDS (Low Voltage Differential Signaling) communication method, a line card, electronic equipment and a device, and relates to the technical field of chips, the LVDS communication method is applied to the line card, the line card stores a corresponding relation between an identifier of an LVDS component and a phase difference of the LVDS component, and the method comprises the following steps: determining whether a first phase difference of a target LVDS component is stored or not; if yes, a first start frame carrying verification data is sent to the target LVDS assembly, so that the target LVDS assembly feeds back the verification data to the line card, and whether the verification data can be correctly collected from the received data according to the first phase difference or not is determined; and if the verification data can be correctly acquired, communicating with the target LVDS component according to the first phase difference. By applying the embodiment of the invention, the time consumed by LVDS training before LVDS communication of the line card can be saved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an LVDS communication method, line card, electronic equipment, and device. Background Art

[0002] In current circuit board designs, LVDS (Low-Voltage Differential Signaling) is typically used as a management channel between line cards and daughter cards on the circuit board. When a line card sends data to an LVDS component configured on a daughter card via LVDS, it transmits both a TX (Transmit) signal and a CLK (Clock) signal. The CLK signal and TX signal sent by the line card maintain a fixed timing relationship. Therefore, the LVDS component directly determines the phase to extract data from the TX signal. However, when the LVDS component sends an RX (Receive) signal to the line card, it does not send a CLK signal. Therefore, the line card cannot determine the phase of the RX signal and cannot directly extract data from the RX signal. In order to determine the phase difference between the RX signal and the line card's clock, the line card needs to perform LVDS training.

[0003] However, if a line card is connected to multiple LVDS components via different LVDS channels, the different hardware links between each LVDS component and the line card will result in different signal delays. Consequently, the phase difference between the RX signal sent by each LVDS component to the line card and the line card's clock will vary. Consequently, LVDS training must be performed again each time the LVDS component accessed by the line card switches. This results in a significant amount of time wasted on LVDS training during LVDS communication between the line card and the LVDS components. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide an LVDS communication method, line card, electronic device, and apparatus to save the time consumed by LVDS training before the line card performs LVDS communication. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides an LVDS communication method, which is applied to a line card, wherein the line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, and the LVDS component is configured on a daughter card. The method includes:

[0006] determining whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored;

[0007] If the first phase difference is stored, sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0008] If the verification data can be correctly collected, communication is performed with the target LVDS component according to the first phase difference.

[0009] In one embodiment of the present application, the method further includes:

[0010] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0011] In one embodiment of the present application, performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0012] Sending a second start frame to the target LVDS component so that the target LVDS component sends and receives an RX signal to the line card;

[0013] Determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card; sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data;

[0014] If the number of sub-data with the same value contained in the first preset number of consecutive frequency doubling sequences reaches the second preset number, then determining that the current training phase difference is the second phase difference, and the second preset number is less than or equal to the preset multiple;

[0015] Otherwise, adjust the training phase difference, return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, sampling the RX signal according to the clock frequency of the multiplier clock, and obtaining the multiplier sequence.

[0016] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0017] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0018] The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame;

[0019] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0020] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code;

[0021] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0022] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0023] In one embodiment of the present application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

[0024] In a second aspect, an embodiment of the present application provides a line card, wherein the line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, wherein the LVDS component is configured on a daughter card, and the line card performs the following steps:

[0025] determining whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored;

[0026] If the first phase difference is stored, sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0027] If the verification data can be correctly collected, communication is performed with the target LVDS component according to the first phase difference.

[0028] In one embodiment of the present application, the line card further performs the following steps:

[0029] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0030] In one embodiment of the present application, performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0031] Sending a second start frame to the target LVDS component so that the target LVDS component sends and receives an RX signal to the line card;

[0032] Determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card; sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data;

[0033] If the number of sub-data with the same value contained in the first preset number of consecutive frequency doubling sequences reaches the second preset number, then determining that the current training phase difference is the second phase difference, and the second preset number is less than or equal to the preset multiple;

[0034] Otherwise, adjust the training phase difference, return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, sampling the RX signal according to the clock frequency of the multiplier clock, and obtaining the multiplier sequence.

[0035] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0036] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0037] The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame;

[0038] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0039] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code;

[0040] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0041] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0042] In one embodiment of the present application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

[0043] In a third aspect, an embodiment of the present application provides an electronic device, comprising:

[0044] processor;

[0045] transceiver;

[0046] A line card storing a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component;

[0047] A daughter card, wherein the daughter card is configured with an LVDS component;

[0048] a machine-readable storage medium storing machine-executable instructions that can be executed by the processor;

[0049] The line card implements any one of the method steps described in the first aspect.

[0050] In a fourth aspect, an embodiment of the present application provides an LVDS communication device, which is applied to a line card. The line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component. The LVDS component is configured on a daughter card. The device includes:

[0051] A first phase difference determining module, configured to determine whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored;

[0052] a first start frame sending module, configured to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0053] The first communication module is configured to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly collected.

[0054] In one embodiment of the present application, the device further comprises:

[0055] The second communication module is used to perform low voltage differential signal LVDS training on the target LVDS component if the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0056] In one embodiment of the present application, the second phase difference is determined by the following modules:

[0057] a second start frame sending module, configured to send a second start frame to the target LVDS component, so that the target LVDS component sends and receives an RX signal to the line card;

[0058] a sequence extraction module, configured to determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, and sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data;

[0059] a second phase difference determining module, configured to determine that the current training phase difference is a second phase difference if the number of sub-data with the same value contained in a first preset number of consecutive frequency doubling sequences reaches a second preset number, and the second preset number is less than or equal to the preset multiple;

[0060] The phase difference adjustment module is used to adjust the training phase difference and return to trigger the execution of the sequence extraction module if there are no consecutive first preset number of frequency doubling sequences containing sub-data with the same value that reach a second preset number.

[0061] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0062] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0063] The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame;

[0064] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0065] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code;

[0066] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0067] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0068] In one embodiment of the present application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

[0069] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the method steps described in the first aspect is implemented.

[0070] In a sixth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the methods described in the first aspect above.

[0071] Beneficial effects of the embodiments of the present application:

[0072] In the solution provided by the embodiment of the present application, before the line card communicates with the target LVDS component to be accessed, it is first determined whether the first phase difference corresponding to the target LVDS component has been stored in the line card. If so, a first start frame is sent to the target LVDS component so that the target LVDS component feeds back the verification data in the first start frame. If the line card can correctly collect the verification data, it means that the first phase difference has passed the verification, so communication can be carried out directly based on the first phase difference. In this case, before communicating with the target LVDS component, it is only necessary to complete the sending of the first start frame, the receiving of the verification data, and the extraction of the verification data. The time required is much less than the time required for an LVDS training. And verifying the first phase difference can also ensure the normal execution of communication in most cases. Therefore, the embodiment of the present application can save the time consumed by the line card in LVDS training before LVDS communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0074] Figure 1 A schematic diagram of the connection relationship between a line card and a sub-card provided in an embodiment of the present application;

[0075] Figure 2 A schematic flow chart of a first LVDS communication method provided in an embodiment of the present application;

[0076] Figure 3 A flow chart of a second LVDS communication method provided in an embodiment of the present application;

[0077] Figure 4 A flowchart of a third LVDS communication method provided in an embodiment of the present application;

[0078] Figure 5 A schematic diagram of the first LVDS training process provided in an embodiment of the present application;

[0079] Figure 6 A schematic diagram of the second LVDS training process provided in an embodiment of the present application;

[0080] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0081] Figure 8A schematic structural diagram of an LVDS communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0083] Because related art line cards are connected to multiple daughter cards, each of which can be configured with one or more LVDS components, communication with different LVDS components requires LDVS training to determine the phase difference of each LVDS component before communicating with it, which wastes a considerable amount of time. To address the above issues, embodiments of the present application provide an LVDS communication method, line card, electronic device, and apparatus.

[0084] First, the application scenarios of the embodiments of the present application are described.

[0085] See also Figure 1 , is a schematic diagram of the connection relationship between a line card and a sub-card provided in an embodiment of the present application.

[0086] In the figure, the Field-Programmable Gate Array (FPGA) to the left of the Complex Programmable Logic Device (CPLD) is a line card, and the N FPGAs to the right of the CPLD are daughter cards, which are equipped with LVDS components. The CPLD is part of the daughter card. It should be noted that the CPLD is not a required part and is only one of the common designs.

[0087] The FPGA, acting as a line card, transmits transmit and clock signals to the CPLD. The strobe module in the CPLD determines whether the received transmit and clock signals are destined for the CPLD itself or the FPGA. If they are destined for the CPLD itself, the signals are transmitted to the low-voltage differential signaling module in the CPLD. If they are destined for the FPGA, the signals are then transmitted to the corresponding FPGA.

[0088] After receiving a signal, the low-voltage differential signal module in the CPLD transmits the received signal to the FPGA serving as the line card through the strobe module. After receiving a signal, the LVDS component on the FPGA serving as the daughter card transmits the received signal to the FPGA serving as the line card through the strobe module.

[0089] It should be noted that the present application does not limit the specific type of chips of the line card and the daughter card. As long as the line card and the daughter card use LVDS as a channel for communication, the solution provided in the embodiment of the present application can be applied.

[0090] See also Figure 2 , is a flow chart of a first LVDS communication method provided in an embodiment of the present application, which is used for a line card and includes steps S201 to S203. The line card stores a correspondence between an identifier of an LVDS component and a phase difference of the LVDS component, and the LVDS component is configured on a daughter card.

[0091] In one embodiment of the present application, the identifier of the above-mentioned LVDS component can be the number, name or starting address of the storage space of the LVDS component. The starting address of each LVDS component is unique in the link, and the line card only records the correspondence between the identifier of the LVDS component and the phase difference of the LVDS component.

[0092] In another embodiment of the present application, the line card stores a correspondence between the identifier and number of an LVDS component and the phase difference of the LVDS component. Different correspondences correspond to different numbers. The number can be referred to as X-phase. For example, the correspondence between the identifier and the phase difference of the LVDS component of the first completed LVDS training is numbered 0, i.e., phase 0; the correspondence between the identifier and the phase difference of the LVDS component of the second completed LVDS training is numbered 1, i.e., phase 1, and so on.

[0093] See Table 1, which is a phase difference storage format table provided in an embodiment of the present application. The identifier of the LVDS component stored in this storage format is the starting address of the LVDS component, and the corresponding number is X phase.

[0094] Table 1

[0095] Starting address X Phase Phase results 24bit 3bit 5bit

[0096] The start address is 24 bits long, the X-Phase is 3 bits long, and the phase result (i.e., phase difference) is 5 bits long. It should be noted that the length of the X-Phase field is related to the number of LVDS components. The number of possible values ​​for the X-Phase field must be greater than or equal to the number of LVDS components. If there are two LVDS components, the X-Phase field must be 1 bit or longer. If there are three to four LVDS components, the X-Phase field must be 2 bits or longer. In this embodiment, the X-Phase field is 3 bits long, allowing for eight different possible values, which can be used to distinguish between up to eight different LVDS components and phase differences.

[0097] S201: Determine whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored.

[0098] Specifically, after obtaining the target identifier of the target LVDS component to be accessed, the line card searches for a corresponding relationship containing the target identifier from its own stored corresponding relationships. If the corresponding relationship contains the target identifier, the line card determines the first phase difference corresponding to the target identifier and executes step S202.

[0099] S202: Sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference.

[0100] The line card sends the first start frame to the target LVDS component via the TX signal and the CLK signal, allowing the target LVDS component to determine the phase of the TX signal based on the CLK signal. Based on this, the first start frame contains a field with a fixed value. The target LVDS component can determine the position of the first start frame in the TX signal by identifying this field. It can then extract the check data from the TX signal based on the bit position of the check data in the first start frame.

[0101] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code.

[0102] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0103] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0104] See Table 2, which is a first starting frame format table provided in an embodiment of the present application.

[0105] Table 2

[0106]

[0107] The lengths of the various fields recorded in the table are merely examples and are not limited in the embodiments of the present application.

[0108] The first idle code and the second idle code have fixed patterns, which are patterns sent when the line card is idle. The two patterns can be the same or different. For example, the pattern of the first idle code and the second idle code can be 0x5c.

[0109] The start flag is set to a preset value, for example, 0xbc. Upon detecting this value, the target LVDS component can determine that the data is the start flag, thus identifying this data segment as the first start frame. It also determines that the 32-bit data following the start flag, separated by an interval of 1+8+24=33 bits, is the check data. Based on this, the target LVDS component can extract the check data.

[0110] The target LVDS component can determine that the received start frame is the second start frame based on the second training flag.

[0111] Different values ​​of the aforementioned second operation instruction instruct the target LVDS component to perform different operations, including an FPGA write operation for controlling the writing of data to the FPGA serving as a daughter card, an FPGA read operation for controlling the reading of data from the FPGA serving as a daughter card, a CPLD read response for controlling the reading of data from the CPLD serving as a daughter card, and a daughter card FPGA load operation for controlling the loading of data into the FPGA serving as a daughter card. The value of the second operation instruction for controlling the FPGA write operation can be 0x00, the value of the second operation instruction for controlling the FPGA read operation can be 0x80, the value of the second operation instruction for controlling the CPLD read response can be 0xb0, and the value of the second operation instruction for controlling the daughter card FPGA load can be 0xcb.

[0112] The second check code may be a CRC (Cyclic Redundancy Check) code, or other check codes, which are not limited.

[0113] In addition, after extracting the verification data, the target LVDS component encapsulates the verification data into a normal frame and sends it to the line card. The normal frame also contains a start flag, and the value of the start flag contained in the normal frame is also a fixed value, which is different from the value of the start flag contained in the first start frame. Therefore, the line card can determine the phase of the RX signal sent by the target LVDS component based on the first phase difference and the phase of its own multiplier clock, and then identify the start flag contained in the normal frame from the RX signal, thereby determining the position of the start flag, and then determining that the 32-bit data after the start flag of the normal frame is the verification data. If the verification data extracted by the line card is the same as the verification data sent, it means that there is no problem in extracting the verification data, the first phase difference is correct, and communication with the target LVDS component can be carried out according to the first phase difference, and step S203 is executed.

[0114] S203: Communicate with the target LVDS component according to the first phase difference.

[0115] As can be seen from the above, first determine whether the first phase difference corresponding to the target LVDS component has been stored in the line card. If so, send the first start frame to the target LVDS component so that the target LVDS component feeds back the verification data in the first start frame. If the line card can correctly collect the verification data, it means that the first phase difference has passed the verification, so communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, it is only necessary to complete the sending of the first start frame, the reception of the verification data, and the extraction of the verification data. The time required is much less than the time required for an LVDS training. And verifying the first phase difference can also ensure the normal execution of communication in most cases. Therefore, the embodiment of the present application can save the time consumed by the line card for LVDS training before LVDS communication.

[0116] See also Figure 3 , is a flow chart of the second LVDS communication method provided in the embodiment of the present application, which is similar to the aforementioned Figure 2 Compared to the embodiment shown, if the line card cannot correctly extract the verification data from the received data according to the first phase difference, it indicates that the recorded first phase difference is incorrect, or the delay between the line card and the target LVDS component has changed, causing the phase difference to change. Therefore, the originally recorded first phase difference is no longer applicable to the current environment. Therefore, the phase difference between the line card and the target LVDS component needs to be re-determined, and step S204 is executed. Alternatively, if the line card does not store the first phase difference, step S204 is executed.

[0117] S204: Perform LVDS training on the target LVDS component, determine a second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0118] In the embodiment of the present application, any LVDS training method in the related art can be used to perform LVDS training, or the following LVDS training method can be used: Figure 4 The embodiment shown performs LVDS training, which is not limited in this application.

[0119] In addition, if the line card does not pre-store the first phase difference corresponding to the target LVDS component, the correspondence between the target LVDS component identifier and the second phase difference is directly recorded. If the line card pre-stores the first phase difference corresponding to the target LVDS component, but the verification data is not correctly extracted based on the first phase difference, the stored first phase difference corresponding to the target LVDS component identifier is updated to the second phase difference.

[0120] As can be seen from the above, in the embodiment of the present application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. After determining the second phase difference, the corresponding relationship between the identifier of the target LVDS component and the second phase difference is stored, so that the second phase difference can be used the next time the target LVDS component is communicated with, saving time consumed in the next communication with the target LVDS component.

[0121] See also Figure 4 , which is a flow chart of a second LVDS communication method provided in an embodiment of the present application, including the following steps S401-S410.

[0122] S401: The line card prepares to initiate communication with the target LVDS component.

[0123] S402: The line card determines whether a first phase difference corresponding to the target LVDS component can be found according to the start address of the target LVDS component.

[0124] If the first phase difference can be found, step S403 is executed; if the first phase difference cannot be found, step S408 is executed.

[0125] S403: The line card adjusts the phase of the frequency-multiplied clock within the line card according to the first phase difference.

[0126] S404: The line card sends a first start frame to the target LVDS component.

[0127] S405: The target LVDS component receives the check data in the first start frame.

[0128] S406: The target LVDS component sends verification data to the line card.

[0129] S407: The line card determines whether the verification is successful.

[0130] If the verification is successful, step S410 is executed; if the verification is unsuccessful, step S408 is executed.

[0131] S408: The line card performs LVDS training to obtain a second phase difference.

[0132] S409: The line card records the correspondence between the start address, X phase, and second phase difference of the target LVDS component.

[0133] S410: The line card and the target LVDS component communicate normally.

[0134] Figure 4 The embodiment shown is Figure 2 and Figure 3 The embodiments shown are similar and will not be described again here.

[0135] See also Figure 5 , which is a schematic diagram of the first LVDS training process provided in an embodiment of the present application, the above-mentioned step of performing LVDS training on the above-mentioned target LVDS component and determining the second phase difference corresponding to the above-mentioned target LVDS component is implemented by the following steps S501 to S504.

[0136] S501: Send a second start frame to the target LVDS component, so that the target LVDS component sends an RX signal to the line card.

[0137] The line card sends a TX signal and CLK signal carrying the second start frame to the target LVDS component. Because the TX and CLK signals have a fixed timing, the target LVDS component can directly determine the phase and extract data from the TX signal. Like the first start frame, the second start frame contains a fixed start flag. After extracting the start flag from the TX signal, the target LVDS component can determine whether the current frame is the first start frame or the second start frame. If the second training flag is also recognized, the current frame is determined to be the second start frame and the RX signal is then sent to the line card. The value of the RX signal is a preset fixed value.

[0138] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0139] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0140] The first training flag is used to indicate that the data frame where the first training flag is located is the second starting frame;

[0141] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0142] The first idle code and the second idle code in the second starting frame are the same as the first idle code and the second idle code in the first starting frame. The first operation instruction in the second starting frame is the same as the second operation instruction in the first starting frame. Detailed description is omitted here.

[0143] The start flag in the second start frame is the same as the start flag in the first start frame, and the first training flag in the second start frame is different from the second training flag in the first start frame. Therefore, when the target LVDS component receives a data frame containing a start flag, it can be determined whether the data frame is the first start frame or the second start frame. Further, if it carries the first training flag, the data frame is the second start frame, and if it carries the second training flag, the data frame is the first start frame.

[0144] See Table 3, which is a second starting frame format table provided in an embodiment of the present application.

[0145] Table 3

[0146]

[0147] The lengths of the various fields recorded in the table are merely examples and are not limited in the embodiments of the present application.

[0148] S502: Determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal, and obtain a multiplier sequence.

[0149] The initial value of the training phase difference is a preset value.

[0150] The multiplied clock has a clock frequency that is a preset multiple of the clock frequency of the original clock in the line card. Therefore, one original clock cycle of the original clock includes a preset multiple of the multiplied clock cycles of the multiplied clock. Since the RX signal transmitted by the target LVDS component should theoretically remain high or low throughout one original clock cycle, if the edges of the line card's CLK signal and the RX signal are aligned, the RX signal level should theoretically remain consistent within the preset number of multiplied clock cycles within the same original clock cycle.

[0151] Each frequency multiplication sequence contains the above-mentioned preset multiple consecutive sub-data. That is, each sub-data is sub-data collected within a frequency multiplication clock cycle. If all sub-data in a frequency multiplication sequence come from the same original clock cycle, then when the edges of the line card's CLK signal and RX signal are aligned, theoretically, the values ​​of all sub-data in the same frequency multiplication sequence should be the same, both 1 or both 0. Conversely, if sub-data with different values ​​exist in the same frequency multiplication sequence, then theoretically, the sub-data with different values ​​must not come from the same original clock cycle. In this case, it indicates that the current training phase difference is not the phase difference between the RX signal of the target LVDS component and the frequency multiplication clock of the line card. The training phase difference needs to be adjusted until the number of sub-data with the same value contained in the first preset number of consecutive frequency multiplication sequences reaches the second preset number. It can then be determined that each of the first preset number of consecutive frequency multiplication sequences theoretically corresponds to exactly one original clock cycle, so the current training phase difference should be the second phase difference corresponding to the target LVDS component, and step S503 is executed. Otherwise, step S504 is executed.

[0152] It should be noted that, although theoretically the level of the RX signal will not change within an original clock cycle, if the level of the RX signal flips within two adjacent original clock cycles, the level flip actually takes a relatively short period of time, and at this time the level of the RX signal within an original clock cycle will not remain completely consistent. After dividing an original clock cycle into a preset multiple of multiplied clock cycles, the level within the first multiplied clock cycle where the level flip occurs within the same original clock cycle may be different from the level of the other second multiplied clock cycles, and the value of the sub-data corresponding to the first multiplied clock cycle is different from the value of the sub-data corresponding to the second multiplied clock cycle. Taking the above into account, when determining the second phase difference, the embodiment of the present application does not require that the values ​​of all sub-data in the multiplied sequence are the same, as long as the sub-data with the same value reaches the second preset number. For example, if the multiplied clock is an 8-fold multiplied clock and the preset multiple is 8, then the second preset number can be 8, 7, 6, etc.

[0153] Furthermore, to ensure the accuracy of the second phase difference detection, the number of consecutive frequency multiplication sequences containing a second preset number of sub-data with the same value must reach a first preset number. For example, the first preset number can be 256, 512, etc. To shorten the LVDS training time, it is not necessary to test the first preset number of frequency multiplication sequences each time step S502 is executed. Instead, step S504 is executed directly as soon as any frequency multiplication sequence containing a number of sub-data with the same value less than the second preset number is detected.

[0154] S503: Determine that the current training phase difference is the second phase difference.

[0155] S504: Adjust the training phase difference.

[0156] Return to step S502 and continue execution.

[0157] Specifically, the value of the training phase difference may be adjusted randomly, or the value of the training phase difference may be adjusted to preset alternative values ​​in a fixed order.

[0158] As can be seen from the above, the embodiment of the present application collects a multiplication sequence based on the phase and clock frequency of the multiplication clock, and determines the second phase difference of the target LVDS component according to the value of the sub-data in the multiplication sequence. Subsequent communication with the target LVDS component can be carried out based on the determined second phase difference.

[0159] See also Figure 6 , is a schematic diagram of the second LVDS training process provided in an embodiment of the present application, taking the frequency multiplication clock in the line card as an 8x frequency multiplication clock as an example, including the following steps S601-S605.

[0160] After training starts, step S601 is executed.

[0161] S601: Sample the RX signal with an 8x multiplied clock.

[0162] S602: Determine whether [7:0] are all 0 or all 1.

[0163] [7:0] is the frequency multiplication sequence obtained by sampling, which contains 8 bits of data from bit 0 to bit 7. In this embodiment, it is required that all sub-data in the frequency multiplication sequence have the same value, that is, the second preset number is equal to the preset multiple.

[0164] If so, execute step S603; otherwise, execute step S604.

[0165] S603: The count is increased by 1.

[0166] After executing step S603 , continue to execute step S605 .

[0167] S604: Clear the count and adjust the bit sliding signal.

[0168] Bit sliding is also called Bitslip. The training phase difference can be adjusted by adjusting the bit sliding signal.

[0169] After executing step S604, the process returns to executing step S601.

[0170] S605: Check whether the count reaches 256.

[0171] That is, the first preset number in this embodiment is 256.

[0172] If it reaches 256, the training ends; if it does not reach 256, the process returns to step S601.

[0173] Corresponding to the aforementioned LVDS communication method applied to the line card, an embodiment of the present application further provides a line card.

[0174] The line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, the LVDS component being configured on a daughter card, and the line card performs the following steps:

[0175] determining whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored;

[0176] If the first phase difference is stored, sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0177] If the verification data can be correctly collected, communication is performed with the target LVDS component according to the first phase difference.

[0178] As can be seen from the above, first determine whether the first phase difference corresponding to the target LVDS component has been stored in the line card. If so, send the first start frame to the target LVDS component so that the target LVDS component feeds back the verification data in the first start frame. If the line card can correctly collect the verification data, it means that the first phase difference has passed the verification, so communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, it is only necessary to complete the sending of the first start frame, the reception of the verification data, and the extraction of the verification data. The time required is much less than the time required for an LVDS training. And verifying the first phase difference can also ensure the normal execution of communication in most cases. Therefore, the embodiment of the present application can save the time consumed by the line card for LVDS training before LVDS communication.

[0179] In one embodiment of the present application, the line card further performs the following steps:

[0180] If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0181] As can be seen from the above, in the embodiment of the present application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. After determining the second phase difference, the corresponding relationship between the identifier of the target LVDS component and the second phase difference is stored, so that the second phase difference can be used the next time the target LVDS component is communicated with, saving time consumed in the next communication with the target LVDS component.

[0182] In one embodiment of the present application, performing LVDS training on the target LVDS component to determine the second phase difference corresponding to the target LVDS component includes:

[0183] Sending a second start frame to the target LVDS component so that the target LVDS component sends and receives an RX signal to the line card;

[0184] Determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card; sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data;

[0185] If the number of sub-data with the same value contained in the first preset number of consecutive frequency doubling sequences reaches the second preset number, then determining that the current training phase difference is the second phase difference, and the second preset number is less than or equal to the preset multiple;

[0186] Otherwise, adjust the training phase difference, return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, sampling the RX signal according to the clock frequency of the multiplier clock, and obtaining the multiplier sequence.

[0187] As can be seen from the above, the embodiment of the present application collects a multiplication sequence based on the phase and clock frequency of the multiplication clock, and determines the second phase difference of the target LVDS component according to the value of the sub-data in the multiplication sequence. Subsequent communication with the target LVDS component can be carried out based on the determined second phase difference.

[0188] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0189] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0190] The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame;

[0191] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0192] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code;

[0193] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0194] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0195] In one embodiment of the present application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

[0196] Corresponding to the aforementioned LVDS communication method applied to the line card, an embodiment of the present application further provides an electronic device.

[0197] See also Figure 7 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device comprising:

[0198] Processor 701;

[0199] transceiver 704;

[0200] A line card 705, wherein the line card 705 stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component;

[0201] a daughter card 706 , wherein the daughter card 706 is configured with an LVDS component;

[0202] a machine-readable storage medium 702 storing machine-executable instructions that can be executed by the processor 701;

[0203] The line card 705 implements any method step described in the LVDS communication method.

[0204] like Figure 7 As shown, the network device may further include a communication bus 703. The processor 701, the machine-readable storage medium 702, and the transceiver 704 communicate with each other via the communication bus 703. The communication bus 703 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 703 may be divided into an address bus, a data bus, a control bus, and the like.

[0205] The transceiver 704 may be a wireless communication module, and under the control of the processor 701 , the transceiver 704 exchanges data with other devices.

[0206] The machine-readable storage medium 702 may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Alternatively, the machine-readable storage medium 702 may be at least one storage device located remote from the processor.

[0207] The processor 701 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0208] The line card 705 may be an FPGA.

[0209] Corresponding to the aforementioned LVDS communication method, an embodiment of the present application further provides an LVDS communication device.

[0210] See also Figure 8, is a schematic structural diagram of an LVDS communication device provided in an embodiment of the present application, which is applied to a line card. The line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component. The LVDS component is configured on a daughter card. The device includes:

[0211] A first phase difference determining module 801 is configured to determine whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored;

[0212] a first start frame sending module 802 configured to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference;

[0213] The first communication module 803 is configured to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly collected.

[0214] As can be seen from the above, first determine whether the first phase difference corresponding to the target LVDS component has been stored in the line card. If so, send the first start frame to the target LVDS component so that the target LVDS component feeds back the verification data in the first start frame. If the line card can correctly collect the verification data, it means that the first phase difference has passed the verification, so communication can be directly based on the first phase difference. In this case, before communicating with the target LVDS component, it is only necessary to complete the sending of the first start frame, the reception of the verification data, and the extraction of the verification data. The time required is much less than the time required for an LVDS training. And verifying the first phase difference can also ensure the normal execution of communication in most cases. Therefore, the embodiment of the present application can save the time consumed by the line card for LVDS training before LVDS communication.

[0215] In one embodiment of the present application, the device further comprises:

[0216] The second communication module is used to perform low voltage differential signal LVDS training on the target LVDS component if the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

[0217] As can be seen from the above, in the embodiment of the present application, LVDS training is only required to determine the second phase difference when the first phase difference fails verification or is not stored. After determining the second phase difference, the corresponding relationship between the identifier of the target LVDS component and the second phase difference is stored, so that the second phase difference can be used the next time the target LVDS component is communicated with, saving time consumed in the next communication with the target LVDS component.

[0218] In one embodiment of the present application, the second phase difference is determined by the following modules:

[0219] a second start frame sending module, configured to send a second start frame to the target LVDS component, so that the target LVDS component sends and receives an RX signal to the line card;

[0220] a sequence extraction module, configured to determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, and sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data;

[0221] a second phase difference determining module, configured to determine that the current training phase difference is a second phase difference if the number of sub-data with the same value contained in a first preset number of consecutive frequency doubling sequences reaches a second preset number, and the second preset number is less than or equal to the preset multiple;

[0222] The phase difference adjustment module is used to adjust the training phase difference and return to trigger the execution of the sequence extraction module if there are no consecutive first preset number of frequency doubling sequences containing sub-data with the same value that reach a second preset number.

[0223] As can be seen from the above, the embodiment of the present application collects a multiplication sequence based on the phase and clock frequency of the multiplication clock, and determines the second phase difference of the target LVDS component according to the value of the sub-data in the multiplication sequence. Subsequent communication with the target LVDS component can be carried out based on the determined second phase difference.

[0224] In one embodiment of the present application, the second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code;

[0225] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag;

[0226] The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame;

[0227] The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

[0228] In one embodiment of the present application, the first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code;

[0229] The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag;

[0230] The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

[0231] In one embodiment of the present application, the line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

[0232] In another embodiment provided in the present application, a computer-readable storage medium is further provided, wherein a computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of any of the above-mentioned LVDS communication methods are implemented.

[0233] In another embodiment provided by the present application, a computer program product including instructions is further provided, which, when executed on a computer, enables the computer to execute any one of the LVDS communication methods in the above embodiments.

[0234] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0235] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0236] Each embodiment in this specification is described in a related manner. Similar portions between embodiments can be referenced across them. Each embodiment focuses on the differences between the other embodiments. In particular, the line card, electronic device, apparatus, computer-readable storage medium, and computer program product embodiments are generally similar to the method embodiments, so their descriptions are simplified. For related portions, refer to the descriptions of the method embodiments.

[0237] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. An LVDS communication method, characterized in that: Applied to a line card, the line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, the LVDS component being configured on a daughter card, the method comprising: determining whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored; If the first phase difference is stored, sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference; If the verification data can be correctly collected, communication is performed with the target LVDS component according to the first phase difference.

2. The method according to claim 1, characterized in that The method further comprises: If the first phase difference is not stored, or the verification data cannot be correctly extracted from the received data according to the first phase difference, low voltage differential signal LVDS training is performed on the target LVDS component to determine the second phase difference corresponding to the target LVDS component, communicate with the target LVDS component according to the second phase difference, and record the phase difference corresponding to the target identifier as the second phase difference.

3. The method according to claim 2, characterized in that The performing LVDS training on the target LVDS component to determine a second phase difference corresponding to the target LVDS component includes: Sending a second start frame to the target LVDS component so that the target LVDS component sends and receives an RX signal to the line card; Determine the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card; sample the RX signal at the clock frequency of the multiplier clock according to the phase of the RX signal to obtain a multiplier sequence, wherein an initial value of the training phase difference is a preset value, the clock frequency of the multiplier clock is a preset multiple of the clock frequency of the original clock in the line card, and each multiplier sequence contains the preset multiple of consecutive sub-data; If the number of sub-data with the same value contained in the first preset number of consecutive frequency doubling sequences reaches the second preset number, then determining that the current training phase difference is the second phase difference, and the second preset number is less than or equal to the preset multiple; Otherwise, adjust the training phase difference, return to the step of determining the phase of the RX signal according to the training phase difference and the phase of the multiplier clock of the line card, sampling the RX signal according to the clock frequency of the multiplier clock, and obtaining the multiplier sequence.

4. The method according to claim 3, characterized in that The second start frame includes at least one of the following fields: a first idle code, a start flag, a first training flag, a first operation instruction, a start address of the target LVDS component, a first check code, and a second idle code; The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame or the second start frame after receiving the data frame containing the start flag; The first training flag is used to indicate that the data frame where the first training flag is located is a second starting frame; The first operation instruction is used to instruct the target LVDS component to perform an operation after receiving the second start frame.

5. The method according to claim 1, wherein The first start frame includes at least one of the following fields: a first idle code, a start flag, a second training flag, a second operation instruction, a start address of the target LVDS component, check data, a second check code, and a second idle code; The value of the start flag is a preset value, so that the target LVDS component determines that the data frame is the first start frame after receiving the data frame including the start flag and the second training flag; The second operation instruction is used to instruct the target LVDS component to perform an operation after receiving the first start frame.

6. The method according to any one of claims 1 to 5, characterized in that The line card stores a correspondence between the identifier and number of the LVDS component and the phase difference of the LVDS component, and different correspondences correspond to different numbers.

7. A line card, characterized in that: The line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, the LVDS component being configured on a daughter card, and the line card performs the following steps: determining whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored; If the first phase difference is stored, sending a first start frame carrying verification data to the target LVDS component, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference; If the verification data can be correctly collected, communication is performed with the target LVDS component according to the first phase difference.

8. An electronic device, characterized in that: The electronic device comprises: processor; transceiver; A line card storing a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component; A daughter card, wherein the daughter card is configured with an LVDS component; a machine-readable storage medium storing machine-executable instructions that can be executed by the processor; The line card implements the method steps described in any one of claims 1-6.

9. An LVDS communication device, characterized in that: Applied to a line card, the line card stores a correspondence between an identifier of a low voltage differential signal (LVDS) component and a phase difference of the LVDS component, the LVDS component being configured on a daughter card, and the device comprising: A first phase difference determining module, configured to determine whether a first phase difference corresponding to a target identifier of a target LVDS component to be accessed is stored; a first start frame sending module, configured to send a first start frame carrying verification data to the target LVDS component if the first phase difference is stored, so that the target LVDS component feeds back the verification data to the line card to determine whether the verification data can be correctly collected from the received data according to the first phase difference; The first communication module is configured to communicate with the target LVDS component according to the first phase difference if the verification data can be correctly collected.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 6 are implemented.

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