Chip, interface reconstruction method and related device
By encapsulating multiple interface units at the system level, flexible switching of interfaces in the test equipment is achieved, solving the problems of complex internal structure and large space occupation of the equipment caused by complex interface circuit design in the existing technology, and realizing miniaturization and simplification of the equipment.
Patent Information
- Application Number
- CN202510808866.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-09-30
AI Technical Summary
The interface circuit design in existing test equipment is complex, resulting in a complex internal structure of the equipment and a large space occupation.
The communication interface unit, reconfigurable interface unit and FPGA reconstruction unit are packaged in a stacking system. The configuration file is loaded into the FPGA reconstruction unit to drive the reconfigurable interface unit to switch to the target interface unit, thus realizing flexible switching of multiple interfaces.
The chip structure is simplified, the installation space requirement is reduced, and the simplicity of the internal structure of the test equipment is improved.
Smart Images
Figure CN120723715A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing, and in particular to a chip, an interface reconstruction method and related devices. Background Art
[0002] After ammunition devices are manufactured and delivered to users, they typically undergo performance testing using testing equipment (also known as ammunition testing equipment) before or during use. By analyzing the test results, it is possible to assess whether the ammunition device meets requirements and, in turn, decide whether to return it to the factory for maintenance or scrap it.
[0003] In related technologies, test equipment covers interfaces such as Ethernet, serial, and 1553B communications. Each interface circuit is typically designed using a dedicated interface chip combined with peripheral components. This results in complex circuit design and numerous associated components. This leads to issues such as internal complexity of the test equipment and the large space required for installation. Summary of the Invention
[0004] In view of this, the embodiments of the present application provide a chip, an interface reconstruction method and related devices, the purpose of which is to simplify the chip structure, thereby simplifying the internal structure of the test equipment and reducing the space required for installation.
[0005] In a first aspect, an embodiment of the present application provides a chip, comprising:
[0006] At least two types of communication interface units, reconfigurable interface units, and field programmable gate array (FPGA) reconfiguration units; the communication interface units, the reconfigurable interface units, and the FPGA reconfiguration units are system-level packaged to the chip in a stacked manner;
[0007] The FPGA reconfiguration unit is configured to load a configuration file corresponding to a target interface unit to drive the reconfigurable interface unit to switch to the target interface unit;
[0008] The reconfigurable interface unit is configured to switch to the target interface unit in response to the FPGA reconfiguration unit loading the configuration file;
[0009] The communication interface unit is used to communicate with the device to be tested.
[0010] Optionally, the chip further includes a memory unit, the FPGA reconstruction unit includes a static area and a reconstruction area, the static area includes a processor and a reconstruction intellectual property IP core;
[0011] The processor is configured to obtain the configuration file from the memory unit and to control the reconstruction IP core to write the configuration file into the reconstruction area;
[0012] The reconfiguration area is used to load the configuration file to drive the reconfigurable interface unit to switch to the target interface unit;
[0013] The reconfigurable interface unit is configured to switch to the target interface unit in response to the reconfiguration area loading the configuration file.
[0014] Optionally, the chip further includes a buffer unit;
[0015] The buffer unit is used to receive the configuration file and the configuration area address sent by the computer device;
[0016] The processor is further configured to control the buffer unit to write the configuration file into the configuration area address of the memory unit.
[0017] Optionally, the FPGA reconstruction unit further includes a communication IP core;
[0018] The processor is further configured to control the communication IP core to drive the communication interface unit to communicate with the device under test.
[0019] Optionally, the at least two types of communication interface units include at least two of the following: an Ethernet communication interface unit, a serial communication interface unit, and a bus communication interface unit.
[0020] Optionally, the chip further includes a digital signal interface unit and an analog signal interface unit;
[0021] The digital signal interface unit is used to receive status information of the device under test and to send a switching signal to the device under test;
[0022] The analog signal interface unit is used to convert the analog signal sent by the device to be tested into a digital signal, and convert the digital signal to be sent into an analog signal and send it to the device to be tested.
[0023] In a second aspect, an embodiment of the present application provides an interface reconstruction method, which is applied to a chip, wherein the chip includes: at least two types of communication interface units, a reconfigurable interface unit, and a field programmable gate array (FPGA) reconstruction unit; the communication interface unit, the reconfigurable interface unit, and the FPGA reconstruction unit are system-level packaged to the chip in a stacked manner; the method includes:
[0024] Get the configuration file corresponding to the target interface unit;
[0025] Loading the configuration file through the FPGA reconstruction unit;
[0026] The reconfigurable interface unit is switched to the target interface unit in response to the FPGA reconfiguration unit loading the configuration file.
[0027] In a third aspect, an embodiment of the present application provides an interface reconstruction device, the device including a memory and a processor:
[0028] The memory is used to store a computer program and transmit the computer program to the processor;
[0029] The processor is used to execute the computer program so that the device performs the interface reconstruction method described in the second aspect.
[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed, the device executing the computer program implements the interface reconstruction method described in the second aspect above.
[0031] In a fifth aspect, an embodiment of the present application provides a testing device, which includes the chip described in the first aspect, is connected to a device to be tested, and is used to test the device to be tested based on the chip.
[0032] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0033] An embodiment of the present application provides a chip, an interface reconstruction method and related devices, wherein the chip includes: at least two types of communication interface units, a reconfigurable interface unit and a field programmable gate array (FPGA) reconstruction unit; the communication interface unit, the reconfigurable interface unit and the FPGA reconstruction unit are system-level packaged into the chip in a stacked manner; wherein the FPGA reconstruction unit is used to load a configuration file corresponding to a target interface unit to drive the reconfigurable interface unit to switch to the target interface unit; the reconfigurable interface unit is used to switch to the target interface unit in response to the loading of the configuration file by the FPGA reconstruction unit; and the communication interface unit is used to communicate with a device to be tested.
[0034] Because the communication interface units, reconfigurable interface units, and FPGA reconfiguration units can be stacked and packaged into a single chip, this single chip integrates multiple interface units. Furthermore, the chip includes a reconfigurable interface unit that can dynamically switch to a target interface unit based on demand, allowing it to be reused as a variety of interface units. This provides high flexibility and reduces the need for dedicated interface units. Consequently, the chip's structure is simple and the space it occupies is significantly reduced, helping to simplify the internal structure of test equipment and reduce the space required for its installation. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the following briefly introduces the drawings required for use in the embodiment or the prior art description. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0036] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of the present application;
[0037] Figure 2 A schematic diagram of the structure of a specific chip provided in an embodiment of the present application;
[0038] Figure 3 A schematic diagram of a reconstruction based on an FPGA reconstruction unit provided in an embodiment of the present application;
[0039] Figure 4 A flowchart of an interface reconstruction method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0041] Currently, test equipment typically covers a large number of interfaces, including Ethernet, serial, and 1553B communications. The interface circuits for each interface are typically designed using a combination of dedicated interface chips and peripheral components. Each interface circuit corresponds to a relatively independent functional board, resulting in complex circuit design and numerous associated components. Consequently, test equipment often includes numerous complex functional boards, resulting in complex internal structures and requiring significant installation space.
[0042] Based on this, in order to solve the above problems, an embodiment of the present application provides a chip, an interface reconstruction method and related devices, the chip including: at least two types of communication interface units, a reconfigurable interface unit and a field programmable gate array FPGA reconstruction unit; the communication interface unit, the reconfigurable interface unit and the FPGA reconstruction unit are system-level packaged to the chip in a stacked manner; wherein the FPGA reconstruction unit is used to load a configuration file corresponding to the target interface unit to drive the reconfigurable interface unit to switch to the target interface unit; the reconfigurable interface unit is used to switch to the target interface unit in response to the loading of the configuration file by the FPGA reconstruction unit; the communication interface unit is used to communicate with the device to be tested.
[0043] Because the communication interface units, reconfigurable interface units, and FPGA reconfiguration units can be stacked and packaged into a single chip, this single chip integrates multiple interface units. Furthermore, the chip also includes a reconfigurable interface unit that can dynamically switch between the two units as needed, allowing for multiplexing into a variety of interface units. This flexibility reduces the need for dedicated interface units. Consequently, the chip's structure is simple, significantly reducing the space it occupies, simplifying the internal structure of test equipment and reducing the space required for its installation.
[0044] The specific implementation of a chip, an interface reconstruction method, and related devices in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0045] See also Figure 1 , FIG is a schematic diagram of the structure of a chip provided in an embodiment of the present application, combined with Figure 1 It is shown that the chip may specifically include: at least two types of communication interface units, a reconfigurable interface unit and a field programmable gate array FPGA reconstruction unit; the communication interface unit, the reconfigurable interface unit and the FPGA reconstruction unit are system-level packaged to the chip in a stacked manner.
[0046] Among them, the communication interface unit, reconfigurable interface unit, FPGA reconstruction unit and other units in the chip can be packaged into the chip using system-in-package (SiP) technology. Specifically, the units can be stacked to tightly combine the units together, which can achieve interconnection and collaborative work between the units, thereby greatly saving space and realizing miniaturization of the chip.
[0047] The communication interface unit and the reconfigurable interface unit can be deployed in the interface integrated circuit wafer, and the FPGA reconfiguration unit can be deployed in the FPGA. Therefore, various interface integrated circuit wafers, FPGAs, and passive components can be system-packaged into the chip provided by the embodiments of this application. Passive components refer to the components required for the design of each interface integrated circuit, such as resistors, inductors, capacitors, and other components.
[0048] In some embodiments, the chip package size can be set to be less than or equal to a size threshold. For example, if the size threshold is 40 millimeters (mm) x 40 mm, the chip package size is no larger than 40 mm x 40 mm. The chip can be packaged in a ball grid array (BGA) package, and the distance between the centers of two adjacent solder balls is no larger than 1 mm (also referred to as no larger than 1 mm).
[0049] In some embodiments, when the chip is in operation, for example, when test equipment equipped with the chip is testing ammunition devices, its operating temperature can be between -40°C and +85°C, and its external operating voltage can be 3.3V±0.1V, 1.0V±0.01V, 1.8V±0.05V, 1.25±0.05V, or 1.2±0.03V. When all interfaces of the interface units in the chip are in operation and all resources of the FPGA are occupied, the power consumption of the chip can be less than or equal to 10 watts (W).
[0050] The FPGA reconfiguration unit is used to load a configuration file corresponding to the target interface unit to drive the reconfigurable interface unit to switch to the target interface unit.
[0051] The reconfigurable interface unit is configured to switch to the target interface unit in response to the FPGA reconfiguration unit loading the configuration file.
[0052] In some embodiments, there is no limit on the number of reconfigurable interface units in a chip, and one or more can be pre-configured. The reconfigurable interface unit can be implemented collaboratively within the programmable logic (PL) and processing system (PS) of a system-on-chip (SoC) within the chip. For example, the SoC can include the aforementioned FPGA, which in turn includes an ARM processor.
[0053] It should be noted that the ARM processor can also exist in parallel with the FPGA in the SoC. Accordingly, in this case, the chip includes the processor.
[0054] The target interface unit can be any interface unit required by actual needs, not a specific one. For example, if an Ethernet communication interface is required in a chip, the target interface unit can be an Ethernet communication interface unit. The configuration file for the Ethernet communication interface unit can be a bitstream file. Loading the configuration file into the FPGA reconfiguration unit activates the corresponding logic unit in the chip and connects the physical pins accordingly, switching the reconfigurable interface unit to an Ethernet communication interface unit.
[0055] In a possible implementation of the present application, the chip may further include a memory unit, and the FPGA reconstruction unit may include a static area and a reconstruction area, wherein the static area includes a processor and a reconstruction intellectual property IP core.
[0056] The processor is used to obtain the configuration file from the memory unit, and to control the reconstruction IP core to write the configuration file into the reconstruction area.
[0057] Among them, the reconstructed IP core can be referred to as the CG IP core. See below Figure 3 shown.
[0058] For example, the processor may be an Advanced RISC Machine (ARM) processor, which may also be referred to as an IP core. The memory unit may be a Flash Memory (Flash) storage unit. The following text will use the ARM processor and the Flash storage unit as an example for description, but this does not limit the present application. Figure 3 shown.
[0059] In some embodiments, the static area may also include an Advanced eXtensible Interface (AXI). The ARM processor can access the peripheral control IP core through AXI to achieve control of the peripherals. Figure 3 shown.
[0060] The peripherals may be various units connected to the FPGA reconfiguration unit, such as a communication interface unit, a memory unit, a buffer unit, etc. The peripheral control IP core may be an IP core for controlling various peripherals, for example, the IP core for controlling the communication interface unit may be a communication IP core, etc.
[0061] In a possible implementation of the present application, the chip may further include a cache unit.
[0062] For example, the buffer unit may be a double data rate (DDR) buffer unit.
[0063] The buffer unit is used to receive the configuration file and the configuration area address sent by the computer device.
[0064] The chip can communicate with a remote computer (also called a computer device). The remote computer can dynamically configure the configuration file of the required target interface unit. The remote computer can then reconfigure the chip and send the configuration file and the configuration area address to the cache unit. The configuration area address refers to the storage area address of the configuration file configured by the remote computer. See below. Figure 3 shown.
[0065] In some embodiments, the configuration area address may be an address where a configuration file is stored in a memory unit.
[0066] The processor is further configured to control the buffer unit to write the configuration file into the configuration area address of the memory unit.
[0067] In the example where the cache unit is a DDR cache unit, the peripheral control IP core may include a DDR IP core, and the processor may control the DDR cache unit through the DDR IP core to write the configuration file into the configuration area address of the memory unit. Figure 3 shown.
[0068] In a possible implementation of the present application, the FPGA reconfiguration unit further includes a communication IP core. The communication IP core is one of the peripheral control IP cores described above.
[0069] The processor is further configured to control the communication IP core to drive the communication interface unit to communicate with the device under test.
[0070] For example, the communication interface unit may be a Peripheral Component Interconnect Express (PCIE) interface unit, and the communication IP core may be a PCIE IP core. Taking an ARM processor as an example, the ARM processor may control the PCIE interface unit to communicate with the device under test through the PCIE IP core. Figure 3 shown.
[0071] The reconfiguration area is used to load the configuration file to drive the reconfigurable interface unit to switch to the target interface unit.
[0072] The FPGA reconfiguration unit may be connected to the reconfigurable interface. Specifically, the reconfiguration area may be connected to the reconfigurable interface unit, and the reconfigurable interface unit may be connected to the functional circuit.
[0073] After the reconstruction area receives the configuration file, it can load the configuration file to dynamically reconstruct its own logic part, drive the reconfigurable interface unit to switch to the target interface unit, and the connected functional circuit can be a functional circuit adapted to the target interface unit. Figure 3 shown.
[0074] In the example where the target interface unit is an Ethernet communication interface unit, the functional circuit may be a data accelerator, a sensor interface, etc., which is not limited in this application.
[0075] The reconfigurable interface unit is configured to switch to the target interface unit in response to the reconfiguration area loading the configuration file.
[0076] The reconfigurable interface unit can be switched to a target interface unit in response to the reconfiguration area loading a configuration file.
[0077] The communication interface unit is used to communicate with the device to be tested.
[0078] In a possible implementation of the present application, the at least two types of communication interface units include at least two of the following: a network port communication interface unit, a serial port communication interface unit, and a bus communication interface unit.
[0079] For example, the bus communication interface unit may be a 1553B communication interface unit, a controller area network (CAN) bus communication interface unit, etc. This application does not limit this and can be designed according to requirements.
[0080] In a possible implementation of the present application, the chip may further include a digital signal interface unit and an analog signal interface unit.
[0081] The digital signal interface unit is used to receive status information of the device under test and to send a switching signal to the device under test.
[0082] For example, the digital signal interface unit may include a discrete input interface unit and a discrete output interface unit.
[0083] The discrete input interface unit can receive status information of the device under test. For example, the device under test can perform self-test and send the self-test status to the discrete input interface unit, which can specifically be status information such as device operation failure and device normal operation.
[0084] The discrete output interface unit can send digital signals, such as "0" or "1", to the device under test, and can perform switch control on the device under test, such as controlling the start or stop of the device under test, and then determine whether the device under test can operate normally according to the switch control.
[0085] The analog signal interface unit is used to convert the analog signal sent by the device to be tested into a digital signal, and convert the digital signal to be sent into an analog signal and send it to the device to be tested.
[0086] For example, the analog signal interface unit may include an analog-to-digital conversion input interface unit and a digital-to-analog conversion output interface unit. A / D conversion can be referred to as the conversion of an analog signal into a digital signal (AD), and D / A conversion can be referred to as the conversion of a digital signal into an analog signal (DA).
[0087] The chip can collect analog signal data such as temperature, pressure, voltage, etc. of the device to be tested through the AD input interface unit and convert it into digital signal data.
[0088] The chip can convert internal digital signal data into analog signal data through the DA output interface unit and send it to the device under test.
[0089] In one example, the chip may include the following interface resources: one 1M intelligent dual-redundant 1553B transceiver interface; four RS232 transceiver interfaces; four intelligent RS422 / RS485 transceiver interfaces; two CAN transceiver interfaces; two Gigabit Ethernet physical layer (PHY) interfaces; eight 16-bit AD input interfaces; four 16-bit DA output interfaces; and one or more reconfigurable interfaces. "1M" refers to a transmission rate of 1 megabit per second (Mbps). "Bit" refers to the unit of digital signal data.
[0090] Among them, the 1-channel 1M intelligent dual-redundant 1553B transceiver interface is an example of the interface of the 1553B communication interface unit; the 4-channel RS232 transceiver interfaces and the 4-channel intelligent RS422 / RS485 transceiver interfaces are examples of the interface of the serial port communication interface unit; the 2-channel CAN transceiver interfaces are examples of the interface of the CAN bus communication interface unit; the 2-channel Gigabit Ethernet PHY interfaces are examples of the interface of the network port communication interface unit; the 8-channel 16-Bit AD input interfaces are examples of the interface of the AD input interface unit; and the 4-channel 16-Bit DA output interfaces are examples of the interface of the DA output interface unit.
[0091] See also Figure 2, which is a schematic diagram of the structure of a specific chip provided in an embodiment of the present application. The chip may include a Z7045 bare core (which refers to the SoC introduced above, the SoC has a built-in FPGA, and the FPGA has a built-in ARM), a 1553B transceiver bare core (that is, the 1553B communication interface unit introduced above), an RS232 transceiver bare core (that is, the serial communication interface unit introduced above), an RS422 / RS485 transceiver bare core (that is, the serial communication interface unit introduced above), a CAN transceiver bare core (that is, the CAN bus communication interface unit introduced above); an Ethernet PHY chip bare core (that is, the network port communication interface unit introduced above); an AD converter bare core (that is, the AD input interface unit introduced above); a DA converter bare core (that is, the DA output interface unit introduced above); a Flash storage unit, a power management unit, an integrated passive device (IPD) resistor-capacitor network (that is, an example of the passive device introduced above) and a clock distribution unit. The power management unit (PMU) provides power to the chip, the clock distribution unit (CDU) sends clock signals to the chip, and the Z7045 die has input and output ports. For more information about other die or units, see the previous section and we won't go into detail here.
[0092] See also Figure 3 , this figure is a schematic diagram of a reconstruction based on an FPGA reconstruction unit provided in an embodiment of the present application. The FPGA reconstruction unit includes a static area and a reconstruction area. The static area may include an ARM processor, AXI, CG IP core, DDR IP core, FL IP core and PCIE IP core. The ARM processor can establish a communication connection with the computer device through an Ethernet communication interface unit. The communication connection can be implemented based on the Transmission Control Protocol (TCP) or based on the Internet Protocol (IP). The reconstruction area can be connected to the functional circuit. The specific reconstruction process can be referred to the above introduction and will not be repeated here.
[0093] The above embodiments of the present application provide some specific implementations of various units in the chip. Based on this, the present application also provides a corresponding interface reconstruction method. The interface reconstruction method provided by the embodiment of the present application will be introduced from a step-by-step perspective.
[0094] See also Figure 4, this figure is a flow chart of an interface reconstruction method provided by an embodiment of the present application, which can be applied to the chip introduced above, wherein the chip includes: at least two types of communication interface units, a reconfigurable interface unit, and a field programmable gate array FPGA reconstruction unit; the communication interface unit, the reconfigurable interface unit, and the FPGA reconstruction unit are system-level packaged to the chip in a stacked manner; combined with Figure 4 As shown, the method may specifically include the following steps:
[0095] S401: Obtain a configuration file corresponding to the target interface unit.
[0096] In some embodiments, the chip may be communicatively connected to a computer device, and the computer device may dynamically configure a configuration file according to requirements and then send the configuration file to the chip.
[0097] S402: Load the configuration file through the FPGA reconstruction unit.
[0098] S403: In response to the FPGA reconfiguration unit loading the configuration file, the reconfigurable interface unit is switched to the target interface unit.
[0099] The specific implementation of S401-S403 can be found in the above introduction about the functions of each unit in the chip, which will not be repeated here.
[0100] An embodiment of the present application also provides a corresponding testing device, characterized in that the testing device includes the chip introduced in the above embodiment, the testing device is connected to the device to be tested, and the testing device is used to test the device to be tested based on the chip.
[0101] The test equipment can communicate and test the various units of the chip.
[0102] The device to be tested may be an ammunition device, etc., which is not limited in this application.
[0103] The embodiments of the present application also provide corresponding interface reconstruction devices and computer-readable storage media for implementing the solutions provided in the embodiments of the present application.
[0104] The interface reconstruction device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to execute the computer program, so that the device executes the interface reconstruction method described in any embodiment of the present application.
[0105] The computer-readable storage medium stores a computer program. When the computer program is executed, a device executing the computer program implements the interface reconstruction method described in any embodiment of the present application.
[0106] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of this application are only used as name identifiers and do not represent the first or second in order.
[0107] Through the description of the above embodiments, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a readable storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or certain parts of the embodiments of the present application.
[0108] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the chip embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the chip embodiment. The chip embodiment described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. A person of ordinary skill in the art can understand and implement it without paying any creative work.
[0109] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A chip, characterized in that: The chip includes: At least two types of communication interface units, reconfigurable interface units, and field programmable gate array (FPGA) reconfiguration units; the communication interface units, the reconfigurable interface units, and the FPGA reconfiguration units are system-level packaged to the chip in a stacked manner; The FPGA reconfiguration unit is configured to load a configuration file corresponding to a target interface unit to drive the reconfigurable interface unit to switch to the target interface unit; The reconfigurable interface unit is configured to switch to the target interface unit in response to the FPGA reconfiguration unit loading the configuration file; The communication interface unit is used to communicate with the device to be tested.
2. The chip according to claim 1, further comprising a memory unit, wherein the FPGA reconfiguration unit comprises a static area and a reconfiguration area, wherein the static area comprises a processor and a reconfiguration intellectual property IP core; The processor is configured to obtain the configuration file from the memory unit and to control the reconstruction IP core to write the configuration file into the reconstruction area; The reconfiguration area is used to load the configuration file to drive the reconfigurable interface unit to switch to the target interface unit; The reconfigurable interface unit is configured to switch to the target interface unit in response to the reconfiguration area loading the configuration file.
3. The chip according to claim 2, characterized in that The chip also includes a buffer unit; The buffer unit is used to receive the configuration file and the configuration area address sent by the computer device; The processor is further configured to control the buffer unit to write the configuration file into the configuration area address of the memory unit.
4. The chip according to claim 2, characterized in that The FPGA reconstruction unit also includes a communication IP core; The processor is further configured to control the communication IP core to drive the communication interface unit to communicate with the device under test.
5. The chip according to any one of claims 1 to 4, characterized in that: The at least two types of communication interface units include at least two of the following: an Ethernet communication interface unit, a serial communication interface unit, and a bus communication interface unit.
6. The chip according to any one of claims 1 to 4, characterized in that: The chip also includes a digital signal interface unit and an analog signal interface unit; The digital signal interface unit is used to receive status information of the device under test and to send a switching signal to the device under test; The analog signal interface unit is used to convert the analog signal sent by the device to be tested into a digital signal, and convert the digital signal to be sent into an analog signal and send it to the device to be tested.
7. An interface reconstruction method, characterized in that: The invention is applied to a chip, the chip comprising: at least two types of communication interface units, a reconfigurable interface unit, and a field programmable gate array (FPGA) reconfiguration unit; the communication interface unit, the reconfigurable interface unit, and the FPGA reconfiguration unit are system-level packaged to the chip in a stacked manner; the method comprises: Get the configuration file corresponding to the target interface unit; Loading the configuration file through the FPGA reconstruction unit; The reconfigurable interface unit is switched to the target interface unit in response to the FPGA reconfiguration unit loading the configuration file.
8. An interface reconstruction device, characterized in that: The device includes a memory and a processor: The memory is used to store a computer program and transmit the computer program to the processor; The processor is configured to execute the computer program so as to enable the device to perform the steps of the interface reconstruction method according to claim 7.
9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program. When the computer program is executed, the device executing the computer program implements the steps of the interface reconstruction method according to claim 7.
10. A testing device, characterized in that: The testing device comprises the chip according to any one of claims 1 to 5, is connected to a device to be tested, and is used to test the device to be tested based on the chip.