A Pixelated Matching Circuit Design and Optimization Method Based on a Large Language Model

Abstract

This invention discloses a pixelated matching circuit design and optimization method based on a large language model, relating to the field of radio frequency circuit technology. The method includes: obtaining the target requirements and physical constraints of the matching circuit; generating an initial topology based on the target requirements and physical constraints; estimating the parameters of the initial topology to obtain an initial binary matrix constrained by the initial topology and the parameters; deriving an optimization problem based on the initial binary matrix and the target requirements; wherein the optimization problem includes the distribution of optimization parameters, optimization objective, and solution space; obtaining key performance indicators and an optimization algorithm based on the optimization problem; iteratively searching within the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology. This invention can generate the optimal pixelated topology and achieve efficient global optimization.

Description

Technical Field

[0001] This invention relates to the field of radio frequency circuit design technology, and in particular to a pixelated matching circuit design and optimization method based on a large language model. Background Technology

[0002] With the increasing prevalence of radio frequency (RF) communication applications, the demands of wireless communication systems for multi-band and wideband capabilities have placed unprecedented performance requirements on power amplifiers (PAs). However, in the era of CMOS technology, known for its low cost and high integration, PA design, especially its core matching circuit design, faces severe challenges. Currently, PA design lacks innovation in topology, with designers often favoring optimization within classic frameworks such as cascode and common-source circuits. While this approach is safe, it struggles to push performance limits to meet the demands of cutting-edge applications. Furthermore, matching circuit design is a complex multi-objective optimization problem, requiring the optimal balance between output power, efficiency, linearity, gain, and stability. This typically necessitates a time-consuming and labor-intensive iterative process that heavily relies on the designer's experience and intuition.

[0003] The design of matching circuits relies heavily on the designer's personal experience and knowledge. However, this experience is often implicit and difficult to quantify, making the design process less than precisely replicable engineering science. Therefore, to seek better matching circuit design and optimization methods, computational intelligence has been utilized for such designs. For example, the method proposed in the paper "Deep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power Amplifiers" treats the physical layout of the matching circuit as a pixelated grid. Machine learning algorithms determine whether each pixel should be filled with a conductor or left empty, thus designing a completely new circuit topology. This algorithm optimizes the binary matrix representing the topology and uses expensive electromagnetic full simulation results as performance feedback, attempting to search for the optimal solution in a vast solution space. While the above methods can optimize the matching circuit design process to some extent, they are costly, time-consuming, and inefficient, failing to achieve truly efficient global optimization.

[0004] In the process of realizing this invention, the inventors discovered at least the following problems in the prior art:

[0005] Existing design and optimization methods for matching circuits have not achieved truly efficient global optimization. Summary of the Invention

[0006] The purpose of this invention is to provide a pixelated matching circuit design and optimization method based on a large language model, so as to solve the technical problem that existing matching circuit design and optimization methods do not achieve truly efficient global optimization.

[0007] The preferred technical solutions among the many technical solutions provided by this invention can produce a variety of technical effects, which are described in detail below.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a method for designing and optimizing pixel-based matching circuits based on a large language model, comprising:

[0010] Obtain the target requirements and physical constraints of the matching circuit;

[0011] An initial topology is generated based on the target requirements and the physical constraints. Parameters of the initial topology are estimated to obtain an initial binary matrix constrained by the initial topology and the parameters.

[0012] An optimization problem is derived based on the initial binary matrix and the target requirement; wherein, the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space;

[0013] Based on the optimization problem, key performance indicators and optimization algorithms are obtained. The optimization algorithm is iteratively searched according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

[0014] Optionally, the optimization problem derived based on the initial binary matrix and the target requirement includes:

[0015] The initial binary matrix is ​​analyzed to identify the pixels that are not fixed, and the optimization parameters are obtained based on these unfixed pixels.

[0016] The optimization objective is obtained by analyzing the target requirements.

[0017] The optimization parameters and optimization objectives are analyzed to confirm the distribution of the solution space.

[0018] Optionally, the step of obtaining key performance indicators and optimization algorithms based on the optimization problem, and iteratively searching within the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology, includes:

[0019] Identify the properties of the optimization problem, and select an optimization algorithm based on the properties of the optimization problem;

[0020] Based on the optimization objective, generate an impedance matching circuit and electromagnetic topology corresponding to the objective requirements, and confirm the physical size parameters required for the impedance matching circuit and electromagnetic topology.

[0021] Simulation analysis is performed on the physical dimension parameters to obtain the key performance indicators corresponding to the physical dimension parameters;

[0022] Based on the key performance indicators, the optimization algorithm is iteratively searched to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology.

[0023] Optionally, confirming the properties of the optimization problem includes:

[0024] Confirm whether the properties of the optimization parameters are in a high-dimensional discrete variable space;

[0025] Confirm the number of the optimization objectives;

[0026] Confirm whether the distribution of the solution space is sparse.

[0027] Optionally, the step of generating an initial topology based on the target requirements and the physical constraints, and performing parameter estimation on the initial topology to obtain an initial binary matrix constrained by the initial topology and the parameters, includes:

[0028] The large language model generates an initial topology based on the target requirements and the physical constraints;

[0029] The initial topology is used to estimate parameters to obtain key physical parameters;

[0030] An initial binary matrix based on the initial topology and the constraints of the key physical parameters.

[0031] Optionally, obtaining the target requirements and physical constraints of the matching circuit includes:

[0032] The matching circuit is simulated and analyzed to obtain simulation results, and the target requirements of the matching circuit are confirmed based on the simulation results.

[0033] The area of ​​the matching circuit and the metal layer in which the matching circuit is located are determined to obtain the physical constraints of the matching circuit.

[0034] Optionally, in the process of performing simulation analysis on the matching circuit, obtaining simulation results, and confirming the target requirements of the matching circuit based on the simulation results, the simulation analysis includes load-driven simulation analysis and source-driven simulation analysis, and the target requirements include input matching network targets, output matching network targets, key performance indicators, and passive device constraints.

[0035] Secondly, the present invention also provides a pixel-based matching circuit design and optimization processing device based on a large language model, comprising:

[0036] The acquisition module obtains the target requirements and physical constraints of the matching circuit.

[0037] The generation module generates an initial topology based on the target requirements and the physical constraints, performs parameter estimation on the initial topology, and obtains an initial binary matrix constrained by the initial topology and the parameters.

[0038] The confirmation module derives an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space;

[0039] The optimization module obtains key performance indicators and optimization algorithms based on the optimization problem, and iteratively searches the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

[0040] Thirdly, the present invention also provides a terminal device, which includes:

[0041] One or more processors and memory;

[0042] The memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processors perform the steps of the pixel-based matching circuit design and optimization method based on the large language model as described above.

[0043] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the pixel-based matching circuit design and optimization method based on a large language model as described above.

[0044] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects:

[0045] In this invention, the large language model first acquires the target requirements and physical constraints of the matching circuit. Then, based on the target requirements and physical constraints, an initial topology is generated, and parameters are estimated to obtain an initial binary matrix constrained by the initial topology and parameters. In subsequent optimization processes, this initial binary matrix serves as the starting point for the optimization algorithm, avoiding blind or random searches.

[0046] Then, based on the initial binary matrix and the target requirements, an optimization problem is derived, which includes optimization parameters, optimization objectives, and the distribution of the solution space. Finally, key performance indicators and optimization algorithms are obtained based on the optimization problem. The optimization algorithm iteratively searches based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology. In this embodiment, the large language model generates an initial binary matrix based on the target requirements and physical constraints of the matching circuit, providing a high-quality initial starting point for subsequent optimization design, saving operation time and improving efficiency. Subsequently, key performance indicators are determined based on the optimization problem, and a suitable optimization algorithm is selected. Finally, the optimization algorithm iterates continuously based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology and achieving efficient global optimization. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0048] Figure 1 This is a flowchart illustrating the pixelated matching circuit design and optimization method based on a large language model according to Embodiment 1 of the present invention.

[0049] Figure 2 This is a flowchart illustrating step S20 in the pixelated matching circuit design and optimization method based on a large language model according to Embodiment 1 of the present invention.

[0050] Figure 3 This is a flowchart illustrating step S40 in the pixelated matching circuit design and optimization method based on a large language model according to Embodiment 1 of the present invention.

[0051] Figure 4 This is a schematic diagram of the pixel-based matching circuit design and optimization processing device based on a large language model according to Embodiment 2 of the present invention;

[0052] Figure 5 This is a schematic diagram of the structure of the terminal device in Embodiment 3 of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0054] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "a plurality" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can refer to fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can refer to the internal communication of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0055] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0056] Example 1:

[0057] like Figure 1 As shown, this invention provides a pixel-based matching circuit design and optimization method based on a large language model, including:

[0058] S10. Obtain the target requirements and physical constraints of the matching circuit;

[0059] S20. Generate an initial topology based on the target requirements and physical constraints, estimate the parameters of the initial topology, and obtain an initial binary matrix constrained by the initial topology and parameters.

[0060] S30. An optimization problem is derived based on the initial binary matrix and the objective requirement; wherein, the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space;

[0061] S40. Based on the optimization problem, obtain the key performance indicators and optimization algorithm. Based on the key performance indicators, iteratively search in the optimization algorithm to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

[0062] In this embodiment, the overall process is implemented within a Large Language Model (LLM). The LLM first acquires the target requirements and physical constraints of the matching circuit. Then, based on the target requirements and physical constraints, it generates an initial topology and performs parameter estimation on the initial topology to obtain an initial binary matrix constrained by the initial topology and parameters. In subsequent optimization processes, this initial binary matrix serves as the starting point for the optimization algorithm, avoiding blind or random searches.

[0063] Then, based on the initial binary matrix and the target requirements, an optimization problem is derived, which includes optimization parameters, optimization objectives, and the distribution of the solution space. Finally, key performance indicators and optimization algorithms are obtained based on the optimization problem. The optimization algorithm iteratively searches based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology. In this embodiment, the large language model generates an initial binary matrix based on the target requirements and physical constraints of the matching circuit, providing a high-quality initial starting point for subsequent optimization design, saving operation time and improving efficiency. Subsequently, key performance indicators are determined based on the optimization problem, and a suitable optimization algorithm is selected. Finally, the optimization algorithm iterates continuously based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology and achieving efficient global optimization.

[0064] Below, we will combine Figure 1 The design and optimization method of pixelated matching circuit based on a large language model in this embodiment are described in detail.

[0065] First, step S10 is executed to obtain the target requirements and physical constraints of the matching circuit. Specifically, obtaining the target requirements and physical constraints of the matching circuit includes the following steps: performing simulation analysis on the matching circuit, obtaining simulation results, confirming the target requirements of the matching circuit based on the simulation results; determining the area of ​​the matching circuit and the metal layer in which the matching circuit is located, and obtaining the physical constraints of the matching circuit. In this embodiment, a CMOS PA operating at 28-34 GHz is used as an example.

[0066] The target requirements for the matching circuit are determined by performing load-pull and source-pull simulation analyses to identify its optimal performance point at the target operating frequency and power level. Specifically, load-pull simulation is used to determine the optimal load impedance, while source-pull simulation is used to determine the optimal source impedance. By combining these two simulation analyses, the matching circuit can achieve its optimal performance state at the set frequency and power. Then, based on the simulation results, the target requirements that the matching circuit needs to achieve are confirmed.

[0067] In this embodiment, the target requirements specifically include input matching network targets, output matching network targets, key performance indicators, and passive device constraints.

[0068] For an input-matched network target to achieve maximum power transfer, the input impedance of the input-matched network target is... It should be the input impedance of the PA die. The signal source impedance is the conjugate of the signal source impedance. It follows the maximum power transfer theorem, which states that when the load impedance and the signal source impedance are conjugate complex numbers (i.e., the resistance parts are equal and the reactance parts are equal in value but opposite in sign), the signal source can transfer the maximum theoretical power to the load, thereby improving the power amplifier's energy conversion efficiency and output power performance.

[0069] For the output matching network target, the output port impedance The system standard impedance (typically 50Ω) should be transformed to the optimal load impedance of the PA die at its maximum gain, power, or efficiency point. Its essence is to achieve impedance matching, ensuring that signal energy is efficiently transmitted from the chip to the subsequent system, while ensuring that the PA operates at the preset optimal performance point.

[0070] The purpose of limiting key performance indicators includes the maximum gain (MaxGain) and output power within a specific frequency band. Power-added efficiency (PAE) and out-of-band rejection, etc. When optimizing the matching circuit, the target performance to be optimized needs to be clearly defined. Maximum gain (MaxGain) is the upper limit of the system's ability to amplify the input signal within a specific frequency band. Output power ( The signal power output of a system is the amount of power it can provide. Power-added efficiency (PAE) measures a system's ability to convert DC input power into RF output power. Out-of-band rejection refers to the ability to attenuate unwanted signals outside the target frequency band, ensuring that the system minimizes interference to other frequency bands during operation.

[0071] Passive component constraints refer to setting inductance values ​​or quality factors as reference targets or constraints if the design includes a defined inductor or capacitor structure (transformer). These constraints ensure that passive components match the overall system performance, preventing circuit performance degradation due to substandard component parameters.

[0072] In addition, load traction simulation is required for the matching circuit. Load traction simulation changes the load impedance of the system and measures key parameters such as output power, efficiency, and gain of the circuit under different load conditions, thereby finding the optimal load impedance point and guiding the design and optimization of the matching circuit.

[0073] Based on the above simulation results, the target requirements of the matching circuit can be confirmed, providing specific design parameters for the subsequent design of the matching circuit.

[0074] Furthermore, step S10 also requires obtaining the physical constraints of the matching circuit, determining the area of ​​the matching circuit and the metal layer on which it resides, thus obtaining the physical constraints of the matching circuit. These physical constraints ensure that the matching circuit meets the corresponding electrical performance requirements, ensuring the manufacturability of the design. Subsequent placement and routing of the matching circuit can then be more targeted to ensure the feasibility and reliability of the final design.

[0075] Next, step S20 is executed to generate an initial topology based on the target requirements and physical constraints. Parameters of the initial topology are then estimated to obtain an initial binary matrix constrained by the initial topology and its parameters. For example... Figure 2 As shown, the specific steps include: S21, the large language model generates an initial topology based on the target requirements and physical constraints; S22, the initial topology is used to estimate parameters to obtain key physical parameters; S23, an initial binary matrix is ​​generated based on the initial topology and key physical parameter constraints.

[0076] Specifically, the large language model will call its knowledge base to generate an initial topology based on the target requirements and physical constraints. The initial topology is a classic initial topology (such as a transformer or LC matching network), that is, the connection method and layout framework of each component.

[0077] Subsequently, the large language model calculates key physical parameters for the recommended initial topology, such as the transformer's linewidth W, number of turns N, and spacing D. The linewidth W defines the cell size of the pixelated mesh. The number of turns N and the topology can be pre-defined with some pixels fixed at 1 in the binary matrix, forming the topological skeleton (e.g., an overpass structure). The spacing D can be pre-defined with some pixels fixed at 0 in the binary matrix, forming isolation zones between the windings.

[0078] Finally, an initial binary matrix is ​​constructed based on the initial topology and key physical parameters. The initial topology and key physical parameters are used as constraints to construct the initial binary matrix. It should be noted that the initial binary matrix consists of a grid of pixels composed of 0s and 1s.

[0079] It should be noted that step S20 combines the relevant parameters of the target requirements and physical constraints to generate an initial binary matrix that conforms to engineering experience through a large language model. The generated initial binary matrix will serve as the starting point for subsequent optimization algorithms, rather than a blind or random search, thus providing a reliable foundation for subsequent optimization.

[0080] Then, step S30 is executed to obtain the optimization problem based on the initial binary matrix and the target requirements; wherein, the optimization problem includes optimization parameters, optimization objectives, and the distribution of the solution space. In this embodiment, it is necessary to obtain the optimization problem based on the initial binary matrix and the target requirements, which includes: analyzing the initial binary matrix to identify the unfixed pixels in the initial binary matrix, and obtaining optimization parameters based on the unfixed pixels; analyzing the target requirements to obtain the optimization objective; and analyzing the optimization parameters and the optimization objective to confirm the distribution of the solution space.

[0081] Specifically, the optimization parameters are obtained by analyzing the initial binary matrix. Since the initial binary matrix consists of a grid of 0s and 1s, the unfixed pixels represent adjustable areas in the matching circuit design. By analyzing these unfixed pixels, their potential role and impact on the overall circuit design can be understood. For example, some unfixed pixels may be located on critical signal transmission paths, and their adjustment may directly affect circuit performance. Other unfixed pixels may be located in more peripheral or non-critical areas, with a relatively smaller impact on circuit performance.

[0082] The optimization objective is derived from the analysis of target requirements. These requirements include input matching network objectives, output matching network objectives, key performance indicators, and passive component constraints. Specifically, the input matching network objective involves impedance matching of the signal source, ensuring that the signal source can effectively transfer power to the matching circuit, reducing reflections and losses. The output matching network objective focuses on impedance matching at the load end to maximize power transfer efficiency and signal quality at the load end. Key performance indicators include maximum gain (MaxGain) within a specific frequency band, output power (… Performance metrics such as power-added efficiency (PAE) and out-of-band rejection directly reflect the performance of the matching circuit. Passive component constraints refer to the actual physical limitations that need to be considered during the design process, such as the size, capacitance, and inductance range of passive components like capacitors and inductors, as well as their layout and interconnection requirements. Analyzing the target requirements yields the optimization objectives.

[0083] More specifically, the optimization objective refers to minimizing multiple This refers to the difference between actual performance metrics and true performance metrics. For the optimization objective, the optimization objective is the core of the optimization problem, guiding the subsequent optimization process.

[0084] In this embodiment, it is also necessary to analyze the optimization parameters and optimization objectives to confirm the distribution of the solution space. Specifically, confirming the distribution of the solution space is based on the designer's experience. Confirming the distribution of the solution space aims to understand all possible parameter combinations and their corresponding performance, representing the set of all possible solutions for a specific problem. Here, it is necessary to confirm whether the solution space is sparse. A sparse space means that effective or feasible solutions account for a small percentage of the entire solution space, with most solutions being infeasible or of poor quality. Therefore, designers need to use their professional knowledge and experience to narrow down the search scope and improve design efficiency. It should be noted that confirming the distribution of the solution space is a crucial step in solving the optimization problem, directly affecting the accuracy and efficiency of subsequent design.

[0085] Finally, step S40 is executed. Based on the optimization problem, key performance indicators and an optimization algorithm are obtained. The optimization algorithm iteratively searches based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology. For example... Figure 3 As shown, the specific steps include: S41, confirming the attributes of the optimization problem and selecting an optimization algorithm based on the attributes; S42, generating an impedance matching circuit and electromagnetic topology corresponding to the target requirements based on the optimization objective, and confirming the physical size parameters required for the impedance matching circuit and electromagnetic topology; S43, performing simulation analysis on the physical size parameters to obtain the key performance indicators corresponding to the physical size parameters; S44, performing iterative search in the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology.

[0086] Specifically, in step S40, the attributes of the optimization problem need to be determined first. For the optimization parameters, it needs to be determined whether they are high-dimensional. For the optimization objectives, it needs to be determined how many objectives there are and whether it is a multi-objective problem. For the distribution of the solution space, it needs to be confirmed whether it is a sparse space. After confirming the attributes of the optimization problem, the large language model will select the appropriate optimization algorithm based on these attributes.

[0087] Next, the large language model will generate impedance matching circuits and electromagnetic topologies corresponding to the target requirements based on the optimization objective, and confirm the physical size parameters required for the impedance matching circuits and electromagnetic topologies. Specifically, the large language model will call upon its internal knowledge base on microwave electrical design to generate the physical size parameters of the impedance matching circuits and electromagnetic topologies corresponding to the target requirements.

[0088] Subsequently, simulation analysis is performed on the physical dimension parameters to derive the corresponding key performance indicators (KPIs). Before this, the physical dimension parameters need to be passed into a script template, which generates a new, simulable script. The generated script is then transferred to the simulation automation packager, which launches the simulation software, executes the script, and automatically parses the simulation logs or output files to extract the KPIs. In this embodiment, the simulation software includes ADS and Cadence Virtuoso, and the KPIs include parameters such as S-parameters, gain, and efficiency.

[0089] Finally, based on key performance indicators, an iterative search is performed in the optimization algorithm to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology.

[0090] Specifically, this embodiment establishes an interaction interface between an automated process and a large language model. The automated process converts the knowledge and experience described in natural language by the large language model into a machine-recognizable scripting language. The automated process includes a simulator and a compiler.

[0091] In this embodiment, the automated process receives key performance indicators and selected optimization algorithms from a large language model. The simulator then executes the simulation task corresponding to the key performance indicators. The compiler compares the key performance indicators with the optimization objective to determine if adjustments to the design parameters are needed. If adjustments are required, the compiler generates new design parameters and passes them to the large language model via an interactive interface. The large language model then generates new design schemes based on these new parameters, repeating this process until the optimal solution satisfying the optimization objective is found. This close collaboration between the automated process and the large language model enables rapid iteration and optimization of design parameters, significantly improving the efficiency and accuracy of pixelated matching circuit design and optimization. Ultimately, the resulting optimal pixelated topology not only meets performance requirements but also offers advantages in cost and size, providing strong support for practical applications.

[0092] The following example uses a CMOS PA operating at 28-34 GHz.

[0093] First, in step S10, a load-pull simulation of the CMOS PA is performed to determine the input and output impedance values ​​of its input matching circuit under the target output power: (45 + j*9) Ω and (6 + j*60) Ω, respectively; the input and output impedance values ​​of the inter-stage matching circuit: (11 + j*19) Ω and (30 + j*13) Ω, respectively; and the input and output impedance values ​​of the output matching circuit: (6.2 + j*35) Ω and (45 + j*9) Ω, respectively. Therefore, the core objective determined in step S10 is to design three passive networks at a frequency of 28-34 GHz to achieve the target impedance values ​​of the six ports for the circuit.

[0094] Then, step S20 is executed, where the large language model generates an initial topology based on the target requirements and physical constraints, performs parameter estimation on the initial topology, and obtains an initial binary matrix constrained by the initial topology and parameters.

[0095] Here, the specific instructions from the large language model are: Design an output matching network for a 28-34GHz PA. The input and output impedance values ​​of the input matching circuit are (45+j*9)Ω and (6+j*60)Ω, respectively. The matching circuit is based on 65nm CMOS technology and distributed across layers M8 and M9. Please fully utilize the internal microwave circuit design knowledge base to recommend one or more classic initial topologies, such as transformers or LC networks, and estimate the key physical parameters of the recommended topologies.

[0096] After analyzing the large language model, a differential transformer structure was recommended, and key initial parameters were estimated: M8 layer linewidth W = 12μm, M8 layer turns N = 1, M9 layer linewidth W = 10μm, M9 layer turns N = 2. Based on this, the pixelated grid cell size of M8 layer was defined as 12μm x 12μm, and the pixelated grid cell size of M9 layer was defined as 10μm x 10μm. Over an area of ​​120μm x 150μm, M8 layer formed a 10x6 initial binary matrix, and M9 layer formed a 12x8 initial binary matrix. Based on the basic form of a 2-turn transformer, a bridge structure between the primary and secondary coils was pre-defined in the M9 matrix and connected via Via. Pixels between coils were fixed to 0 to ensure spacing. Finally, a rough transformer topology was formed as the starting point for optimization.

[0097] Design an output matching network for a 28-34GHz power amplifier (PA). The input and output impedances of the interstage matching circuit are (11+j*19)Ω and (30+j*13)Ω, respectively. The matching circuit is based on a 65nm CMOS process and is distributed across layers M8 and M9. Please fully utilize the internal microwave circuit design knowledge base to recommend one or more classic initial topologies, such as transformers or LC networks, and estimate the key physical parameters of the recommended topologies.

[0098] After large-scale language model analysis, a transformer structure was recommended, and the initial parameters were estimated as follows: M8 layer linewidth W = 10μm, M8 layer turns N = 2, M9 layer linewidth W = 8μm, M9 layer turns N = 1. Based on this, the pixelated grid cell size of M8 layer was defined as 10μm x 10μm, and the pixelated grid cell size of M9 layer was defined as 8μm x 8μm. On an area of ​​120μm x 150μm, M8 layer formed a 12x8 initial binary matrix, and M9 layer formed a 15x9 initial binary matrix. Based on the basic shape of a 2-turn transformer, a bridge structure between the primary and secondary coils was pre-defined in the M8 matrix and connected via Via. Pixels between coils were fixed to 0 to ensure spacing. Finally, a rough transformer topology was formed as the starting point for optimization.

[0099] Design an output matching network for a 28-34GHz power supply (PA). The input and output impedances of the matching circuit are (6.2 + j * 35) Ω and (45 + j * 9) Ω, respectively. The matching circuit is based on a 65nm CMOS process and is distributed across layers M8 and M9. Please utilize the internal microwave circuit design knowledge base to recommend one or more classic initial topologies, such as transformers or LC networks, and estimate the key physical parameters of the recommended topologies.

[0100] After analyzing the large language model, a transformer structure was recommended, and the initial parameters were estimated as follows: M8 layer line width W = 10μm, M8 layer number of turns N = 1, M9 layer line width W = 8μm, M9 layer number of turns N = 1.

[0101] Based on this: the pixelated grid cell size of layer M8 is defined as 10μm x 10μm, and the pixelated grid cell size of layer M9 is defined as 8μm x 8μm. Over an area of ​​120μm x 150μm, layer M8 forms an initial 12x8 binary matrix, and layer M9 forms an initial 15x9 binary matrix. Based on the fundamental structure of a single-turn transformer, no constraints are imposed on the electromagnetic topology.

[0102] Then, steps S30 and S40 are executed to obtain the optimization problem based on the initial binary matrix and the target requirements. Key performance indicators and an optimization algorithm are derived from the optimization problem. The optimization algorithm is iteratively searched based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating the optimal pixelated topology. Following the specific steps described in Example 1, further processing of the initial binary matrix, etc., can generate the optimal pixelated topology. The optimal pixelated topology generated based on the above example is shown below.

[0103] Input matching:

[0104] M8: M9:

[0105] Inter-level matching:

[0106] M8: M9:

[0107] Output matching:

[0108] M8: M9: .

[0109] The embodiment is merely a specific example and does not indicate that this is the only way to implement the present invention.

[0110] Example 2:

[0111] like Figure 4 As shown, the present invention also provides a pixel-based matching circuit design and optimization processing device based on a large language model, comprising:

[0112] Obtain module S100 to acquire the target requirements and physical constraints of the matching circuit;

[0113] The generation module S200 generates an initial topology based on the target requirements and the physical constraints, performs parameter estimation on the initial topology, and obtains an initial binary matrix constrained by the initial topology and the parameters.

[0114] The confirmation module S300 obtains an optimization problem based on the initial binary matrix and the target requirement; wherein, the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space;

[0115] The optimization module S400 obtains key performance indicators and optimization algorithms based on the optimization problem, and iteratively searches the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

[0116] Since the pixel-based matching circuit design and optimization processing device based on a large language model described in this embodiment is the same device used to implement the pixel-based matching circuit design and optimization method based on a large language model in Embodiment 1 of this application, those skilled in the art can understand the specific implementation and various variations of the pixel-based matching circuit design and optimization processing device based on a large language model in this embodiment based on the pixel-based matching circuit design and optimization method described in Embodiment 1 of this application. Therefore, how this pixel-based matching circuit design and optimization processing device based on a large language model implements the method in Embodiment 1 of this application will not be described in detail here. Any device used by those skilled in the art to implement the pixel-based matching circuit design and optimization method based on a large language model in Embodiment 1 of this application falls within the scope of protection of this application.

[0117] Example 3:

[0118] Based on the same inventive concept, the third embodiment of the present invention also provides a terminal device, such as... Figure 5 As shown, it includes one or more processors 301 and a memory 302; wherein, the memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processors perform the features / steps of the pixel-matching circuit design and optimization method based on a large language model as described in Embodiment 1.

[0119] Those skilled in the art will understand that all or part of the features / steps of the above-described method embodiments can be implemented by methods, data processing systems, or computer programs. These features may be implemented without hardware, entirely in software, or in a combination of hardware and software. The aforementioned computer program may be stored in one or more computer-readable storage media. When the computer program is executed (e.g., by a processor), it performs the steps of the above-described embodiments of the pixel-based matching circuit design and optimization method based on a large language model.

[0120] Example 4:

[0121] Based on the same inventive concept, the fourth embodiment of the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the methods of the pixel-based matching circuit design and optimization method based on a large language model described in the first embodiment above.

[0122] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A pixel-based matching circuit design and optimization method based on a large language model, characterized in that, include: Obtain the target requirements and physical constraints of the matching circuit; An initial topology is generated based on the target requirements and the physical constraints. The parameters of the initial topology are estimated to obtain an initial binary matrix that is constrained by the initial topology and the estimated parameters. An optimization problem is derived based on the initial binary matrix and the target requirement; wherein, the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space; Based on the optimization problem, key performance indicators and optimization algorithms are obtained. The optimization algorithm is iteratively searched according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology. The optimization problem derived based on the initial binary matrix and the target requirement includes: analyzing the initial binary matrix to identify unfixed pixels and obtaining the optimization parameters based on the unfixed pixels; analyzing the target requirement to obtain the optimization objective; and analyzing the optimization parameters and the optimization objective to confirm the distribution of the solution space. The process of obtaining key performance indicators and optimization algorithms based on the optimization problem, and iteratively searching within the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem and generate the optimal pixelated topology includes: identifying the attributes of the optimization problem; selecting an optimization algorithm based on the attributes of the optimization problem; generating an impedance matching circuit and electromagnetic topology structure corresponding to the target requirements based on the optimization objective; identifying the physical size parameters required for the impedance matching circuit and electromagnetic topology structure; performing simulation analysis on the physical size parameters to obtain the key performance indicators corresponding to the physical size parameters; and iteratively searching within the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem and generate the optimal pixelated topology.

2. The pixel-based matching circuit design and optimization method based on a large language model according to claim 1, characterized in that, The confirmation of the attributes of the optimization problem includes: Confirm whether the properties of the optimization parameters are in a high-dimensional discrete variable space; Confirm the number of the optimization objectives; Confirm whether the distribution of the solution space is sparse.

3. The pixel-based matching circuit design and optimization method based on a large language model according to claim 1, characterized in that, The process of generating an initial topology based on the target requirements and physical constraints, estimating the parameters of the initial topology, and obtaining an initial binary matrix constrained by both the initial topology and the estimated parameters includes: The large language model generates an initial topology based on the target requirements and the physical constraints; The initial topology is used to estimate parameters to obtain key physical parameters; Based on the common constraints of the initial topology and the key physical parameters, an initial binary matrix is ​​obtained.

4. The pixel-based matching circuit design and optimization method based on a large language model according to claim 1, characterized in that, The target requirements and physical constraints for obtaining the matching circuit include: The matching circuit is simulated and analyzed to obtain simulation results, and the target requirements of the matching circuit are confirmed based on the simulation results. The area of ​​the matching circuit and the metal layer in which the matching circuit is located are determined to obtain the physical constraints of the matching circuit.

5. The pixel-based matching circuit design and optimization method based on a large language model according to claim 4, characterized in that, In the process of performing simulation analysis on the matching circuit, obtaining simulation results, and confirming the target requirements of the matching circuit based on the simulation results, the simulation analysis includes load-driven simulation analysis and source-driven simulation analysis. The target requirements include input matching network targets, output matching network targets, key performance indicators, and passive device constraints.

6. A pixel-based matching circuit design and optimization processing device based on a large language model, characterized in that, The pixel-based matching circuit design and optimization method based on a large language model as described in any one of claims 1-5 includes: The acquisition module obtains the target requirements and physical constraints of the matching circuit. The generation module generates an initial topology based on the target requirements and the physical constraints, performs parameter estimation on the initial topology, and obtains an initial binary matrix constrained by the initial topology and the estimated parameters. The confirmation module derives an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objective, and the distribution of the solution space; The optimization module obtains key performance indicators and optimization algorithms based on the optimization problem, and iteratively searches the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

7. A terminal device, characterized in that, include: One or more processors and memory; The memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processors perform the steps of the pixel-based matching circuit design and optimization method based on a large language model as described in any one of claims 1-5.

8. A computer-readable storage medium storing a computer program thereon, characterized in that, When executed by the processor, the program implements the steps of the pixel-based matching circuit design and optimization method based on a large language model as described in any one of claims 1-5.

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