A chip verification method, device, medium and program product

Abstract

The application discloses a chip verification method, device, medium and program product, and relates to the field of chip verification, and comprises the following steps: constructing an initial directed graph based on each component module of a to-be-tested chip and multi-level function division of each component module; setting weights for directed edges in the initial directed graph to obtain a target directed graph; the weight of a first directed edge in the target directed graph is zero, and the sum of the weights of second directed edges corresponding to the same parent vertex is a preset value; the first directed edge comprises directed edges for connecting different component modules; the second directed edge is other directed edge except the first directed edge in the target directed graph; searching for corresponding paths from the target directed graph based on preset verification requirements to construct a verification target set, and realizing verification of the to-be-tested chip. The application constructs a weight directed graph for the to-be-tested chip, so that the chip is verified purposefully and selectively, the efficiency and flexibility of chip verification are improved, and the process of putting the chip into mass production and market application is accelerated.

Description

Technical Field

[0001] This invention relates to the field of chip verification, and in particular to a chip verification method, apparatus, medium, and program product. Background Technology

[0002] In IC (Integrated Circuit) design, Bring Up (BU) is the process of powering on a chip for the first time after production and performing functional verification and debugging. This process is a crucial transition stage from theoretical design to practical application, primarily ensuring that the chip functions correctly according to design specifications. Bring Up is a critical step in chip development; it not only verifies the correctness of the hardware design but also ensures seamless integration of hardware and software. A successful Bring Up is a prerequisite for the chip to smoothly enter mass production and market application. Currently, the Bring Up stage typically involves full-coverage testing of all chip functions, which is extremely time-consuming and resource-intensive, and may affect the chip's progress towards mass production and market application.

[0003] It is evident that, during the Bring Up phase, how to achieve targeted and selective verification of the chip without having to perform full-coverage testing of all its functions is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a chip verification method, device, medium, and program product. By constructing a weighted directed graph of the chip under test, targeted and selective chip verification can be achieved, improving the efficiency and flexibility of chip verification, thereby accelerating the process of chip entering mass production and market application. The specific solution is as follows.

[0005] In a first aspect, the present invention provides a chip verification method, comprising:

[0006] Based on the components of the chip under test and the multi-level functional division of each component, an initial directed graph is constructed.

[0007] Weights are assigned to the directed edges in the initial directed graph to obtain the target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes directed edges used to connect different component modules; the second directed edge is other directed edges in the target directed graph besides the first directed edge.

[0008] Based on the preset verification requirements, the corresponding path is searched in the target directed graph, and a verification target set is constructed according to the corresponding path to verify the chip under test.

[0009] Optionally, based on the constituent modules of the chip under test and the multi-level functional partitioning of each constituent module, an initial directed graph is constructed, including:

[0010] Based on the multi-level functional division of the constituent modules, the constituent modules are classified into multi-level categories to obtain multi-level classification results;

[0011] Based on the multi-level classification results of each component module, the vertices used to construct the initial directed graph are determined;

[0012] Using preset connection rules, the vertices used to construct the initial directed graph are sequentially connected to obtain the initial directed graph;

[0013] The preset connection rules are constructed based on the order of use of each component module and the hierarchical relationship of each vertex.

[0014] Optionally, the component module includes an input channel; the multi-level classification results of the input channel include the first-level classification results of the input channel and other level classification results;

[0015] The first-level classification result of the input channel includes at least one input interface, and different input interfaces are used to receive input information from different sources;

[0016] Other hierarchical classification results for the input channel include several input interfaces obtained by classifying the previous level classification results of the input channel based on the first classification reference information;

[0017] The first category of reference information includes any one or a combination of the transmission line type, information type, and sender of the input information.

[0018] Optionally, the component module includes an output channel; the multi-level classification results of the output channel include the first-level classification results and other level classification results of the output channel;

[0019] The first-level classification result of the output channel includes at least one output interface, and different output interfaces are used to output different types of output information;

[0020] Other hierarchical classification results of the output channel include several output interfaces obtained after classifying the previous level classification results of the output channel based on the second classification reference information;

[0021] The second category of reference information includes any one or a combination of the transmission line type, information type, and receiver of the output information.

[0022] Optionally, the constituent modules include a configuration module, and the multi-level classification results of the configuration module include the first-level classification results of the configuration module and other level classification results;

[0023] The first-level classification result of the configuration module is the result obtained by classifying the configuration functions of the configuration module according to the parameter type of the configuration parameters; the first-level classification result of the configuration module includes the first configuration function about data parameters, the second configuration function about selection parameters, and the third configuration function about state machine parameters; the selection parameters are used to specify the direction of the control branch in the chip;

[0024] The other hierarchical classification results of the configuration module are obtained by classifying the previous level classification results of the configuration module based on the third classification reference information;

[0025] The third category of reference information includes the parameter type and / or function used for configuration parameters.

[0026] Optionally, using preset connection rules, the vertices used to construct the initial directed graph are sequentially connected to obtain the initial directed graph, including:

[0027] Using the first vertex determined by the multi-level classification results based on the configuration module, a subgraph is constructed for each configuration function; each configuration function includes a first configuration function, a second configuration function, and a third configuration function.

[0028] Using preset connection rules and the order in which each configuration function is used, each subgraph and the second vertex determined based on the multi-level classification results of the input and output channels are sequentially connected to obtain the initial directed graph.

[0029] Optionally, using the first vertex determined by the multi-level classification results based on the configuration module, a subgraph is constructed for each configuration function, including:

[0030] The vertex in the first vertex that corresponds to any configuration function is determined as the starting vertex; any configuration function is any one of the configuration functions.

[0031] According to the hierarchical relationship of each vertex, the starting vertex, intermediate vertices and newly added return vertices are connected sequentially to construct a subgraph corresponding to any configuration function;

[0032] Among them, the middle vertex is the vertex in the first vertex that corresponds to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after performing multi-level classification on any configuration function; the return vertex represents the path returning to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

[0033] Optionally, the first directed edge may also include directed edges in the target directed graph that connect to the returned vertex.

[0034] Optionally, the process of setting the weight of the second directed edge corresponding to the same parent vertex includes:

[0035] Based on the importance of each child vertex corresponding to the same parent vertex, weights are assigned to the second directed edges between the same parent vertex and each child vertex, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

[0036] Optionally, based on preset verification requirements, a corresponding path can be searched from the target directed graph, including:

[0037] Search the target directed graph for the corresponding path with the first preset vertex as the starting point, the second preset vertex as the ending point, and the path weights satisfying the preset weight conditions.

[0038] Optional, the path weight determination process includes:

[0039] The path weight of a given path is determined by summing the weights of all directed edges in that path.

[0040] Optionally, the preset weight conditions include any one or a combination of the following: the path weight is greater than the first preset weight threshold, the path weight is less than the second preset weight threshold, and the path weight is within the preset weight range.

[0041] In a second aspect, the present invention provides an electronic device, comprising:

[0042] Memory, used to store computer programs;

[0043] A processor is used to execute a computer program to implement the steps of the aforementioned chip verification method.

[0044] Thirdly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned chip verification method.

[0045] Fourthly, the present invention provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned chip verification method.

[0046] In this invention, an initial directed graph is constructed based on the constituent modules of the chip under test and the multi-level functional division of each constituent module; weights are set for the directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes directed edges used to connect different constituent modules; the second directed edge is other directed edges in the target directed graph besides the first directed edge; based on preset verification requirements, corresponding paths are searched from the target directed graph, and a verification target set is constructed according to the corresponding paths to verify the chip under test.

[0047] Beneficial Effects: This invention constructs an initial directed graph based on the constituent modules of the chip under test and the multi-level functional division of each module. Weights are then assigned to the directed edges in the initial directed graph according to the rule of zero weight setting for directed edges and the rule that the sum of the weights of directed edges corresponding to the same parent vertex equals a preset value, thus obtaining a target directed graph. Then, according to preset verification requirements, corresponding paths are searched from the target directed graph, and a set of verification targets that meets user needs is constructed based on these paths. This allows for the purposeful and selective selection of verification targets for the chip under test, achieving the verification of the chip. Therefore, compared to performing full-coverage testing of all chip functions during the Bring-Up stage, this invention enables purposeful and selective chip verification, improving the efficiency and flexibility of chip verification, and thus accelerating the process of chip entering mass production and market application. Attached Figure Description

[0048] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A flowchart of a chip verification method provided in an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of a multi-level classification result of an input channel provided in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of a multi-level classification result of an output channel provided in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the multi-level classification results of a configuration module provided in an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of a directed edge weight relationship provided in an embodiment of the present invention;

[0054] Figure 6 A schematic diagram of a weighted directed graph of a chip under test provided in an embodiment of the present invention;

[0055] Figure 7 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0057] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0058] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] Bring-up is a crucial step in chip development. It not only verifies the correctness of the hardware design but also ensures seamless integration of hardware and software. A successful Bring-up is a prerequisite for the chip to smoothly enter mass production and market application. Currently, the Bring-up stage typically involves full-coverage testing of all chip functions, which is very time-consuming and resource-intensive, and may affect the chip's progress towards mass production and market application. To address this, this invention provides a chip verification method that constructs a weighted directed graph of the chip under test, enabling targeted and selective verification of the chip, improving the efficiency and flexibility of chip verification, and thus accelerating the chip's progress towards mass production and market application.

[0060] See Figure 1 As shown, an embodiment of the present invention provides a chip verification method, including:

[0061] Step S11: Based on the components of the chip under test and the multi-level functional division of each component, construct an initial directed graph.

[0062] This invention, from an application development perspective, divides the structure of a chip IP (Intellectual Property, a hardware description language program with specific circuit functions, which is independent of integrated circuit technology and can be ported to different semiconductor processes to produce integrated circuit chips) to obtain the constituent modules of the chip under test. According to the business unit requirements, the multi-level functional division of each constituent module of the chip under test is determined from the category perspective. Then, using the chip functional flow and based on each constituent module of the chip under test and the multi-level functional division of each constituent module, an initial directed graph of the chip under test is constructed.

[0063] Specifically, in this embodiment of the invention, the constituent modules of the chip under test are divided into multi-level functional categories to obtain multi-level classification results; based on the multi-level classification results of each constituent module, the vertices used to construct the initial directed graph are determined; and the vertices used to construct the initial directed graph are sequentially connected using preset connection rules to obtain the initial directed graph.

[0064] The preset connection rules are constructed based on the usage order of each component module and the hierarchical relationship of each vertex. It should be noted that the hierarchical relationship of each vertex corresponds to the multi-level classification results of the component modules.

[0065] According to one specific example, the constituent modules of the chip under test include an input channel, and the multi-level classification results of the input channel include the first-level classification result of the input channel and other-level classification results; specifically, the first-level classification result of the input channel includes at least one input interface, and different input interfaces are used to receive input information from different sources; the other-level classification results of the input channel include several input interfaces obtained after classifying the previous-level classification result of the input channel according to the first classification reference information.

[0066] That is, the second-level classification result of the input channel includes several input interfaces obtained after classifying the first-level classification result of the input channel according to the first classification reference information, the third-level classification result of the input channel includes several input interfaces obtained after classifying the second-level classification result of the input channel according to the first classification reference information, and so on, so that the multi-level classification results of the input channel can be obtained.

[0067] The first category of reference information includes any one or a combination of the transmission line type, information type, and sender of the input information. Of course, it may also include other reference information of the input information, which is not specifically limited here.

[0068] For example, the types of transmission lines for input information include, but are not limited to, AMBA (Advanced Microcontroller Bus Architecture) bus, I2C (Inter-Integrated Circuit) bus, and SPI (Serial Peripheral Interface) bus. The AMBA bus further includes four different types of buses: AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), and AXI (Advanced eXtensible Interface). The types of input information include, but are not limited to, reset information, clock information, debug information, and bus information. The senders of input information include, but are not limited to, clock sources, bus devices, debug devices, and reset devices.

[0069] by Figure 2 For example, based on the first-level classification results of the input channels, the input channels can be divided into the following four types of interfaces according to the different sources of input information: bus input interface, debug input interface, global reset input interface, and clock input interface. That is, these four types of interfaces are used to receive input information from different sources. Among them, the bus input interface, as the most important input source for the chip IP, is the core foundation for the implementation of IP functions, and in current chip designs, the AMBA bus is the mainstream solution; the debug input interface is used for debug access input of the chip IP, and can serve as a direct configuration and testing interface for internal registers and memories of the IP; the global reset input interface is used to perform a global reset of the IP; and the clock input interface is used to provide clock signals to the chip IP, mainly providing a stable timing reference for the internal operation of the chip IP. It should be noted that embodiments of the present invention can further divide the input channels into deeper levels based on the first classification reference information.

[0070] According to another specific example, the constituent modules of the chip under test include output channels, and the multi-level classification results of the output channels include the first-level classification results of the output channels and other-level classification results; specifically, the first-level classification results of the output channels include at least one output interface, and different output interfaces are used to output different types of output information; the other-level classification results of the output channels include several output interfaces obtained after classifying the previous-level classification results of the output channels according to the second classification reference information.

[0071] That is, the second-level classification result of the output channel includes several output interfaces obtained after classifying the first-level classification result of the output channel according to the second classification reference information, the third-level classification result of the output channel includes several output interfaces obtained after classifying the second-level classification result of the output channel according to the second classification reference information, and so on, so that the multi-level classification results of the output channel can be obtained.

[0072] The second category of reference information includes any one or a combination of the transmission line type, information type, and receiver of the output information. Of course, it may also include other reference information of the output information, which is not specifically limited here.

[0073] For example, the transmission line types for output information include, but are not limited to, AMBA bus, PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard), and USB (Universal Serial Bus). The types of output information include, but are not limited to, normal output information and abnormal output information. Normal output information includes debug output information, interrupt output information, and status output information, while abnormal output information includes fatal abnormal output information, correctable abnormal output information, and uncorrectable abnormal output information. The recipients of output information include, but are not limited to, other internal IPs of the chip, external devices of the chip, the interrupt controller of the chip's internal processor, internal registers of the chip, and external registers of the chip.

[0074] by Figure 3 For example, for the first-level classification result of the output channel, the output channel can be divided into two types of interfaces based on the information type of the output information: normal output interface and abnormal output interface. For the second-level classification result of the output channel, the normal output interface can be divided into five types of interfaces based on the second classification reference information: bus output interface, protocol output interface, debug output interface, interrupt output interface, and normal state output interface. Abnormal output interfaces can be divided into three types of interfaces: fatal abnormal output interface, correctable abnormal output interface, and uncorrectable abnormal output interface. It should be noted that, in this embodiment of the invention, the output channel can be further divided into deeper levels based on the second classification reference information.

[0075] The chip IP's internal output interface is used to output data processing results to other IPs within the chip. It typically uses an AMBA bus interface, such as a DMA (Direct Memory Access) controller writing data to RAM (Random Access Memory). The protocol output interface is used to encode data processing results according to the implemented communication protocol and output them externally via chip pins, such as PCIe bus output or USB bus output. The debug output interface is used to output debug trace data within the chip IP. There are various implementation methods; for example, the bus output interface can be used to output debug trace data to a dedicated debug trace unit, or GPIO (General-purpose input / output) can be used to directly output debug trace data to chip pins. The interrupt output interface is used by the chip IP to output important states to the interrupt controller of the internal processor via interrupts. The normal state output interface is used by the chip IP to output important states to internal registers or external global registers for access by other IPs within the chip.

[0076] The interface for fatal exceptions outputs information such as AXI access errors, which directly cause the functional state machine to stop abnormally. Correctable exceptions output information indicates an exception that does not affect the execution of the functional state machine. For example, a register value might be out of bounds, but the IP will correct the error and only indicate a configuration error. The interface for uncorrectable exceptions outputs information that not only indicates an exception but also that the IP cannot correct it, yet the execution of the functional state machine is not affected, but the execution result will show data anomalies. For example, a DMA write operation might indicate a verification error, but the data can still be written, although the written data will not be as expected.

[0077] According to another specific example, the components of the chip under test include a configuration module, and the multi-level classification results of the configuration module include the first-level classification results and other-level classification results. Specifically, the first-level classification results of the configuration module are obtained by classifying the configuration functions of the configuration module according to the parameter types of the configuration parameters. The first-level classification results of the configuration module include the first configuration function regarding data parameters, the second configuration function regarding selection parameters, and the third configuration function regarding state machine parameters. The selection parameters are used to specify the direction of the control branches in the chip. The other-level classification results of the configuration module are obtained by classifying the previous-level classification results of the configuration module according to the third-level classification reference information.

[0078] In other words, the second-level classification result of the configuration module is obtained by classifying the first-level classification result of the configuration module according to the third-level classification reference information, and the third-level classification result of the configuration module is obtained by classifying the second-level classification result of the configuration module according to the third-level classification reference information. And so on, the multi-level classification results of the configuration module can be obtained.

[0079] The third category of reference information includes the parameter type and / or function of the configuration parameters. Of course, it may also include other reference information of the configuration parameters, which are not specifically limited here.

[0080] by Figure 4For example, considering that configuration parameters include data parameters and control parameters, and control parameters include selection parameters and state machine parameters, the first-level classification result of the configuration module can be specifically divided into three categories based on the parameter type: first configuration function related to data parameters, second configuration function related to selection parameters, and third configuration function related to state machine parameters. For the second-level classification result of the configuration module, the first configuration function related to data parameters can be further divided into three categories based on the third classification reference information: configuration function related to parameter ranges, configuration function related to buffer parameters, and configuration function related to clock source parameters. The second configuration function related to selection parameters can be divided into five categories: configuration function related to priority selection, configuration function related to read / write direction selection, configuration function related to channel selection, configuration function related to mode selection, and configuration function related to explicit selection. Finally, the third configuration function related to state machine parameters can be divided into four categories: configuration function related to start / enable, configuration function related to pause, configuration function related to reset, and configuration function related to completion / idle. For the third-level classification results of the configuration module, specifically, based on the third classification reference information, the configuration functions related to parameter ranges can be divided into the following three categories: configuration functions related to random parameters, configuration functions related to boundary parameters, and configuration functions related to branch parameters. The configuration functions related to buffer parameters can be divided into the following three categories: configuration functions related to position parameters, configuration functions related to size parameters, and configuration functions related to full / empty parameters. The configuration functions related to clock source parameters can be divided into the following two categories: configuration functions related to source parameters and configuration functions related to frequency division parameters. It should be noted that, in this embodiment of the invention, the configuration module can be further divided into deeper levels based on the third classification reference information.

[0081] Among them, the data parameters are used to configure the data processing function in the data processing module of the chip under test; the selection parameters are used to specify the direction of the control branch in the chip under test; the state machine parameters are used to configure the functional state machine of the chip under test. The functional state machine is an abstraction of the overall operation control of the chip IP, and does not specifically refer to the specific state machine in the implementation of the IP hardware code. The overall operation control here mainly refers to the core external output function of the chip IP, such as the read data and write data output function of the DMA controller, and the IO (Input / Output) read and write output of the SSD (Solid State Disk).

[0082] Data parameters are further divided into parameter ranges, buffer parameters, and clock source parameters. Parameter ranges are abstractions of data processing function configurations with range-sized characteristics, such as the number of IP channels and queue depth. Based on the characteristics of parameter ranges, they can be simplified into three categories: random parameters, boundary parameters, and branch parameters. Random parameters and boundary parameters refer to selecting random and boundary values ​​within the parameter range, respectively, while branch parameters refer to the key parameters that change the IP data processing module's path to different branches.

[0083] Buffer parameters are abstractions of the memory area configuration used within a chip IP, such as FIFO (First Input First Output), buffers, and queues. Based on their characteristics, buffer parameters can be simplified into three categories: position parameters, size parameters, and full / empty parameters. Position parameters configure whether the memory area is inside or outside the IP; size parameters configure the size of the memory area used; and full / empty parameters configure the empty, half-full, full, and watermark-related characteristics of the memory area used.

[0084] Clock source parameters are an abstraction of clock input configuration. Based on their characteristics, clock source parameters can be simplified into two categories: source parameters and divider parameters. Source parameters configure which clock tree within the chip the clock originates from; divider parameters configure the operating frequency division of the chip IP.

[0085] Selection parameters are abstractions of functional configurations that specify the direction of control branches. Based on their characteristics, selection parameters can be simplified into five categories: priority selection, read / write direction selection, channel selection, mode selection, and explicit selection. Priority selection specifies the priority or arbitration mode of the control branch; read / write direction selection specifies the destination direction of the IP's data flow, such as the read and write directions of DMA; channel selection specifies the working channel sequence number of multi-channel or multi-engine IPs; mode selection specifies the relevant transmission mode in the data flow; and explicit mode specifies the masking characteristics of relevant status, interrupt, and other indicative parameters.

[0086] In addition, the state machine parameters can be simplified into the following four categories: Start / Enable, Pause, Reset, and Complete / Idle. Among them, Start / Enable is used to control the start / enable of the functional state machine; Pause is used to control the pause of the functional state machine; Reset is used to control the reset of the functional state machine; and Complete / Idle is used to control the termination of the functional state machine, so that the functional state machine is in the Complete / Idle state.

[0087] After determining the vertices for constructing the initial directed graph based on the multi-level classification results of each component module of the chip under test, the first vertex determined based on the multi-level classification results of the configuration module can be used to construct subgraphs for each configuration function. Each configuration function includes a first configuration function, a second configuration function, and a third configuration function. Then, using preset connection rules and the order of use of each configuration function, each subgraph and the second vertex determined based on the multi-level classification results of the input and output channels are sequentially connected to obtain the initial directed graph.

[0088] The multi-level classification results of the configuration module include the first-level classification results and other-level classification results. The first-level classification results of the configuration module include the first configuration function regarding data parameters, the second configuration function regarding selection parameters, and the third configuration function regarding state machine parameters. The other-level classification results of the configuration module are obtained by classifying the previous-level classification results of the configuration module based on the third-level classification reference information. It can also be understood that the other-level classification results of the configuration module include the multi-level classification results of the first configuration function regarding data parameters, the multi-level classification results of the second configuration function regarding selection parameters, and the multi-level classification results of the third configuration function regarding state machine parameters.

[0089] Based on this, the construction process of the corresponding subgraph for any of the first, second, and third configuration functions can specifically include: determining the vertex in the first vertex that corresponds to any configuration function as the starting vertex; sequentially connecting the starting vertex, intermediate vertices, and newly added return vertices according to the hierarchical relationship of each vertex to construct the subgraph corresponding to any configuration function; wherein, the intermediate vertex is the vertex in the first vertex that corresponds to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after performing multi-level classification on any configuration function; the return vertex represents the path returning to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

[0090] After constructing the subgraphs corresponding to the first, second, and third configuration functions, based on the usage order of input channel -> configuration module -> output channel, the usage order of second configuration function -> first configuration function -> third configuration function, and the hierarchical relationship of each vertex, the second vertex determined by the multi-level classification results based on the input channel, the second vertex determined by the multi-level classification results based on the output channel, and each subgraph are sequentially connected to construct the initial directed graph for the chip under test.

[0091] Step S12: Set weights for the directed edges in the initial directed graph to obtain the target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes directed edges used to connect different component modules; the second directed edge is other directed edges in the target directed graph besides the first directed edge.

[0092] In this embodiment of the invention, after constructing the initial directed graph for the chip under test, it is necessary to further set weights for each directed edge in the initial directed graph to convert the initial directed graph into a weighted directed graph, thereby obtaining the target directed graph.

[0093] Specifically, weights are set for each directed edge in the initial directed graph. This includes setting the weights of directed edges connecting different component modules and directed edges connecting to the return vertex in the initial directed graph to zero. That is, the weight of the first directed edge in the target directed graph is zero, and the first directed edge includes not only directed edges connecting different component modules but also directed edges connecting to the return vertex.

[0094] In this way, the present invention proposes a zero-weight setting rule. On the one hand, the directed edges connecting the constituent modules on the necessary path of chip startup and operation are set to zero weight. On the other hand, the directed edges connected to the return vertex are set to zero weight. By setting the directed edges to zero weight, they only serve to connect the paths for forward reasoning of the weighted directed graph.

[0095] Specifically, weights are assigned to each directed edge in the initial directed graph. This includes assigning weights to all directed edges in the initial directed graph except those with a weight of zero, for those edges corresponding to the same parent vertex, such that the sum of the weights of all directed edges corresponding to the same parent vertex equals a preset value. That is, for all directed edges in the target directed graph except the first directed edge (denoted as the second directed edge), the sum of the weights of the second directed edges corresponding to the same parent vertex in the target directed graph equals the preset value.

[0096] According to one example, the process of setting the weight of the second directed edge corresponding to the same parent vertex in the target directed graph may specifically include: setting the weight of the second directed edge between the same parent vertex and each child vertex based on the importance of each child vertex corresponding to the same parent vertex, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

[0097] Specifically, based on the chip composition or function reflected by each child vertex corresponding to the same parent vertex, the importance of each child vertex to chip operation, usage frequency, and the degree of impact on the chip when a fault occurs are considered. The importance of each child vertex is then determined, and the sum of their importance is calculated. The degree ratio of each child vertex is determined based on the ratio of its importance to the sum. This degree ratio is then multiplied by 10 to obtain the weights of the second directed edges between the same parent vertex and its child vertices. For example, assuming the importance of the two child vertices S1 and S2 corresponding to the parent vertex F is 4 and 8 respectively, the sum of their importance is 12. Then, based on the ratio of S1's importance to the sum, the degree ratio of S1 is determined to be 0.33, and the degree ratio of S2 is determined to be 0.67. This degree ratio is then multiplied by 10 to obtain the weights of the second directed edges between the parent vertex F and its two child vertices S1 and S2 as 3.3 and 6.7 respectively.

[0098] Taking a preset value of 10 as an example, such as Figure 5 As shown, vertex F is the parent vertex of vertices S1 and S2, and correspondingly, vertices S1 and S2 are the child vertices of vertex F. Let be the weight of the directed edge between vertex F and vertex S1. Let S be the weight of the directed edge between vertex F and vertex S2, which needs to satisfy... Vertex S1 is the parent vertex of vertices S1W1 and S1W2, and correspondingly, vertices S1W1 and S1W2 are the child vertices of vertex S1. Let S1 be the weight of the directed edge between vertex S1 and vertex S1W1. Let S1 be the weight of the directed edge between vertex S1 and vertex S1W2, which needs to satisfy... Vertex S2 is the parent vertex of vertices S2W1, S2W2, and S2W3; correspondingly, vertices S2W1, S2W2, and S2W3 are the child vertices of vertex S2. Let S2 be the weight of the directed edge between vertex S2 and vertex S2W1. Let S2 be the weight of the directed edge between vertex S2 and vertex S2W2. Let S2 be the weight of the directed edge between vertex S2 and vertex S2W3, which needs to satisfy... .

[0099] Taking a preset value of 10 as an example, and considering that the components of the chip under test include an input channel, a configuration module, and an output channel, a weighted directed graph is constructed for the chip under test according to the steps described above. The final constructed weighted directed graph is shown below. Figure 6 As shown. It should be noted that, Figure 6This is merely one specific example of an embodiment of the present invention, and not the only example; of course, other situations may exist.

[0100] Step S13: Search for the corresponding path from the target directed graph based on the preset verification requirements, and construct the verification target set according to the corresponding path to verify the chip under test.

[0101] In this embodiment of the invention, after constructing the target directed graph for the chip under test, the preset verification requirements input by the user terminal or the preset verification requirements pre-configured are obtained. Then, based on the preset verification requirements, the corresponding path is searched from the target directed graph, and a verification target set is constructed according to the corresponding path, so as to use the verification target set to verify the chip under test.

[0102] The preset verification requirements are verification requirements constructed based on preset vertices and preset weight conditions. Specifically, based on the preset verification requirements, the corresponding path is searched from the target directed graph. The corresponding path can include: searching from the target directed graph for a path with a first preset vertex as the starting point, a second preset vertex as the ending point, and a path weight that satisfies the preset weight condition.

[0103] The process of determining path weights can specifically include: determining the path weight of a given path based on the sum of the weights of all directed edges in that path. For example, if a path is A->B->C, where the weight of the directed edge between A and B is 5 and the weight of the directed edge between B and C is 3, then the path weight of this path is 8.

[0104] In this embodiment of the invention, the preset weight conditions include any one or a combination of several of the following: the path weight is greater than a first preset weight threshold, the path weight is less than a second preset weight threshold, and the path weight is within a preset weight range. The first preset weight threshold, the second preset weight threshold, and the preset weight range can be set according to actual chip verification requirements.

[0105] For example, preset weight conditions can include path weight greater than 8, path weight less than 12, path weight between 8 and 12, or path weight less than 8 or path weight greater than 12, etc., without further examples here.

[0106] Beneficial Effects: This invention constructs an initial directed graph based on the constituent modules of the chip under test and the multi-level functional division of each module. Weights are then assigned to the directed edges in the initial directed graph according to the rule of zero weight setting for directed edges and the rule that the sum of the weights of directed edges corresponding to the same parent vertex equals a preset value, thus obtaining a target directed graph. Then, according to preset verification requirements, corresponding paths are searched from the target directed graph, and a set of verification targets that meets user needs is constructed based on these paths. This allows for the purposeful and selective selection of verification targets for the chip under test, achieving the verification of the chip. Therefore, compared to performing full-coverage testing of all chip functions during the Bring-Up stage, this invention enables purposeful and selective chip verification, improving the efficiency and flexibility of chip verification, and thus accelerating the process of chip entering mass production and market application.

[0107] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 11, at least one memory 12, a power supply 13, a communication interface 14, an input / output interface 15, and a communication bus 16. The memory 12 stores a computer program, which is loaded and executed by the processor 11 to implement the relevant steps in the chip verification method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0108] In this embodiment, the power supply 13 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 14 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 15 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0109] In addition, the memory 12, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 121, computer program 122, etc., and the storage method can be temporary storage or permanent storage.

[0110] The operating system 121 is used to manage and control the various hardware devices on the electronic device and the computer program 122, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the chip verification method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 122 may further include a computer program capable of performing other specific tasks.

[0111] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned disclosed chip verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0112] Furthermore, this application also discloses a computer program product, including a computer program / instructions, wherein the computer program / instructions, when executed by a processor, implement the aforementioned disclosed chip verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0113] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0114] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0115] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0116] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0117] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip verification method, characterized in that, include: Based on the components of the chip under test and the multi-level functional division of each component, an initial directed graph is constructed. Weights are assigned to the directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes directed edges used to connect different component modules; the second directed edge is other directed edges in the target directed graph besides the first directed edge. Based on the preset verification requirements, the corresponding path is searched from the target directed graph, and a verification target set is constructed according to the corresponding path to verify the chip under test. The construction of an initial directed graph based on the constituent modules of the chip under test and the multi-level functional division of each constituent module includes: Based on the multi-level functional division of the constituent modules, the constituent modules are classified in a multi-level manner to obtain multi-level classification results; based on the multi-level classification results of each constituent module, the vertices used to construct the initial directed graph are determined. Using preset connection rules, the vertices used to construct the initial directed graph are sequentially connected to obtain the initial directed graph; wherein, the preset connection rules are rules constructed based on the usage order of each component module and the hierarchical relationship of each vertex; The constituent modules include an input channel, an output channel, and a configuration module; the multi-level classification results of the configuration module include the first-level classification results and other-level classification results of the configuration module; The first-level classification result of the configuration module is the result obtained by classifying the configuration functions of the configuration module according to the parameter type of the configuration parameters; the first-level classification result of the configuration module includes a first configuration function about data parameters, a second configuration function about selection parameters, and a third configuration function about state machine parameters; the selection parameters are used to specify the direction of the control branch in the chip; The other hierarchical classification results of the configuration module are obtained by classifying the previous level classification results of the configuration module according to the third classification reference information; wherein, the third classification reference information includes the parameter type and / or function of the configuration parameters; The step of searching for the corresponding path from the target directed graph based on preset verification requirements includes: Search the target directed graph for the corresponding path with the first preset vertex as the starting point, the second preset vertex as the ending point, and the path weight satisfying the preset weight condition.

2. The chip verification method according to claim 1, characterized in that, The component module includes an input channel; the multi-level classification results of the input channel include the first-level classification results and other-level classification results of the input channel; The first-level classification result of the input channel includes at least one input interface, and different input interfaces are used to receive input information from different sources; Other hierarchical classification results of the input channel include several input interfaces obtained by classifying the previous level classification result of the input channel according to the first classification reference information; The first classification reference information includes any one or a combination of the transmission line type, information type, and sender of the input information.

3. The chip verification method according to claim 2, characterized in that, The component module includes an output channel; the multi-level classification results of the output channel include the first-level classification results and other-level classification results of the output channel; The first-level classification result of the output channel includes at least one output interface, and different output interfaces are used to output different types of output information; Other hierarchical classification results of the output channel include several output interfaces obtained after classifying the previous level classification result of the output channel according to the second classification reference information; The second category of reference information includes any one or a combination of the transmission line type, information type, and receiver of the output information.

4. The chip verification method according to claim 3, characterized in that, The step of sequentially connecting the vertices used to construct the initial directed graph using preset connection rules to obtain the initial directed graph includes: Using the first vertex determined based on the multi-level classification results of the configuration module, a subgraph is constructed for each configuration function; each configuration function includes the first configuration function, the second configuration function, and the third configuration function. Using preset connection rules and the order in which the configuration functions are used, the subgraphs and the second vertices determined based on the multi-level classification results of the input and output channels are sequentially connected to obtain the initial directed graph.

5. The chip verification method according to claim 4, characterized in that, The step of constructing subgraphs for each configuration function using the first vertex determined based on the multi-level classification results of the configuration module includes: The vertex in the first vertex that corresponds to any configuration function is determined as the starting vertex; the any configuration function is any one of the configuration functions. According to the hierarchical relationship of each vertex, the starting vertex, intermediate vertices and newly added return vertices are sequentially connected to construct a subgraph corresponding to any of the configuration functions; Wherein, the intermediate vertex is the vertex in the first vertex that corresponds to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after performing multi-level classification on any configuration function; the return vertex represents the path returning to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

6. The chip verification method according to claim 5, characterized in that, The first directed edge also includes the directed edge in the target directed graph that connects to the returned vertex.

7. The chip verification method according to claim 1, characterized in that, The process of setting the weight of the second directed edge corresponding to the same parent vertex includes: Based on the importance of each child vertex corresponding to the same parent vertex, a weight is set for the second directed edge between the same parent vertex and each child vertex, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

8. The chip verification method according to claim 1, characterized in that, The process of determining path weights includes: The path weight of the corresponding path is determined based on the sum of the weights of each directed edge in the corresponding path.

9. The chip verification method according to claim 8, characterized in that, The preset weight conditions include any one or a combination of the following: the path weight is greater than the first preset weight threshold, the path weight is less than the second preset weight threshold, and the path weight is within the preset weight range.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip verification method as described in any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the chip verification method as described in any one of claims 1 to 9.

12. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the chip verification method according to any one of claims 1 to 9.

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