Chip design performance analysis method and device, related equipment and program

Abstract

The embodiment of the invention provides a chip design performance analysis method and device, related equipment and a program. The performance analysis method for the chip design comprises the following steps: acquiring simulation data of the chip design; the simulation data comprises interaction information obtained after simulation of each design module in different test scenes is finished in the chip design; processing the interaction information to generate a performance test value of each design module in the chip design in each test scene; and comparing the performance test value by using the performance theoretical value in the test scene to obtain a performance analysis result. According to the technical scheme provided by the embodiment of the invention, when the chip design is changed and a topological structure or a transmission protocol of the chip design is changed, the performance analysis program in the simulation process is prevented from being modified, and the modification of the performance analysis program is reduced, so that the time and human resource investment of the performance analysis method of the chip design is reduced, and the efficiency of the chip design is improved. And the efficiency of the chip design performance analysis method is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit technology, and specifically to a performance analysis method, apparatus, related equipment, and program for chip design. Background Art

[0002] In the field of integrated circuit design, chip design and optimization are becoming increasingly important as chip performance continues to improve and functionality becomes increasingly complex. Chip design performance analysis is a key step in evaluating chip performance and reliability before silicon is implemented. However, existing chip design performance analysis methods require extensive modifications to the test environment when chip designs are modified, consuming additional manpower and time. This means that the efficiency of existing chip design performance analysis methods needs to be improved.

[0003] It can be seen that how to provide a technical solution to improve the efficiency of the performance analysis method of chip design has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0004] The embodiments of the present invention provide a chip design performance analysis method, apparatus, related equipment and program to improve the efficiency of the chip design performance analysis method.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a performance analysis method for a chip design, comprising:

[0007] Acquire simulation data of the chip design; the simulation data includes interactive information obtained after simulation of each design module in the chip design under different test scenarios;

[0008] Processing the interaction information to generate performance test values ​​of each design module in the chip design under each test scenario;

[0009] The performance test values ​​are compared with the theoretical performance values ​​under the test scenario to obtain performance analysis results.

[0010] In a second aspect, an embodiment of the present invention provides a performance analysis device for chip design, comprising:

[0011] A data acquisition module is used to obtain simulation data of the chip design; the simulation data includes interactive information obtained after the simulation of each design module in different test scenarios in the chip design;

[0012] A data processing module, configured to process the interaction information and generate performance test values ​​of each design module in the chip design under each test scenario;

[0013] The comparison and analysis module is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the performance analysis method of the chip design as described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present invention provides a storage medium storing a program, which, when executed, implements the performance analysis method for chip design as described in the first aspect.

[0016] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which, when executed, implements the performance analysis method for chip design as described in the first aspect.

[0017] It can be seen that in the performance analysis method of the chip design provided by the embodiment of the present invention, the simulation data of the chip design is first obtained, wherein the simulation data includes the interaction information obtained after the simulation of each design module in the chip design under different test scenarios; then the interaction information is converted into the performance test value of each design module in the chip design under each test scenario, and the performance test value is compared with the theoretical design value of the chip design to complete the performance analysis of the chip design. Since the performance test value of each design module in the chip design is obtained by analyzing the interaction information of each design module obtained in the simulation data, the technical solution provided by the embodiment of the present invention can perform performance test analysis after the chip design simulation is completed, without the need to use a performance analysis program to perform performance analysis during the simulation process of the chip design. In this way, it is possible to avoid modifying the performance analysis program in the simulation process when the chip design changes, resulting in changes in the topology structure or transmission protocol of the chip design, reducing the modification of the performance analysis program, thereby reducing the time and human resource investment in the performance analysis method of the chip design, and improving the efficiency of the performance analysis method of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 It is a schematic diagram of a chip design and testing method.

[0020] Figure 2 This is a flow chart of a chip design performance analysis method provided by an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of a chip design provided by an embodiment of the present invention.

[0022] Figure 4 This is a flowchart of the performance analysis method for chip design provided by an embodiment of the present invention in a first test scenario.

[0023] Figure 5 This is a flowchart of the performance analysis method for chip design provided by an embodiment of the present invention in the second test scenario.

[0024] Figure 6 This is a flowchart of the performance analysis method for chip design provided by an embodiment of the present invention in the third test scenario.

[0025] Figure 7 Schematic diagram of a performance analysis device for chip design provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background technology section, the efficiency of existing chip design performance analysis methods needs to be improved.

[0027] Chip design, for example, involves the design of integrated circuits such as SOCs (System-on-Chip) and ASICs (Application Specific Integrated Circuit). To verify that the chip design meets expectations, simulation verification is required. For example, a verification environment is built and used to verify the chip design, thereby verifying that the chip design functions as expected.

[0028] With the advancement of semiconductor technology, the integration of chip design is becoming increasingly higher, and the operating frequency is constantly increasing. The transmission delay and bandwidth limitation of signals in the circuit have an increasingly significant impact on the performance of chip design. Therefore, through pre-silicon verification and analysis of the bandwidth and delay of chip design, we can accurately understand the performance of chip design in data transmission. This helps to determine whether the chip design can meet its requirements for data processing speed and throughput, thereby discovering the bandwidth bottleneck and potential performance limitations of the chip design, and providing a clear direction for subsequent chip design improvements.

[0029] An existing chip design test method is as follows Figure 1As shown, the method completes the performance verification of the chip design under test (DUT) based on the stimulus module, performance detection module and platform scenario configuration file (CFG) in the verification environment ENV (Environment). The method uses a BFM (Behavior Function Model) device to generate the read and write memory access behavior of each IP core (Intellectual Property Core) in different test scenarios, abstracts the IP core's memory access behavior into a minimum repeatable memory access unit, and then repeatedly sends the minimum memory access unit according to the bandwidth requirement of each IP core; uses a performance indicator statistical model (BFM Master BW / Latency) to calculate the bandwidth, latency, and outstanding (number of pending transactions) of each IP core in a specific scenario, and outputs and prints the data in a log file (log). In this method, the performance indicator statistical model realizes the calculation of average read and write bandwidth, circuit structure delay, average delay, minimum delay and maximum delay within the statistical time window, and also calculates the outstanding trend of different IP cores within the entire time window.

[0030] As can be seen, this method verifies the memory access performance of the chip design to be tested based on BFM. However, based on the above chip design testing method, when the chip design is changed, the verification environment and performance analysis program (i.e., the program that forms the performance detection module) need to be modified; and for any module interface changes in the verification environment, the BFM stimulus module and performance analysis program need to be rewritten, and a large amount of time must be spent on debugging before the performance of the chip design can be analyzed and evaluated again. In addition, when the performance focus to be tested (different test scenarios have different performance focuses) changes, for example, when the performance focus changes to the internal state of the IP core, the page hit of DDR (Double Data Rate, DDR memory) during memory access, etc., not only does it need to be rewritten in the verification environment, but it also needs to rerun the modified simulation test case, which takes even longer.

[0031] Existing pre-silicon methods for analyzing chip design transmission bandwidth and delay can also view the bandwidth and delay of modules of interest by directly observing the waveforms generated by simulation. However, when it is necessary to understand the delay bandwidth of different design modules in the chip design, it is time-consuming and laborious. When the bandwidth fails to meet expectations, it is difficult to determine the bottleneck of the chip design.

[0032] It can be seen that in the existing chip design performance analysis method, when the chip design changes, a large number of modifications to the test environment are required, which consumes additional manpower and time resources. In other words, the efficiency of the existing chip design performance analysis method needs to be improved.

[0033] To solve the above problems, an embodiment of the present invention provides a performance analysis method for chip design, so as to improve the efficiency of the performance analysis method for chip design.

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] Figure 2 This is a flow chart of a performance analysis method for chip design provided by an embodiment of the present invention. Figure 2 The performance analysis method of chip design provided by the present invention includes the following steps.

[0036] Step S10: Acquire simulation data of the chip design; the simulation data includes interactive information obtained after simulation of each design module in the chip design under different test scenarios.

[0037] The behavior of each design module will change under different test scenarios. Therefore, after the simulation is completed in each test scenario, the interaction information obtained can reflect the behavior of each design module in the test scenario, which can be used to verify whether each design module works correctly in the test scenario according to the design specifications.

[0038] The interaction information can provide performance data of the design modules, such as response time, processing speed, data throughput, etc. For example, in signal integrity (SI) simulation, the signal transmission performance between various design modules can be evaluated, including high-frequency attenuation, crosstalk and other issues.

[0039] In order to avoid performance analysis during the chip design simulation process, the embodiment of the present invention obtains the interactive information after the simulation is completed, so as to facilitate the subsequent analysis of the interactive information and obtain the performance analysis results, thereby avoiding the increase in time consumption due to the adjustment of the performance analysis program when using the performance analysis program for verification.

[0040] In one embodiment, step S10 may include:

[0041] Determine a test scenario; generate a test vector based on the test scenario; perform simulation testing on the chip design according to the test vector to obtain simulation data.

[0042] In the performance analysis of the chip design, the chip design may be simulated and tested based on test vectors. The test vectors are designed based on different test scenarios to meet the test requirements of different test scenarios.

[0043] For example, when the test scenario is a scenario of testing the memory access performance of a design module, after generating a test vector based on the test scenario, the simulation test performed on the chip design to be tested includes a test of the memory access operation to obtain the simulation data formed after the test is completed, which facilitates the subsequent analysis of whether the memory access performance of the design module of the chip design meets the theoretical performance value.

[0044] For ease of explanation, the following is a schematic diagram of a chip design provided in an embodiment of the present invention. Figure 3 The chip design includes multiple design modules: a processor core CORE, a data transmission unit DF (Data Fabric), and a memory DDR. When the test scenario is to test the memory access performance of the design module, the process of simulating the chip design using test vectors can be as follows: the processor core CORE sends a data read request to the memory DDR, the data read request is transmitted to the memory DDR through at least one submodule (Module) in the data transmission unit DF, and the memory DDR returns the data corresponding to the data read request to the processor core CORE through the data transmission unit DF.

[0045] In the above-mentioned simulation test process example, the processor core CORE, the data transfer unit DF and the memory DDR interact continuously to generate data read requests and return data corresponding to the data read requests, thereby generating a variety of interaction information. These interaction information reflect the operation and working status of different design modules in the chip design. Therefore, it is necessary to obtain these data (i.e., the interaction information) after the simulation test process is completed.

[0046] For example, during simulation testing of a chip design, interaction information may include request status signals (req_vld) and response status signals (rsp_vld) from different design modules. The request status signal (req_vld) indicates that the current design module's request is valid and is ready to send a request to its downstream design module; the response status signal (rsp_vld) indicates that the current design module's response is valid and is ready to send a response to its upstream design module. Subsequent analysis and processing of these signals can yield test values ​​for performance analysis.

[0047] Continue to refer Figure 2After obtaining the simulation data, execute step S20.

[0048] Step S20: Process the interactive information to generate performance test values ​​of each design module in the chip design under each test scenario.

[0049] Since the interactive information is information obtained after the simulation is completed, and the information after the simulation is usually displayed as waveform information, in order to facilitate subsequent performance analysis, the interactive information is converted into a numerical form that is easy to analyze, namely the performance test value.

[0050] The performance test value represents the actual result of each design module of the chip design after the simulation is completed in a specific test scenario, reflecting the actual performance of the design module in the test scenario, so that the subsequent performance analysis results based on the performance test value can be accurate.

[0051] Step S30: comparing the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result.

[0052] The theoretical performance value is an ideal value set based on the design requirements of the chip design, that is, the performance value that the design module is expected to have. For example, when the test scenario is a scenario for testing the memory access performance of the design module, the theoretical performance value at least includes a theoretical value of memory access latency. By comparing the performance test value with the theoretical performance value under the test scenario, it is possible to determine whether the chip design has achieved the expected performance, and if the performance of the chip design fails to meet expectations, analyze the factors that caused the chip design to fail to meet expectations.

[0053] It can be seen that in the performance analysis method of the chip design provided by the embodiment of the present invention, the simulation data of the chip design is first obtained, wherein the simulation data includes the interaction information obtained after the simulation of each design module in the chip design under different test scenarios; then the interaction information is converted into the performance test value of each design module in the chip design under each test scenario, and the performance test value is compared with the theoretical design value of the chip design to complete the performance analysis of the chip design. Since the performance test value of each design module in the chip design is obtained by analyzing the interaction information of each design module obtained in the simulation data, the technical solution provided by the embodiment of the present invention can perform performance test analysis after the chip design simulation is completed, without the need to use a performance analysis program to perform performance analysis during the simulation process of the chip design. In this way, it is possible to avoid modifying the performance analysis program in the simulation process when the chip design changes, resulting in changes in the topology structure or transmission protocol of the chip design, reducing the modification of the performance analysis program, thereby reducing the time and human resource investment in the performance analysis method of the chip design, and improving the efficiency of the performance analysis method of the chip design.

[0054] To accurately generate the performance test value for each test scenario, in one embodiment, step S20 may include:

[0055] In each test scenario, the module delay of each design module is determined based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information; and the performance test value of each design module is generated at least based on the module delay of each design module.

[0056] The performance of a design module generally refers to the speed or efficiency with which the design module completes the test task within the test scenario. Delay refers to the time required for a signal to propagate within a circuit or design module. This delay directly affects the response speed and overall performance of the design module. Therefore, determining the module delay of a design module is crucial for determining its performance test value.

[0057] Based on this, in the embodiment of the present invention, when generating the performance test value of each design module, at least the module delay of each design module in different test scenarios is used to achieve it.

[0058] According to the delay calculation method: delay is the time interval from the change of input signal to the change of output signal, the module delay of each design module is determined. Therefore, it can be calculated based on the time when each design module sends and receives interactive information.

[0059] The time of sending the interactive information corresponds to the time when the design module sends a signal (the time when the output signal changes), and the time of receiving the interactive information corresponds to the time when the design module receives a signal (the time when the input signal changes).

[0060] After the module delays of the respective design modules are determined, a performance test value of the design module may be determined based at least on the module delays.

[0061] In some embodiments, reference Figure 4 The test scenario includes a first test scenario for testing the module delay of each design module when the chip design is in an idle state; in each test scenario, after step S10 is completed, determining the module delay of each design module based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information, including:

[0062] Step S210: In the first test scenario, the interaction information obtained from the first test scenario is processed using the defined calculation method for the module delay of the design module to obtain the module delay of the design module corresponding to the first test scenario.

[0063] The module delay of the defined design module is calculated as follows:

[0064] For each design module, the first delay difference is obtained by subtracting the time when it sends the interactive information from the time when it receives the interactive information; the upstream design module and downstream design module of each design module are determined, and the module delay of the design module is calculated using the first delay difference of the upstream design module and the first delay difference of its downstream design module.

[0065] It can be understood that in the transmission path of interactive information, the first delay difference of the design modules from upstream to downstream is decreasing. Therefore, in the transmission path of interactive information, the module delay of each design module can be iteratively calculated from downstream to upstream based on the first delay difference of different design modules.

[0066] It should be noted that when a design module has no downstream design module (that is, the design module is the most downstream design module), its first delay difference can be calculated based on the time difference between the design module sending interactive information to its upstream design module and receiving the interactive information sent by its upstream design module.

[0067] Continue to refer Figure 4 When the test scenario includes the first test scenario, generating the performance test value of each design module based at least on the module delay of each design module includes:

[0068] Step S211: taking the module delay of the design module corresponding to each first test scenario as the performance test value of each design module under the first test scenario.

[0069] Since the first test scenario is a test scenario for testing the module delay of each design module when the chip design is in an unloaded state, in the first test scenario, the performance test value of each design module is the calculated module delay of each design module.

[0070] The process of obtaining the interaction information in the first test scenario may be:

[0071] First, construct the test vector for the first test scenario;

[0072] Then, simulation is started based on the test vectors.

[0073] Exemplarily, in the first test scenario, the chip design is simulated and tested according to the test vector to obtain simulation data, including: iteratively simulating and testing the chip design according to the test vector issued each time; and combining the corresponding interactive information obtained after each test vector simulation test to obtain simulation data.

[0074] For example, the simulation process can be as follows: the design module CORE sends a read request req (test vector) to other design modules and waits for the other design modules to return a response (rsp). After receiving the rsp, the CORE continues to send the next req request and waits for the rsp to return. After sending a specified number of req requests, it stops sending.

[0075] At this point, the simulation is terminated and the generation of simulation data (in the form of a waveform file) is awaited. The generated simulation data includes interaction information of each design module under the first test scenario.

[0076] To facilitate subsequent processing of the interaction information, an EDA (Electronic Design Automation) tool can be used to parse the waveform file, extract the simulation time points when req and rsp are valid in each design module (i.e., the time when the interaction information is sent and the time when the interaction information is received), and generate a readable file, such as a CSV file.

[0077] Then, the readable file can be processed, for example, the CSV file can be parsed, so that the calculation method of the module delay of the design module defined in the first test scenario can be used to obtain the first delay difference between rsp and req of each design module; and for each design module, the first delay difference of its upstream design module is subtracted from the first delay difference of its downstream design module to obtain the module delay of each design module in the first test scenario.

[0078] For example, Figure 3 Taking the chip design shown in the figure as an example, the performance signal includes at least a request status signal req_vld and a response status signal rsp_vld. When a data read request is issued, the transmission order of the request in the data transmission unit DF is Module1, Module2, and Module3. For the design module Module2, its upstream and downstream design modules are Module1 and Module3 respectively. The time t at which Module2 can send a response to its upstream design module Module1 (i.e., the response status signal rsp_vld of Module2 changes from invalid to valid) is based on the time t rsp2 , and the time t when Module2 sends a request to its downstream design module Module1 (that is, the request status signal req_vld of Module2 changes from invalid to valid). req2 , calculate t rsp2 and t req2 The difference between the two values ​​is the first delay difference t of Module2 Module2 =t rsp2 -t req2 As for the memory DDR, in the first test scenario, the design module is at the most downstream position according to the sending direction of the data read request. The time t when the memory DDR sends a response to its upstream design module Module3 is recorded. rspD The time t at which the upstream design module Module3 receives the request reqD , then the first delay difference of memory DDR is t DDR =t rspD -t reqD .

[0079] After calculating the first delay difference of each design module, the module delay of each design module can be calculated based on the first delay difference of the design module. For example, let the first delay difference of the memory DDR be t DDR Since DDR is at the downstream of the data read request, the module delay of DDR is the first delay difference t DDR , that is, T DDR =t DDR For the design module Module3, the first delay difference of the design module Module3 is t Module3 , then the module delay T of Module3 Module3 The first delay difference t of the upstream design module Module2 Module2 Subtract the first delay difference t of its downstream design module DDR DDR The difference, that is, T Module3 =t DDR -t Module2By analogy, the module delay of each design module can be obtained by performing calculations in sequence.

[0080] Through the above method, the performance test values ​​of each design module in the first test scenario are obtained, and then performance analysis is performed.

[0081] In one embodiment, the theoretical performance value in the first test scenario is the no-load delay design value; please continue to refer to Figure 4 , the method further comprises:

[0082] Step S31: comparing the module delay of the design module corresponding to the first test scenario with the no-load delay design value to obtain a corresponding performance analysis result.

[0083] The no-load delay design value reflects the memory access performance of the chip design in a no-load state. The theoretical design value of the chip design in a no-load state (corresponding to the first test scenario) includes the no-load delay design value. It is necessary to iteratively simulate the chip design in the first test scenario according to the test vector issued each time; combine the corresponding interactive information obtained after each test vector simulation test to obtain simulation data, and calculate the module delay of each design module based on the simulation data. The module delay obtained in the first test scenario is compared with the no-load delay design value to determine whether the memory access performance of the chip design in the first test scenario meets expectations, that is, to obtain a performance analysis result.

[0084] In order to improve the comprehensiveness of the performance of the test chip design, in other embodiments, reference Figure 5 The test scenario also includes: a second test scenario in which each design module is tested when the chip design reaches the limit bandwidth; in each test scenario, determining the module delay of each design module based on the time when each design module sends and receives the interaction information in the interaction information includes:

[0085] Step S220: using the defined calculation method for the module delay of the design module, the interaction information obtained from the second test scenario is processed to obtain the module delay of the design module corresponding to the second test scenario.

[0086] Step S221: In the second test scenario, the interaction information obtained in the second test scenario is processed using the defined bandwidth calculation method for each design module to obtain the bandwidth of the design module corresponding to the second test scenario.

[0087] The bandwidth of the defined design module is calculated as follows:

[0088] Obtain a preset data transmission volume; obtain a corresponding data transmission start time based on the time when each design module sends the interaction information in the interaction information obtained from the test scenario, and obtain a corresponding data transmission end time based on the time when each design module receives the interaction information, and determine the data transmission delay of each design module; calculate the bandwidth of each design module based on the data transmission delay and the preset data transmission volume.

[0089] The data transmission delay for each design module is the time required for different design modules in the chip design to transmit the data included in the interaction information. Since the preset data transmission volume included in the interaction information, i.e., the data volume corresponding to the data access request, is known, after calculating the data transmission delay for each design module, the bandwidth of each design module can be calculated based on the preset data transmission volume and the data transmission delay, thereby enabling a more comprehensive performance analysis of the chip design based on the bandwidth of each design module.

[0090] Continue to refer Figure 5 When the test scenario includes the second test scenario, generating the performance test value of each module based at least on the module delay of each design module includes:

[0091] Step S222: The bandwidth of the design module corresponding to the second test scenario and the module delay of the design module corresponding to the second test scenario are used as the performance test values ​​of each design module under the second test scenario.

[0092] Since the bandwidth and module delay of the design module in the second test scenario reflect the actual performance of the design module, it is necessary to use the bandwidth and module delay of the design module as the performance test values ​​of each design module in the second test scenario to ensure the comprehensiveness of the performance analysis.

[0093] In the second test scenario, that is, when testing the limit bandwidth of the chip design, the module delay of each design module and its corresponding bandwidth before reaching the limit bandwidth can be calculated.

[0094] For example, in the second test scenario, the process of calculating the performance test value may be:

[0095] First, construct the test vector for the second test scenario.

[0096] Then, a simulation test under the second test scenario is started based on the test vector. The simulation process can be: the design module CORE sends a read and write request to another design module DDR until a specified number of requests (test vectors) are sent and then stops sending. Wait for the simulation to end and generate simulation data, such as a waveform file containing a simulation waveform. By sending a specified number of requests, the design module DF is fully loaded to test the limit bandwidth of the chip design. In some embodiments, the interaction information includes a full load signal indicating that the data transmission module has reached a full load.

[0097] Next, use EDA tools to analyze the simulation data, for example, analyze the waveform file to extract performance-related signal values ​​such as req_vld, rsp_vld, tx_vld (data transmission start time), and rx_vld (data transmission end time) in each design module.

[0098] Finally, using the module latency calculation method defined in the first test scenario, we can determine the module latency for each design module when the bandwidth limit is reached. Parsing the CSV file also yields the preset data transfer rate provided in the second test scenario. The bandwidth of the design module can then be calculated using the formula BW = trans byte / trans time, where BW is the bandwidth, trans byte is the preset data transfer rate, and trans time is the module latency.

[0099] After obtaining the performance test values ​​under the second test scenario, the calculated module delay and bandwidth of each design module can also be output to an Excel file for subsequent query by designers.

[0100] In the second test scenario, the theoretical performance value is a designed value of the data transmission bandwidth; and comparing the performance test value with the theoretical performance value in the test scenario to obtain a performance analysis result includes:

[0101] Step S32: comparing the bandwidth and module delay of the designed module corresponding to the second test scenario with the designed value of the data transmission bandwidth to obtain corresponding performance analysis results.

[0102] Since the theoretical performance value of the chip design includes the data transmission bandwidth design value, it is necessary to test the chip design under a second test scenario and obtain simulation data, and calculate the data transmission bandwidth performance indicator based on the simulation data; based on the comparison result of the data transmission bandwidth design value and the data transmission bandwidth performance indicator, determine whether the memory access performance of the chip design under full load meets expectations, that is, obtain the performance analysis result.

[0103] The data transmission bandwidth design value reflects the ultimate bandwidth of the chip design. Since the theoretical design value of the chip design includes the data transmission bandwidth design value, it is necessary to test each design module in a second test scenario based on the test vectors while the chip design reaches the ultimate bandwidth, obtain simulation data, and calculate the module delay and bandwidth of each design module based on the simulation data. The module delay and bandwidth obtained in the second test scenario are compared with the data transmission bandwidth design value to determine whether the ultimate bandwidth of the chip design meets expectations, that is, to obtain a performance analysis result.

[0104] In order to further improve the comprehensiveness of the performance of the test chip design, refer to Figure 6 ,In some other implementations, the test scenario further includes: a third test scenario in which the chip design tests each design module at different preset bandwidths;

[0105] After step S10 is completed, in each test scenario, determining the module delay of each design module according to the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information includes:

[0106] Step S230: using the defined calculation method for the module delay of the design module, the interaction information obtained from the third test scenario is processed to obtain the module delay of the design module corresponding to the third test scenario.

[0107] Step S231: Under each bandwidth injection rate provided by the third test scenario, the interaction information obtained from the third test scenario is processed using the defined bandwidth calculation method of the design module to obtain the bandwidth of the design module corresponding to the third test scenario.

[0108] The bandwidth injection rate is the rate at which data is injected into the data transmission path in the chip design. Testing the performance of the chip design under different bandwidth injection rates can more accurately analyze the bandwidth bottleneck of the chip design in the future.

[0109] Step S232: combining the module delay of the design module corresponding to the third test scenario and the bandwidth of the design module corresponding to the third test scenario to obtain a set of bandwidth-delay combinations.

[0110] Continue to refer Figure 6 When the test scenario includes the third test scenario, generating the performance test value of each module based at least on the module delay of each design module includes:

[0111] Step S233: The bandwidth-delay combination obtained under each bandwidth injection rate is used as the performance test value of the design module under the third test scenario.

[0112] The third test scenario can be to test the relationship between the bandwidth and module delay of the design module under different bandwidth injection rates. At this time, the performance test value under the third test scenario can be calculated using the calculation method of the defined bandwidth and module delay described above.

[0113] Since the bandwidth-delay combination of the design module in the third test scenario reflects the actual performance of the design module under different bandwidth injection rates, it is necessary to use the bandwidth-delay combination obtained at each bandwidth injection rate as the performance test value of the design module in the third test scenario to ensure the accuracy of the performance analysis.

[0114] For example, in the third test scenario, the specific process of calculating the performance test value may be:

[0115] First, construct the test vector for the third test scenario.

[0116] Then, the simulation test under the third test scenario is started. According to the bandwidth calculation formula BW = trans_data_num / (end_time–start_time), trans_data_num is the test data volume, end_time and start_time are the end time and start time of the test respectively; it can be understood that when the test bandwidth BW and the test data volume trans_data_num are determined, the time required for the simulation can be obtained, and the start time start_time of the simulation process can be determined. According to the above formula, by controlling the end time end_time of the simulation, different bandwidth injection rates can be simulated;

[0117] For example, reference Figure 3 In the simulation test under the third test scenario, the design module CORE sends a request to the design module DDR and saves the simulation start time; according to the formula end_time_exp=

[0118] Trans_data_num / BW + start_time checks whether the simulation time reaches the expected end time (end_time_exp). If not, continue waiting. Otherwise, continue to build a test vector at another bandwidth and simulate until the specified amount of data is transmitted. Wait for the simulation to end and generate simulation data.

[0119] Because the simulation test for the third test scenario was based on test vectors at different bandwidth injection rates, it was necessary to use the defined bandwidth calculation method for the design module to obtain the bandwidth of each design module at different bandwidth injection rates, and to use the defined module delay calculation method for the design module to obtain the module delay of each design module. These combinations were then used to obtain the performance test values ​​of the design modules for the third test scenario.

[0120] The module delay of each module in the chip design will change with the bandwidth injection rate. By analyzing the relationship between the data transmission bandwidth and delay of each module under different bandwidth injection rates, the performance of the chip design can be analyzed in detail.

[0121] by Figure 3 Taking the chip design shown as an example, when the bandwidth injection rate of Module3 is 30GB / s, its bandwidth is calculated to be 20GB / s and the data transmission delay is 300ms; when the bandwidth injection rate of Module3 is 40GB / s, its bandwidth is calculated to be 25GB / s and the data transmission delay is 900ms. This shows that when the bandwidth injection rate is 40GB / s, the performance of Module3 has a bottleneck, affecting the performance of the chip design.

[0122] Continue to refer Figure 6 , in the third test scenario, the theoretical performance value is the bandwidth-delay theoretical design value;

[0123] The performance theoretical value under the test scenario is compared with the performance test value to obtain a performance analysis result, including:

[0124] Step S33: using each bandwidth-delay combination in the third test scenario, compare it with the bandwidth-delay theoretical design value to obtain a corresponding performance analysis result.

[0125] Since the theoretical design value of the chip design includes the theoretical design value of bandwidth-delay, it is necessary to conduct a third data transmission simulation test and obtain simulation data, and calculate the bandwidth-delay combination based on the simulation data; based on the comparison result of the theoretical design value of bandwidth-delay and the bandwidth-delay combination, determine whether the memory access performance of the chip design under full load meets expectations, that is, obtain the performance analysis result.

[0126] Likewise Figure 3Taking the chip design shown as an example, when the bandwidth injection rate of Module3 is 40GB / s, its data transmission rate is calculated to be 25GB / s, and the data transmission delay is 900ms. In the bandwidth-delay theoretical design value, the theoretical design value of the data transmission rate of Module3 when the bandwidth injection rate is 40GB / s is 30GB / s, and the theoretical design value of the data transmission delay is 450ms. This indicates that the performance of the chip design has failed to meet expectations, and targeted optimization adjustments can be made subsequently based on the performance analysis results.

[0127] In some embodiments, after the step of determining the module delay of each design module based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information, the step further includes:

[0128] Acquire a buffer signal of each design module according to the interaction information; and calculate a buffer usage rate of each design module based on the buffer signal.

[0129] The buffer signal indicates the buffer occupancy of each design module in the chip design. By analyzing the buffer signal, the buffer utilization rate can be obtained for subsequent optimization. The buffer of each module can be, for example, a FIFO memory (First In, First Out).

[0130] Regarding the buffer utilization of different modules in the chip design, if the buffer utilization of a module is too high or too low, it indicates that the memory access performance of the chip design still has room for optimization. In the chip design performance analysis method provided by the present invention, the buffer utilization rate of each design module is calculated based on the buffer signal obtained from each design module. This can analyze the performance of the chip design from multiple dimensions and improve the comprehensiveness of the chip design performance analysis.

[0131] The embodiment of the present invention also provides a performance analysis device for chip design, referring to Figure 7 , the chip design performance analysis device 3 includes:

[0132] A data acquisition module 30 is used to acquire simulation data of the chip design; the simulation data includes interactive information obtained after simulation of each design module in different test scenarios in the chip design;

[0133] A data processing module 31 is used to process the interaction information and generate performance test values ​​of each design module in the chip design under each test scenario;

[0134] The comparison and analysis module 32 is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result.

[0135] In some embodiments, the data processing module 31 is configured to process the interaction information to generate performance test values ​​of each design module in the chip design under each test scenario, including:

[0136] In each test scenario, the module delay of each design module is determined based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information; and the performance test value of each design module is generated at least based on the module delay of each design module.

[0137] In some embodiments, the data acquisition module 30 is used to acquire simulation data of chip design, including:

[0138] A scenario determination unit, used to determine a test scenario;

[0139] A test vector generating unit, configured to generate a test vector based on the test scenario;

[0140] The simulation data acquisition unit performs simulation testing on the chip design according to the test vector to obtain simulation data.

[0141] In some embodiments, the test scenario includes a first test scenario for testing module delays of various design modules when the chip design is in an idle state;

[0142] The data processing module 31 is configured to determine the module delay of each design module in each test scenario based on the time when each design module sends and receives the interaction information in the interaction information, including:

[0143] In the first test scenario, the interaction information obtained from the first test scenario is processed using a defined calculation method for the module delay of the design module to obtain the module delay of the design module corresponding to the first test scenario;

[0144] The module delay of the defined design module is calculated as follows:

[0145] For each design module, a first delay difference is obtained by subtracting the time when the module sends the interaction information from the time when the module receives the interaction information.

[0146] Determine the upstream design module and the downstream design module of each design module, and calculate the module delay of the design module using the first delay difference of the upstream design module and the first delay difference of the downstream design module;

[0147] The data processing module 31 is configured to generate a performance test value of each module based at least on the module delay of each design module, including:

[0148] The module delay of the design module corresponding to each first test scenario is used as the performance test value of each design module under the first test scenario.

[0149] In some embodiments, the simulation data acquisition unit is configured to perform simulation testing on the chip design according to the test vector to obtain simulation data, including:

[0150] Iteratively perform simulation testing on the chip design according to the test vector issued each time;

[0151] The corresponding interactive information obtained after each test vector simulation test is combined to obtain simulation data.

[0152] In some embodiments, the theoretical performance value is a no-load delay design value;

[0153] The comparison and analysis module 32 is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result, including:

[0154] The module delay of the design module corresponding to the first test scenario is compared with the no-load delay design value to obtain a corresponding performance analysis result.

[0155] In some embodiments, the test scenario further includes: a second test scenario in which each design module is tested when the chip design reaches a limit bandwidth; the data processing module 31 is configured to determine the module delay of each design module in each test scenario based on the time when each design module sends and receives the interaction information in the interaction information, including:

[0156] Using the defined calculation method for the module delay of the design module, the interaction information obtained from the second test scenario is processed to obtain the module delay of the design module corresponding to the second test scenario;

[0157] The data processing module 31 is further configured to:

[0158] In the second test scenario, the interaction information obtained from the second test scenario is processed using the defined bandwidth calculation method for each design module to obtain the bandwidth of the design module corresponding to the second test scenario;

[0159] The bandwidth of the defined design module is calculated as follows:

[0160] Get the preset data transfer volume;

[0161] According to the interaction information obtained from the test scenario, the corresponding data transmission start time is obtained from the time when each design module sends the interaction information, and the corresponding data transmission end time is obtained from the time when each design module receives the interaction information, thereby determining the data transmission delay of each design module;

[0162] Calculating the bandwidth of each design module according to the data transmission delay and the preset data transmission volume;

[0163] The data processing module 31 is configured to generate a performance test value of each module based at least on the module delay of each design module, including:

[0164] The bandwidth of the design module corresponding to the second test scenario and the module delay of the design module corresponding to the second test scenario are used as the performance test values ​​of each design module under the second test scenario.

[0165] In some embodiments, the theoretical performance value is a data transmission bandwidth design value;

[0166] The comparison and analysis module 32 is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result, including:

[0167] The bandwidth and module delay of the designed module corresponding to the second test scenario are compared with the designed value of the data transmission bandwidth to obtain corresponding performance analysis results.

[0168] In some embodiments, the test scenario further includes: a third test scenario in which the chip design tests each design module under different preset bandwidths; the data processing module 31 is configured to determine the module delay of each design module in each test scenario based on the time when each design module sends and receives the interaction information in the interaction information, including:

[0169] Using the defined calculation method for the module delay of the design module, the interaction information obtained from the third test scenario is processed to obtain the module delay of the design module corresponding to the third test scenario;

[0170] The data processing module 31 is further configured to:

[0171] At each bandwidth injection rate provided by the third test scenario, using the defined bandwidth calculation method for the design module, the interaction information obtained from the third test scenario is processed to obtain the bandwidth of the design module corresponding to the third test scenario; combining the module delay of the design module corresponding to the third test scenario with the bandwidth of the design module corresponding to the third test scenario to obtain a set of bandwidth-delay combinations;

[0172] The data processing module 31 is configured to generate a performance test value of each module based at least on the module delay of each design module, including:

[0173] The bandwidth delay combination obtained under each bandwidth injection rate is used as the performance test value of the design module in the third test scenario.

[0174] In some embodiments, the theoretical performance value is a bandwidth-delay theoretical design value;

[0175] The comparison and analysis module 32 is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result, including:

[0176] Each bandwidth-delay combination in the third test scenario is compared with the bandwidth-delay theoretical design value to obtain corresponding performance analysis results.

[0177] In some embodiments, further comprising:

[0178] The buffer usage rate calculation module is configured to obtain a buffer signal of each design module according to the interaction information; and calculate a buffer usage rate of each design module based on the buffer signal.

[0179] It can be seen that in the performance analysis method of the chip design provided by the embodiment of the present invention, the simulation data of the chip design is first obtained, wherein the simulation data includes the interaction information obtained after the simulation of each design module in the chip design under different test scenarios; then the interaction information is converted into the performance test value of each design module in the chip design under each test scenario, and the performance test value is compared with the theoretical design value of the chip design to complete the performance analysis of the chip design. Since the performance test value of each design module in the chip design is obtained by analyzing the interaction information of each design module obtained in the simulation data, the technical solution provided by the embodiment of the present invention can perform performance test analysis after the chip design simulation is completed, without the need to use a performance analysis program to perform performance analysis during the simulation process of the chip design. In this way, it is possible to avoid modifying the performance analysis program in the simulation process when the chip design changes, resulting in changes in the topology structure or transmission protocol of the chip design, reducing the modification of the performance analysis program, thereby reducing the time and human resource investment in the performance analysis method of the chip design, and improving the efficiency of the performance analysis method of the chip design.

[0180] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the performance analysis method of the chip design as described in any of the above embodiments.

[0181] An embodiment of the present invention further provides a storage medium storing a program, which, when executed, implements the performance analysis method for chip design as described in any one of the aforementioned embodiments.

[0182] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed, implements the performance analysis method for chip design as described in any of the aforementioned embodiments.

[0183] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0184] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A performance analysis method for chip design, characterized in that: include: Acquire simulation data of the chip design; the simulation data includes interactive information obtained after simulation of each design module in the chip design under different test scenarios; Processing the interaction information to generate performance test values ​​of each design module in the chip design under each test scenario; The performance test values ​​are compared with the theoretical performance values ​​under the test scenario to obtain performance analysis results.

2. The chip design performance analysis method according to claim 1, wherein: The processing of the interaction information to generate performance test values ​​of each design module in the chip design under each test scenario includes: In each test scenario, the module delay of each design module is determined based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information; and the performance test value of each design module is generated at least based on the module delay of each design module.

3. The chip design performance analysis method according to claim 2, wherein: The obtaining of simulation data of the chip design includes: Determine the test scenario; generating a test vector based on the test scenario; The chip design is simulated and tested according to the test vector to obtain simulation data.

4. The chip design performance analysis method according to claim 3, wherein: The test scenario includes a first test scenario for testing module delay of each design module when the chip design is in an idle state; In each test scenario, determining the module delay of each design module according to the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information includes: In the first test scenario, the interaction information obtained from the first test scenario is processed using a defined calculation method for the module delay of the design module to obtain the module delay of the design module corresponding to the first test scenario; The module delay of the defined design module is calculated as follows: For each design module, a first delay difference is obtained by subtracting the time when the module sends the interaction information from the time when the module receives the interaction information. Determine the upstream design module and the downstream design module of each design module, and calculate the module delay of the design module using the first delay difference of the upstream design module and the first delay difference of the downstream design module; Generating the performance test value of each design module based at least on the module delay of each design module includes: The module delay of the design module corresponding to each first test scenario is used as the performance test value of each design module under the first test scenario.

5. The chip design performance analysis method according to claim 4, wherein: The performing simulation test on the chip design according to the test vector to obtain simulation data includes: Iteratively perform simulation testing on the chip design according to the test vector issued each time; The corresponding interactive information obtained after each test vector simulation test is combined to obtain simulation data.

6. The chip design performance analysis method according to claim 5, wherein: The performance theoretical value is the no-load delay design value; The performance theoretical value under the test scenario is compared with the performance test value to obtain a performance analysis result, including: The module delay of the design module corresponding to the first test scenario is compared with the no-load delay design value to obtain a corresponding performance analysis result.

7. The chip design performance analysis method according to claim 4, wherein: The test scenario also includes: a second test scenario in which each design module is tested when the chip design reaches the limit bandwidth; in each test scenario, determining the module delay of each design module based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information includes: Using the defined calculation method for the module delay of the design module, the interaction information obtained from the second test scenario is processed to obtain the module delay of the design module corresponding to the second test scenario; The method further comprises: In the second test scenario, the interaction information obtained from the second test scenario is processed using the defined bandwidth calculation method for each design module to obtain the bandwidth of the design module corresponding to the second test scenario; The bandwidth of the defined design module is calculated as follows: Get the preset data transfer volume; According to the interaction information obtained from the test scenario, the corresponding data transmission start time is obtained from the time when each design module sends the interaction information, and the corresponding data transmission end time is obtained from the time when each design module receives the interaction information, thereby determining the data transmission delay of each design module; Calculating the bandwidth of each design module according to the data transmission delay and the preset data transmission volume; Generating the performance test value of each module based at least on the module delay of each design module includes: The bandwidth of the design module corresponding to the second test scenario and the module delay of the design module corresponding to the second test scenario are used as the performance test values ​​of each design module under the second test scenario.

8. The chip design performance analysis method according to claim 7, wherein: The performance theoretical value is the data transmission bandwidth design value; The performance theoretical value under the test scenario is compared with the performance test value to obtain a performance analysis result, including: The bandwidth and module delay of the designed module corresponding to the second test scenario are compared with the designed value of the data transmission bandwidth to obtain corresponding performance analysis results.

9. The chip design performance analysis method according to claim 7, wherein: The test scenario also includes: a third test scenario in which each design module is tested under different preset bandwidths in the chip design; after calculating the bandwidth of each design module based on the data transmission delay and the preset data transmission volume, determining the module delay of each design module in each test scenario based on the time when each design module sends and receives the interaction information in the interaction information, including: Using the defined calculation method for the module delay of the design module, the interaction information obtained from the third test scenario is processed to obtain the module delay of the design module corresponding to the third test scenario; The method further comprises: Under each bandwidth injection rate provided by the third test scenario, using the defined bandwidth calculation method of the design module, the interaction information obtained from the third test scenario is processed to obtain the bandwidth of the design module corresponding to the third test scenario; Combining the module delay of the design module corresponding to the third test scenario and the bandwidth of the design module corresponding to the third test scenario to obtain a set of bandwidth-delay combinations; Generating the performance test value of each module based at least on the module delay of each design module includes: The bandwidth delay combination obtained under each bandwidth injection rate is used as the performance test value of the design module in the third test scenario.

10. The chip design performance analysis method according to claim 9, wherein: The theoretical performance value is the bandwidth-delay theoretical design value; The performance theoretical value under the test scenario is compared with the performance test value to obtain a performance analysis result, including: Each bandwidth-delay combination in the third test scenario is compared with the bandwidth-delay theoretical design value to obtain corresponding performance analysis results.

11. The chip design performance analysis method according to any one of claims 2 to 10, wherein: After the step of determining the module delay of each design module based on the time when each design module sends the interaction information and the time when each design module receives the interaction information in the interaction information, the method further includes: Acquire buffer signals of each design module according to the interaction information; The buffer usage rate of each design module is calculated based on the buffer signal.

12. A performance analysis device for chip design, characterized in that: include: A data acquisition module is used to obtain simulation data of the chip design; the simulation data includes interactive information obtained after the simulation of each design module in different test scenarios in the chip design; A data processing module, configured to process the interaction information and generate performance test values ​​of each design module in the chip design under each test scenario; The comparison and analysis module is used to compare the performance test value with the performance theoretical value under the test scenario to obtain a performance analysis result.

13. An electronic device comprising a memory and a processor, characterized in that: The memory stores a program, and the processor calls the program stored in the memory to execute the performance analysis method for chip design according to any one of claims 1 to 11.

14. A storage medium storing a program, characterized in that: When the program is executed, the performance analysis method for chip design according to any one of claims 1 to 11 is implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed, the performance analysis method for chip design according to any one of claims 1 to 11 is implemented.

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