Ultralow-temperature quantum controller applied to low-temperature superconducting quantum computer

Abstract

The invention discloses an ultralow-temperature quantum controller applied to a low-temperature superconducting quantum computer, which comprises an analog circuit part and a digital circuit part, and is characterized in that the analog circuit part comprises two XY channels and three Z channels, each XY channel comprises two signal paths and an on-chip balun; each signal path comprises a nonlinear digital-to-analog converter NLDAC, an intermediate-frequency filter, an adjustable gain amplifier VGA, a quadrature mixer and a quadrature local oscillator signal generator, the input end of the quadrature mixer is connected with the output end of the quadrature local oscillator signal generator, and the output ends of the two signal paths of the XY channel generate XY channel control signals of the XY channel through on-chip balun combination. Each of the three Z channels includes three independent, independently adjustable digital-to-analog converters (DACs) for generating Z channel control signals for the three Z channels. The invention aims to shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer and reduce the expense of quantum error correction.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to an ultra-low temperature quantum controller applied to a low-temperature superconducting quantum computer. Background Art

[0002] With the rapid development of quantum computing technology, platforms such as superconducting qubits and spin qubits have demonstrated the potential to achieve practical quantum computing. However, the manipulation and reading of qubits require high-precision, low-noise electronic control systems. The long-distance interconnection between traditional room-temperature electronic devices and cryogenic quantum processors introduces thermal noise, signal attenuation, and timing delays, severely limiting the scalability and operational fidelity of quantum systems. To address this challenge, cryogenic CMOS (Cryo-CMOS) quantum controller chips for low-temperature superconducting quantum computers have emerged. By directly integrating control circuits in a cryogenic environment (e.g., 4K or lower), they significantly shorten signal paths, reduce power consumption and noise, and provide a feasible solution for the integrated control of large-scale quantum processors.

[0003] The two-qubit module is a minimal, representative subcircuit demonstrating the basic functionality required for universal control of large-scale quantum processors. For example, the qubits in Google's Sycamore quantum processor architecture are interconnected on a two-dimensional grid via tunable couplers. These qubits are implemented using flux-tunable transmons, essentially nonlinear LC resonators in which a superconducting quantum interference device (SQUID) acts as a flux-tunable nonlinear inductor. Each transmon requires two control signals: a microwave signal (XY channel) to resonate the qubit, and a baseband current (Z channel) to tune the qubit frequency via the SQUID flux bias. A readout port is also provided to detect the qubit state using microwave reflectometry. The tunable coupler is implemented using an additional transmon embedded between the two qubits, capacitively coupled to adjacent qubits. The transmons in the tunable coupler operate in a non-resonant state, acting as flux-tunable impedances. By tuning the tunable coupler propagator to a specific frequency, coupling between qubits can be completely eliminated. Deviating from this bias point, continuously adjustable, deterministic coupling between qubits is achieved, forming the basis for a two-qubit gate. Each coupler has a single bias current (g-channel) that controls the operating frequency of the coupler propagator. Therefore, controlling a two-qubit module requires a qubit controller that can provide control waveforms for two XY channels, two Z channels, and one g-channel. The required microwave pulse signals are generated by a microwave pulse transmitter with two XY channels, two Z channels, and one g-channel.

[0004] The system architecture of a qubit controller must strike a balance between multi-channel integration, control pulse accuracy, and power consumption constraints. The high power consumption of the microwave pulse transmitters in the XY channels of qubit controllers currently limits multi-channel integration. Existing microwave pulse transmitters for the XY channels of qubit controllers include direct up-conversion transmitters, polar coordinate transmitters, transmitters based on direct digital synthesis (DDS), and transmitters using arbitrary signal generators (AWGs). However, direct up-conversion transmitters require a separate clock line for each qubit, polar coordinate transmitters are not conducive to large-scale integration, and transmitters based on direct digital synthesis (DDS) and arbitrary signal generators (AWGs) require lookup tables and waveform memory, consuming significant area and power. This field currently faces numerous challenges, including extremely high-channel integration, low-power design, and noise suppression. Summary of the Invention

[0005] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, an ultra-low temperature quantum controller for use in a low-temperature superconducting quantum computer is provided. The present invention aims to shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer, and reduce the overhead of quantum error correction.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A super-low-temperature quantum controller for a low-temperature superconducting quantum computer includes an analog circuit portion and a digital circuit portion. The analog circuit portion includes two XY channels and three Z channels. Each XY channel includes two signal paths and an on-chip balun. Each signal path includes a nonlinear digital-to-analog converter (NLDAC), an intermediate frequency filter, an adjustable gain amplifier (VGA), a quadrature mixer, and a quadrature local oscillator (LOO) signal generator. The input end of the nonlinear DOO converter (NLDAC) is connected to the triangular wave output end of the digital circuit portion to output a sinusoidal current signal based on the input triangular wave. The input end of the quadrature mixer is also connected to the quadrature local oscillator signal output end of the LOO signal generator. The output ends of the quadrature mixers in the two signal paths of the XY channel are combined via the on-chip balun to generate an XY channel control signal for the XY channel. The three Z channels each include three independent, independently adjustable DACs to generate Z channel control signals for the three Z channels.

[0007] Optionally, the nonlinear digital-to-analog converter NLDAC includes a nonlinear coarse adjustment DAC and a linear fine adjustment DAC. The nonlinear coarse adjustment DAC uses a resistor R1 with an adjustment accuracy of 8 bits to generate a reference current. The generated reference current enters the drain and gate of transistor Q1 among the transistors Q1, Q2 and Q3 with common source and gate, and is copied into two paths and output through the drains of transistors Q2 and Q3 respectively. Then, it inputs a wide-swing common-source and common-gate current mirror composed of transistors Q4, Q5, Q6, Q7, Q8, Q9 and Q10 to drive an 8×8 coarse adjustment current generating unit. The coarse adjustment current generating unit is composed of transistors Q10 and Q11 in series, whose gates are respectively connected to the output ends of the common-source and common-gate current mirrors, and the current of the coarse adjustment current generating unit is The size is determined by the size ratio between transistors Q10 and Q11. The current generated by each current generating unit is switched by switch S1 to be connected to the main path or the linear fine-tuning DAC. The main path is switched by switch S2 to output the positive electrode out_p or the negative electrode out_n. The current sent to the linear fine-tuning DAC is first copied into a 1 / 16 circuit by transistors Q12, Q13 and Q14, and then output to four fine-tuning current generating units, each consisting of a single transistor Q15. The transistors Q15 of the four fine-tuning current generating units are respectively 1x, 2x, 4x and 8x, and are respectively connected to the corresponding switches S3 to switch the output to the positive electrode out_p or the negative electrode out_n, thereby merging with the output current of the positive electrode out_p and the negative electrode out_n of the main path to form an output differential current.

[0008] Optionally, switches S1 to S3 of the nonlinear digital-to-analog converter NLDAC are connected to a digital control array, the digital control array including a row binary-to-thermometer encoder, a column binary-to-thermometer encoder, and an 8×8 current matrix unit. Each current matrix unit stores a signal for controlling switches S1 to S2. The 64 current matrix units are divided into half a sine wave cycle to sequentially control the signals of switches S1 to S2 to activate a coarse current generating unit to generate a sine wave. The 8th to 10th bits din of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC are < 9:7> inputs the row binary to thermometer encoder to generate row code, the 5th to 7th bits din<6:4> inputs the column binary to thermometer encoder to generate column code, the row code and column code are combined to select a current matrix unit to generate a signal to control switches S1 to S2, the 1st to 4th bits din<3:0> of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC generate a signal to control switch S3 to control the fine-tuning current generating unit to generate a subdivided current, and finally merge with the output current of the positive pole out_p and the negative pole out_n of the main path to form an output differential current.

[0009] Optionally, the intermediate frequency filter includes digitally adjustable capacitors C1 and C2 and 8-bit switches S4 and S5. The digitally adjustable capacitors C1 and C2 are arranged in parallel between the positive electrode out_p and the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC. The positive electrode out_p of the nonlinear digital-to-analog converter NLDAC is connected to one input end of the 8-bit switch S4, and the other input end of the 8-bit switch S4 is grounded; the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC is connected to one input end of the 8-bit switch S5, and the other input end of the 8-bit switch S5 is grounded; the output ends of the 8-bit switches S4 and S5 are connected to the input end of the adjustable gain amplifier VGA as the positive output and the negative output, respectively.

[0010] Optionally, the adjustable gain amplifier VGA includes transistors Q16 and Q17, digitally adjustable capacitors C3 to C6, and resistors Rb1 and Rb2; the source of transistor Q16 is connected to the positive output of the intermediate frequency filter, the source of transistor Q17 is connected to the negative output of the intermediate frequency filter, the gate of transistor Q16 is connected to the gate of Q17 via resistors Rb1 and Rb2 in sequence so that transistors Q16 and Q17 form a second-order low-pass filter in a common-gate configuration, the digitally adjustable capacitor C3 is connected in parallel between the drain and source of transistor Q16, the digitally adjustable capacitor C4 is connected in parallel between the drain and source of transistor Q17, the drains of transistors Q16 and Q17 are connected via digitally adjustable capacitors C5 and C6, the drain of transistor Q16 is output as a positive differential current in_p to the orthogonal mixer, and the drain of transistor Q17 is output as a negative differential current in_n to the orthogonal mixer.

[0011] Optionally, the quadrature mixer includes two orthogonal channels, an I-channel and a Q-channel, each channel consisting of four transistors Q18 to Q21, the sources of transistors Q18 and Q19 are connected to the positive differential current of the corresponding channel, and the drains are connected to the primary side of the on-chip balun, the sources of transistors Q20 and Q21 are connected to the negative differential current of the corresponding channel, and the drains are connected to the primary side of the on-chip balun, and the gate of transistor Q18 is connected to the voltage V B The gates of transistors Q19 and Q20 are connected to each other and to the negative local oscillator signal output by the orthogonal local oscillator signal generator through capacitor C8. The gate of transistor Q21 is connected to voltage V B And it is connected to the positive local oscillator signal output by the orthogonal local oscillator signal generator through capacitor C9.

[0012] Optionally, the on-chip balun is connected to a bandpass filter composed of adjustable capacitors C10 and C11, the adjustable capacitor C10 is connected in parallel to the primary side of the on-chip balun, and the adjustable capacitor C11 is connected in parallel to the secondary side of the on-chip balun.

[0013] Optionally, the orthogonal local oscillator signal generator includes a duty cycle adjustment driver and a two-frequency division circuit. The duty cycle adjustment driver includes capacitors C12 and C13, resistors R2 and R3, and transistors Q20 to Q23. The externally provided doubled frequency local oscillator signal is coupled to the gates of transistors Q20 and Q21 through capacitors C12 and C13, respectively. The gate of transistor Q20 is connected to the positive gate voltage V through resistor R2. BP The gate of transistor Q21 is connected to the negative gate voltage V through resistor R3. BN The source of transistor Q20 is connected to the power supply, the source of transistor Q21 is grounded, the drains of transistors Q20 and Q21 are connected and connected to the gates of transistors Q22 and Q23 as output terminals, the source of transistor Q22 is connected to the power supply, the source of transistor Q23 is grounded, the drains of transistors Q22 and Q23 are connected and connected to a divide-by-two circuit as output terminals, and the divide-by-two circuit is composed of two cascaded latches to output two positive local oscillation signals and two negative local oscillation signals.

[0014] Optionally, the positive gate voltage V BP and negative gate voltage V BN The duty cycle of the duty cycle adjustment driver is adjusted by voltage division through a digitally adjustable resistor. The control end of the digitally adjustable resistor is connected to a control logic. The input end of the control logic is also connected to a comparator, a resistor R4, and a capacitor C14. The output end of the duty cycle adjustment driver is also connected to the input end of the comparator through the resistor R4. The input end of the comparator is grounded through the capacitor C14. The integrator formed by the resistor R4 and the capacitor C14 extracts the average value of the duty cycle of the output signal and realizes automatic duty cycle adjustment of the digital adjustment resistor through the comparator and the control logic.

[0015] Optionally, the digital circuit part includes a digitally controlled oscillator NCO, a phase modulator and a triangular wave generator TRI, and the digitally controlled oscillator NCO, the phase modulator and the triangular wave generator TRI are connected in sequence to generate a triangular wave.

[0016] Compared with the existing technology, the present invention can mainly achieve the following beneficial effects: the ultra-low temperature quantum controller of the present invention adopts the single-sideband adjustment structure of direct digital frequency synthesis DDS, adopts two-channel phase modulation, and designs a nonlinear digital-to-analog converter NLDAC to implement direct digital frequency synthesis DDS, including two XY channels and three Z channels. Compared with the traditional DDS mode, this embodiment does not require a lookup table, reduces the size of the required memory, can shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer, and reduce the overhead of quantum error correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1Schematic diagram of the circuit principle of the ultra-low temperature quantum controller in an embodiment of the present invention.

[0018] Figure 2 FIG. 4 is a schematic diagram of the circuit principle of a nonlinear digital-to-analog converter NLDAC according to an embodiment of the present invention.

[0019] Figure 3 Schematic diagram of the circuit principle of the digital control array in an embodiment of the present invention.

[0020] Figure 4 Schematic diagram of the circuit principle of the intermediate frequency filter and the adjustable gain amplifier VGA in an embodiment of the present invention.

[0021] Figure 5 Schematic diagram of the circuit principle of the orthogonal mixer and the on-chip balun part in an embodiment of the present invention.

[0022] Figure 6 2 is a schematic diagram of the circuit principle of the orthogonal local oscillator signal generator in an embodiment of the present invention.

[0023] Figure 7 1 is the input and output waveform simulation result of the nonlinear digital-to-analog converter NLDAC in an embodiment of the present invention, where (a) is the input triangle wave and (b) is the output sine wave.

[0024] Figure 8 1 is the output spectrum simulation result of the nonlinear digital-to-analog converter NLDAC in an embodiment of the present invention.

[0025] Figure 9 : is the single tone spectrum of the output of the on-chip balun simulation in an embodiment of the present invention.

[0026] Figure 10 Schematic diagram of the circuit principle of the digital circuit part in an embodiment of the present invention.

[0027] Figure 11 Schematic diagram of the circuit interface principle of the digital circuit part and the analog circuit part in an embodiment of the present invention.

[0028] Figure 12 Schematic diagram of the circuit principle of the phase modulator in an embodiment of the present invention.

[0029] Figure 13 These are various pulse test results in the embodiments of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] like Figure 1As shown, the ultra-low-temperature quantum controller applied to a low-temperature superconducting quantum computer in this embodiment includes an analog circuit portion and a digital circuit portion. The analog circuit portion includes two XY channels and three Z channels. Each XY channel includes two signal paths and an on-chip balun. Each signal path includes a nonlinear digital-to-analog converter (NLDAC), an intermediate frequency filter, an adjustable gain amplifier (VGA), an orthogonal mixer, and an orthogonal local oscillator (LOS) signal generator. The input end of the nonlinear DOS converter (NLDAC) is connected to the triangular wave output end of the digital circuit portion to output a sinusoidal current signal based on the input triangular wave. The input end of the orthogonal mixer is also connected to the orthogonal local oscillator signal output end of the orthogonal local oscillator (LOS) signal generator. The output ends of the quadrature mixers in the two signal paths of the XY channel are combined through the on-chip balun to generate the XY channel control signal of the XY channel. The three Z channels each include three independent and independently adjustable DACs to generate the Z channel control signals of the three Z channels.

[0032] The nonlinear digital-to-analog converter NLDAC of this embodiment realizes direct digital frequency synthesis DDS. Figure 2 As shown, the nonlinear digital-to-analog converter NLDAC of this embodiment includes a nonlinear coarse adjustment DAC and a linear fine adjustment DAC. The nonlinear coarse adjustment DAC uses a resistor R1 with an adjustment precision of 8 bits to generate a reference current. The generated reference current enters the drain and gate of transistor Q1 among transistors Q1, Q2, and Q3 with common source and gate, is copied into two paths, and is output through the drains of transistors Q2 and Q3 respectively. Then, it enters a wide-swing cascode current mirror composed of transistors Q4, Q5, Q6, Q7, Q8, Q9, and Q10 to drive an 8×8 coarse adjustment current generating unit. The coarse adjustment current generating unit is composed of transistors Q10 and Q11 connected in series, whose gates are respectively connected to the output ends of the cascode current mirror, and the current size of the coarse adjustment current generating unit is determined by transistors Q10 and Q11. The size ratio between them is determined by the size ratio. The current generated by each current generating unit is switched by switch S1 to be connected to the main path or the linear fine-tuning DAC. The output of the main path is switched by switch S2 to be the positive electrode out_p or the negative electrode out_n. The current sent to the linear fine-tuning DAC is first copied into a 1 / 16 circuit (represented as ×16 in the figure) by transistors Q12, Q13 and Q14, and then output to four fine-tuning current generating units each composed of a single transistor Q15. The transistors Q15 of the four fine-tuning current generating units are 1 times, 2 times, 4 times and 8 times (represented as ×1, ×2, ×4, ×8 in the figure) respectively and are connected to the corresponding switch S3 to switch the output to the positive electrode out_p or the negative electrode out_n, thereby merging with the output current of the positive electrode out_p and the negative electrode out_n of the main path to form an output differential current.

[0033] like Figure 3As shown, switches S1 to S3 of the nonlinear digital-to-analog converter NLDAC of this embodiment are connected to a digital control array, which includes a row binary-to-thermometer encoder, a column binary-to-thermometer encoder, and an 8×8 current matrix unit. Each current matrix unit stores a signal for controlling switches S1 to S2. The 64 current matrix units are divided into half a sine wave cycle to sequentially control the signals of switches S1 to S2 to activate the coarse adjustment current generating unit to generate a sine wave. The 8th to 10th bits din of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC <9:7> inputs the row binary to thermometer encoder to generate row code, the 5th to 7th bits din<6:4> inputs the column binary to thermometer encoder to generate column code, the row code and column code combination selects a current matrix unit to generate a signal to control switches S1 to S2, the 10-bit control word of the nonlinear digital-to-analog converter NLDAC, the 1st to 4th bits din<3:0> generate a signal to control switch S3 to control the fine-tuning current generating unit to generate a subdivided current, and finally merge with the output current of the positive pole out_p and the negative pole out_n of the main path to form an output differential current. In this embodiment, 4-bit binary code + 6-bit thermometer code is used for control to achieve 10-bit accuracy, 8 rows and 8 columns are used for coarse adjustment through 6-bit thermometer code, and then fine adjustment is performed through 4-bit binary code. Nonlinear control can be achieved by performing sinusoidal weight coding on the current matrix unit of each current source. In the 8×8 current matrix unit, the current of each unit is a segmented quantized value of a sinusoidal half cycle. For example, in Figure 3 The gray current matrix unit on the upper side is the forward current output terminal, and the current of the white current matrix unit is switched to the reverse current output terminal. The current matrix unit with a value of 24 is copied to the fine-tuning DAC. The switch S3 of the 4-bit linear fine-tuning DAC controls 1 / 2, 1 / 4, 1 / 8, and 1 / 16 of the current to flow to the forward or reverse current output terminal respectively, realizing linear interpolation. In this embodiment, a nonlinear digital-to-analog converter NLDAC is simulated, using a frequency control word of 1000, a digital input triangle wave in the range of 0-1023, an output sine wave frequency of 15.3MHz, a reference current of 1uA, and an output load of 100 ohms. Figure 7 1 is the input and output waveform simulation result of the nonlinear digital-to-analog converter NLDAC in this embodiment, where (a) is the input triangle wave and (b) is the output sine wave. Figure 8 : This is the output spectrum simulation result of the nonlinear digital-to-analog converter NLDAC in this embodiment. The maximum simulated spurious wave is the third harmonic, and the spurious-free dynamic range (SFDR) of the output waveform is 52 dB.

[0034] In this embodiment, an intermediate frequency filter based on a current mode common gate amplifier is used to implement the intermediate frequency filtering function. Figure 4 As shown, the intermediate frequency filter of this embodiment includes digitally adjustable capacitors C1 and C2 and 8-bit switches S4 and S5. The digitally adjustable capacitors C1 and C2 are arranged in parallel between the positive electrode out_p and the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC to further provide a filtering effect. The positive electrode out_p of the nonlinear digital-to-analog converter NLDAC is connected to one input end of the 8-bit switch S4, and the other input end of the 8-bit switch S4 is grounded; the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC is connected to one input end of the 8-bit switch S5, and the other input end of the 8-bit switch S5 is grounded; the output ends of the 8-bit switches S4 and S5 are connected to the input end of the adjustable gain amplifier VGA as the positive output and the negative output, respectively.

[0035] like Figure 4 As shown, the adjustable gain amplifier VGA of this embodiment includes transistors Q16 and Q17, digitally adjustable capacitors C3 to C6, and resistors Rb1 and Rb2. The source of transistor Q16 is connected to the positive output of the intermediate frequency filter, the source of transistor Q17 is connected to the negative output of the intermediate frequency filter, the gate of transistor Q16 is connected to the gate of Q17 via resistors Rb1 and Rb2 in sequence, so that transistors Q16 and Q17 form a second-order low-pass filter in a common-gate configuration. The digitally adjustable capacitor C3 is connected in parallel between the drain and source of transistor Q16, the digitally adjustable capacitor C4 is connected in parallel between the drain and source of transistor Q17, and the drains of transistors Q16 and Q17 are connected via digitally adjustable capacitors C5 and C6. The drain of transistor Q16 is output as a positive differential current in_p, and the drain of transistor Q17 is output as a negative differential current in_n.

[0036] This embodiment uses an orthogonal mixer with adjustable bias voltage. The orthogonal mixer can adjust the bias to balance harmonics, and achieve single-ended output and impedance matching through the on-chip balun at the output end. Figure 5 As shown, the quadrature mixer includes two orthogonal channels, the I-channel and the Q-channel. Each channel consists of four transistors Q18 to Q21. The sources of transistors Q18 and Q19 are connected to the positive differential current of the corresponding channels, and the drains are connected to the primary side of the on-chip balun. The sources of transistors Q20 and Q21 are connected to the negative differential current of the corresponding channels, and the drains are connected to the primary side of the on-chip balun. The gate of transistor Q18 is connected to the voltage V B The gates of transistors Q19 and Q20 are connected to each other and to the negative local oscillator signal output by the orthogonal local oscillator signal generator through capacitor C8. The gate of transistor Q21 is connected to voltage V B And it is connected to the positive local oscillator signal output by the orthogonal local oscillator signal generator through capacitor C9. Figure 5 middle, and Represent the positive differential current and negative differential current of the I- channel respectively, and Represents the positive differential current and negative differential current of the Q-channel respectively. The gate voltage V B It can be adjusted through digital control and by increasing the bias voltage, the problem of increasing the switching threshold voltage at low temperatures can be solved.

[0037] like Figure 5 As shown, the two outputs of the quadrature mixer are combined and converted from differential to single-ended using an on-chip balun. An on-chip balun is a balanced-to-unbalanced converter integrated within a semiconductor chip and widely used in radio frequency (RF) integrated circuits, wireless communications, microwave systems, and other fields. The on-chip balun in this embodiment is a transformer balun connected to a bandpass filter consisting of adjustable capacitors C10 and C11. Adjustable capacitor C10 is connected in parallel to the primary side of the on-chip balun, while adjustable capacitor C11 is connected in parallel to the secondary side. A DC path is provided by the center tap of the primary side of the on-chip balun. The on-chip balun's function is to provide a DC path, a load at high frequencies, filter out high-order harmonics of the local oscillator, and achieve differential-to-single-ended conversion. The on-chip balun adopts a planar structure with ultra-thick metal winding on the top layer, and a thick metal layer to improve the quality factor. Three turns of winding are used, two turns of the primary coil, and one turn of the secondary coil. The AP layer and thick metal layer are used to achieve the crossover connection and center tap. The line width is 9µm, the line spacing is 3µm, the internal diameter is 183µm, and the external ground isolation ring is included. At 5GHz, the primary coil quality factor of the balun is 15.3, the secondary coil quality factor is 7.4, the primary coil inductance is 1.47nH, the secondary coil inductance is 0.43nH, the coupling coefficient is 0.73, and the self-resonant frequency is 12GHz. The resonant capacitors C10 and C11 of the primary and secondary coils are digitally adjustable to achieve real impedance near the output signal frequency. Figure 9 This is the single-tone spectrum of the output of the on-chip balun simulation in an embodiment of the present invention, see Figure 9 It can be seen that all spurious signals are suppressed and the output spurious-free dynamic range SFDR is less than 40dB.

[0038] The local oscillator signal in this embodiment is realized by an orthogonal local oscillator signal generator, which can realize the conversion of a single-ended clock signal into a four-phase orthogonal signal and balance the harmonics by adjusting the duty cycle of the orthogonal signal. Figure 6 As shown, the orthogonal local oscillator signal generator in this embodiment includes a duty cycle adjustment driver and a two-frequency division circuit. The duty cycle adjustment driver includes capacitors C12 and C13, resistors R2 and R3, and transistors Q20 to Q23. The doubled frequency local oscillator signal (frequency 2fLO ) are coupled to the gates of transistors Q20 and Q21 through capacitors C12 and C13 respectively. The gate of transistor Q20 is connected to the positive gate voltage V through resistor R2. BP The gate of transistor Q21 is connected to the negative gate voltage V through resistor R3. BN The source of transistor Q20 is connected to the power supply, the source of transistor Q21 is grounded, the drains of transistors Q20 and Q21 are connected and connected to the gates of transistors Q22 and Q23 as output terminals, the source of transistor Q22 is connected to the power supply, the source of transistor Q23 is grounded, the drains of transistors Q22 and Q23 are connected and used as output terminals (the output frequency is 2f LO ) is connected to a divide-by-two frequency circuit, which is composed of two cascaded latches to output two positive local oscillation signals and two negative local oscillation signals (frequency is f LO The divide-by-two circuit is composed of two cascaded latches. By adjusting the duty cycle, the problem of IQ phase imbalance of the local oscillator can be effectively solved.

[0039] like Figure 6 As shown, the positive gate voltage V BP and negative gate voltage V BN The duty cycle of the duty cycle adjustment driver is adjusted by voltage division through a digitally adjustable resistor. The control end of the digitally adjustable resistor is connected to a control logic. The input end of the control logic is also connected to a comparator, a resistor R4, and a capacitor C14. The output end of the duty cycle adjustment driver is also connected to the input end of the comparator through the resistor R4. The input end of the comparator is grounded through the capacitor C14. The integrator formed by the resistor R4 and the capacitor C14 extracts the average value of the duty cycle of the output signal and realizes automatic duty cycle adjustment of the digital adjustment resistor through the comparator and the control logic.

[0040] like Figure 1 As shown, the digital circuit part in this embodiment includes a digitally controlled oscillator NCO, a phase modulator and a triangular wave generator TRI, and the digitally controlled oscillator NCO, the phase modulator and the triangular wave generator TRI are connected in sequence to generate a triangular wave.

[0041] like Figure 1 、 Figure 10 and Figure 11As shown, the digital circuit portion of this embodiment is based on a DDS architecture and includes an SPI module, a main controller, an instruction memory, a parameter memory, a current DAC memory, and a waveform memory. The SPI module is responsible for writing memory data and configuring parameters, while the controller is responsible for instruction decoding and controlling waveform playback. The digital circuit clock is externally input. Based on the DDS model, the orthogonal intermediate frequency sinusoidal signal is generated by a digitally controlled oscillator (NCO) and a phase modulator to generate a triangular wave, which is then generated by a nonlinear digital-to-analog converter (NLDAC). Compared to traditional DDS models, this embodiment eliminates the need for a lookup table, reducing the required memory size. The output waveform of this embodiment is adjusted by an adjustable gain amplifier in the analog circuit portion, avoiding multiplication operations in the digital portion. This architecture can also generate a DRAG waveform. Using polar coordinates, the DRAG waveform is decomposed into amplitude and phase waveforms, and the phase waveforms are added by the digital circuit portion. Therefore, this structure does not increase the scale of the analog circuit or the data bit width of the digital circuit, which helps reduce power consumption and area. The main controller and waveform memory are connected to DDS controller channel 1 and DDS controller channel 2, respectively, to control the two quadrature channels, the I-channel and the Q-channel. The current DAC memory is connected to the analog circuitry via current DAC controller channels 1 through 3, respectively, to control the three independently adjustable digital-to-analog converters (DACs) of the three Z channels. In this embodiment, the instruction memory is 256×22 bits in size, with an 8-bit address line width. It can store 256 instructions, each 22 bits long, including the parameter memory addresses for the two XY channels (with a 4-bit address line width), the enable signals for the two XY channels, and the IDAC memory addresses for the three Z channels (with a 4-bit address line width). The parameter memory is 16×56 bits in size, with a 4-bit address line width, and can store 16 sets of parameters. Each set of parameters includes a 16-bit frequency control word, a 16-bit initial phase, a 1-bit sideband select, an 8-bit waveform memory initial address, a 3-bit idle cycle count, an 8-bit waveform playback cycle count, and a 4-bit divider upper limit, for a total of 56 bits. The sideband selection determines whether to select the upper or lower sideband. The idle period specifies the number of periods of delay before playing the waveform. The waveform playback period specifies the waveform length. For example, if the clock frequency is 1 GHz, the period is 1 ns, and the number of waveform periods is 30, then 30 waveform data points will be played starting from the waveform memory, with a pulse length of 30 ns. The frequency divider can extend the waveform period. If this parameter is set to 5, the aforementioned pulse length can be increased from 30 ns to 150 ns. The waveform memory is 256 × 16 bits in size, with an 8-bit address line width, and can store 255 waveform data points, each consisting of 8 bits of amplitude and 8 bits of phase.The current DAC memory is 16×22 bits in size, and the IDAC memory address line width is 8 bits. It can store 16 sets of parameters, each of which includes a 10-bit current DAC control word, an 8-bit current duration cycle count, and a 4-bit divider upper limit. In this embodiment, the required memory size of the above memory is 10976 bits, which has the advantage of small storage capacity.

[0042] The structure of the phase modulator in this embodiment is as follows Figure 12 As shown, the phase modulator is used to generate a control signal for the nonlinear digital-to-analog converter NLDAC. The phase modulator consists of a phase accumulator, a phase adder, and a triangle wave generator. It mainly realizes phase accumulation and generates a triangle wave control signal to control the nonlinear digital-to-analog converter NLDAC, so that the nonlinear digital-to-analog converter NLDAC can generate any fractional intermediate frequency signal. At the same time, the phase modulator can set the starting phase to achieve orthogonal intermediate frequency output. The input control word is a 16-bit frequency control word, and the intermediate frequency output frequency is f IF =F CW × f CLK / 2 b , where F CW is the frequency control word, f CLK is the digital clock, b is the bit width of the DDS accumulator, so the frequency control accuracy is ∆ f IF = f CLK / 2 b When the digital clock f CLK The frequency accuracy of 16 bits is 15.26kHz at 1GHz, and 30.52kHz at 2GHz, which meets the requirements of quantum controllers. The phase accumulation is a two-stage structure. In two clock cycles, two 8-bit full adders are used for addition. Compared with 16-bit full adders, it is more conducive to high-speed operation. The phase adder operates in the same way, adding the 16-bit initial phase and 8-bit phase control word to the phase after the accumulator in sequence. The I-channel and Q-channel are realized by different initial phases. The phase control word is a constant in the conventional waveform generation mode and a variable when the DRAG waveform is generated. The triangle wave generator is obtained by taking the XOR operation of the highest bit and each bit in turn. Finally, the first 10 bits of output are intercepted, and the encoder outputs the coarse adjustment line control word and fine adjustment control word required by the nonlinear digital-to-analog converter NLDAC in sequence.

[0043] In this embodiment, the pulse test results of three waveforms, square wave, raised cosine and DRAG, are respectively carried out. When the square wave pulse is tested, the local oscillator frequency of the pulse is f LO5.1GHz, intermediate frequency f IF is 125MHz, the output frequency is f LO − f IF The frequency is 4.975GHz and the pulse width is 10ns. The frequency range is usually 150MHz to 300MHz less than the frequency of the quantum bit, where Represents a quantum system from a low energy state ( ) transitions to a higher energy state ( This process typically requires external energy input (such as photon irradiation, electric or magnetic fields) to cause the system to absorb and alter energy. The tested square wave pulse spectrum exhibited suppression ratios of 18.4dB at -150MHz, 23.4dB at -200MHz, 23.1dB at -2500MHz, and 24.7dB at -300MHz. The left sidelobe, being outside the lowpass filter's band, was suppressed to some extent, resulting in a lower amplitude than the right sidelobe. The average suppression ratio from -300MHz to -150MHz was 23.52dB. The tested raised cosine pulse spectrum exhibited suppression ratios of 17.9dB at -150MHz, 25.8dB at -200MHz, 29.4dB at -250MHz, and 26.8dB at -300MHz. Compared with the spectrum of the square wave, the energy is more concentrated and the sidelobe amplitude is lower. The average suppression ratio in the range of -300MHz to -150MHz is 26.28dB. The suppression ratio of the tested DRAG pulse spectrum is 21.7dB at -150MHz, 28.4dB at -200MHz, 29.9dB at -250MHz, and 29.8dB at -300MHz. Compared with the spectrum of the raised cosine pulse, the amplitude on the left is suppressed to a certain extent. The average suppression ratio in the range of -300MHz to -150MHz is 28.34dB. Comparison of the pulse test results of the three waveforms of square wave, raised cosine and DRAG. Figure 13 As shown, the amplitude of the spectrum is normalized to obtain the normalized spectrum, from Figure 13 It can be seen that in the spectrum range of -150MHz to -300MHz, the amplitudes of square wave pulses, raised cosine pulses and DRAG pulses decrease in turn, with average suppression ratios of 23.52dB, 26.28dB and 28.34dB respectively. DRAG pulses are 2dB higher than raised cosine pulses and 4.8dB higher than square wave pulses. Therefore, the DRAG pulses generated by the ultra-low temperature quantum controller of this embodiment are beneficial for suppressing The stimulation.

[0044] Power consumption was tested on the ultra-low-temperature quantum controller of this embodiment. With a power supply voltage of 1.0V and a digital circuit clock of 1GHz, the XY channel consumed 2.87mW, the Z channel consumed 0.45mW, the local oscillator frequency divider consumed 1.449mW, the digital circuit consumed 17.6mW, and the total power consumption was 26.2mW. Within the XY channel, the DDS consumed 1.3mW, the transformer's DC path consumed 1.3mW, and the amplitude modulator consumed 0.27mW. Each XY channel consumed 2.87mW analog power, and approximately 8.8mW digital power. Excluding the Z channel, the average total power consumption per XY channel was approximately 11.67mW.

[0045] The performance comparison of the ultra-low temperature quantum controller of this embodiment and other existing quantum controllers (ISSCC'23, ISSCC'22, ISSCC'20 and ISSCC'19) is shown in Table 1.

[0046] Table 1: Performance comparison of the ultra-low temperature quantum controller of this embodiment and other existing quantum controllers

[0047] As shown in Table 1, the ultra-cold quantum controller of this embodiment supports superconducting qubit control in the 4-6 GHz range. The pulse generation DAC resolution reaches 10 bits, and the sampling rate exceeds 1 GS / s. The output power is -20 dBm, the single-tone SFDR is greater than -40 dB, the controlled target fidelity reaches 99.9%, and it supports DRAG pulse generation. The power consumption per channel is 11.67 mW, of which 2.87 mW is analog power, and the area per channel is 0.2 mm². The power consumption at ISSCC'19 was less than 2 mW. Using a direct up-conversion architecture, the local oscillator for each channel must be provided externally, which does not reduce the number of cables and hinders subsequent multi-channel integration. Compared to ISSCC'23, ISSCC'22, and ISSCC'20, the DAC performance is comparable, the SFDR meets quantum controller requirements, and the single-sideband architecture is more suitable for multi-channel integration. Each channel offers improved power consumption and area, and the ultra-cold quantum controller of this embodiment also supports DRAG pulses.

[0048] In summary, this embodiment designs an ultra-cold quantum controller for superconducting quantum computing applications. It includes two channels of XY control and three channels of Z channel control, and its digital circuitry supports a variety of commands and pulse generation. To address the high power consumption of qubit control, this embodiment employs current multiplexing technology. The intermediate frequency filter and variable gain controller (VGA) operate in current mode, reducing power consumption in the analog circuitry. The use of a nonlinear digital-to-analog converter (NLDAC) and a current source controlled by a switch array eliminates the need for a lookup table, reducing both area and power consumption. Amplitude and phase modulation support DRAG waveforms without the need for an additional quadrature modulation circuit, reducing both area and power consumption. Furthermore, the XY channel utilizes a single-sideband architecture, allowing multiple channels to share a single local oscillator module. This allows for compatibility with frequency-division multiple access (FDMA) for multi-qubit control, facilitating multi-channel integration. To address the significant variations in transistor threshold voltage in cryogenic environments, this embodiment employs a more stable bias current generation method, incorporates a local oscillator duty cycle calibration module, and incorporates a mixer structure with adjustable bias. The test results show that the SFDR of the single-tone output of the ultra-low temperature quantum controller of this embodiment is greater than -40dB, and the area of ​​each channel is only 0.2mm 2 The power consumption of each channel is 11.67mW, of which the analog power consumption is only 2.87mW. This can shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer, and reduce the overhead of quantum error correction.

[0049] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. An ultra-low temperature quantum controller for a low temperature superconducting quantum computer, characterized in that: The device comprises an analog circuit portion and a digital circuit portion. The analog circuit portion comprises two XY channels and three Z channels. Each XY channel comprises two signal paths and an on-chip balun. Each signal path comprises a nonlinear digital-to-analog converter, an intermediate frequency filter, an adjustable gain amplifier, a quadrature mixer, and a quadrature local oscillator signal generator. The input end of the nonlinear digital-to-analog converter is connected to the triangular wave output end of the digital circuit portion to output a sinusoidal current signal based on the input triangular wave. The input end of the quadrature mixer is also connected to the quadrature local oscillator signal output end of the quadrature local oscillator signal generator. The output ends of the quadrature mixers in the two signal paths of the XY channel are combined through the on-chip balun to generate the XY channel control signal of the XY channel. The three Z channels each comprise three independent and independently adjustable digital-to-analog converters to generate the Z channel control signals of the three Z channels.

2. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The nonlinear digital-to-analog converter includes a nonlinear coarse adjustment DAC and a linear fine adjustment DAC. The nonlinear coarse adjustment DAC uses a resistor (R1) with an adjustment accuracy of 8 bits to generate a reference current. The generated reference current enters the drain and gate of transistor (Q1) among transistors (Q1), (Q2) and (Q3) with common source and gate, is copied into two paths, and then outputs through the drains of transistors (Q2) and (Q3) respectively. Then, it inputs a wide-swing common-source and common-gate current mirror composed of transistors (Q4), (Q5), (Q6), (Q7), (Q8), (Q9) and (Q10) to drive an 8×8 coarse adjustment current generating unit. The coarse adjustment current generating unit is composed of transistors (Q10) and (Q11) connected in series, whose gates are respectively connected to the output ends of the common-source and common-gate current mirrors, and the current size of the coarse adjustment current generating unit is determined by the transistors (Q10) and (Q11). The size ratio between the body transistors (Q10) and (Q11) determines the current generated by each current generating unit. The switch (S1) switches the current generated by each current generating unit to be connected to the main path or the linear fine-tuning DAC. The switch (S2) on the main path switches the output to be positive (out_p) or negative (out_n). The current sent to the linear fine-tuning DAC is first copied into a 1 / 16 circuit by transistors (Q12), (Q13) and (Q14) and then output to four fine-tuning current generating units each consisting of a single transistor (Q15). The transistors (Q15) of the four fine-tuning current generating units are 1x, 2x, 4x and 8x respectively and are connected to the corresponding switches (S3) to switch the output to be positive (out_p) or negative (out_n), thereby merging with the output current of the positive (out_p) and negative (out_n) of the main path to form an output differential current.

3. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 2, characterized in that: The switches (S1) to (S3) of the nonlinear digital-to-analog converter are connected to a digital control array, which includes a row binary-to-thermometer encoder, a column binary-to-thermometer encoder, and an 8×8 current matrix unit. Each current matrix unit stores a signal for controlling the switches (S1) to (S2). The 64 current matrix units are divided into half a sine wave cycle to sequentially control the signals of the switches (S1) to (S2) to start the coarse adjustment current generating unit to generate a sine wave. The first bit of the 10-bit control word of the nonlinear digital-to-analog converter is The 8th to 10th bits are input into a row binary to thermometer encoder to generate a row code, the 5th to 7th bits are input into a column binary to thermometer encoder to generate a column code, the row code and the column code are combined to select a current matrix unit to generate a signal for controlling switches (S1) to (S2), the 1st to 4th bits of the 10-bit control word of the nonlinear digital-to-analog converter generate a signal for controlling switch (S3) to control the fine-tuning current generating unit to generate a subdivided current, and finally the current is combined with the output current of the positive pole (out_p) and the negative pole (out_n) of the main path to form an output differential current.

4. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The intermediate frequency filter includes digitally adjustable capacitors (C1) and (C2) and 8-bit switches (S4) and (S5). The digitally adjustable capacitors (C1) and (C2) are arranged in parallel between the positive electrode (out_p) and the negative electrode (out_n) of the nonlinear digital-to-analog converter. The positive electrode (out_p) of the nonlinear digital-to-analog converter is connected to one input end of the 8-bit switch (S4), and the other input end of the 8-bit switch (S4) is grounded. The negative electrode (out_n) of the nonlinear digital-to-analog converter is connected to one input end of the 8-bit switch (S5), and the other input end of the 8-bit switch (S5) is grounded. The output ends of the 8-bit switches (S4) and (S5) are connected to the input end of the adjustable gain amplifier as the positive output and the negative output, respectively.

5. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 4, characterized in that: The adjustable gain amplifier includes transistors (Q16) and (Q17), digitally adjustable capacitors (C3) to (C6), and resistors (Rb1) and (Rb2); The source of the transistor (Q16) is connected to the positive output of the intermediate frequency filter, the source of the transistor (Q17) is connected to the negative output of the intermediate frequency filter, the gate of the transistor (Q16) is connected to the gate of (Q17) through resistors (Rb1) and (Rb2) in sequence so that the transistors (Q16) and (Q17) form a second-order low-pass filter in a common-gate configuration, a digitally adjustable capacitor (C3) is connected in parallel between the drain and source of the transistor (Q16), a digitally adjustable capacitor (C4) is connected in parallel between the drain and source of the transistor (Q17), the drains of the transistors (Q16) and (Q17) are connected through digitally adjustable capacitors (C5) and (C6), the drain of the transistor (Q16) is output as a positive differential current (in_p) to the orthogonal mixer, and the drain of the transistor (Q17) is output as a negative differential current (in_n) to the orthogonal mixer.

6. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The quadrature mixer includes two orthogonal channels, an I-channel and a Q-channel. Each channel is composed of four transistors (Q18) to (Q21). The sources of transistors (Q18) and (Q19) are connected to the positive differential current of the corresponding channels, and the drains are connected to the primary side of the on-chip balun. The sources of transistors (Q20) and (Q21) are connected to the negative differential current of the corresponding channels, and the drains are connected to the primary side of the on-chip balun. The gate of transistor (Q18) is connected to the voltage (V B ) and connected to the positive local oscillator signal output by the orthogonal local oscillator signal generator through capacitor (C7), the gates of transistors (Q19) and (Q20) are connected to each other and connected to the negative local oscillator signal output by the orthogonal local oscillator signal generator through capacitor (C8), and the gate of transistor (Q21) is connected to the voltage (V B ) and is connected to the positive local oscillator signal output by the orthogonal local oscillator signal generator through a capacitor (C9).

7. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The on-chip balun is connected to a bandpass filter composed of adjustable capacitors (C10) and (C11), the adjustable capacitor (C10) is connected in parallel to the primary side of the on-chip balun, and the adjustable capacitor (C11) is connected in parallel to the secondary side of the on-chip balun.

8. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The orthogonal local oscillator signal generator includes a duty cycle adjustment driver and a two-frequency division circuit. The duty cycle adjustment driver includes capacitors (C12) and (C13), resistors (R2) and (R3), and transistors (Q20) to (Q23). The doubled-frequency local oscillator signal provided externally is coupled to the gates of transistors (Q20) and (Q21) through capacitors (C12) and (C13), respectively. The gate of transistor (Q20) is connected to a positive gate voltage (V BP ), the gate of transistor (Q21) is connected to negative gate voltage (V BN ), the source of transistor (Q20) is connected to the power supply, the source of transistor (Q21) is grounded, the drains of transistors (Q20) and (Q21) are connected and connected as output terminals to the gates of transistors (Q22) and (Q23), the source of transistor (Q22) is connected to the power supply, the source of transistor (Q23) is grounded, the drains of transistors (Q22) and (Q23) are connected and connected as output terminals to a divide-by-two frequency circuit, wherein the divide-by-two frequency circuit is composed of two cascaded latches to output two positive local oscillation signals and two negative local oscillation signals.

9. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 8, characterized in that: The positive gate voltage (V BP ) and negative gate voltage (V BN ) is generated by dividing the voltage of a digitally adjustable resistor to adjust the duty cycle of the duty cycle adjustment driver, the control end of the digitally adjustable resistor is connected to a control logic, the input end of the control logic is also connected to a comparator, a resistor (R4) and a capacitor (C14), the output end of the duty cycle adjustment driver is also connected to the input end of the comparator through the resistor (R4), the input end of the comparator is grounded through the capacitor (C14), the integrator composed of the resistor (R4) and the capacitor (C14) extracts the average value of the duty cycle of the output signal and realizes automatic duty cycle adjustment of the digital adjustment resistor through the comparator and the control logic.

10. The ultra-low temperature quantum controller for a low temperature superconducting quantum computer according to claim 1, characterized in that: The digital circuit part includes a digitally controlled oscillator, a phase modulator and a triangular wave generator, which are connected in sequence to generate a triangular wave.

Images