Display device and driving method thereof

Abstract

A display apparatus includes: a display panel including a sub-pixel having a light emitting device emitting light based on a duty ratio of a light emission control signal and a driving transistor supplying a driving current to the light emitting device, and a data line connected to the sub-pixel; a controller configured to obtain a compensation value for compensating for an abnormal brightness change of the display panel based on a coupling between a gate node of the driving transistor and the data line, and correct a data signal to be written to the display panel based on the compensation value; and a data driver configured to convert the corrected data signal into a data voltage and output the data voltage to the data line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0043284, filed on March 29, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a driving method thereof. Background Art

[0004] As information technology develops, the market for display devices, which serve as a connection medium between users and information, is growing. As a result, the use of display devices such as light-emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0005] The display device includes a display panel including a plurality of sub-pixels, a driver that outputs a drive signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver. When a drive signal (e.g., a scan signal and a data signal) is supplied to a sub-pixel set in the display panel, the selected sub-pixel can emit light, thereby achieving the brightness of the displayed image. Each sub-pixel may include a drive transistor that generates a drive current and a light-emitting device that emits light using the drive current. Summary of the Invention

[0006] To overcome various technical problems found in the prior art, various embodiments of the present disclosure may provide a display device and a driving method thereof, which may reduce brightness deviation caused by coupling between a data line and a gate node of a driving transistor during a blank period.

[0007] To achieve these and other technical effects and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including sub-pixels and data lines connected to the sub-pixels, the sub-pixels having light-emitting devices that emit light based on a duty cycle of a light-emitting control signal and a driving transistor that supplies a driving current to the light-emitting devices; a controller configured to obtain a compensation value for compensating for abnormal brightness variations of the display panel based on coupling between a gate node of the driving transistor and the data line, and to correct a data signal to be written to the display panel based on the compensation value; and a data driver configured to convert the corrected data signal into a data voltage and output the data voltage to the data line.

[0008] In another aspect of the present disclosure, a driving method for a display device based on a display panel is provided, wherein the display panel includes sub-pixels and data lines connected to the sub-pixels, the sub-pixels having light-emitting devices that emit light based on a duty cycle of a light-emitting control signal and a driving transistor that supplies a driving current to the light-emitting device, the driving method including: obtaining a compensation value for compensating for abnormal brightness changes of the display panel based on coupling between a gate node of the driving transistor and the data line, and correcting a data signal to be written to the display panel based on the compensation value; and converting the corrected data signal into a data voltage and outputting the data voltage to the data line.

[0009] The present disclosure can reduce the light emitting time and increase the current flowing through the light emitting device through EM PWM (pulse width modulation) driving, thereby reducing brightness unevenness occurring under low brightness driving.

[0010] In addition, the present disclosure can also effectively compensate for abnormal brightness variations caused by coupling between the data line and the gate node of the driving transistor during the vertical blank period, thereby significantly improving the display quality of low-brightness light bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present disclosure includes accompanying drawings to provide a further understanding of the present disclosure, which are incorporated into and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0012] Figure 1 is a block diagram schematically illustrating a display device according to the present disclosure;

[0013] Figure 2 is a block diagram illustrating an example of a gate driver in a display device according to the present disclosure;

[0014] Figure 3 is a diagram showing a stacked structure of a display panel according to an embodiment of the present disclosure;

[0015] Figure 4 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0016] Figure 5 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0017] Figure 6 and Figure 7 is applied to Figure 5 Driving waveform diagram of the sub-pixel;

[0018] Figure 8 It shows Figure 5Figure 4 shows the variable refresh rate (VRR) driving of the sub-pixel;

[0019] Figure 9A and Figure 9B is a diagram showing an example of the number of times the voltage of a data line changes depending on the refresh rate in VRR driving;

[0020] Figure 10 The voltage change of the data line due to the coupling effect is reflected in Figure 5 a graph showing an example of a voltage at a gate node of a driving transistor in a sub-pixel;

[0021] Figure 11 is a circuit diagram of a sub-pixel according to another embodiment of the present disclosure;

[0022] Figure 12 The voltage change of the data line due to the coupling effect is reflected in Figure 11 a graph showing an example of a voltage at a gate node of a driving transistor in a sub-pixel;

[0023] Figure 13 is a diagram showing horizontal band mura (HBM), which is a brightness defect caused by coupling between a data line and a gate node of a driving transistor;

[0024] Figures 14 to 16 It is a diagram used to describe the occurrence mechanism of HBM;

[0025] Figure 17 and Figure 18 is a diagram showing an example in which the shape of the HBM changes based on the duty ratio of the light emission control signal EM;

[0026] Figure 19 is a diagram illustrating a driving method of a display device for reducing HBM according to the present disclosure;

[0027] Figure 20 and Figure 21 is a diagram showing that HBM occurs when the voltage of the data line is switched from the data voltage to the first bias voltage in a blank period or an anode reset frame;

[0028] Figure 22 and Figure 23 FIG. 1 is a diagram showing an example of calculating an EM profile by reflecting a change in the duty ratio of the light emission control signal EM;

[0029] Figure 24 is a diagram showing an example of calculating a compensation curve and an occurrence position of HBM based on a result of integrating an EM profile during a blank period;

[0030] Figure 25 is a diagram showing an example of applying a position-based HBM compensation value to a calculated compensation curve to calculate a final compensation profile;

[0031] Figure 26 is a diagram showing an example of reducing HBM by a final compensation profile;

[0032] Figure 27 and Figure 28 is a diagram showing an example of setting the HBM compensation value in different ways based on the display grayscale and the light wavelength band; and

[0033] Figure 29 Graphs showing the luminance difference before and after HBM compensation at representative positions of a display panel. DETAILED DESCRIPTION

[0034] As used herein, the terms "connect" and "couple" are intended to be understood in the broadest possible sense. Specifically, the phrase "A is connected to B" includes both a direct connection between A and B (there are no intermediate parts or intermediate elements), and an indirect connection between A and B (there are one or more intermediate parts or intermediate elements between A and B). Similarly, the term "coupled" should also be understood in the same way. For example, "A is coupled to B" includes both direct physical or electrical coupling, and indirect coupling that is easily achieved through one or more intermediate parts or intermediate elements. Unless explicitly stated otherwise (e.g., "directly connected"), these terms do not imply or require direct physical contact.

[0035] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings in which exemplary embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0036] The display device according to the present disclosure may be implemented as a light-emitting display device or a quantum dot display (QDD) device. Hereinafter, for ease of description, a light-emitting display device based on self-luminescence of an inorganic light-emitting diode or an organic light-emitting diode will be described as an example.

[0037] In addition, the thin film transistor (TFT) described below can be implemented as an n-type TFT, a p-type TFT, or a combination of an n-type TFT and a p-type TFT. A TFT can be a three-electrode element including a gate, a source, and a drain. The source electrode can be an electrode that provides carriers to the transistor. In a TFT, carriers can flow from the source electrode. The drain electrode can be an electrode through which carriers flow from the TFT to the outside. That is, in a TFT, carriers flow from the source electrode to the drain electrode.

[0038] In a p-type TFT, since the carriers are holes, the source voltage can be higher than the drain voltage, causing holes to flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, current can flow from the source to the drain. On the other hand, in an n-type TFT, since the carriers are electrons, the source voltage can be lower than the drain voltage, causing electrons to flow from the source to the drain. In an n-type TFT, since electrons flow from the source to the drain, current can flow from the drain to the source. However, based on the voltage applied to the source and drain of the TFT, the source and drain can switch between the two. Based on this, in the following description, one of the source and drain will be described as a first electrode, and the other of the source and drain will be described as a second electrode.

[0039] Figure 1 is a block diagram schematically showing a display device 10 according to the present disclosure, Figure 2 is a block diagram illustrating an example of a gate driver in the display device 10 according to the present disclosure.

[0040] like Figure 1 As shown, the display device 10 may include a display panel 100 having a plurality of sub-pixels SP, a controller 200, a gate driver 300 supplying gate signals to the plurality of sub-pixels SP, a data driver 400 supplying data signals (or data voltages) to the plurality of sub-pixels SP, and a power supply 500 supplying power to the plurality of sub-pixels SP.

[0041] The display panel 100 may include a display area provided with a plurality of sub-pixels SP (see Figure 2 AA) and a non-display area (see FIG. 1 ) which is provided to surround the display area AA and to which the gate driver 300 and the data driver 400 are provided. Figure 2 of NA).

[0042] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL may intersect each other, and each of a plurality of sub-pixels SP may be connected to the gate line GL and the data line DL. Specifically, a gate signal may be supplied from the gate driver 300 to one sub-pixel SP via the gate line GL, a data signal may be supplied from the data driver 400 to one sub-pixel SP via the data line DL, and a high-level voltage EVDD and a low-level voltage EVSS may be supplied from the power supply 500 to one sub-pixel SP.

[0043] The gate lines GL can transmit scan signals SC and emission control signals EM to the plurality of sub-pixels SP, and the data lines DL can transmit data voltages Vdata to the plurality of sub-pixels SP. Depending on the embodiment, the gate lines GL may include a plurality of scan lines SCL for supplying scan signals SC and a plurality of emission control lines EML for supplying emission control signals EM. Voltages Vini, Var, Vobs, and Vpark can be supplied to the plurality of sub-pixels SP via a plurality of voltage lines VL. The voltages Vini, Var, Vobs, and Vpark applied via the plurality of voltage lines VL will be described below.

[0044] Each of the plurality of sub-pixels SP may include a sub-pixel driving circuit. The sub-pixel driving circuit may include a plurality of switching elements, a driving element, and a capacitor. The switching element and the driving element may each be configured as a TFT. The switching transistor may be turned on based on a scan signal SC supplied via a scan line SCL and a light emission control signal EM supplied via a light emission control line EML. The driving transistor may control the amount of current supplied to the light-emitting device OLED (controlling the amount of emitted light) based on a data voltage Vdata.

[0045] The display panel 100 can be implemented as a non-transparent display panel or a transparent display panel. The transparent display panel can be used in a transparent display device that displays an image on its screen while allowing real objects in the background to be seen. The display panel 100 can be implemented as a flexible display panel. The flexible display panel can be a plastic substrate. Each of the multiple sub-pixels SP can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each of the multiple sub-pixels SP can also include a white sub-pixel.

[0046] A touch sensor may also be provided in the display panel 100 to sense touch input. The touch sensor may be arranged as an on-cell or add-on type in the screen of the display panel 100, or may be implemented as an in-cell touch sensor embedded in the display panel 100. In addition, touch input may be sensed by a plurality of sub-pixels SP without requiring a separate touch sensor.

[0047] The controller 200 can process the image data RGB input from the outside based on the size and resolution of the display panel 100 to supply it to the data driver 400. The controller 200 can generate a gate control signal GCS and a data control signal DCS by using synchronization signals (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside. The controller 200 can supply the gate control signal GCS to the gate driver 300 to control the operation timing of the gate driver 300. The controller 200 can supply the data control signal DCS to the data driver 400 to control the operation timing of the data driver 400. The controller 200 can synchronize the operation timing of the gate driver 300 with the operation timing of the data driver 400 by using the gate control signal GCS and the data control signal DCS.

[0048] The controller 200 can be configured to be combined with various processors (e.g., microprocessors, mobile processors, and application processors) based on the devices installed thereon. The host system provided at the front end relative to the controller 200 can be one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and an automotive system.

[0049] The controller 200 can drive the display panel 100 at different refresh rates. The refresh rate can be referred to as the frame frequency. The refresh rate can be defined as the reciprocal of the time interval between adjacent refresh frames (i.e., one refresh period). The controller 200 can drive the display panel 100 in a variable refresh rate (VRR) mode, i.e., the refresh rate of the display panel 100 can be switched between a first refresh rate and a second refresh rate.

[0050] In VRR mode, the length of the vertical blanking period (or blanking time) may vary based on the refresh rate, and the length of the vertical display period (or display time) may be fixed regardless of the variable refresh rate. The vertical blanking period may be fixed relative to the highest refresh rate of the predetermined refresh rate and may be set to gradually increase as the refresh rate decreases. The vertical display period may be defined as a period during which a data signal is input to the display panel 100. On the other hand, the vertical blanking period may be defined as a period during which the input of a data signal to the display panel 100 is stopped.

[0051] In addition, the controller 200 may change only the speed of the clock signal, or may generate a synchronization signal so as to generate horizontal blanking or vertical blanking, or may drive the gate driver 300 in a mask mode to drive the display panel 100 at different refresh rates. The vertical blanking period may be repeated within one frame period, and various signals used for the operation of the display device may be synchronized with each other during the corresponding period.

[0052] The voltage level of the gate control signal GCS output from the controller 200 can be converted into a gate-on voltage VGL (VEL) and a gate-off voltage VGH (VEH) by a level converter (not shown), and can be supplied to the gate driver 300. The level converter can convert the low-level voltage of the gate control signal GCS into the gate low voltage VGL, and can convert the high-level voltage of the gate control signal GCS into the gate high voltage VGH. The gate control signal GCS may include a start signal and a clock signal.

[0053] The gate driver 300 may supply a gate signal to the gate line GL based on a gate control signal GCS supplied from the controller 200. The gate driver 300 may be provided on one or both sides of the display panel 100 in the form of a gate in panel (GIP).

[0054] The gate driver 300 may sequentially output gate signals to the plurality of gate lines GL based on the control of the controller 200. The gate driver 300 may sequentially supply the gate signals to the gate lines GL by shifting the gate signals using a shift register.

[0055] The gate signal may include a scan signal SC and an emission control signal EM. The scan signal SC may include a scan signal that swings between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include a emission control signal that swings between a gate-on voltage VEL and a gate-off voltage VEH. The scan signal SC may select a subpixel SP of a pixel row to which a data voltage Vdata is to be written. The emission control signal EM may define the emission time of each subpixel SP.

[0056] The gate driver 300 may include a light emission control driver 310 and one or more scan drivers 320. The light emission control driver 310 may output a light emission control signal in response to a start signal and a shift clock signal from the controller 200, and may sequentially shift the light emission control signal according to the shift clock. The one or more scan drivers 320 may output a scan signal in response to a start signal and a shift clock from the controller 200, and may shift the scan signal based on the timing of the shift clock.

[0057] The data driver 400 may convert the image data RGB into the data voltage Vdata based on the data control signal DCS supplied from the controller 200 and may output the data voltage Vdata to the data line DL.

[0058] exist Figure 1, a single data driver 400 is shown disposed on one side of the display panel 100, but the number and arrangement position of the data driver 400 are not limited thereto. That is, the data driver 400 may be configured to have a plurality of integrated circuits (ICs) and may be provided in plurality, and the plurality of data drivers 400 may be separated and disposed on both sides of the display panel 100.

[0059] The power supply 500 can generate the direct current (DC) power required to drive the driver of the display panel and the sub-pixel array of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a transformer, a buck converter, and a boost converter. The power supply 500 can receive a DC input voltage applied from a host system (not shown) to generate DC voltages, such as a gate-on voltage VGL (VEL), a gate-off voltage VGH (VEH), a high-level voltage EVDD, and a low-level voltage EVSS. The gate-on voltage VGL (VEL) and the gate-off voltage VGH (VEH) can be supplied to a level converter (not shown) and the gate driver 300. The high-level voltage EVDD and the low-level voltage EVSS can be commonly supplied to a plurality of sub-pixels SP.

[0060] like Figure 1 and Figure 2 As shown, the gate driver 300 may include a light emission control driver 310 and a scan driver 320. The scan driver 320 may include a first scan driver 321, a second scan driver 322, a third scan driver 323, and a fourth scan driver 324. In addition, the second scan driver 322 may include an odd-numbered second scan driver 322O and an even-numbered second scan driver 322E.

[0061] The shift registers constituting the gate driver 300 may be symmetrically arranged on both sides of the display area AA. The shift registers on one side of the display area AA may include second scan drivers 322O and 322E, a fourth scan driver 324, and a light emission control driver 310, while the shift registers on the other side of the display area AA may include a first scan driver 321, second scan drivers 322O and 322E, and a third scan driver 323. Figure 2 , an example of a structure in which the odd second scan driver 322O and the even second scan driver 322E have a structure in which the odd sub-pixels and the even sub-pixels share the second scan driver 322 is shown. The arrangement configuration of the light emission control driver 310 and the first to fourth scan drivers 321 to 324 is not limited to Figure 2 The arrangement configuration of the light emission control driver 310 and the first to fourth scan drivers 321 to 324 can be the same as Figure 2 Implemented differently.

[0062] The stages STG1 to STGn of the shift register may respectively include a plurality of first scan signal generators 321 , a plurality of second scan signal generators 322O and 322E, a plurality of third scan signal generators 323 , a plurality of fourth scan signal generators 324 , and a plurality of light emitting control signal generators 310 .

[0063] The first scan signal generator 321 can output first scan signals SC1(1) to SC1(n) respectively through the first scan lines of the display panel 100. The second scan signal generators 322O and 322E can output second scan signals SC2O(1) to SC2O(n) and SC2E(1) to SC2E(n) respectively through the second scan lines of the display panel 100. The third scan signal generator 323 can output third scan signals SC3(1) to SC3(n) respectively through the third scan lines of the display panel 100. The fourth scan signal generator 324 can output fourth scan signals SC4(1) to SC4(n) respectively through the fourth scan lines of the display panel 100. The emission control signal generator 310 can output emission control signals EM(1) to EM(n) respectively through the emission lines EML of the display panel 100.

[0064] The first scan signals SC1(1) to SC1(n) can be used as signals for driving the Ath transistor (e.g., compensation transistor) included in the sub-pixel driving circuit. The second scan signals SC2(1) to SC2(n) can be used as signals for driving the Bth transistor (e.g., data supply transistor) included in the sub-pixel driving circuit. The third scan signals SC3(1) to SC3(n) can be used as signals for driving the Cth transistor (e.g., bias transistor) included in the sub-pixel driving circuit. The fourth scan signals SC4(1) to SC4(n) can be used as signals for driving the Dth transistor (e.g., initialization transistor) included in the sub-pixel driving circuit. The light-emitting control signals EM(1) to EM(n) can be used as signals for driving the Eth transistor (e.g., light-emitting control transistor) included in the sub-pixel driving circuit. For example, when the light-emitting control transistor is controlled using the light-emitting control signals EM(1) to EM(n), the light-emitting time of the light-emitting device may vary.

[0065] Meanwhile, the configuration and output of the gate driver 300 described above are merely examples and may vary depending on the sub-pixel driving circuit. Figure 5 and Figure 10 The sub-pixel driving circuit SP shown can be supplied with a first scanning signal SC1(n), a second scanning signal SC2(n), a third scanning signal SC3(n), a fourth scanning signal SC3(n) and a light emitting control signal EM(n) to drive the pixel. Figure 11 and Figure 12 The sub-pixel driving circuit SP shown may be supplied with a previous stage first scan signal SC1(n-1), a second scan signal SC2(n), a third scan signal SC3(n) and a light emitting control signal EM(n) to drive pixels.

[0066] A bias voltage line VobsL transmitting the second bias voltage Vobs, a first initialization voltage line ViniL transmitting the first initialization voltage Vini, and a second initialization voltage line VaraL transmitting the second initialization voltage Var may be provided between the gate driver 300 and the display area AA.

[0067] In the accompanying drawings, each of the bias voltage line VobsL, the first initialization voltage line ViniL and the second initialization voltage line VaraL is illustrated as being set on one side of the left side or the right side of the display area AA, but is not limited to this and may also be set on both sides, or even if set on one side, the position is not limited to the left or right side.

[0068] In addition, one or more optical areas OA1 and OA2 may be provided in the display area AA. The optical areas OA1 and OA2 may be provided to overlap with one or more optoelectronic devices (eg, imaging devices such as cameras (image sensors) and sensing sensors such as proximity sensors and illumination sensors).

[0069] The optical areas OA1 and OA2 may have a light-transmitting structure for operation of the optoelectronic device, and thus may have a light transmittance above a certain level. Assuming that the areas other than the optical areas OA1 and OA2 in the display area AA are normal areas, the pixels per inch (PPI) in the optical areas OA1 and OA2 may be lower than the PPI in the normal areas. In other words, the resolution of each of the optical areas OA1 and OA2 may be lower than that of the normal areas.

[0070] In the optical areas OA1 and OA2, a light-transmitting structure can be configured by patterning the cathode in the portion where no sub-pixels are set. In this case, the patterned cathode can be removed using a laser, or the cathode can be selectively formed and patterned using a material such as a cathode deposition prevention layer.

[0071] Furthermore, in the optical areas OA1 and OA2, a light-transmitting structure can be formed by separately forming the light-emitting devices and sub-pixel driving circuits included in the sub-pixels. In other words, the light-emitting devices of the sub-pixels can be arranged in the optical areas OA1 and OA2, and the multiple transistors constituting the sub-pixel driving circuits can be arranged near the optical areas OA1 and OA2. Thus, the light-emitting devices can be electrically connected to the sub-pixel driving circuits via a transparent metal layer.

[0072] Figure 3is a diagram illustrating a stacked structure of a display panel 100 according to an embodiment of the present disclosure.

[0073] like Figure 3 As shown, transistors TFT1 and TFT2 and capacitor CST for driving the light-emitting device OLED can be arranged in the display area AA on the substrate 111 of the display panel 100. One of the transistors TFT1 and TFT2 can include a thin film transistor including a polycrystalline semiconductor material, and the other can include a thin film transistor including an oxide semiconductor material. The thin film transistor including a polycrystalline semiconductor material can be referred to as a polycrystalline thin film transistor TFT1, and the thin film transistor including an oxide semiconductor material can be referred to as an oxide thin film transistor TFT2. For example, the polycrystalline thin film transistor can be the transistor TFT1 connected to the light-emitting device OLED, and the oxide thin film transistor can be the transistor TFT2 connected to the capacitor CST.

[0074] The substrate 111 may include a first substrate layer 111a, a second substrate layer 111b, and a third substrate layer 111c. The first substrate layer 111a and the third substrate layer 111c may be organic layers containing polyimide, and the second substrate layer 111b disposed between the first substrate layer 111a and the third substrate layer 111c may be an inorganic layer containing silicon dioxide (SiO2). The second substrate layer 111b, configured as an inorganic layer, can effectively prevent the penetration of external moisture.

[0075] A lower buffer layer 112a may be formed on the substrate 111. The lower buffer layer 112a may be used to prevent external moisture from penetrating and may be a multi-layered silicon dioxide (SiO2) layer. An auxiliary buffer layer 112b may also be provided on the lower buffer layer 112a to protect the device from moisture penetration.

[0076] The polycrystalline thin film transistor TFT1 may be formed on the substrate 111. The polycrystalline thin film transistor TFT1 may use a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor TFT1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel for electrons or holes to move. The first gate insulating layer 113 may be provided between the first gate electrode GE1 and the first active layer ACT1 and may be an inorganic layer stacked as a single layer or multiple layers, such as silicon nitride (SiN x ) or SiO2 layer.

[0077] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side of the first channel region. The first source region and the first drain region may each be a region made conductive by doping an intrinsic polycrystalline semiconductor material with Group V or Group III impurity ions (e.g., phosphorus (P) or boron (B)) at a certain concentration. The first channel region may maintain the polycrystalline semiconductor material in an intrinsic state and may provide a path for electrons or holes to move.

[0078] According to embodiments, the polycrystalline thin-film transistor TFT1 may be implemented as a top-gate structure in which the first gate electrode GE1 is disposed on the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-blocking layer LS included in the oxide thin-film transistor TFT2 may be formed of the same material as the first gate electrode GE1 and in the same layer. The first gate electrode GE1, the first electrode CST1, and the light-blocking layer LS may be formed using a single mask process, thereby reducing the number of mask processes.

[0079] The first gate GE1 may include a metal material. For example, the first gate GE1 may be a single layer or a multilayer, including one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of the foregoing metals, but is not limited thereto. A first interlayer insulating layer 114 may be provided on the first gate GE1. The first interlayer insulating layer 114 may be made of SiO2 or SiN x form.

[0080] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114, and the polycrystalline thin film transistor TFT1 may include a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 117 and connected to the first source region and the first drain region, respectively.

[0081] The first source electrode SD1 and the first drain electrode SD2 of the polycrystalline thin film transistor TFT1 may be single-layer or multi-layer, and include one of Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or alloys thereof, but not limited thereto.

[0082] The upper buffer layer 115 may separate the second active layer ACT2 of the oxide thin film transistor TFT2 formed of an oxide semiconductor material from the first active layer ACT1 formed of a polycrystalline semiconductor material, and may provide a basis for forming the second active layer ACT2 .

[0083] The second gate insulating layer 116 may cover the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 116 may be formed on the second active layer ACT2 formed of an oxide semiconductor material, and thus, the second gate insulating layer 116 may be formed of an inorganic layer. For example, the second interlayer insulating layer 116 may be made of SiO2 or SiN x form.

[0084] The second gate GE2 may be formed of a metal material, for example, a single layer or multiple layers including one of Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof, but is not limited thereto.

[0085] The oxide thin film transistor TFT2 may be formed on the upper buffer layer 115. The oxide thin film transistor TFT2 may include a second active layer ACT2 formed of an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 117. The second active layer ACT2 may be formed of an oxide semiconductor material and may include an intrinsic second channel region that is not doped with impurities, and second source and second drain regions that are conductive by being doped with impurities.

[0086] The oxide thin film transistor TFT2 may further include a light blocking layer LS disposed below the upper buffer layer 115 and overlapping the second active layer ACT2. The light blocking layer LS may prevent light from being incident on the second active layer ACT2, thereby preventing abnormal operation of the oxide thin film transistor TFT2. The light blocking layer LS may be formed of the same material as the first gate electrode GE1 and may be disposed on the upper surface of the first gate insulating layer 113. The light blocking layer LS may be electrically connected to the second gate electrode GE2 to form a dual gate.

[0087] The second source electrode SD3 and the second drain electrode SD4 may be formed of the same material as the first source electrode SD1 and the first drain electrode SD2 on the second interlayer insulating layer 117 at the same time, and thus the number of mask processes may be reduced.

[0088] Furthermore, the second electrode CST2 may be disposed on the first interlayer insulating layer 114 and overlap the first electrode CST1, thereby forming a capacitor CST. The second electrode CST2 may be, for example, a single layer or multiple layers containing one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.

[0089] The capacitor CST may store a data voltage applied through the data line DL during a certain period. The capacitor CST may include two electrodes corresponding to each other and a dielectric disposed between the two electrodes. A first interlayer insulating layer 114 may be disposed between the first electrode CST1 and the second electrode CST2.

[0090] The first electrode CST1 or the second electrode CST2 of the capacitor CST may be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, the embodiment is not limited thereto, and the connection relationship of the capacitor CST may be changed based on the sub-pixel driving circuit.

[0091] A first planarization layer 118 and a second planarization layer 119 for planarizing the surface may be sequentially provided on the substrate 111 on which the transistors TFT1 and TFT2 and the capacitor CST are formed. Each of the first planarization layer 118 and the second planarization layer 119 may be an organic layer, such as polyimide or acrylic resin. A light-emitting device OLED may be formed on the second planarization layer 119.

[0092] The light-emitting device OLED may include an anode ANO, a cathode CAT, and a light-emitting layer EL disposed between the anode ANO and the cathode CAT. In a sub-pixel driving circuit that shares a low-level voltage connected to the cathode CAT, the anode ANO may be separated and patterned for each sub-pixel. On the other hand, in a sub-pixel driving circuit that shares a high-level voltage, the cathode CAT may be separated and patterned for each sub-pixel.

[0093] The light emitting device OLED can be electrically connected to the driving element through the connection electrode CNE provided on the first planarization layer 118. For example, the anode electrode ANO of the light emitting device OLED and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the sub-pixel driving circuit can be connected to each other through the connection electrode CNE.

[0094] The anode electrode ANO may be connected to the connection electrode CNE exposed through a contact hole passing through the second planarization layer 119. The connection electrode CNE may be connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0095] The connection electrode CNE may be used as a medium for connecting the first source electrode SD1 and the anode electrode ANO. The connection electrode CNE may include a conductive material, such as Cu, Ag, Mo, or Ti.

[0096] The anode ANO can be formed into a multilayer structure including a transparent conductive layer and an opaque conductive layer with high reflection efficiency. The transparent conductive layer may include a material with a relatively large work function value (for example, indium tin oxide (ITO) or indium zinc oxide (IZO)), and the opaque conductive layer may be formed into a single layer or multilayer structure including an alloy of Al, Ag, Cu, lead (Pb), Mo or Ti or the aforementioned metals. For example, the anode ANO can be formed into a structure in which a transparent conductive layer, an opaque conductive layer and a transparent conductive layer are stacked in sequence, or can be formed into a structure in which a transparent conductive layer and an opaque conductive layer are stacked in sequence. The light-emitting layer EL can be formed by stacking a hole-related layer, an organic light-emitting layer and an electron-related layer on the anode ANO in sequence or in reverse order.

[0097] The bank layer BNK may be a sub-pixel defining layer that exposes the anode electrode ANO of each sub-pixel. The bank layer BNK may be formed of an opaque material (e.g., black) to prevent light interference between adjacent sub-pixels. In this case, the bank layer BNK may include a light-blocking material containing at least one of a color pigment, organic black, and carbon.

[0098] The cathode CAT may be formed on the upper surface and side surfaces of the light-emitting layer EL, opposite the anode ANO, with the light-emitting layer EL located between the cathode CAT and the anode ANO. The cathode CAT may be formed integrally to cover the entire display area AA. When the cathode CAT is applied to a top-emission organic light-emitting display device, the cathode CAT may include a transparent conductive layer, such as ITO or IZO.

[0099] An encapsulation layer 120 for preventing water penetration may also be provided on the cathode CAT. Encapsulation layer 120 prevents external water or oxygen from penetrating into the light-emitting layer EL, which is susceptible to external water or oxygen. To this end, encapsulation layer 120 may include, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. Encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123, which are stacked in sequence.

[0100] The first encapsulation layer 121 and the third encapsulation layer 123 may include an inorganic insulating material capable of low temperature deposition, such as SiN x 、SiO x , silicon oxynitride (SiON) or aluminum oxide (Al2O3). The first encapsulation layer 121 and the third encapsulation layer 123 can be deposited in a low-temperature atmosphere. Therefore, when performing the deposition process of the first encapsulation layer 121 and the third encapsulation layer 123, the light emitting layer EL, which is susceptible to the high-temperature atmosphere, can be prevented from being damaged.

[0101] The second encapsulation layer 122 can play a buffering role in reducing interlayer stress caused by bending of the display device 10 and can flatten the step height between layers. The second encapsulation layer 122 can be formed on the substrate 111 formed with the first encapsulation layer 121, and can include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polyethylene, or a non-photosensitive organic insulating material such as silicon oxide carbon (SiOC), or a photosensitive organic insulating material such as photosensitive acrylic, but the embodiment is not limited thereto.

[0102] In the case where the second encapsulation layer 122 is formed by an inkjet process, a dam DAM may be provided to prevent the liquid second encapsulation layer 122 from spreading to the edge of the substrate 111. The dam DAM may be provided closer to the edge of the substrate 111 than the second encapsulation layer 122. The dam DAM may prevent the second encapsulation layer 122 from spreading to the outermost pad region of the substrate 111 where the conductive pad is provided.

[0103] The dam DAM can be designed to prevent the second encapsulation layer 122 from spreading. However, if the second encapsulation layer 122 is formed to a height that exceeds the dam DAM during processing, the second encapsulation layer 122, as an organic layer, may be exposed to the outside, thereby potentially causing water to penetrate the light-emitting device OLED. To address this issue, multiple overlapping dams DAM can be provided.

[0104] The dam DAM may be provided on the second interlayer insulating layer 117 of the non-display area NA. The dam DAM may be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. The first planarization layer 118 may be formed together with the lower layer of the dam DAM, and the second planarization layer 119 may be formed together with the upper layer of the dam DAM. Thus, the dam DAM may be stacked and formed into a double-layer structure. As described above, the dam DAM may include the same material as the first planarization layer 118 and the second planarization layer 119, but the embodiment is not limited thereto.

[0105] The dam DAM may be formed to overlap the low-level voltage line EVSS. For example, the low-level voltage line EVSS may be provided below the area of ​​the non-display area NA where the dam DAM is provided. The low-level voltage line EVSS may be provided outside the gate driver 300 and may surround the display area AA. For example, the low-level voltage line EVSS may include the same material as the first gate electrode GE1, but is not limited thereto and may include the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2. The low-level voltage line EVSS may be electrically connected to the cathode electrode CAT to apply the low-level voltage EVSS to the plurality of sub-pixels included in the display area AA.

[0106] A touch layer may be provided on the encapsulation layer 120. In the touch layer, a touch buffer layer 151 may be provided between the cathode electrode CAT of the light emitting device OLED and the touch sensor metal layer including the touch electrodes 155 and 156 and the touch electrode connection lines 152 and 154.

[0107] The touch buffer layer 151 can prevent external water or chemical agents (e.g., developer or etchant) used in the manufacturing process of the touch sensor metal layer provided on the touch buffer layer 151 from penetrating into the light-emitting layer EL including an organic material. Therefore, the touch buffer layer 151 can prevent the light-emitting layer EL, which is susceptible to chemical solutions or water, from being damaged.

[0108] The touch buffer layer 151 may include an organic insulating material having a low dielectric constant of 1 to 3 and capable of being formed at a low temperature (e.g., 100°C) or lower to prevent damage to the light-emitting layer (EL) comprising organic materials susceptible to high temperatures. For example, the touch buffer layer 151 may include an acrylic material, an epoxy material, or a siloxane-based material. The touch buffer layer 151, comprising an organic insulating material and having planarization properties, can prevent damage to the encapsulation layer 120 caused by device bending and fracture of the touch sensor metal layer formed on the touch buffer layer 151.

[0109] According to the touch sensor structure based on mutual capacitance, touch electrodes 155 and 156 can be provided on the touch buffer layer 151, and the touch electrodes 155 and 156 can be provided so as to intersect with each other. Touch electrode connection lines 152 and 154 can electrically connect the touch electrodes 155 and 156 to each other. The touch electrode connection lines 152 and 154 can be provided in a different layer from the touch electrodes 155 and 156, with the touch insulation layer 153 interposed therebetween. The touch electrode connection lines 152 and 154 can be provided so as to overlap with the bank layer BNK, thereby preventing a decrease in the aperture ratio.

[0110] In the touch electrodes 155 and 156, a portion of the touch electrode connection line 152 may pass through the upper portion and side surfaces of the encapsulation layer 120 and the upper portion and side surfaces of the dam DAM, and may be electrically connected to a touch drive circuit (not shown) through a touch pad PAD. A portion of the touch electrode connection line 152 may be supplied with a touch drive signal from the touch drive circuit and may transmit the touch drive signal to the touch electrodes 155 and 156, or may transmit a touch sensing signal of the touch electrodes 155 and 156 to the touch drive circuit.

[0111] A touch protection layer 157 may be provided on the touch electrodes 155 and 156. In the drawings, the touch protection layer 157 is shown as being provided only on the touch electrodes 155 and 156, but the embodiment is not limited thereto. The touch protection layer 157 may extend to the front or rear portion relative to the dam DAM and may be provided on the touch electrode connection line 152. Furthermore, a color filter (not shown) may be provided on the encapsulation layer 120. The color filter may be provided on the touch layer or between the encapsulation layer 120 and the touch layer.

[0112] Figure 4 is a schematic circuit diagram of a sub-pixel SP according to an embodiment of the present disclosure.

[0113] Reference Figure 4 The subpixel SP may include a driving transistor DT, a first transistor DT, and a light-emitting device OLED. The driving transistor DT may be implemented as a p-type polycrystalline thin-film transistor. The p-type driving transistor DT may be turned on in response to a low voltage. The first transistor T1 may be formed of an n-type oxide thin-film transistor. The n-type driving transistor DT may be turned on in response to a high voltage. The light-emitting device OLED may emit light using a driving current generated by the operation of the driving transistor DT and the first transistor T1.

[0114] The sub-pixel SP may further include a compensation circuit for compensating the driving transistor DT or the light emitting device OLED. The compensation circuit may be configured in different ways.

[0115] Figure 5 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure. Figure 6 and Figure 7 is applied to Figure 5 Driving waveform diagram of sub-pixel. Figure 8 It shows Figure 5 Figure 1 shows the sub-pixel VRR driver.

[0116] Reference Figure 5 , the sub-pixel SP may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a driving transistor DT, a capacitor CST and a light emitting device OLED. Figure 5 In the embodiment of the present invention, the first transistor T1 and the fifth transistor T5 can each be implemented as an n-type oxide thin film transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the driving transistor DT can each be implemented as a p-type polycrystalline thin film transistor. Hereinafter, this composite structure may be referred to as MTO.

[0117] In the sub-pixel SP of the MTO structure, since the first transistor T1 and the fifth transistor T5 implemented as oxide thin film transistors have low leakage current characteristics, low-speed refresh rate driving of the sub-pixel SP is possible, and thus power consumption can be reduced. Figure 5 This is only an embodiment of the sub-pixel SP of the MTO structure, and the embodiment is not limited to Figure 5 .

[0118] In the MTO structured sub-pixel SP, low-speed refresh rate driving is possible based on the low leakage current characteristics of the oxide thin film transistor. To reduce flicker during low-speed driving and reduce the difference in optical characteristics between different frequencies, a first bias voltage Vpark and a second bias voltage Vobs may also be applied to the sub-pixel SP. Each of the first bias voltage Vpark and the second bias voltage Vobs may be a direct current (DC) voltage fixed to a specific voltage level.

[0119] The first transistor T1 may include a gate to which a first scan signal SC1(n) is applied, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be turned on in response to the first scan signal SC1(n). When the first transistor T1 is turned on, a threshold voltage of the driving transistor DT may be sampled and stored at the second node N2.

[0120] The second transistor T2 may include a gate to which a second scan signal SC2(n) is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second transistor T2 may be turned on in response to the second scan signal SC2(n). When the second transistor T2 is turned on, the data voltage Vdata charged in the data line DL may be applied to the first node N1. During a vertical blank period, the voltage of the data line DL may be switched from the data voltage Vdata to the first bias voltage Vpark, thereby helping to adjust the brightness.

[0121] The third transistor T3 may include a gate to which the light emission control signal EM(n) is applied, a first electrode connected to the high-level voltage line EVDD, and a second electrode connected to the first node N1. The third transistor T3 may be turned on in response to the light emission control signal EM(n). When the third transistor T3 is turned on, a high-level voltage applied via the high-level voltage line EVDD may be transmitted to the first node N1.

[0122] The fourth transistor T4 may also be referred to as a light emission control transistor and includes a gate to which a light emission control signal EM(n) is applied, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light-emitting device OLED. The fourth transistor T4 may be turned on in response to the light emission control signal EM(n). When the fourth transistor T4 is turned on, a drive current generated by the drive transistor DT may be applied to the light-emitting device OLED. The light-emitting device OLED may emit light based on the drive current applied from the drive transistor DT.

[0123] The fifth transistor T5 may include a gate to which the fourth scan signal SC4(n) is applied, a first electrode connected to the first initialization voltage line ViniL, and a second electrode connected to the second node N2. The fifth transistor T5 may be turned on in response to the fourth scan signal SC4(n). When the fifth transistor T5 is turned on, the first initialization voltage Vini applied via the first initialization voltage line ViniL may be transmitted to the second node N2. When the fifth transistor T5 is turned on, the charge held in each of the second electrode of the capacitor CST and the gate of the drive transistor DT connected to the second node N2 may be initialized.

[0124] The sixth transistor T6 may include a gate to which the third scan signal SC3(n) is applied, a first electrode connected to the second initialization voltage line VaraL, and a second electrode connected to the anode of the light-emitting device OLED. The sixth transistor T6 may be turned on in response to the third scan signal SC3(n). When the sixth transistor T6 is turned on, the second initialization voltage Var applied via the second initialization voltage line VaraL may be transmitted to the anode of the light-emitting device OLED. When the sixth transistor T6 is turned on, the charge retained in the anode of the light-emitting device OLED may be initialized.

[0125] The seventh transistor T7 may include a gate to which the third scan signal SC3(n) is applied, a first electrode connected to the second bias voltage line VobsL, and a second electrode connected to the first node N1. The seventh transistor T7 may be turned on in response to the third scan signal SC3(n). When the seventh transistor T7 is turned on, the second bias voltage Vobs applied via the second bias voltage line VobsL may be transmitted to the first node N1. When the seventh transistor T7 is turned on, the drive transistor DT connected to the first node N1 may maintain a stronger saturation state based on the second bias voltage Vobs. Based on the on-bias stress operation, the hysteresis of the drive transistor DT may be further reduced.

[0126] As the level of the second bias voltage Vobs used for the on-bias stress operation increases, the voltage of the third node N3 (which is the drain of the drive transistor DT) increases, and the gate-source voltage or drain-source voltage of the drive transistor DT decreases. Therefore, the level of the second bias voltage Vobs can preferably be at least higher than the level of the data voltage Vdata. Under this condition, the stress of the drive transistor DT and the magnitude of the drain-source current Id flowing through the drive transistor DT can be reduced, thereby reducing the charging delay of the third node N3. When the on-bias stress operation is performed before and after the threshold voltage of the drive transistor DT is sampled, the hysteresis of the drive transistor DT can be further alleviated.

[0127] The driving transistor DT may include a gate connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The driving transistor DT may be driven based on the data voltage Vdata of the compensated threshold voltage and may generate a driving current.

[0128] The capacitor CST may include a first electrode connected to the high-level voltage line EVDD and a second electrode connected to the second node N2. The capacitor CST may store the data voltage Vdata of the compensated threshold voltage for a certain period of time.

[0129] The light emitting device OLED may include an anode connected to the second electrode of the fourth transistor T4 and a cathode connected to the low-level voltage line EVSS. The light emitting device OLED may emit light based on the driving current transmitted to the turned-on fourth transistor T4.

[0130] In the VRR mode, a portion of the plurality of frames driving the display panel 100 may be refresh frames performing a data programming operation, and the other frames may be anode reset frames performing an anode reset operation.

[0131] Reference Figure 1 、 Figure 5 and Figure 6 , the refresh frame may include a first bias period OBS1, an initialization period INI, a sampling period SAM, a second bias period OBS2, and a light emitting period EMS.

[0132] During the first bias period OBS1, the emission control signal EM, the first scan signal SC1, and the second scan signal SC2 may be applied as a high voltage H, and the third scan signal SC3 and the fourth scan signal SC4 may be applied as a low voltage L. During the first bias period OBS1, the sixth transistor T6 and the seventh transistor T7 may be turned on, and the other transistors may be turned off.

[0133] During the first bias period OBS1, the second bias voltage Vobs may be applied to the first electrode (or first node) of the driving transistor DT, and the second initialization voltage Var may be applied to the anode of the light emitting device OLED. Before the sampling period SAM, when the second bias voltage Vobs is directly applied to the first electrode of the driving transistor DT, the hysteresis of the driving transistor DT may be alleviated.

[0134] During the initialization period INI, the emission control signal EM, the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4 may be applied as the high voltage H, and the first scan signal SC1 may be applied as the low voltage L and then may be applied as the high voltage H. During the initialization period INI, the fifth transistor T5 may be turned on.

[0135] During the initialization period INI, a first initialization voltage Vini may be applied to the second node N2 , and the gate electrode of the driving transistor DT and the second electrode of the capacitor CST may be initialized to the first initialization voltage Vini.

[0136] During the sampling period SAM, the emission control signal EM, the first scan signal SC1, and the third scan signal SC3 may be applied as a high voltage H, and the second scan signal SC2 and the fourth scan signal SC4 may be applied as a low voltage L. During the sampling period SAM, the first transistor T1, the second transistor T2, and the driving transistor DT may be turned on, and the other transistors may be turned off.

[0137] During the sampling period SAM, the data voltage Vdata charged in the data line DL can be transmitted to the second node N2 through the second transistor T2, the driving transistor DT, and the first transistor T1. During this process, the threshold voltage Vth of the driving transistor DT can be sampled and reflected in the voltage of the second node N2. During the sampling period SAM, the gate and the second electrode of the driving transistor DT can be in a diode connection state, and the voltage of the second node N2 can be set to "Vdata-|Vth|" based on the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0138] During the second bias period OBS2, the emission control signal EM, the first scan signal SC1, and the second scan signal SC2 may be applied as a high voltage H, and the third scan signal SC3 and the fourth scan signal SC4 may be applied as a low voltage L. During the second bias period OBS2, the sixth transistor T6 and the seventh transistor T7 may be turned on, and the other transistors may be turned off.

[0139] During the second bias period OBS2, the second bias voltage Vobs may be applied again to the first electrode (or first node) of the driving transistor DT, and the second initialization voltage Var may be applied again to the anode of the light-emitting device OLED. After the sampling period SAM is performed, when the second bias voltage Vobs is applied again to the first electrode of the driving transistor DT, the hysteresis of the driving transistor DT may be further alleviated.

[0140] During the light emission period EMS, the light emission control signal EM, the first scan signal SC1, and the fourth scan signal SC4 may be applied as a low voltage L, and the second scan signal SC2 and the third scan signal SC3 may be applied as a high voltage H. During the light emission period EMS, the third transistor T3, the fourth transistor T4, and the driving transistor DT may be turned on, and the other transistors may be turned off.

[0141] During the emission period EMS, the driving current flowing through the driving transistor DT may be independent of the threshold voltage Vth of the driving transistor DT. The driving current may be applied to the light emitting device OLED through the fourth transistor T4 to cause the light emitting device OLED to emit light.

[0142] In addition, refer to Figure 1 、 Figure 5 and Figure 7 , the anode reset frame may include a third bias period OBS3 and a light emitting period EMS.

[0143] During the third bias period OBS3, the emission control signal EM and the second scan signal SC2 may be applied as a high voltage H, and the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 may be applied as a low voltage L. During the third bias period OBS3, the sixth transistor T6 and the seventh transistor T7 may be turned on, and the other transistors may be turned off.

[0144] During the third bias period OBS3 , the second bias voltage Vobs may be applied to the first electrode (or first node) of the driving transistor DT, and the second initialization voltage Var may be applied to the anode electrode of the light emitting device OLED.

[0145] During the third bias period OBS3, the light emitting device OLED can stop emitting light based on the second initialization voltage Var applied to the anode of the light emitting device OLED. Based on the third bias period OBS3, the problem that the brightness of the anode reset frame is higher than that of the refresh frame can be solved.

[0146] During the emission period EMS, the emission control signal EM, the first scan signal SC1, and the fourth scan signal SC4 may be applied as a low voltage L, and the second scan signal SC2 and the third scan signal SC3 may be applied as a high voltage H. During the emission period EMS, the third transistor T3, the fourth transistor T4, and the driving transistor DT may be turned on, and the other transistors may be turned off.

[0147] During the emission period EMS, the driving current flowing through the driving transistor DT may be independent of the threshold voltage Vth of the driving transistor DT. The driving current may be applied to the light emitting device OLED through the fourth transistor T4 to cause the light emitting device OLED to emit light.

[0148] Reference Figure 1 and Figure 8 , the display panel 100 can operate in VRR mode. VRR can be a driving mode in which the display panel is driven at a certain driving frequency, and then increases or decreases the refresh rate required to update the data voltage Vdata based on high-speed driving or low-speed driving conditions to reduce power consumption. For example, in VRR mode, the display panel 100 can be driven at 120 Hz (1 frame = 1 / 120 second), or can be driven at 60 Hz (1 frame = 1 / 60 second), or can be driven at 24 Hz (1 frame = 1 / 24 second). In addition, in VRR mode, the display panel 100 can be driven at 10 Hz (1 frame = 1 / 10 second), or can be driven at 1 Hz (1 frame = 1 second).

[0149] Under high-speed driving conditions such as 120 Hz, each frame can be configured to have one refresh frame. Under 60 Hz driving conditions, each frame can be configured to have one refresh frame and one anode reset frame. Under 24 Hz driving conditions, each frame can be configured to have one refresh frame and four anode reset frames.

[0150] In the refresh frame, the data voltage Vdata can be written into the display panel 100, based on which the gate-source voltage of the driving transistor DT can be set. On the other hand, in the anode reset frame, the operation of writing the data voltage Vdata into the display panel 100 can be omitted. Therefore, the anode reset frame can be called a skip frame.

[0151] The anode reset frame can be a subframe that completes a frame. The anode reset frame can be implemented under conditions where there is little motion in the image or a still image is displayed (for example, under low-speed driving conditions). The gate-source voltage of the drive transistor set in the refresh frame can be continuously maintained in the anode reset frame.

[0152] In addition, the display device according to the present disclosure can drive the display panel by a driving method (defined herein as "EM PWM") that increases the driving current applied to the light-emitting device based on the light-emitting control signal EM in one frame instead of reducing the time for driving the light-emitting device (defined herein as "EM On time").

[0153] When the display panel 100 is driven at low brightness without EM PWM driving, a low drive current may flow through the light-emitting device. In this case, the light-emitting device may not be fully charged during the non-driving period of the light-emitting device (defined herein as "EMOff time"). As a result, pixels (or sub-pixels) may emit less than the required brightness in the display panel, and uneven brightness may occur under low brightness driving.

[0154] On the other hand, when EM PWM driving is performed, the EM ON time can be reduced, and the light-emitting device can be fully charged by the high drive current flowing for a short time. Therefore, compared with other driving methods, EM PWM driving can more easily achieve the desired brightness. In particular, it can more easily reduce the brightness unevenness that occurs with low-brightness driving.

[0155] Figure 9A and Figure 9B This is a diagram showing an example of the number of times the voltage of a data line changes depending on the refresh rate in VRR driving.

[0156] Reference Figure 9A and Figure 9B ,Under high-speed driving conditions, in VRR driving, the number of voltage changes on the ,data line based on the refresh rate may be relatively large.

[0157] For example, in Figure 9A In the embodiment of the present invention, when the frame frequency is 120 Hz, each frame can be configured to have one refresh frame. The refresh frame may include a vertical display period and a vertical blank period. During the vertical display period, the voltage of the data line may maintain the data voltage Vdata, and then during the vertical blank period, the data voltage Vdata may be switched to the first bias voltage Vpark. When the frame frequency is 120 Hz, the number of times the voltage of the data line switches from the data voltage Vdata to the first bias voltage Vpark may be 12 times.

[0158] In another example, Figure 9BIn the embodiment of the present invention, when the frame frequency is 10 Hz, each frame can be divided into one refresh frame and eleven anode reset frames. During the vertical display period of the refresh frame, the data voltage Vdata can be maintained, and then can be switched to the first bias voltage Vpark during the vertical blank period of the refresh frame. In addition, during the eleven anode reset frames, the voltage of the data line can maintain the first bias voltage Vpark. When the frame frequency is 10 Hz, the number of times the voltage of the data line is switched from the data voltage Vdata to the first bias voltage Vpark can be one.

[0159] The first bias voltage Vpark may be a DC voltage fixed to a specific voltage level, but the data voltage Vdata may vary between multiple optical bands and multiple grayscales. Therefore, the level of the first bias voltage Vpark may be greater than or less than the level of the data voltage Vdata.

[0160] Figure 10 The voltage change of the data line due to the coupling effect is reflected in Figure 5 FIG. 1 is a diagram of an example of the voltage at the gate node of the driving transistor in a sub-pixel.

[0161] Reference Figure 10 The gate node (e.g., the second node N2) of the driving transistor and the data line DL may be arranged to overlap each other, with one or more insulating layers interposed between the gate node of the driving transistor and the data line DL. A parasitic capacitor Cpara may be formed at the location where the second node N2 overlaps the data line DL.

[0162] In the MTO subpixel SP circuit, a first bias voltage Vpark for VRR driving can be applied to the data line DL during the vertical blank period of the anode reset frame and the refresh frame. When the first bias voltage Vpark is applied, the voltage of the data line DL can be switched from the data voltage Vdata to the first bias voltage Vpark. At this time, since the data line DL is coupled to the second node N2 via the parasitic capacitor Cpara, the gate voltage of the drive transistor may vary due to the voltage variation of the data line.

[0163] When the gate voltage of the driving transistor varies during the vertical blank period of a refresh frame, horizontal banding non-uniformity (hereinafter defined as "HBM") may occur in the screen of the display panel 100. The horizontal banding non-uniformity may be a type of brightness distortion and may indicate dark blocks having banding.

[0164] Figure 11 is a circuit diagram of a sub-pixel according to another embodiment of the present disclosure. Figure 12 The voltage change of the data line due to the coupling effect is reflected in Figure 11FIG. 1 is a diagram of an example of the voltage at the gate node of the driving transistor in a sub-pixel.

[0165] and Figure 10 compared to, Figure 11 and Figure 12 The sub-pixel SP circuit may differ in that: i) the seventh transistor T7 is omitted, ii) the fifth transistor T5 is turned on in response to the previous first scan signal SC1(n-1), iii) the second transistor T2 and the sixth transistor T6 are turned on in response to the third scan signal SC3(n), and iv) the data voltage Vdata and the first bias voltage Vpark and the second bias voltage Vobs are time-divisionally supplied to the sub-pixel circuit through the data line.

[0166] Reference Figure 11 and Figure 12 In the sub-pixel SP circuit of the MTO structure, a first bias voltage Vpark for VRR driving can be applied to the data line DL during the vertical blank period of the anode reset frame and the refresh frame. When the first bias voltage Vpark is applied, the voltage of the data line DL can be switched from the data voltage Vdata to the first bias voltage Vpark. At this time, since the data line DL is coupled to the second node N2 via the parasitic capacitor Cpara, the gate voltage of the drive transistor may vary due to the voltage variation of the data line. When the gate voltage of the drive transistor varies during the vertical blank period of the refresh frame, HBM may also occur in the screen of the display panel 100.

[0167] Figure 13 is a graph showing HBM, which is a brightness defect caused by coupling between a data line and a gate node of a driving transistor.

[0168] Reference Figure 13 When the voltage of the data line DL switches from the data voltage Vdata to the first bias voltage Vpark during the vertical blank period, the gate voltage of the driving transistor may vary due to the voltage variation of the data line in all sub-pixels SP of the display panel 100. However, only the brightness of the pixel row that is in the EM On state and emits light may be affected by the gate voltage variation of the driving transistor, and HBM may occur.

[0169] Because the HBM phenomenon only affects the brightness of pixel rows that include EM-On pixels and emit light, the thickness of the HBM may vary depending on the EM-On duty cycle. In the high-brightness optical band (Band A), where the EM-On duty cycle is relatively large, the brightness change time affected by coupling (i.e., the time required to reduce or increase the brightness) may be longer, and therefore the HBM thickness may be relatively thick.

[0170] On the other hand, in the low-brightness optical band (Band B) where the EM On duty cycle is relatively small, the brightness change time affected by coupling (i.e., the time required to reduce the brightness or the time required to increase the brightness) may be short, so the thickness of the HBM may be relatively thin.

[0171] The following will refer to Figures 14 to 16 Describe the pathogenesis of HBM in detail.

[0172] exist Figure 14 and Figure 15 In the aa region, the pixel row in the EM On state can enter the vertical blank period, so the period affected by the switching caused by coupling can gradually increase. Therefore, the brightness in the aa region can gradually decrease.

[0173] also, Figure 14 and Figure 15 The bb indicates that all pixel rows in the EM On state enter the vertical blank period. At this time, since the period length affected by the switching caused by coupling does not reach the maximum state, the low brightness state can be maintained.

[0174] exist Figure 14 and Figure 15 In the CC, the pixel rows in the EM On state can enter the vertical blank period, so the period affected by the switching caused by coupling can be gradually reduced. Therefore, the brightness in the CC area can be gradually improved.

[0175] exist Figures 14 to 16 In the embodiment of the present invention, for the convenience of description, the EM On / Off operation is shown to be performed once, but the EM On / Off operation can be performed multiple times within one frame. Therefore, multiple HBMs can occur in the display panel during the vertical blanking period.

[0176] like Figure 16 As shown, the voltage change of the data line DL may affect the gate voltage (N2 voltage) of the driving transistor (for example, the voltage of N2 increases), so the brightness of the pixel row that emits light during the vertical blank period may change (for example, decrease), and multiple HBMs may occur in the display panel.

[0177] Figure 17 and Figure 18 is a diagram showing an example in which the shape of the HBM changes based on the EM On duty ratio.

[0178] As described above for the HBM mechanism, the HBM phenomenon may occur only in a pixel row in the EM On state, and thus the shape of the HBM may vary based on the change in the EM On duty cycle.

[0179] Figure 17 The case where the EM On duty cycle is A% is shown. Figure 18 Shows the case where the EM On duty ratio is B%. When A < B, comparing the shapes of the HBMs, it can be seen that when the EM On duty ratio is B%, the number of pixel rows affected by coupling is relatively large, so the shape of the HBM increases more.

[0180] As Figure 17 shown, when the EM On duty ratio is A%, the widths of the HBM can be a, b, and c, as Figure 18 shown, when the EM On duty ratio is B% which is greater than A%, the widths of the HBM can be A, B, and C. Here, the relationships A > a, B > b, and C > c can be established.

[0181] Figure 19 is a diagram showing a driving method of a display device for reducing HBM according to the present disclosure. Figure 20 and Figure 21 is a diagram showing the occurrence of HBM when the voltage of the data line switches from the data voltage to the first bias voltage during the blank period or the anode reset frame. Figure 22 and Figure 23 is a diagram showing an example of calculating the EM profile by reflecting the change in the duty ratio of the emission control signal EM. Figure 24 is a diagram showing an example of calculating the compensation curve and the occurrence position of HBM based on the result of integrating the EM profile during the blank period. Figure 25 is a diagram showing an example of applying the position-based HBM compensation value to the calculated compensation curve to calculate the final compensation profile. Figure 26 is a diagram showing an example of reducing HBM through the final compensation profile.

[0182] Referring to Figure 19 and Figure 20 , during the vertical blank period, when the first bias voltage Vpark is applied to the data line, the voltage of the data line can be switched from the data voltage Vdata to the first bias voltage Vpark (S110).

[0183] The first bias voltage Vpark can be a voltage of a fixed level. On the other hand, the data voltage Vdata can be a level voltage that changes according to the gray level. The amount of voltage change of the data line can vary according to the data gray level (that is, the level of the data voltage). For example, at a voltage level of Vdata' higher than Vdata, the amount of voltage change may be relatively small, while at a voltage level of Vdata" lower than Vdata, the amount of voltage change may be relatively large.

[0184] In a sub-pixel connected to a data line, the gate node of the driving transistor may be coupled to the data line through a parasitic capacitor. Based on the coupling effect, a voltage change of the data line may be reflected in the voltage of the gate node of the driving transistor. Therefore, the gate voltage of the driving transistor may change, and thus the gate-source voltage Vgs of the driving transistor may change. Figure 21 As shown, HBM may occur in the display panel 100 ( S120 ).

[0185] In order to calculate the HBM occurrence position, Figure 22 As shown in FIG. 1 , the controller may calculate the EM profile in the vertical blank period (S130). In the case of calculating the EM profile, as shown in FIG. Figure 23 As shown, the controller can reflect the changes in the EM On duty cycle (T1, T2, etc.) based on the gray level and light band.

[0186] The controller may calculate the EM profile based on the EM On duty ratio of the vertical blank period, and thus may effectively calculate the compensation profile according to the HBM whose shape varies based on the EM On duty ratio.

[0187] The controller may integrate the EM profile during the vertical blank period according to the following Equation 1 to calculate a compensation curve corresponding to the HBM occurrence position ( S140 ).

[0188] Formula 1

[0189]

[0190] like Figure 22 As shown in FIG. 1 , a coupling effect based on the first bias voltage Vpark may occur in the vertical blank period. Therefore, in Formula 1, EM profile (V) represents the result of integrating the light emitting control signal EM of the vertical pixel row V from time "T=T1" to time "T=T2=T1+Blank", where "T1" represents the time when the blank period starts, "T2" represents the time when the blank period ends, "EM(duty, T, V)" represents the function of the light emitting control signal EM of the vertical pixel row V with respect to time T, "duty" represents the duty cycle of the light emitting control signal EM, and "Blank" represents the duration of the blank period. In other words, the result EM of integrating the light emitting control signal EM profile (V) Figure 23 The right curve of . Figure 24 is the compensation curve relative to vertical pixel rows.

[0191] To provide additional description, a graph shown in the vertical direction by integrating the profile of EM during a blanking period (e.g., 8.33 milliseconds for 120 Hz) is Figure 24The HBM generation position may correspond to the pixel row in the EM On state and may be set at the top, middle, and bottom of the display panel. Figure 24 The compensation curve of FIG. 1 shows the magnitude of compensation values ​​for compensating HBM at multiple locations. Therefore, in the compensation curve, the magnitude of compensation may be different between the HBM non-occurrence location and the HBM occurrence location.

[0192] Based on the IR drop (eg, potential difference) effect, the HBM size at each location may be different. The controller may also calculate a final compensation profile based on the location-based HBM size differences (S150).

[0193] To this end, the controller may calculate a position-based gain α to compensate for the position-based HBM size, and may multiply the result of integrating the EM profile by the position-based gain α to obtain a final compensated profile HBM IP(V), as shown in Equation 2 below.

[0194] Formula 2

[0195] HBM IP(V)=EM profile (V)×α(V), α: Gain based on panel position

[0196] like Figure 25 As shown, the controller can apply HBM compensation values ​​in different ways based on the location of HBM. The magnitude of the HBM compensation value can be adjusted to be proportional to the amount of IR drop. When the magnitude of the IR drop in the display panel is highest at the top, second highest in the middle, and lowest at the bottom, the controller can apply the HBM compensation value so that it is highest at the top, second highest in the middle, and lowest at the bottom.

[0197] The controller can compensate the image data to be written to the corresponding position based on the HBM compensation data corresponding to each position where HBM occurs, thereby completing the HBM compensation operation (S160). Figure 26 As shown, the luminance deviation (HBM) generated in the display panel 100 can be eliminated, and thus, the image quality can be improved.

[0198] Figure 27 and Figure 28 is a diagram showing an example of differently setting the HBM compensation value based on the display grayscale and the light wavelength band.

[0199] As described above, the HBM compensation algorithm can detect the HBM position by calculating the EM profile of the vertical blank period, and can calculate and apply the compensation profile to the position where the HBM occurs, thereby compensating for the HBM.

[0200] like Figure 27As shown in the figure, HBM may occur due to coupling between the data line and the N2 node, indicating that the magnitude of HBM varies depending on the level of ΔVdata to Vpark. When the level of the first bias voltage Vpark is fixed and the level of the data voltage Vdata varies, the level of ΔVdata to Vpark may vary. As a result, the amount of coupling at the N2 node may vary, which may ultimately cause a change in the Vgs value of the drive transistor, thereby affecting the magnitude of HBM.

[0201] The first bias voltage Vpark may be fixed to a specific value within the same optical band, and thus the level of ΔVdata˜Vpark may vary according to the display grayscale and the optical band.

[0202] like Figure 28 As shown, the lookup table LUT can be configured to compensate and reduce HBM regardless of the display grayscale and optical bands 1, 2, and 3 when the optimal gain for each condition is applied.

[0203] To this end, a lookup table LUT may be provided corresponding to the representative optical bands 1, 2, and 3. In the lookup table LUT corresponding to the representative optical bands 1, 2, and 3, different gain values ​​may be mapped to display grayscales.

[0204] Furthermore, gain values ​​corresponding to respective display grayscales of wavelength bands disposed between the representative light wavelength bands may be obtained by interpolating corresponding gain values ​​of the representative light wavelength bands.

[0205] Figure 29 Graphs showing the luminance difference before and after HBM compensation at representative positions of a display panel.

[0206] Reference Figure 29 ,It can be seen that the brightness variation width is greatly improved by HBM compensation.

[0207] The HBM generated due to the coupling between the data line and the gate node of the driving transistor can be clearly identified in the low-brightness light band, and as described in this embodiment, when the HBM compensation operation is performed in real time, the HBM occurring due to the coupling effect in the low-brightness light band can be effectively reduced.

[0208] In addition, this embodiment can reduce the light emitting time and increase the current flowing through the light emitting device through EM PWM driving, thereby reducing the brightness unevenness occurring under low brightness driving.

[0209] The effects according to the present disclosure are not limited to the above-described examples, and other various effects may be included in the specification.

[0210] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

[0211] These and other modifications can be made to the embodiments based on the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the scope of the claims is not limited by what is disclosed.

Claims

1. A display device comprising: Display panel, including: a sub-pixel and a data line connected to the sub-pixel, the sub-pixel having a light-emitting device configured to emit light based on a duty cycle of a light-emitting control signal and a driving transistor configured to supply a driving current to the light-emitting device; The controller is configured as: When the voltage of the data line is switched from the data voltage to the bias voltage during a vertical blank period of one frame, a compensation value for compensating for abnormal brightness variation of the display panel based on coupling between the gate node of the driving transistor and the data line is obtained; and correcting a data signal to be written to the display panel based on the compensation value; and The data driver is configured to convert the corrected data signal into a data voltage and output the data voltage to the data line.

2. The display device according to claim 1, wherein A gate voltage of the driving transistor varies based on a voltage variation of the data line.

3. The display device according to claim 1, wherein The controller calculates a light emitting control signal profile, ie, an EM profile, based on a duty ratio of the light emitting control signal during the vertical blank period of the one frame, and detects a position where an abnormal brightness change occurs in the display panel.

4. The display device according to claim 3, wherein During the vertical blank period, the controller integrates the EM profile to calculate the compensation value corresponding to the position where the abnormal brightness change occurs.

5. The display device according to claim 4, wherein During the vertical blank period, the controller reflects a position-based first gain value of the display panel based on an IR drop in the compensation value. The display device according to claim 4 , wherein: During the vertical blank period, the controller reflects a second gain value independently set based on a light wavelength band and a display grayscale in the compensation value.

7. A method for driving a display device including a display panel, the method comprising: obtaining a compensation value for compensating for abnormal brightness variation of a display panel due to coupling between a gate node of a driving transistor and the data line when a voltage of the data line is switched from a data voltage to a bias voltage during a vertical blank period of one frame, and correcting a data signal to be written to the display panel based on the compensation value, wherein the data line is connected to a sub-pixel included in the display panel; converting the corrected data signal into a data voltage; and outputting the data voltage to the data line, wherein the light emitting device included in the sub-pixel emits light according to the duty cycle of the light emitting control signal, and The driving transistor included in the sub-pixel supplies a driving current to the light emitting device.

8. The driving method according to claim 7, wherein: A gate voltage of the driving transistor varies based on a voltage variation of the data line.

9. The driving method according to claim 7, further comprising: calculating an EM profile based on the duty cycle of the light emitting control signal during the vertical blank period of the one frame; as well as A position where an abnormal brightness change occurs in the display panel is detected.

10. The driving method according to claim 9, further comprising: The EM profile is integrated during the vertical blanking period to calculate the compensation value corresponding to the position where the abnormal brightness change occurs. 11 . The driving method of claim 10 , further comprising reflecting a position-based first gain value of the display panel based on an IR drop in the compensation value during the vertical blank period. 12 . The driving method according to claim 10 , further comprising reflecting a second gain value independently set based on a light wavelength band and a display grayscale in the compensation value during the vertical blank period.

13. A display device comprising: Display panel, including: a sub-pixel having a light-emitting device, a light-emitting control transistor, and a driving transistor; a scan line connected to a gate node of the driving transistor; a data line connected to the first node of the driving transistor; controller, wherein the first node of the light emission control transistor is connected to the second node of the driving transistor, the second node of the light emission control transistor is connected to the light emitting device, and a light emission control signal is applied to the gate node of the light emission control transistor, and The controller obtains the compensation value by integrating the light emitting control signal during a vertical blank period.

14. The display device according to claim 13, wherein: When the voltage of the data line is switched to a bias voltage during a vertical blank period, coupling occurs between the gate node of the driving transistor and the data line.

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