Dynamic impedance adjustment device for semiconductor signal circuit and adjustment method thereof

Abstract

Embodiments of the present application provide a dynamic impedance adjustment device for a semiconductor signal circuit and an adjustment method thereof, and belong to the technical field of semiconductor signal detection. The dynamic impedance adjustment device comprises: a first adjustment unit, which is configured to electrically connect a first switch array and a first resistance array to perform binary coarse adjustment through different resistance value combinations to determine a target resistance value to preliminarily match impedance; a second adjustment unit, which is configured to electrically connect a second switch array and a second resistance array to perform sub-ohm step linear fine adjustment to precisely correct the target resistance value obtained through the first adjustment unit to complete impedance matching; and a control unit, which is electrically connected to the first adjustment unit and the second adjustment unit to control the on-off of each switch in the first switch array and the second switch array. The dynamic impedance adjustment device of the present application performs high-precision real-time dynamic adjustment on impedance matching through the mixed adjustment of coarse adjustment of combined resistance and fine adjustment of small resistance value by means of multi-switch series connection resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor signal detection, and in particular to a dynamic impedance adjustment device for a semiconductor signal circuit and an adjustment method thereof. BACKGROUND

[0002] In high-speed digital communication (such as 5G / 6G, high-speed SerDes) and radio frequency systems, the impedance matching accuracy of the signal transmission line directly determines the signal integrity and system performance. The traditional impedance adjustment technology has the following bottlenecks: (1) Adjustment mode lags behind: mechanical potentiometers need to be manually calibrated and cannot adapt to real-time dynamic environmental changes; digital potentiometers (DigiPOT) rely on MOS switches, and the on-resistance and parasitic capacitance cause precision drift, and the isolation is insufficient at high frequencies. (2) Conflict between speed and power consumption: the switching speed of the MOS-based resistance array is limited (microsecond level), which is difficult to meet the nanosecond-level signal compensation requirement; large-size relay switches have high power consumption and bulky size, and cannot be integrated on high-density PCBs. (3) Precision and range are difficult to balance, and existing impedance adjustment methods cannot optimize both.

[0003] Therefore, the present application provides a new dynamic impedance adjustment device for a semiconductor signal circuit and an adjustment method thereof to solve the above problems. SUMMARY

[0004] In order to solve at least one aspect of the above problems and defects in the prior art, embodiments of the present application provide a dynamic impedance adjustment device for a semiconductor signal circuit and an adjustment method thereof, which controls a plurality of MESE switches in series with resistors to perform a hybrid adjustment architecture of wide-range multiple combination resistors for coarse adjustment and small-resistance sub-ohm level fine adjustment, and performs high-precision real-time dynamic adjustment on the impedance matching of the semiconductor signal circuit. The technical solution is as follows:

[0005] According to one aspect of the present application, a dynamic impedance adjustment device for a semiconductor signal circuit is provided. The dynamic impedance adjustment device comprises:

[0006] A first adjustment unit is configured to control a first switch array and a first resistance array connected in series to perform binary coarse adjustment through different resistance value combinations to determine a target resistance value for preliminary impedance matching;

[0007] A second adjustment unit is configured to control a second switch array and a second resistance array connected in series to perform sub-ohm level step-by-step linear fine adjustment to precisely correct the target resistance value obtained by the first adjustment unit to complete impedance matching;

[0008] A control unit is electrically connected to the first adjustment unit and the second adjustment unit to control the on-off of each switch in the first switch array and the on-off of each switch in the second switch array.

[0009] In some embodiments, specifically, the first switch array includes n first switches, and the first resistance array includes n coarse adjustment resistances, where n is a positive integer greater than or equal to 1. The n first switches are connected in parallel, and each of the n coarse adjustment resistances is connected in series with each of the n first switches in parallel. Alternatively, the n first switches are connected in series, and each of the n coarse adjustment resistances is connected in parallel with each of the n first switches in series.

[0010] In some embodiments, further, the dynamic impedance adjustment device further includes an intermediate transmission unit electrically connected to the first adjustment unit, which transmits the target resistance value obtained through binary coarse adjustment to the control unit.

[0011] In some embodiments, further, each of the coarse adjustment resistances has a fixed resistance value different from each other, and the control unit controls the on-off of the n first switches to provide different combined resistance values, and the n first switches provide a total of 2n combined resistance values. n In some embodiments, further, each of the coarse adjustment resistances has a fixed resistance value different from each other, and the control unit controls the on-off of the n first switches to provide different combined resistance values, and the n first switches provide a total of 2n combined resistance values.

[0012] In some embodiments, specifically, the second switch array includes N second switches connected in parallel, and the second resistance array includes N fine adjustment resistances, where each of the N fine adjustment resistances is connected in series with each of the N second switches, and N is a positive integer greater than or equal to 1.

[0013] In some embodiments, further, the dynamic impedance adjustment device further includes a final transmission unit electrically connected to the second adjustment unit, which transmits the fine corrected target resistance value obtained through linear fine adjustment to the control unit or an external detection circuit.

[0014] In some embodiments, further, each of the fine adjustment resistances has the same and fixed fine adjustment resistance value, and the fine adjustment resistance value ranges from 0.1 to 0.4Ω. The control unit controls the on-off of the N second switches to finely adjust the target resistance value in steps of 0.1Ω at the minimum.

[0015] In some embodiments, preferably, the n first switches in the first switch array and the N second switches in the second switch array are MEMS switches. A switch control circuit is arranged inside the MEMS switch, which performs the on-off action of the switch through FPGA or buffer chip.

[0016] In some embodiments, preferably, the control unit comprises an emulation module, a verification module and a feedback module. The emulation module inputs the simulated combined resistance value to the verification module for testing the impedance adjustment effect and outputs the simulated combined resistance value that passes the test to the first adjustment unit through the control unit for actual binary coarse adjustment. The feedback module is electrically connected with the verification module and the second adjustment unit to form a control closed loop for automatically matching the impedance. The control unit is an FPGA (field programmable gate array) or an MCU (micro central processing unit).

[0017] In some embodiments, preferably, the control unit further comprises a collection module that collects initial signal parameters of the semiconductor circuit, and the initial signal parameters are used as an accuracy evaluation reference for circuit verification by the verification module.

[0018] According to another aspect of the present application, a method for adjusting the dynamic impedance of a semiconductor signal circuit is provided. The adjusting method uses the dynamic impedance adjustment device described in the above aspect to dynamically adjust the impedance of the semiconductor signal circuit in real time. The adjusting method comprises:

[0019] The control unit controls the on-off of the first switch array of the first adjustment unit to obtain different combined resistance values and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test result;

[0020] Based on the at least one combined resistance value, the control unit controls the on-off of the second switch array of the second adjustment unit to perform sub-ohm level step-by-step linear fine adjustment to precisely correct the at least one combined resistance value;

[0021] After each precise correction, the control unit retests the signal quality;

[0022] The control unit outputs the impedance matching resistance value based on the test result of the retested signal quality.

[0023] In some embodiments, specifically, the signal quality includes any one or any combination of the eye height or width, the reflection loss, the transmission loss, the time domain reflection analysis and the loopback signal error analysis.

[0024] The dynamic impedance adjustment device for a semiconductor signal circuit and the adjusting method thereof provided by the embodiments of the present application have at least one or part of the following advantages:

[0025] (1) The FPGA or MCU control unit controls the multi-path MESE switch series resistance to perform mixed adjustment of wide-range multi-combined resistance coarse adjustment and small resistance sub-ohm level fine adjustment, thereby performing high-precision real-time dynamic adjustment of the impedance matching of the semiconductor signal circuit, especially the dense high-speed signal circuit;

[0026] (2) By setting n MESE switches and n resistors with different resistance values ​​in the first adjustment unit to form each independent resistor circuit, a binary weighted array is realized to obtain a combination resistor with a wide range of adjustable resistance values, which can quickly locate the target resistor.

[0027] (3) By setting N MESE switches and N small resistance values ​​in the second adjustment unit, higher accuracy correction or compensation can be achieved after obtaining the target resistance, and a minimum step size of 0.1Ω can be provided for linear fine adjustment.

[0028] (4) By repeatedly performing impedance fine-tuning through the verification module and feedback module in the control unit, the impedance value can be dynamically changed during signal transmission according to the actual conditions of the semiconductor chip, thereby suppressing reflection, maintaining signal integrity, and improving the reliability and robustness of the high-speed communication system.

[0029] (5) The simulation module in the control unit can simulate the combined resistance value for binary coarse adjustment in advance and provide the initial impedance adjustment range for the first adjustment unit after circuit verification, thereby further improving the impedance matching efficiency.

[0030] (6) By using MEMS mechanical switches, without relying on MOS or potentiometers, it has the characteristics of high impedance isolation, ultra-low power consumption and nanosecond-level switching speed.

[0031] (7) Compared with traditional VR or MOS matrices, MEMS structures are more suitable for miniaturized, high-density circuit wiring, and have almost zero power consumption in static conditions. They are also suitable for scenarios such as online adjustment and mismatch correction of interfaces such as ATE, DDR / PCIe, production testing (ATE), system compensation, and aging self-calibration. Attached Figure Description

[0032] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 This is a schematic diagram of a dynamic impedance adjustment device for a semiconductor signal circuit according to an embodiment of the present invention.

[0034] Figure 2 for Figure 1 A schematic diagram of the structure of the first adjustment unit in one embodiment of the dynamic impedance adjustment device shown;

[0035] Figure 3 for Figure 1 A schematic diagram of the structure of the first adjustment unit of another embodiment of the dynamic impedance adjustment device shown;

[0036] Figure 4 forFigure 1 Structure diagram of the second adjusting unit of one embodiment of the dynamic impedance adjusting device shown;

[0037] Figure 5 Flow chart of the adjusting method for dynamic impedance of a semiconductor signal circuit according to one embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions of the present application will be further described below by way of examples in conjunction with the accompanying drawings. In the description, identical or similar reference numerals indicate identical or similar components. The following description of the embodiments of the present application with reference to the accompanying drawings is intended to explain the general inventive concept of the present application and should not be construed as a limitation of the present application.

[0039] It should also be understood that, although the terms "first", "second", "third" and the like can be used in the following embodiments of the present application to describe certain components, two or more of such components should not be limited by these terms. These terms are only used to distinguish each component from each other, and should not be construed as a limitation of the present application.

[0040] In semiconductor communication, especially high-speed digital communication and radio frequency systems, the impedance matching accuracy of the signal transmission line directly determines the signal integrity and system performance. Therefore, embodiments of the present application provide a dynamic impedance adjusting device for a semiconductor signal circuit and an adjusting method thereof, which uses a control unit based on FPGA or MCU to control a multi-path MESE switch and parallel resistance to perform a hybrid adjusting framework of wide-range multi-combination resistance coarse adjustment and small-resistance sub-ohm level fine adjustment for high-precision real-time dynamic adjustment of impedance matching of the semiconductor signal circuit.

[0041] According to one aspect of the present application, a dynamic impedance adjusting device for a semiconductor signal circuit is provided.

[0042] Referring to Figure 1 , the specific structure and circuit connection of the dynamic impedance adjusting device of one embodiment are shown. The dynamic impedance adjusting device 100 mainly consists of five modules, i.e. a control unit 10, a first adjusting unit 20 for binary coarse adjustment, a second adjusting unit 30 for linear fine adjustment, an intermediate transmission unit 40 and a final transmission unit 50, which are electrically connected to each other.

[0043] The first adjusting unit 20 internally electrically connects a first switch array 21 and a first resistance array 22 to perform binary coarse adjustment through different resistance value combinations to determine the target resistance value for impedance preliminary matching.

[0044] The second adjusting unit 30 is electrically connected with the second switch array 31 and the second resistance array 32, and the impedance matching is completed by the sub-ohm step linear fine adjustment to precisely correct the target resistance value obtained by the first adjusting unit 20.

[0045] The control unit 10 is electrically connected with the first adjusting unit 20 and the second adjusting unit 30 to control the on-off of each switch in the first switch array 21 and the on-off of each switch in the second switch array 31.

[0046] The dynamic impedance adjusting device 100 combines the binary-weighted coarse adjustment and the small resistance linear fine adjustment to form a controllable and adjustable resistance array through the first adjusting unit 20 and the second adjusting unit 30. The dynamic impedance adjusting device 100 supports and realizes the multi-level resolution impedance adjusting control, and achieves the high-resolution resistance matching adjustment from the large-range coarse adjustment to the small-step fine adjustment.

[0047] The working process of the dynamic impedance adjusting device 100, in which the control unit 10 controls the on-off of the switches connected with the resistance, can be divided into two stages, i.e., coarse adjustment and fine adjustment. The combination of multiple switches (especially the MEMS switch) and the resistance for adjusting the impedance can provide multiple different combination resistance values for adjusting the impedance, so as to realize the dynamic adjustment of the equivalent resistance in the semiconductor circuit and adjust the impedance of the signal path in the matching circuit.

[0048] The two-stage impedance matching framework of coarse adjustment + fine adjustment provides a large range of combination resistance values in the coarse adjustment and quickly finds the adaptive impedance adjusting range in combination with the analog adjustment in the control unit 10, and supports the sub-ohm level adjusting step in the fine adjustment, with the response speed reaching the nanosecond level. The two-stage impedance matching framework is suitable for the high-speed application scenarios such as DDR5, GDDR6, PCIe 5.0 / 6.0, and makes up for the limitations of the precision and responsiveness of the traditional static matching structure. In addition, the two-stage impedance matching framework can also realize the dynamic optimization of the signal quality of the semiconductor product during the operation.

[0049] Referring to Figure 2 , the internal specific structure, electrical connection and signal transmission connection relationship of the first adjusting unit 20 of one embodiment are shown. The switches in the first switch array 21 in the first adjusting unit 20 are arranged in parallel.

[0050] In one example, specifically, the first switch array 21 includes n first switches arranged in parallel, for example Figure 2 MEMS1-1, MEMS1-2, MEMS1-3...MEMS1-n shown in the drawing; and the first resistance array 22 includes n coarse adjustment resistances, for example Figure 2R1-1, R1-2, R1-3...R1-n. Wherein each of the n coarse adjustment resistors is respectively in series with each of the n first switches, n is a positive integer greater than or equal to 1.

[0051] Referring to Figure 3 , the internal specific structure, electrical connection and signal transmission connection relationship of the first adjustment unit 20' of another embodiment are shown. The switches in the first switch array 21' in the first adjustment unit 20' are arranged in series.

[0052] In one example, specifically, the first switch array 21' includes n first switches in series, for example Figure 3 MEMS1-1, MEMS1-2, MEMS1-3...MEMS1-n; and the first resistance array 22' includes n coarse adjustment resistors, for example Figure 3 R1-1, R1-2, R1-3...R1-n. Wherein each of the n coarse adjustment resistors is respectively in parallel with each of the n first switches, n is a positive integer greater than or equal to 1.

[0053] As Figure 2 or Figure 3 In one example, further, the dynamic impedance adjustment device 100 further includes an intermediate transmission unit 40 electrically connected with the first adjustment unit 20 (which can also be the first adjustment unit 20'), which transmits the target resistance value obtained through binary coarse adjustment to the control unit 10.

[0054] In one example, further, each coarse adjustment resistor has a fixed resistance value different from each other, and the control unit 10 controls the on-off of the n first switches to provide different combined resistance values, and the n first switches provide a total of 2 n combined resistance values.

[0055] In one example, the n first switches are in series with the n coarse adjustment resistors one by one, and after the power supply module (which can be independently arranged outside the dynamic impedance adjustment device 100, or can be arranged together with the control unit 10 of the dynamic impedance adjustment device 100) is powered, the action of switch on-off can be realized according to the control signal or control instruction of the control unit 10 to form a total of 2 n combined resistance values. This combination mode follows the binary weight logic, thereby forming a binary weighted resistance array, which is used to cover a wider range of impedance adjustment compensation in the coarse adjustment stage.

[0056] Exemplarily, in Figure 2As shown in the parallel switch layout, four first switches MEMS1-1, MEMS1-2, MEMS1-3 and MEMS1-4 are arranged in the first switch array 21, and four coarse adjustment resistors R1-1, R1-2, R1-3 and R1-4 are correspondingly arranged in the first resistor array 22, and the coarse adjustment resistors are exemplarily assigned values R1-1=R, R1-2=2R, R1-3=4R and R1-4=8R. The binary weighted array means that the control unit 10 controls the multiple MEMS switches in series with different resistance values to combine resistors. For example, turning on MEMS1-1 connects R1-1 to obtain a coarse adjustment resistor with a resistance value of R, and turning on MEMS1-2 connects R1-2 to obtain a coarse adjustment resistor with a resistance value of 2R, and then the combined resistance value is R+2R=3R. In this way, the maximum number of combined resistance values that can be obtained by n MEMS switches is 2n. n . Figure 3 The resistance combination mode of the series switch layout shown can be obtained in the same way, which will not be described here. The actual circuit design can select the configuration of parallel switches or series switches according to the impedance adjustment requirements of the semiconductor signal circuit and the actual situation of parameters such as antenna effect.

[0057] Referring to Figure 4 , the internal specific structure, electrical connection and signal transmission connection relationship of the second adjustment unit 30 are shown.

[0058] In one example, specifically, the second switch array 31 includes N parallel second switches, for example Figure 4 MEMS2-1, MEMS2-2, MEMS2-3...MEMS2-N shown; the second resistor array 32 includes N fine adjustment resistors, for example Figure 4 R2-1, R2-2, R2-3...R2-N shown. Each of the N fine adjustment resistors is respectively connected in series with each of the N second switches, and N is a positive integer greater than or equal to 1.

[0059] In one example, further, the dynamic impedance adjustment device 100 further includes a final transmission unit 50 electrically connected to the second adjustment unit 30, which transmits the precise corrected target resistance value obtained by linear fine adjustment to the control unit 10 or an external detection circuit.

[0060] In one example, further, each fine adjustment resistor has the same and fixed fine adjustment resistance value, and the range of the fine adjustment resistance value is 0.1-0.4Ω. The control unit 10 controls the on-off of the N second switches to precisely adjust the target resistance value with a step of 0.1Ω.

[0061] Exemplarily, the resistance of each trimming resistor is 0.1 Ω, and thus the minimum resistance step for linearly trimming the target resistance obtained by the first adjusting unit 20 is 0.1 Ω. That is, when a second switch (for example, MEMS2-1) is turned on, a trimming resistor (corresponding to R2-1) is connected, and the target resistance can be trimmed in steps of 0.1 Ω. After repeated trimming, the final adjusted impedance resistance value can be obtained.

[0062] Generally, the impedance matching error of most PCB traces needs to be as small as possible, less than 1 Ω. The minimum step resolution of the traditional fine adjustment method or device structure for adjusting impedance is 0.5 Ω. It can be seen that the dynamic impedance adjusting device 100 can achieve a smaller impedance adjusting step.

[0063] In an example, preferably, the n first switches in the first switch array 21 and the N second switches in the second switch array 31 are MEMS switches. A switch control circuit is arranged inside the MEMS switch, which performs the on-off action of the switch through an FPGA or a buffer chip. By arranging the MEMS switches in the first adjusting unit 20 and the second adjusting unit 30 respectively and corresponding to the series-connected adjusting resistors, a MEMS microswitch matrix-based adjustable and controllable resistance network structure is formed.

[0064] The MEMS switch is a micro-mechanical switch, which does not rely on MOS or potentiometer, and thus has the characteristics of high impedance isolation, ultra-low power consumption, nanosecond switching speed, etc. At the same time, the MEMS switch can support dynamic switching to adjust the resistance online automatic compensation, feedback control, temperature drift self-adaptation, etc., and can also support real-time programming to realize the self-repairing impedance matching function. Exemplarily, all the MEMS switches can be controlled by an FPGA or an MCU.

[0065] In an example, preferably, as shown in Figure 1 The control unit 10 includes an emulation module 11, a verification module 12, and a feedback module 13. The emulation module 11 inputs the simulated combined resistance value to the verification module 12 for testing the impedance adjusting effect, and outputs the simulated combined resistance value that passes the test to the first adjusting unit 20 through the control unit 10 for actual binary coarse adjustment. The feedback module 13 is electrically connected with the verification module 12 and the second adjusting unit 30 to form a control closed loop automatic matching impedance. Alternatively, the control unit 10 is controlled in real time by an FPGA or an MCU, dynamically adjusts and selects suitable combined resistors according to the running state of the signal circuit, and realizes fine adjustment and compensation of the impedance of the signal circuit.

[0066] Exemplarily, when the simulation module 11 and the verification module 12 are integrated inside the control unit 10, the impedance adjustment can not be performed by actual impedance matching adjustment in the initial stage, but the simulation test of the resistance value combination can be first performed in the simulation module 11 and the verification module 12 through the simulation-loop-test flow mode provided by the combined resistance value of the first adjustment unit 20. When the better combined resistance value is obtained through the simulation test, the impedance matching is started in the actual loading into the MEMS switch resistance array network structure connected to the semiconductor signal circuit.

[0067] Exemplarily, a MEMS switch resistance array network structure exactly the same as the first adjustment unit 20 can be established in the simulation module 11. Then, the transmission signal quality test is performed on all the 2 n combined resistances through the loop test of the verification module 12, at least one better combined resistance value is obtained, and the first-stage coarse adjustment is performed on the first adjustment unit 20.

[0068] In an example, preferably, the control unit 10 further comprises a collection module 14 which collects the initial signal parameters of the semiconductor circuit, and the initial signal parameters are used as the precision evaluation reference of the impedance adjustment and are verified by the verification module 12. That is, the parameters collected in the initial stage (such as S11, eye height, jitter, reflection point, etc.) are used to establish the reference model of the impedance adjustment and are used as the evaluation reference of the subsequent adjustment effect.

[0069] The main functions of the initial signal parameters include but are not limited to comparing the signal quality changes of each group of combined resistances used in the subsequent adjustment, judging whether the impedance compensation is effective, being used as the original state or fallback state in the loop debugging process, and being used as the training sample of the adjustment model. Further, the fine-tuned target resistance value is received by the final transmission unit 50 which is electrically connected to the second adjustment unit 30, and is fed back to the feedback module 13 of the control unit 10 to enter the verification module 12 again for the signal quality test and analysis. Thus, in the fine-tuning stage, the resistance value of the target resistance can be continuously fine-tuned to approach the optimal adjustment impedance or be continuously dynamically fine-tuned according to the real-time working state changes of the signal circuit through the closed-loop feedback.

[0070] Exemplarily, when the FPGA is used as the control unit 10, the ADC analyzer (such as EyeScan) can be accessed inside the FPGA, and the debugging high-speed sampling device is externally connected. The FPGA performs the closed-loop scanning through the FSM control structure, dynamically adjusts the on-off state of the switch array in the first adjustment unit 20 and / or the second adjustment unit 30 according to the current signal score. For example, in the test stage of determining the coarse adjustment combined resistance value, the pseudo-random code (PRBS) or the specific edge transition data is sent, and the evaluation score is sorted after the test and evaluation of each combined resistance value to select the best value.

[0071] According to another aspect of the present application, there is provided a method for adjusting dynamic impedance of a semiconductor signal circuit. The adjusting method uses the dynamic impedance adjusting device 100 described in the above aspects to dynamically adjust the impedance of the semiconductor signal circuit in real time.

[0072] Referring to Figure 5 , a flowchart of the steps of the adjusting method is shown. In combination with the specific structure of the dynamic impedance adjusting device shown in Figure 1 , the adjusting method comprises:

[0073] Step S100: The control unit 10 controls the on-off of the first switch array 21 of the first adjusting unit 20 to obtain different combined resistance values and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test results.

[0074] Step S200: Based on the at least one combined resistance value obtained in step S100, the control unit 10 controls the on-off of the second switch array 31 of the second adjusting unit 30 to perform sub-ohm level step-by-step linear fine tuning to precisely correct the at least one combined resistance value.

[0075] Step S300: After each precise correction, the signal quality is retested by the control unit 10.

[0076] Step S400: The control unit 10 outputs the impedance matching resistance value based on the test results of the retested signal quality obtained in step S300.

[0077] Exemplarily, the signal quality includes any one or any combination of eye height or width, return loss, transmission loss, time domain reflectometry, and loopback signal error analysis.

[0078] Exemplarily, during the testing process, the evaluation criteria are dynamically adjusted. For example, a separate set of indicators is established for each type of interface signal on the semiconductor circuit, or a general set of indicators is first established and then supplemented with a specific set of indicators, etc. The general indicators that can be used for testing evaluation are, for example, eye height > 200 mV, return loss < -10 dB, minimum ISI (inter-symbol interference), etc., and the specific indicators are, for example, attention to Setup / Hold time alignment with Read DQS for DDR4, attention to BER after Equalization for PCIe, CTLE+DFE effect, consideration of overshoot caused by too fast signal switching rate for GDDR6, etc.

[0079] In one example, the dynamic impedance adjusting device 100 described in combination with the above aspects and the adjusting method of the dynamic impedance thereof are described below through an exemplary control flow embodiment.

[0080] The control unit 10 uses an FPGA and can be realized by an FPGA internal state machine (FSM) programmable dynamic control.

[0081] In the initialization phase, all MEMS switches in the first adjusting unit 20 and the second adjusting unit 30 are closed, and the system enters a default state. Initial signal parameters (such as reflection intensity, line end waveform) are collected by the collection module 14 in the control unit 10.

[0082] In the coarse adjustment phase of the first adjusting unit 20 (for example, a plurality of switches in the first switch array 21 are connected in parallel, and the same applies to series connection, which will not be described again), the control unit 10 scans the MEMS switch resistance array network structure composed of the first switch array 21 and the first resistance array 22 in series, tests the signal integrity of adjusting impedance using each combined resistance value. Based on the test results, the target resistance value of the coarse adjustment with the best performance is selected.

[0083] In the fine adjustment phase of the second adjusting unit 30, on the basis of coarse adjustment, the MEMS switches in the second switch array 31 are opened one by one and gradually, realizing fine compensation adjustment with small resistance step. After each step adjustment, the signal quality needs to be re-evaluated by the verification module 12 of the control unit 10 until the optimal index is reached or continuously approaches the optimal index.

[0084] In the dynamic balance or adjustment phase, the dynamic impedance adjusting device 100 maintains the current best state. If the control unit 10 or other external detection equipment detects that the working environment of the semiconductor circuit has changed (for example, temperature change, load change) or impedance adjustment timing trigger, the dynamic impedance adjusting device 100 reenters the impedance adjustment working mode and re-performs coarse adjustment + fine adjustment to match the better impedance adjustment resistance value again.

[0085] The embodiment of the application provides at least one or part of the following advantages:

[0086] (1) The mixed adjustment architecture of wide-range multi-combination resistance coarse adjustment and small-resistance sub-ohm fine adjustment of the plurality of MESE switches connected in series controlled by the FPGA control unit realizes high-precision real-time dynamic adjustment of impedance matching of the semiconductor signal circuit, especially the dense high-speed signal circuit;

[0087] (2) By setting corresponding n MESE switches and n resistances with different resistance values in the first adjusting unit to form each independent resistance circuit, a binary weighted array is obtained to quickly locate the target resistance;

[0088] (3) By setting corresponding N MESE switches and N small resistance in the second adjusting unit, higher precision correction or compensation can be achieved after obtaining the target resistance, and the minimum step size can be 0.1Ω;

[0089] (4) By the verification module and feedback module in the control unit, impedance fine tuning can be repeated, and impedance value can be dynamically changed in signal transmission process according to actual semiconductor chip conditions, so as to suppress reflection, maintain signal integrity, and improve reliability and robustness of high-speed communication system;

[0090] (5) By the simulation module in the control unit, the combined resistance value for binary coarse adjustment can be simulated in advance, and the initial impedance adjustment range can be provided for the first adjusting unit after circuit verification, so as to further improve impedance matching efficiency;

[0091] (6) By using MEMS mechanical switch, high impedance isolation, ultra-low power consumption, and nanosecond switching speed are achieved without relying on MOS or potentiometer;

[0092] (7) Compared with traditional VR or MOS matrix, MEMS structure is more suitable for miniaturization and high-density circuit wiring, and the power consumption is almost zero in static state, and is suitable for online adjustment and mismatch correction of interfaces such as ATE, DDR / PCIe, production test (ATE), system compensation, aging self-calibration and other scenes.

[0093] Although some embodiments of the general inventive concept have been shown and described, those of ordinary skill in the art will understand that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, and the scope of the invention is defined by the claims and their equivalents.

Claims

1. A dynamic impedance adjustment device for a semiconductor signal circuit, characterized by The dynamic impedance adjusting device comprises: a first adjusting unit, in which a first switch array and a first resistance array connected electrically are arranged to perform binary coarse adjustment through different resistance value combinations to determine a target resistance value to preliminarily match impedance; a second adjusting unit, in which a second switch array and a second resistance array connected electrically are arranged to perform sub-ohm level step linear fine adjustment to precisely correct the target resistance value obtained through the first adjusting unit to complete impedance matching; each of the first switches in the first switch array and the second switches in the second switch array is a MEMS switch, in which a switch control circuit is arranged to perform switch on-off action through an FPGA or a buffer chip; a control unit connected electrically with the first adjusting unit and the second adjusting unit to control on-off of each switch in the first switch array and on-off of each switch in the second switch array; wherein, the control unit is an FPGA or an MCU, which comprises a simulation module, a verification module and a feedback module, the simulation module inputs simulated combined resistance values to the verification module for impedance adjusting effect test and outputs the simulated combined resistance values that pass the test to the first adjusting unit through the control unit for actual binary coarse adjustment, the feedback module is connected electrically with the verification module and the second adjusting unit to form a control closed loop to automatically match impedance.

2. The dynamic impedance adjusting device according to claim 1, wherein the first switch array comprises n first switches, and the first resistance array comprises n coarse adjustment resistances, wherein n is a positive integer greater than or equal to 1; the n first switches are connected in series, and each of the n coarse adjustment resistances is connected in parallel with each of the n first switches in series; the dynamic impedance adjusting device further comprises an intermediate transmission unit connected electrically with the first adjusting unit, which transmits the target resistance value obtained through binary coarse adjustment to the control unit.

3. The dynamic impedance adjusting device according to claim 2, wherein each of the coarse adjustment resistances has a fixed resistance value different from each other, the control unit controls on-off of the n first switches to provide different combined resistance values, The n first switches provide in total 2 n of the combined resistance values.

4. The dynamic impedance adjusting device according to claim 2, wherein the second switch array comprises N second switches connected in parallel, the second resistance array comprises N fine adjustment resistances, each of which is connected in series with each of the N second switches, wherein N is a positive integer greater than or equal to 1; the dynamic impedance adjusting device further comprises a final transmission unit connected electrically with the second adjusting unit, which transmits the precisely corrected target resistance value obtained through linear fine adjustment to the control unit or an external detection circuit.

5. The dynamic impedance adjusting device according to claim 4, wherein Each trimming resistor has the same and fixed trimming resistor value, the trimming resistor value ranges from 0.1 to 0.4Ω; The control unit controls the on-off of the N second switches respectively to precisely adjust the target resistance value in steps of 0.1Ω at least. 6.The dynamic impedance adjustment device according to any one of claims 1-5, characterized in that, The control unit further comprises a collection module, The collection module collects initial signal parameters of the semiconductor circuit, and the initial signal parameters are used as an accuracy evaluation reference for impedance adjustment and are verified by the verification module.

7. A method for adjusting the dynamic impedance of a semiconductor signal circuit, using the dynamic impedance adjustment device according to any one of claims 1-6 to dynamically adjust the impedance of a semiconductor signal circuit in real time, characterized in that, The adjustment method comprises: The control unit controls the on-off of the first switch array of the first adjustment unit to obtain different combined resistance values and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test result; On the basis of the at least one combined resistance value, the control unit controls the on-off of the second switch array of the second adjustment unit to perform sub-ohm step linear trimming for precise correction of the at least one combined resistance value; After each precise correction, the control unit retests the signal quality; The control unit outputs the impedance matching resistance value based on the test result of the retested signal quality. 8.The adjustment method according to claim 7, characterized in that, The signal quality comprises any one or any combination of eye height or width, reflection loss, transmission loss, time domain reflection analysis, and loopback signal error analysis.

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