High-precision parallel trigger release suppression method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a high-precision parallel trigger release suppression method based on an FPGA (Field Programmable Gate Array), which comprises the following steps of: sampling an input signal through a digital acquisition system, and preprocessing the sampled signal to obtain a shaped signal; then, finding out the position of a starting point of triggering release and suppression through a shaping signal at the triggering time release and suppression module, and calculating the number of sampling points needing release and suppression; calculating masks of all sampling moments based on the initial masks; and finally, performing trigger suppression release on the sampling data of all the sampling moments by using the masks.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic measuring instruments, and more particularly, relates to a high-precision parallel trigger holdoff method based on FPGA. Background Art

[0002] Trigger hold-off technology is a core function in electronic measuring instruments, especially in oscilloscopes and signal analysis equipment. It is primarily used to solve the problem of stable triggering in complex signal environments. With the significant increase in signal complexity in modern electronic systems, especially with the widespread use of high-speed digital signals (such as PCIe 6.0 and USB4), pulse signals, and multi-channel signals, traditional trigger mechanisms face severe challenges in scenarios with high-frequency noise (noise density ≥ -150dBc / Hz), signal jitter (jitter ≥ 200ps), and complex waveforms (such as PAM4 modulated signals), with false trigger rates as high as 32%-45%. Traditional trigger systems use a fixed response mode of "trigger and acquire." When the signal contains repetitive noise, periodic interference, or complex waveforms, it is prone to multiple false triggers, affecting measurement accuracy. Trigger holdoff technology introduces a "hold-off time" after the trigger event, prohibiting the trigger circuit from responding to new signal changes within a specific time window, thereby effectively avoiding false triggering problems and significantly improving the capture accuracy and stability of pulse signals, burst signals and high repetition rate signals.

[0003] The traditional serial trigger holdoff block diagram is as follows Figure 1 As shown in the figure, the analog waveform signal enters the acquisition system through the analog channel, is converted into a digital waveform signal by the ADC, and then sent to the acquisition board FPGA for digital signal processing. The digital waveform signal is sent to the trigger hold-off module and the data path (DDR_data_path) module respectively through the ADC_DATA_RX module.

[0004] In recent years, with the increasing demand for measurement accuracy and real-time performance in electronic systems, trigger holdoff technology has gradually developed towards high-precision, adaptive, and intelligent features. In high-energy physics experiments, radar signal processing, and high-speed communication systems, signals exhibit extremely high temporal resolution and complex time-domain characteristics, making traditional fixed holdoff time mechanisms inadequate. To address this, researchers have begun exploring dynamic holdoff time adjustment techniques based on digital signal processing (DSP) and field-programmable gate arrays (FPGAs), which automatically optimize holdoff time through real-time analysis of signal characteristics. Furthermore, the increasing prevalence of multi-channel measurement equipment has driven the development of distributed trigger holdoff mechanisms based on inter-channel correlation analysis. These mechanisms dynamically adjust the holdoff time of each channel to achieve synchronized capture and stable triggering of multi-channel signals. These innovative technologies have significant application value in high-precision measurement, real-time signal analysis, and intelligent instrument design. For example, in high-speed serial signal analyzers, the trigger holdoff function solves the problem of stable display of complex waveforms (e.g., those containing multiple non-repeating trigger points within a cycle) by precisely controlling trigger conditions, significantly improving the reliability and observability of measurement results. In the future, with the further development of signal processing technology and hardware platforms, trigger holdoff technology will play a key role in a wider range of fields.

[0005] When using a high-speed serial signal analyzer for measurement, the signal to be measured is usually not an ideal waveform such as a regular square wave, sine wave or triangle wave, but is often a complex signal with a large period and multiple non-repetitive waveform data points that meet the trigger conditions within the same period. Figure 2 As shown, the signal to be measured is a multi-cycle pulse square wave signal. In this case, if only the rising edge trigger is used as the trigger condition, a trigger point is generated when the rising edge is higher than the trigger level. Figure 2 The signal in the display will generate multiple trigger points. The existence of multiple trigger points will cause the following to appear on the display screen: Figure 3 The waveform shaking and chaos phenomenon will seriously affect the stability and observability of the measurement results. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a high-precision parallel trigger release method based on FPGA. Starting from the first valid edge signal detected, the subsequent edge signals are shielded within a preset release time to achieve stable trigger control.

[0007] To achieve the above-mentioned object of the invention, the present invention provides a high-precision parallel trigger holdoff method based on FPGA, characterized by comprising the following steps:

[0008] (1) Set the trigger holdoff time T0 in the FPGA; set the initial mask M0 of the trigger holdoff: the initial mask M0 is a column vector with a length of n and all elements are 1; set the sampling time t, t = 1, 2, 3, ...;

[0009] (2) Signal acquisition: Starting from t=1, the digital acquisition system samples the input signal and obtains N parallel sampling data X N ;

[0010] (3) Generate comparison signal: Compare each sampling value in the sampled data with the preset trigger comparison level. If the sampling value is higher than the trigger comparison level, it outputs logic 1; if it is lower than the trigger comparison level, it outputs logic 0. Otherwise, the output logic is the same as the output logic corresponding to the previous sampling point, thereby generating N parallel comparison signals B. N ;

[0011] (4) Comparison signal extraction: uniformly extract the N-way parallel comparison signal by N / n times to obtain the n-way parallel comparison signal B n ;

[0012] (5) Generate shaping signal: traverse n parallel comparison signals, find the element position in the comparison signal that jumps from 0 to 1, set its element value to 1, and set the rest of the element values ​​to 0, thus obtaining n parallel shaping signal L n ;

[0013] (6) Send the n parallel shaping signals to the trigger time holdoff module to find the first starting point of the trigger holdoff, that is, find the first element position in the shaping signal that jumps from 0 to 1, and record it as the starting point position W of the trigger holdoff. start ;

[0014] (7) Calculate the number of sampling points N that need to be released num :N num =T0 / f s / n,f s is the sampling rate of the digital acquisition system;

[0015] (8) Calculate the mask M1 at the first sampling time t = 1: According to the starting point position W of the trigger release start Find the corresponding position in the initial mask M0, and then release the number of sampling points N as needed num The initial mask M0 corresponds to the starting point position W start The values ​​of all subsequent elements are set to 0, and the starting point position start_location and the elements before it remain unchanged, thus obtaining the mask M1;

[0016] (9) Use mask M1 to trigger and hold off the sampling data at the first sampling moment;

[0017] (9.1), the shaped signal L n Perform bitwise AND operation with mask M1 to obtain the trigger release intermediate state

[0018] (9.2) for the trigger release intermediate state Perform bitwise expansion: will trigger the release intermediate state Each element in is expanded into N / n bits, and the expanded element value is the same as the element value of the bit, thus obtaining N-way parallel holdoff results.

[0019] (9.3) and the suppression result Compare with signal B N Perform bitwise AND operation to obtain the final holdoff result of the sampling data at the first sampling moment Then it is sent to the edge trigger module for trigger judgment to obtain the expected trigger release result;

[0020] (10) Trigger and hold back the sampling data at each subsequent sampling moment;

[0021] At the second sampling time t=2, the mask M2 of the second sampling time t=2 is calculated first:

[0022] According to the starting point position W of trigger holdoff start And the number of sampling points N that need to be suppressed num , count the corresponding starting point position W in the initial mask M0 start The number of elements with a value of 0 is recorded as N0; calculate the intermediate quantity ΔN=N num -N0, then set the first ΔN elements of mask M2 to 0 and the last n-ΔN elements to 1 to obtain mask M2;

[0023] Then, process according to steps (2) to (6), and then execute step (9) with mask M2 to complete the trigger release of the sampling data at the second sampling moment, and then, by analogy, trigger release of the sampling data at each subsequent sampling moment.

[0024] The object of the invention of the present invention is achieved like this:

[0025] The present invention discloses a high-precision parallel trigger holdoff method based on FPGA. The method samples an input signal through a digital acquisition system and pre-processes the sampled signal to obtain a shaped signal. Then, a trigger time holdoff module uses the shaped signal to find the starting point of the trigger holdoff and calculate the number of sampling points that need to be held off. Then, a mask for each sampling moment is calculated based on the initial mask. Finally, the mask is used to trigger and hold off the sampled data at each sampling moment.

[0026] At the same time, the high-precision parallel trigger holdoff method based on FPGA of the present invention also has the following beneficial effects:

[0027] (1) The parallel trigger holdoff method provided by the present invention has greatly improved accuracy compared to the traditional serial trigger holdoff method; the accuracy of the traditional serial trigger holdoff method is only one clock cycle, while the present invention adopts N-way parallel processing, and the accuracy is N times the original.

[0028] (2) Compared with the traditional serial trigger holdoff method, the parallel trigger holdoff method provided by the present invention is completely based on FPGA implementation, has good real-time performance, and the data processing throughput is N times the original. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is the traditional serial trigger holdoff schematic;

[0030] Figure 2 This is a serial trigger diagram;

[0031] Figure 3 This is a waveform diagram of the serial trigger holdoff function being turned off;

[0032] Figure 4 This is a schematic diagram of the high-precision parallel trigger holdoff principle based on FPGA of the present invention;

[0033] Figure 5 This is an example of an unstable trigger waveform caused by the holdoff time being less than the falling edge interval time.

[0034] Figure 6 This is an example diagram of the trigger waveform recovering and stabilizing after the holdoff time is greater than the falling edge interval time. DETAILED DESCRIPTION

[0035] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0036] Example

[0037] In this embodiment, if Figure 4 As shown, the present invention provides a high-precision parallel trigger holdoff method based on FPGA, comprising the following steps:

[0038] (1) Set the trigger holdoff time T0 = 10ns in FPGA;

[0039] Set the initial mask M0 for trigger holdoff: the initial mask M0 is a column vector with a length of 8 and all elements are 1;

[0040]

[0041] Set sampling time t, t = 1, 2, 3, ...;

[0042] (2) Signal acquisition: Starting from t=1, the digital acquisition system samples the input signal and obtains N parallel sampling data X N ;

[0043] In this embodiment, assuming that the digital acquisition system acquires 80 channels of sampled data in parallel, that is, N=80, then at the first sampling moment, the 80 channels of sampled data in parallel are expressed as:

[0044]

[0045] (3) Generate comparison signal: Compare each sampling value in the sampled data with the preset trigger comparison level. If the sampling value is higher than the trigger comparison level, it outputs logic 1; if it is lower than the trigger comparison level, it outputs logic 0. Otherwise, the output logic is the same as the output logic corresponding to the previous sampling point, thereby generating 80 parallel comparison signals B. 80 ;

[0046]

[0047] (4) Comparison signal extraction: uniformly extract the 80-way parallel comparison signal by 80 / 8 times to obtain the 8-way parallel comparison signal B8;

[0048]

[0049] (5) Generate shaping signal: traverse the 8-way parallel comparison signal, find the position of the element in the comparison signal that jumps from 0 to 1, set the element to 1, and set the rest of the elements to 0, thereby obtaining the 8-way parallel shaping signal L8;

[0050]

[0051] In this embodiment, in the comparison signal B8, only the second to third elements change from 0 to 1. Therefore, the third element value in the shaped signal L8 is 1, and the values ​​of the remaining elements are all 0.

[0052] (6) Send the 8-way parallel shaping signal to the trigger time release module to find the first starting point of the trigger release, that is, find the first element position in the shaping signal that jumps from 0 to 1, and record it as the starting point position W of the trigger release. start In this embodiment, only the second to third elements of the shaped signal L8 jump from 0 to 1, so the third element is recorded as the starting point position W of the trigger release start ;

[0053] (7) Calculate the number of sampling points N that need to be released num:N num =T0 / f s , f s is the sampling rate of the digital acquisition system; in this embodiment, the trigger holdoff time T0 is 10ns, and the system sampling rate f s =1Gsps, therefore, the number of sampling points required for holdoff is N num =10;

[0054] (8) Calculate the mask M1 at the first sampling time t = 1: According to the starting point position W of the trigger release start Find the corresponding position in the initial mask M0, and then release the number of sampling points N as needed num The initial mask M0 corresponds to the starting point position W start The values ​​of all subsequent elements are set to 0, and the starting point position start_location and the elements before it remain unchanged, thus obtaining the mask M1;

[0055] In this embodiment, the starting point position in the initial mask M0 is the third element, so the values ​​of the first, second, and third elements in the initial mask M0 remain unchanged, that is, all are 1, and the number of sampling points that need to be suppressed is N. num =10, so the values ​​of the last five elements of the initial mask M0 are all set to 0, and the resulting mask M1 is:

[0056]

[0057] (9) Use mask M1 to trigger and hold off the sampling data at the first sampling moment;

[0058] (9.1) Perform bitwise AND operation on the shaped signal L8 and the mask M1 to obtain the trigger release intermediate state.

[0059]

[0060] (9.2) for the trigger release intermediate state Perform bitwise expansion: will trigger the release intermediate state Each element in the bit is expanded to 80 / 8=10 bits, and the expanded element value is the same as the element value of the bit, thus obtaining 80 parallel holdoff results.

[0061] In this embodiment, Take the first and third elements as an example: if the first element is 0, then after expansion, we get 10 zeros, that is: The third element is 1, so after expansion we get 10 1s, namely: final The 8 elements in the result are expanded bit by bit to get 80 groups of elements;

[0062] (9.3) and the suppression result Compare with signal B 80 Perform bitwise AND operation to obtain the final holdoff result of the sampling data at the first sampling moment Then it is sent to the edge trigger module for trigger judgment to obtain the expected trigger release result;

[0063] (10) Trigger and hold back the sampling data at each subsequent sampling moment;

[0064] At the second sampling time t=2, the mask M2 of the second sampling time t=2 is calculated first:

[0065] According to the starting point position W of trigger holdoff start And the number of sampling points N that need to be suppressed num , count the corresponding starting point position W in the initial mask M0 start The number of elements with a value of 0 is recorded as N0; calculate the intermediate quantity ΔN=N num -N0, then set the first ΔN elements of mask M2 to 0 and the last n-ΔN elements to 1 to obtain mask M2;

[0066] In this embodiment, the number of sampling points that need to be held back is 10. At the first sampling moment, the last five elements of the initial mask M1 have been held back, that is, the element values ​​are set to 0. Therefore, at the second sampling moment, the first five elements of the mask M2 need to be held back again, that is, the element values ​​are set to 0, and the last three elements are set to 1, thereby obtaining the mask M2:

[0067]

[0068] Then, process according to steps (2) to (6), and then execute step (9) with mask M2 to complete the trigger release of the sampling data at the second sampling moment, and then, by analogy, trigger release of the sampling data at each subsequent sampling moment.

[0069] In this embodiment, if Figure 5 As shown in the figure, in a 20GSPS data acquisition system, when the trigger holdoff time is set to 76ns, the system uses the falling edge trigger mode. Figure 5 The interval between the two farthest falling edges is 76.8ns. Since the holdoff time is less than the interval between the falling edges (the difference is 0.8ns), multiple trigger points will be generated, resulting in unstable trigger waveform.

[0070] However, if Figure 6As shown in the figure, when the trigger holdoff time is adjusted to 77ns, the two signals are still the same as before, and the time interval between the two farthest falling edges is still 76.8ns. However, because the holdoff time is greater than the falling edge interval, the triggered waveform regains stability.

[0071] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. A high-precision parallel trigger holdoff method based on FPGA, characterized in that: The following steps are involved: (1) Set the trigger holdoff time T0 in FPGA; Set the initial mask M0 for trigger holdoff: the initial mask M0 is a column vector of length n, with all elements set to 1; set the sampling time t, t = 1, 2, 3, ...; (2) Signal acquisition: Starting from t=1, the digital acquisition system samples the input signal and obtains N parallel sampling data X N ; (3) Generate comparison signal: Compare each sampling value in the sampled data with the preset trigger comparison level. If the sampling value is higher than the trigger comparison level, it outputs logic 1; if it is lower than the trigger comparison level, it outputs logic 0. Otherwise, the output logic is the same as the output logic corresponding to the previous sampling point, thereby generating N parallel comparison signals B. N ; (4) Comparison signal extraction: uniformly extract the N-way parallel comparison signal by N / n times to obtain the n-way parallel comparison signal B n ; (5) Generate shaping signal: traverse n parallel comparison signals, find the element position in the comparison signal that jumps from 0 to 1, set its element value to 1, and set the rest of the element values ​​to 0, thus obtaining n parallel shaping signal L n ; (6) Send the n parallel shaping signals to the trigger time holdoff module to find the first starting point of the trigger holdoff, that is, find the first element position in the shaping signal that jumps from 0 to 1, and record it as the starting point position W of the trigger holdoff. start ; (7) Calculate the number of sampling points N that need to be released num :N num =T0 / f s / n,f s is the sampling rate of the digital acquisition system; (8) Calculate the mask M1 at the first sampling time t = 1: According to the starting point position W of the trigger release start Find the corresponding position in the initial mask M0, and then release the number of sampling points N as needed num The initial mask M0 corresponds to the starting point position W start The values ​​of all subsequent elements are set to 0, and the starting point position start_location and the elements before it remain unchanged, thus obtaining the mask M1; (9) Use mask M1 to trigger and hold off the sampling data at the first sampling moment; (9.1), the shaped signal L n Perform bitwise AND operation with mask M1 to obtain the trigger release intermediate state (9.2) for the trigger release intermediate state Perform bitwise expansion: will trigger the release intermediate state Each element in is expanded into N / n bits, and the expanded element value is the same as the element value of the bit, thus obtaining N-way parallel holdoff results. (9.3) and the suppression result Compare with signal B N Perform bitwise AND operation to obtain the final holdoff result of the sampling data at the first sampling moment Then it is sent to the edge trigger module for trigger judgment to obtain the expected trigger release result; (10) Trigger and hold back the sampling data at each subsequent sampling moment; At the second sampling time t=2, the mask M2 of the second sampling time t=2 is calculated first: According to the starting point position W of trigger holdoff start And the number of sampling points N that need to be suppressed num , count the corresponding starting point position W in the initial mask M0 start The number of elements with a value of 0 is recorded as N0; calculate the intermediate quantity ΔN=N num -N0, then set the first ΔN elements of mask M2 to 0 and the last n-ΔN elements to 1 to obtain mask M2; Then, process according to steps (2) to (6), and then execute step (9) with mask M2 to complete the trigger release of the sampling data at the second sampling moment, and then, by analogy, trigger release of the sampling data at each subsequent sampling moment.

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