Signal processing method, terminal equipment and computer readable storage medium

Abstract

The invention is suitable for the technical field of signal processing, and particularly relates to a signal processing method, terminal equipment and a computer readable storage medium. The method comprises the following steps: receiving a first signal sent by a first target network; if the first target network is a redundant network, performing redundancy detection on the first signal to obtain a detection result; converting the first signal into a second signal, wherein the data structure of the second signal accords with the data structure of the network protocol of the non-redundant network; and if the detection result shows that the first signal is not the redundant signal, caching the second signal to instruct the central processing unit to obtain the second signal. In the embodiment of the invention, the network card can be flexibly accessed to the redundant network, the redundant signal is converted into the common Ethernet message through the FPGA, the redundancy processing is automatically carried out, a CPU (Central Processing Unit) does not need to process a redundancy protocol, and the complexity of the redundancy processing is reduced. And additional redundancy boxes or switches and the like do not need to be adopted, so that the hardware cost of redundancy processing is reduced.

Description

Technical Field

[0001] The present application belongs to the field of signal processing technology, and in particular relates to a signal processing method, a terminal device, and a computer-readable storage medium. Background Art

[0002] In smart substations, the boards in the power secondary relay protection equipment mainly adopt the structure of central processing unit (CPU) + programmable logic device (Field-Programmable Gate Array, FPGA). The performance of the CPU of a single board and the peripheral expansion are limited, but the board with the CPU + FPGA structure mentioned above can implement an extended network card through the FPGA, thereby realizing external network communication for the CPU. Specifically, the CPU writes the content of the message to be sent into the cache of the FPGA through the bus, and the FPGA drives the physical layer (PHY) chip to send it; correspondingly, the message received by the FPGA through the PHY chip is packaged and processed, and then transmitted back to the CPU through the bus. In this mode, the FPGA is only responsible for driving the interface of the PHY chip and does not care about the content of the sent and received messages. This method is simple and efficient, and each FPGA can realize the expansion of multiple network ports.

[0003] However, in real-world applications, redundant network access is often required. Currently, the CPU still implements the network protocols for redundant networks, which is highly complex. Using redundant boxes or switches to achieve this requires increased equipment costs. Summary of the Invention

[0004] The embodiments of the present application provide a signal processing method, a terminal device, and a computer-readable storage medium, which can enable a network card to flexibly access a redundant network, thereby reducing the complexity and equipment cost of connecting the network card to the redundant network.

[0005] In a first aspect, an embodiment of the present application provides a signal processing method applied to a programmable logic device in a network card, wherein the network card further includes a central processing unit (CPU); the network card is connected to a first network and at least one second network, the first network is a non-redundant network, the second network is a redundant network, and the CPU and the first network use the same network protocol; the method includes:

[0006] receiving a first signal sent by a first target network; wherein the first target network is the first network or the second network;

[0007] If the first target network is the second network, performing redundancy detection on the first signal to obtain a detection result;

[0008] Converting the first signal into a second signal, wherein a data structure of the second signal complies with a data structure of a network protocol of the first network;

[0009] If the detection result indicates that the first signal is not a redundant signal, the second signal is cached to instruct the central processing unit to obtain the second signal.

[0010] In the embodiments of the present application, the network card can flexibly access a redundant network, convert redundant signals into ordinary Ethernet messages through the FPGA, and automatically perform redundant processing, eliminating the need for the CPU to process redundant protocols and reducing the complexity of redundant processing. Furthermore, there is no need to use additional redundant boxes or switches, reducing the hardware cost of redundant processing.

[0011] In a possible implementation of the first aspect, performing redundancy detection on the first signal to obtain a detection result includes:

[0012] Verifying the correctness of the first signal to obtain a first result;

[0013] detecting whether a third signal is received before the first signal to obtain a second result; wherein the third signal and the first signal are redundant signals to each other;

[0014] If the first result indicates that the verification is passed and the second result indicates that the third signal is not received, then the detection result indicates that the first signal is not a redundant signal;

[0015] If the first result indicates that the verification fails, and / or the second result indicates that the third signal is received, then the detection result indicates that the first signal is a redundant signal.

[0016] In a possible implementation of the first aspect, converting the first signal into a second signal includes:

[0017] Converting the first signal from a binary stream to a byte stream to obtain a fourth signal;

[0018] The preset mark in the fourth signal is deleted to obtain the second signal; wherein the preset mark is a data field used to represent a redundant signal.

[0019] In a possible implementation of the first aspect, the method further includes:

[0020] receiving a fifth signal and a first instruction sent by the central processor; wherein the first instruction is used to indicate a second target network, and the second target network is the first network or the second network;

[0021] If the second target network is the second network, converting the fifth signal into a sixth signal in a data format that complies with a network protocol of the second network;

[0022] The sixth signal is sent to the second target network.

[0023] In a possible implementation of the first aspect, converting the fifth signal into a sixth signal in a data format that complies with a network protocol of the second network includes:

[0024] generating a seventh signal according to a combination of a preset mark and the fifth signal; wherein the preset mark is a data field for indicating a redundant signal;

[0025] The seventh signal is converted from a byte stream into a binary stream to obtain the sixth signal.

[0026] In a possible implementation of the first aspect, the method further includes:

[0027] receiving an eighth signal and a second instruction sent by a third target network; wherein the third target network is the second network; and the second instruction is used to instruct a fourth target network, where the fourth target network is a network in the first network or the second network that is redundant with the third target network;

[0028] determining whether to forward the eighth signal;

[0029] If the eighth signal is forwarded, the eighth signal is sent to the fourth target network.

[0030] In a possible implementation of the first aspect, the determining whether to forward the eighth signal includes:

[0031] Get the network protocol currently set by the CPU;

[0032] If the network protocol currently set by the CPU is not the high-availability seamless redundancy protocol, it is determined not to forward the eighth signal;

[0033] If the network protocol currently set by the CPU is a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is inconsistent with the physical address of the network card, determining to forward the eighth signal;

[0034] If the third target network adopts a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is consistent with the physical address of the network card, it is determined not to forward the eighth signal.

[0035] In a possible implementation of the first aspect, the method further includes:

[0036] If the first target network is the first network, buffering the first signal to instruct the central processor to obtain the first signal;

[0037] If the second target network is the first network, the fifth signal is sent to the second target network.

[0038] In a second aspect, an embodiment of the present application provides a signal processing device, including:

[0039] A receiving circuit is configured to receive a first signal transmitted by a first target network; wherein the first target network is the first network or the second network; if the first target network is the second network, performing redundancy detection on the first signal to obtain a detection result; converting the first signal into a second signal, wherein the data structure of the second signal conforms to the data structure of the network protocol of the first network; and if the detection result indicates that the first signal is not a redundant signal, caching the second signal to instruct the central processing unit to obtain the second signal.

[0040] In a third aspect, an embodiment of the present application provides a terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the signal processing method as described in any one of the first aspects above is implemented.

[0041] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the signal processing method as described in any one of the above-mentioned first aspects is implemented.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a terminal device, enables the terminal device to execute the signal processing method described in any one of the above-mentioned first aspects.

[0043] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1Schematic diagram of the functional modules of the FPGA receiving circuit provided in an embodiment of the present application;

[0046] Figure 2 is a flow chart of a signal processing method provided in an embodiment of the present application;

[0047] Figure 3 Schematic diagram of the functional modules of the FPGA transmission circuit provided in an embodiment of the present application;

[0048] Figure 4 is a flow chart of a signal processing method provided in an embodiment of the present application;

[0049] Figure 5 is a flowchart of a signal processing method provided by another embodiment of the present application;

[0050] Figure 6 is a structural block diagram of a signal processing device provided in an embodiment of the present application;

[0051] Figure 7 It is a structural diagram of the terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0053] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0054] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0055] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0056] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized.

[0058] In smart substations, the boards in the power secondary relay protection equipment mainly adopt the structure of central processing unit (CPU) + programmable logic device (FPGA). The performance of the CPU of a single board and the peripheral expansion are limited, but the board with the CPU + FPGA structure can implement an extended network card through the FPGA, thereby realizing external network communication for the CPU. Specifically, the CPU writes the content of the message to be sent into the cache of the FPGA through the bus, and the FPGA drives the physical layer (PHY) chip to send it; correspondingly, the message received by the FPGA through the PHY chip is packaged and processed, and then transmitted back to the CPU through the bus. In this mode, the FPGA is only responsible for driving the interface of the PHY chip and does not care about the content of the sent and received messages. This method is simple and efficient, and each FPGA can realize the expansion of multiple network ports.

[0059] However, in real-world applications, redundant network access is often required. Currently, the CPU still implements the network protocols for redundant networks, which is highly complex. Using redundant boxes or switches to achieve this requires increased equipment costs.

[0060] Based on this, embodiments of the present application provide a signal processing method. In these embodiments, a network card can flexibly access a redundant network, convert redundant signals into common Ethernet messages via an FPGA, and automatically perform redundant processing, eliminating the need for the CPU to handle redundant protocols and reducing the complexity of redundant processing. Furthermore, there is no need for additional redundant boxes or switches, reducing the hardware cost of redundant processing.

[0061] The signal processing method in the embodiments of the present application can be applied to an FPGA in a network card. The network card also includes a central processing unit (CPU). The network card can be connected to a first network and at least one second network, where the first network is a non-redundant network and the second network is a redundant network. The CPU and the first network use the same network protocol.

[0062] For example, the first network is a common Ethernet, and accordingly, the network protocol of the first network is a basic communication protocol.

[0063] For another example, the second network can use redundancy protocols such as the Parallel Redundancy Protocol (PRP) or the High-availability Seamless Redundancy Protocol (HSR). The principle of the PRP protocol is that the sending device sends the same data frame simultaneously through two independent and logically or physically separated subnets (network A and network B). After receiving the data, the receiving device retains the first-arrived frame and discards the last-arrived frame according to the "first come, first served" principle to achieve redundant transmission. For example, in a substation automation system, data can be transmitted through two subnets at the same time. When one subnet fails, the other can still ensure that the data is transmitted without delay or packet loss. The principle of the HSR protocol is to adopt a ring topology structure. The devices on the ring have two network interfaces. The same data frame is transmitted simultaneously along the ring in a clockwise and counterclockwise direction. When the source device receives the frame it sent, it discards it.

[0064] In some embodiments, the functional structure of the FPGA can be improved so that the FPGA can implement the signal processing method in the embodiments of the present application.

[0065] It is understandable that the signal processing process can be divided into a signal receiving process and a signal sending process. Figure 1 and Figure 2 Example) and signaling process (see Figure 3-Figure 5 These two processes are introduced separately.

[0066] See also Figure 1 , is a schematic diagram of the functional modules of the FPGA receiving circuit provided in the embodiment of the present application. As an example and not a limitation, Figure 1As shown, the receiving loop may include a cyclic redundancy check (CRC) module 11 , a message conversion module 12 , a redundant frame arbitration module 13 and a message buffer module 14 .

[0067] The CRC module 11 verifies the correctness of messages. The message conversion module 12 converts received messages into a data format that conforms to the CPU's network protocol. The redundant frame arbitration module 13 determines whether a received message is redundant. The message buffer module 14 determines whether a received message needs to be written to the buffer based on the detection results of the CRC module 11 and the determination results of the redundant frame arbitration module 13.

[0068] like Figure 1 As shown, the receiving circuit may include a first connection end and a second connection end. The first connection end is used to connect to the external network, and the second connection end is used to connect to the CPU. It is understandable that for each subnet in the redundant network, it is possible to connect to Figure 1 For example, the redundant network includes two sub-networks, network A and network B. Accordingly, the receiving loop may include two first connection terminals, connected to network A and network B respectively.

[0069] Optionally, a network card can access multiple networks at the same time. Accordingly, the number of first connection ends of the FPGA's receiving loop can be determined according to the number of networks accessed by the network card. For example, the network card simultaneously accesses ordinary Ethernet (based on the basic communication protocol), PRP redundant network (including two subnets) and HSR redundant network (including two network interfaces). In this case, the PFGA's receiving loop can include 5 first connection ends, which are respectively connected to ordinary Ethernet, two subnets of the PRP redundant network and two network interfaces of the HSR redundant network.

[0070] based on Figure 1 The functional modules of the receiving circuit of the FPGA shown in FIG. 3 are shown in FIG. 4 , and the signal receiving process is described below. It should be noted that the signal receiving process in the embodiment of the present application refers to the process of the network card receiving the signal.

[0071] See also Figure 2 , is a flow chart of the signal processing method provided in the embodiment of the present application. As an example and not a limitation, Figure 2 As shown, the signal processing method may include the following steps:

[0072] S201: Receive a first signal sent by a first target network; wherein the first target network is the first network or the second network.

[0073] In one implementation, the message conversion module 12 in the receive circuit drives the PHY chip to receive signals. The PHY chip then sends the received signals in parallel to the CRC module 11, message conversion module 12, and redundant frame arbitration module 13 in the receive circuit. Accordingly, the CRC module 11, message conversion module 12, and redundant frame arbitration module 13 process the received signals in parallel and send their processing results to the message buffer module 14.

[0074] Of course, in other implementations, the CRC module 11, the message conversion module 12, and the redundant frame arbitration module 13 may also perform serial processing. Compared with serial processing, the above-mentioned parallel processing method can improve processing efficiency.

[0075] Compared to ordinary Ethernet packets, redundant network packets not only have the same structure as ordinary Ethernet packets, but also have specific tags. For example, PRP packets have a 6-byte PRP tag inserted before the trailing CRC checksum. HSR packets have a 6-byte HSR tag inserted after the source Media Access Control (MAC) address or after the VLAN tag.

[0076] Based on this, in one implementation, the message conversion module 12 converts the received signal from a binary stream (bit stream) into a byte stream, which can be recorded as the first signal. If the first signal includes a preset flag, the first target network is determined to be the second network; if the first signal does not include the preset flag, the first target network is determined to be the first network. The preset flag is a data field used to indicate redundant signals, such as a PRP flag or an HSR flag.

[0077] S202: If the first target network is the first network, cache the first signal to instruct the central processor to obtain the first signal.

[0078] In one implementation, after determining that the first target network is the first network, the CRC module 11 and the redundant frame arbitration module 13 do not need to process the first signal, and the message conversion module 12 directly sends the first signal to the message cache module 14; if the message cache module 14 receives the first signal and does not receive the processing results of the CRC module 11 and the redundant frame arbitration module 13, it directly caches the first signal.

[0079] In another implementation, after determining that the first target network is the first network, CRC module 11 verifies the correctness of the first signal, obtains a first result, and sends the first result to message buffer module 14. Redundant frame arbitration module 13 directly outputs a second result to message buffer module 14, indicating that the first signal is not a redundant signal. Message buffer module 14 determines whether to cache the first signal based on the first and second results. Specifically, if the first result indicates that the verification passes (i.e., the first signal is correct), message buffer module 14 caches the first signal. If the first result indicates that the verification fails (i.e., the first signal is incorrect), message buffer module 14 discards the first signal.

[0080] Compared with the former implementation, the latter implementation requires CRC check, which can effectively ensure the correctness of the message and reduce the CPU's processing of invalid messages, thereby helping to improve processing efficiency and reliability.

[0081] S203: If the first target network is the second network, perform redundancy detection on the first signal to obtain a detection result.

[0082] It is understood that if the first target network is the second network, it indicates that the first target network is a redundant network, that is, the received first signal may be a redundant signal. To reduce repeated processing of redundant signals, in the embodiment of the present application, redundancy detection is performed on the first signal and the detection results are cached, thereby achieving automatic processing of redundant signals.

[0083] In one implementation, the redundancy detection process of S203 may include:

[0084] Verifying the correctness of the first signal to obtain a first result;

[0085] detecting whether a third signal is received before the first signal to obtain a second result; wherein the third signal and the first signal are redundant signals to each other;

[0086] If the first result indicates that the verification is passed and the second result indicates that the third signal is not received, then the detection result indicates that the first signal is not a redundant signal;

[0087] If the first result indicates that the verification fails, and / or the second result indicates that the third signal is received, then the detection result indicates that the first signal is a redundant signal.

[0088] based on Figure 1In the receiving circuit shown, the CRC module 11 can verify the correctness of the first signal to obtain a first result. The redundant frame arbitration module 13 can detect whether a third signal is received before the first signal to obtain a second result. The message buffer module 14 can determine whether the first signal needs to be buffered based on the first and second results.

[0089] In the above implementation, a signal correctness verification process is added to the redundancy detection process, which can effectively ensure the correctness of the message and reduce the CPU's processing of invalid messages, thereby helping to improve processing efficiency and reliability.

[0090] CRC is a data transmission error detection function used to detect errors during data transmission. It calculates a checksum (CRC code) on the original data and compares it with the received data to determine data integrity. For example, one CRC verification process involves padding the original data with zeros (the number of zeros is equal to the number of bits in the generator polynomial minus 1). The remainder obtained by dividing the zero-padded data by the generator polynomial is the CRC value. The sender transmits the original data along with the CRC value, and the receiver repeatedly calculates and compares the CRC value to verify the data.

[0091] Optionally, the first signal and the third signal have the same source MAC address and the same PRP / HSR frame sequence number. Accordingly, the process of detecting whether the third signal exists may include: detecting whether a signal with the same source MAC address as the first signal is received before the first signal; if not, determining that the third signal does not exist; if so, determining whether the PRP / HSR frame sequence number of the signal is the same as that of the first signal; if different, determining that the third signal does not exist; if the same, recording the signal as the third signal.

[0092] Optionally, if the third signal exists, the first signal may be discarded, so that only the third signal received first is retained in the cache, which can reduce the CPU's repeated processing of redundant signals.

[0093] S204: Convert the first signal into a second signal, where the data structure of the second signal complies with the data structure of the network protocol of the first network.

[0094] like Figure 1 In the receiving circuit shown, S202 may be executed by the message conversion module 12 .

[0095] In one implementation, the conversion process of S204 may include:

[0096] Converting the first signal from a binary stream to a byte stream to obtain a fourth signal;

[0097] The preset mark in the fourth signal is deleted to obtain the second signal; wherein the preset mark is a data field used to represent a redundant signal.

[0098] As described in the above embodiment, when the first target network adopts the PRP protocol, the preset mark is the PRP mark. When the first target network adopts the HSR protocol, the preset mark is the HSR mark.

[0099] Through the above conversion processing, the FPGA converts the signals of other redundant protocols into signals of the basic communication protocol. In this way, the CPU does not need to care about the protocol of the external connection network and still processes it according to ordinary Ethernet messages, which greatly reduces the processing complexity of the CPU.

[0100] S205: If the detection result indicates that the first signal is not a redundant signal, cache the second signal to instruct the central processing unit to obtain the second signal.

[0101] like Figure 1 In the receiving circuit shown, after the message buffer module 14 determines that the first signal is not a redundant signal, it buffers the second signal.

[0102] In some implementations, the message cache module 14 may set a corresponding cache area for each redundant network. For example, a network card connects network A and network B, where network A and network B are redundant networks using the PRP protocol. The message cache module 14 may set a cache area a corresponding to network A and a cache area b corresponding to network B.

[0103] When the FPGA receives the first signal sent by network A, the redundant frame arbitration module 13 can detect whether there is a third signal in the cache area b corresponding to network B; if the third signal is detected, it means that before receiving the first signal, network B has sent a third signal that is redundant with the first signal to the network card. In this case, the message cache module 14 discards the first signal and retains the third signal in the cache area b; if the third signal is not detected, it means that before receiving the first signal, network B has not sent a third signal that is redundant with the first signal to the network card. In this case, the message cache module 14 stores the first signal in the cache area a corresponding to network A.

[0104] Similarly, when the FPGA receives the first signal sent by network B, the redundant frame arbitration module 13 can detect whether a third signal exists in cache area a corresponding to network A. If the third signal is detected, it means that network A has already sent a third signal that is redundant with the first signal to the network card before receiving the first signal. In this case, the message cache module 14 discards the first signal and retains the third signal in cache area a. If the third signal is not detected, it means that network A has not sent a third signal that is redundant with the first signal to the network card before receiving the first signal. In this case, the message cache module 14 stores the first signal in cache area b corresponding to network B. The CPU can poll cache areas a and b via the bus to obtain the cached signals.

[0105] In the embodiments of the present application, the FPGA not only converts redundant signals into ordinary Ethernet messages but also automatically performs redundancy processing. This allows the network card to flexibly access redundant networks, reduces the complexity of implementing redundant protocols on the CPU, and eliminates the need for additional redundancy boxes or switches, thus reducing the hardware cost of redundancy processing.

[0106] See also Figure 3 , is a schematic diagram of the functional modules of the FPGA transmission circuit provided in an embodiment of the present application. By way of example and not limitation, the FPGA transmission circuit may include a transmission buffer unit 31 and a transmission control unit 32. The transmission buffer unit 31 may include a transmission buffer module 311, a forwarding arbitration module 312, a forwarding buffer module 313, and a cache polling state machine 314. The transmission control unit 32 may include a transmission controller state machine 321, a first message transmission control module 322, a second message transmission control module 323, a third message transmission control module 324, and a selection module 325.

[0107] like Figure 3 As shown, the FPGA's transmission loop may include a third connection terminal, a fourth connection terminal, and a fifth connection terminal. The third connection terminal is used to connect to the external network, the fourth connection terminal is used to connect to the CPU, and the fifth connection terminal is used to connect to the external network. It should be noted that when the network card is connected to a redundant network, the third connection terminal and the fifth connection terminal are respectively used to connect to the two subnets of the redundant network. For example, when the network is connected to a PRP redundant network, the third connection terminal is connected to network A, and the fifth connection terminal is connected to network B.

[0108] In the transmit buffer unit 31, the transmit buffer module 311 is used to store network messages sent by the CPU. The forwarding buffer module 313 is used to store messages received from a redundant network subnet that need to be forwarded. The forwarding arbitration module 312 is used to determine whether a message received from one redundant network subnet should be forwarded to another redundant network subnet. The cache polling state machine 314 is used to poll the messages to be sent stored in the transmit buffer module 311 and the forwarding buffer module 313.

[0109] In the transmit control unit 32, the transmit controller state machine 321 is used to read the cache from the cache polling state machine 314. The first, second, and third message transmit control modules 322, 323, and 324 are used to convert cached signals into different types of signals. For example, the first message transmit control module 322 is used to convert cached signals into signals corresponding to the base protocol; the second message transmit control module 323 is used to convert cached signals into signals corresponding to the PRP protocol; and the third message transmit control module 324 is used to convert cached signals into signals corresponding to the HSR protocol. The selection module 325 is used to select which message transmit control module's converted signal to use to drive the PHY chip, based on the network card's configured mode.

[0110] It should be noted that the number of message sending control modules in the sending control unit 32 can be determined according to the number of types of networks connected to the network card, and can include more than Figure 3 More numbers and types of message sending control modules can also be included. Figure 3 The message sending control modules shown are fewer in number and fewer in types, and the embodiments of the present application do not make specific limitations on this.

[0111] based on Figure 3 The functional module of the FPGA sending circuit is shown in FIG. The signal sending process is described below. It should be noted that the signal sending process in the embodiment of the present application refers to the process of the network card sending a signal.

[0112] See also Figure 4 , is a flow chart of the signal processing method provided in an embodiment of the present application. Figure 4 The figure shows the process of FPGA sending the message sent by CPU to the network. As an example and not a limitation, Figure 4 As shown, the signal processing method may include the following steps:

[0113] S401, receiving a fifth signal and a first instruction sent by a CPU; wherein the first instruction is used to indicate a second target network, and the second target network is the first network or the second network.

[0114] Optionally, the first instruction may be sent by the CPU. For example, the CPU sends the fifth signal and the first instruction to the sending buffer module 311 via the fourth connection terminal. Accordingly, after receiving the fifth signal and the first instruction, the sending buffer module 311 of the FPGA determines whether the second target network indicated by the first instruction is the first network or the second network. For another example, the CPU sends the fifth signal, the first instruction, and the network type (first network or second network) described in the second target network to the sending buffer module 311 via the fourth connection terminal. Accordingly, after receiving the fifth signal, the first instruction, and the network type, the sending buffer module 311 of the FPGA can determine the network type of the second target network.

[0115] S402: If the second target network is the first network, send the fifth signal to the second target network.

[0116] In this case, since the first network and the CPU use the same network protocol, no signal conversion processing is required.

[0117] like Figure 3 In the sending loop shown, the cache polling state machine 314 obtains the fifth signal from the sending cache module 311, and the sending controller state machine 321 reads the fifth signal from the cache polling state machine 314; the first message sending control module 322, the second message sending control module 323 and the third message sending control module 324 work in parallel, the first message sending control module 322 converts the fifth signal from a byte stream to a bit stream, the second message sending control module 323 converts the fifth signal from a byte stream to a bit stream and then converts it into a signal corresponding to the PRP protocol, and the third message sending control module 324 converts the fifth signal from a byte stream to a bit stream and then converts it into a signal corresponding to the HSR protocol; the selection module 325 selects to use the conversion signal of the first message sending control module 322 to drive the PHY chip according to the first instruction to send the converted signal to the second target network.

[0118] S403: If the second target network is the second network, convert the fifth signal into a sixth signal in a data format that complies with a network protocol of the second network.

[0119] In this case, since the second network and the network protocol used by the CPU are not consistent, signal conversion processing is required.

[0120] In one implementation, the conversion process of S403 may include:

[0121] generating a seventh signal according to a combination of a preset mark and the fifth signal; wherein the preset mark is a data field for indicating a redundant signal;

[0122] The seventh signal is converted from a byte stream into a binary stream to obtain the sixth signal.

[0123] like Figure 3 In the illustrated transmission loop, the above conversion process can be performed by the message transmission control module. For example, the second message transmission control module 323 generates a seventh signal based on the PRP flag and the fifth signal, and then converts the seventh signal from a byte stream to a binary stream to obtain the sixth signal. For another example, the third message transmission control module 324 generates a seventh signal based on the HSR flag and the fifth signal, and then converts the seventh signal from a byte stream to a binary stream to obtain the sixth signal.

[0124] S404: Send the sixth signal to the second target network.

[0125] like Figure 3 In the transmission circuit shown, the selection module 325 can select the corresponding converted signal of the message transmission control module according to the first instruction to drive the PHY chip. For example, when the second target network uses the PRP protocol, the selection module 325 selects the sixth signal converted by the second message transmission control module 323 to drive the PHY chip, thereby transmitting the sixth signal to the second target network. For another example, when the second target network uses the HSR protocol, the selection module 325 selects the sixth signal converted by the third message transmission control module 324 to drive the PHY chip, thereby transmitting the sixth signal to the second target network.

[0126] In this embodiment of the present application, the FPGA can automatically convert messages sent by the CPU into signals for the redundant network. This allows the network card to flexibly access the redundant network, reducing the complexity of the CPU implementing the redundant protocol and eliminating the need for additional redundant boxes or switches, thus reducing the hardware cost of the redundant processing.

[0127] See also Figure 5 , is a flowchart of a signal processing method provided by another embodiment of the present application. Figure 5 The figure shows the process of FPGA forwarding a message from one subnet of a redundant network to another subnet. Figure 5 As shown, the signal processing method may include the following steps:

[0128] S501, receiving an eighth signal and a second instruction sent by a third target network; wherein the third target network is the second network; the second instruction is used to indicate a fourth target network, and the fourth target network is a network in the first network or the second network that is redundant with the third target network.

[0129] Optionally, the second instruction may be sent by the third target network. For example, the third target network sends the eighth signal and the second instruction to the forwarding arbitration module 312 via the fifth connection terminal. Accordingly, after receiving the eighth signal and the second instruction, the forwarding arbitration module 312 of the FPGA determines whether the fourth target network indicated by the second instruction is the first network or the second network. For another example, the third target network sends the eighth signal, the second instruction, and the network type (first network or second network) described by the fourth target network to the forwarding arbitration module 312 via the fifth connection terminal. Accordingly, after receiving the eighth signal, the second instruction, and the network type, the forwarding arbitration module 312 of the FPGA can determine the network type of the fourth target network.

[0130] S502: Determine whether to forward the eighth signal.

[0131] like Figure 3 The sending loop shown may be executed by the forwarding arbitration module 312 in step S502 .

[0132] In one implementation, the determination process of S502 may include:

[0133] Get the network protocol currently set by the CPU;

[0134] If the network protocol currently set by the CPU is not the High Availability Seamless Redundancy Protocol (HSR protocol), it is determined not to forward the eighth signal;

[0135] If the network protocol currently set by the CPU is a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is inconsistent with the physical address of the network card, determining to forward the eighth signal;

[0136] If the third target network adopts a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is consistent with the physical address of the network card, it is determined not to forward the eighth signal.

[0137] In this implementation, the forwarding arbitration module 312 performs arbitration only when the network is configured to use the HSR protocol. When the network is configured to use the PRP protocol or a common Ethernet protocol, the forwarding arbitration module 312 does not perform arbitration and directly prohibits forwarding messages, i.e., does not write the eighth signal into the forwarding buffer module 313.

[0138] S503: If the eighth signal is forwarded, the eighth signal is sent to the fourth target network.

[0139] like Figure 3In the transmission loop shown, if the eighth signal is forwarded, the forwarding arbitration module 312 sends the eighth signal to the forwarding cache module 313. The cache polling state machine 314 obtains the eighth signal from the forwarding cache module 313, and the transmission controller state machine 321 reads the eighth signal from the cache polling state machine 314. The first message sending control module 322, the second message sending control module 323, and the third message sending control module 324 operate in parallel. The first message sending control module 322 converts the eighth signal from a byte stream to a bit stream, the second message sending control module 323 converts the eighth signal from a byte stream to a bit stream, and then converts it into a signal corresponding to the PRP protocol. The third message sending control module 324 converts the eighth signal from a byte stream to a bit stream, and then converts it into a signal corresponding to the HSR protocol. The selection module 325 selects the conversion signal of the corresponding message sending control module to drive the PHY chip according to the second instruction to send the converted signal to the fourth target network.

[0140] In this embodiment of the present application, the FPGA can forward messages sent from the redundant network to the standard Ethernet or another subnet of the redundant network. This allows the network card to flexibly access the redundant network and automatically process redundant signals, reducing the complexity of the CPU's redundant protocol implementation and eliminating the need for additional redundant boxes or switches, thus reducing the hardware cost of redundant processing.

[0141] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0142] Corresponding to the signal processing method described in the above embodiment, Figure 6 This is a structural block diagram of the signal processing device provided in an embodiment of the present application. For the sake of convenience, only the parts related to the embodiment of the present application are shown.

[0143] Reference Figure 6 , the device 6 comprises:

[0144] A receiving circuit 61 is configured to receive a first signal transmitted by a first target network; wherein the first target network is the first network or the second network; if the first target network is the second network, performing redundancy detection on the first signal to obtain a detection result; converting the first signal into a second signal, wherein the data structure of the second signal conforms to the data structure of the network protocol of the first network; and if the detection result indicates that the first signal is not a redundant signal, caching the second signal to instruct the central processing unit to obtain the second signal.

[0145] Optionally, the receiving circuit 61 is further configured to verify the correctness of the first signal to obtain a first result;

[0146] Detect whether a third signal is received before the first signal to obtain a second result; wherein, the third signal and the first signal are redundant signals to each other; if the first result indicates that the check is passed and the second result indicates that the third signal is not received, then the detection result indicates that the first signal is not a redundant signal; if the first result indicates that the check is not passed, and / or the second result indicates that the third signal is received, then the detection result indicates that the first signal is a redundant signal.

[0147] Optionally, the receiving circuit 61 is further used to convert the first signal from a binary stream into a byte stream to obtain a fourth signal; delete a preset mark in the fourth signal to obtain the second signal; wherein the preset mark is a data field used to represent a redundant signal.

[0148] Optionally, the device 6 further includes:

[0149] The sending circuit 62 is used to receive the fifth signal and the first instruction sent by the central processing unit; wherein the first instruction is used to indicate a second target network, and the second target network is the first network or the second network; if the second target network is the second network, the fifth signal is converted into a sixth signal in a data format that complies with the network protocol of the second network; and the sixth signal is sent to the second target network.

[0150] Optionally, the sending circuit 62 is further used to generate a seventh signal based on a preset mark and the fifth signal combination; wherein the preset mark is a data field used to represent a redundant signal; and convert the seventh signal from a byte stream into a binary stream to obtain the sixth signal.

[0151] Optionally, the sending loop 62 is also used to receive an eighth signal and a second instruction sent by a third target network; wherein the third target network is the second network; the second instruction is used to indicate a fourth target network, and the fourth target network is a network in the first network or the second network that is redundant with the third target network; determine whether to forward the eighth signal; if the eighth signal is forwarded, send the eighth signal to the fourth target network.

[0152] Optionally, the sending loop 62 is also used to obtain the network protocol currently set by the CPU; if the network protocol currently set by the CPU is not the high-availability seamless redundancy protocol, it is determined not to forward the eighth signal; if the network protocol currently set by the CPU is the high-availability seamless redundancy protocol, and the source physical address of the eighth signal is inconsistent with the physical address of the network card, it is determined not to forward the eighth signal; if the third target network adopts the high-availability seamless redundancy protocol, and the source physical address of the eighth signal is consistent with the physical address of the network card, it is determined not to forward the eighth signal.

[0153] Optionally, the receiving circuit 61 is further configured to cache the first signal if the first target network is the first network, so as to instruct the central processing unit to obtain the first signal.

[0154] Optionally, the sending loop 62 is further configured to send the fifth signal to the second target network if the second target network is the first network.

[0155] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0156] in addition, Figure 6 The signal processing device shown can be a software unit, a hardware unit, or a combination of software and hardware units built into an existing terminal device, or can be integrated into the terminal device as an independent accessory, or can exist as an independent terminal device.

[0157] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0158] Figure 7 This is a schematic diagram of the structure of the terminal device provided in the embodiment of the present application. Figure 7As shown, the terminal device 7 of this embodiment includes: at least one processor 70 ( Figure 7 Only one is shown in the figure) a processor, a memory 71, and a computer program 72 stored in the memory 71 and executable on the at least one processor 70, wherein the processor 70 implements the steps of any of the above-mentioned signal processing method embodiments when executing the computer program 72.

[0159] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art will understand that Figure 7 It is only an example of the terminal device 7 and does not constitute a limitation on the terminal device 7. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0160] The processor 70 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0161] In some embodiments, the memory 71 may be an internal storage unit of the terminal device 7, such as a hard disk or memory of the terminal device 7. In other embodiments, the memory 71 may also be an external storage device of the terminal device 7, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device 7. Furthermore, the memory 71 may also include both an internal storage unit of the terminal device 7 and an external storage device. The memory 71 is used to store an operating system, application programs, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 71 may also be used to temporarily store data that has been output or is about to be output.

[0162] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.

[0163] An embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0164] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, a computer-readable medium cannot be an electric carrier signal or a telecommunication signal.

[0165] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0166] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0167] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0168] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0169] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A signal processing method, characterized in that: A programmable logic device used in a network card, the network card also including a central processing unit (CPU); the network card is connected to a first network and at least one second network, the first network is a non-redundant network, the second network is a redundant network, and the CPU and the first network use the same network protocol; the method comprising: receiving a first signal sent by a first target network; wherein the first target network is the first network or the second network; If the first target network is the second network, performing redundancy detection on the first signal to obtain a detection result; Converting the first signal into a second signal, wherein a data structure of the second signal complies with a data structure of a network protocol of the first network; If the detection result indicates that the first signal is not a redundant signal, the second signal is cached to instruct the central processing unit to obtain the second signal.

2. The signal processing method according to claim 1, wherein: The performing redundancy detection on the first signal to obtain a detection result includes: Verifying the correctness of the first signal to obtain a first result; detecting whether a third signal is received before the first signal to obtain a second result; wherein the third signal and the first signal are redundant signals to each other; If the first result indicates that the verification is passed and the second result indicates that the third signal is not received, then the detection result indicates that the first signal is not a redundant signal; If the first result indicates that the verification fails, and / or the second result indicates that the third signal is received, then the detection result indicates that the first signal is a redundant signal.

3. The signal processing method according to claim 1, wherein: The converting the first signal into a second signal comprises: Converting the first signal from a binary stream to a byte stream to obtain a fourth signal; The preset mark in the fourth signal is deleted to obtain the second signal; wherein the preset mark is a data field used to represent a redundant signal.

4. The signal processing method according to claim 1, wherein: The method further comprises: receiving a fifth signal and a first instruction sent by the central processor; wherein the first instruction is used to indicate a second target network, and the second target network is the first network or the second network; If the second target network is the second network, converting the fifth signal into a sixth signal in a data format that complies with a network protocol of the second network; The sixth signal is sent to the second target network.

5. The signal processing method according to claim 4, characterized in that Converting the fifth signal into a sixth signal in a data format conforming to a network protocol of the second network includes: generating a seventh signal according to a combination of a preset mark and the fifth signal; wherein the preset mark is a data field for indicating a redundant signal; The seventh signal is converted from a byte stream into a binary stream to obtain the sixth signal. The signal processing method according to claim 1 , wherein: The method further comprises: receiving an eighth signal and a second instruction sent by a third target network; wherein the third target network is the second network; and the second instruction is used to instruct a fourth target network, where the fourth target network is a network in the first network or the second network that is redundant with the third target network; determining whether to forward the eighth signal; If the eighth signal is forwarded, the eighth signal is sent to the fourth target network.

7. The signal processing method according to claim 5, characterized in that: The determining whether to forward the eighth signal includes: Get the network protocol currently set by the CPU; If the network protocol currently set by the CPU is not the high-availability seamless redundancy protocol, it is determined not to forward the eighth signal; If the network protocol currently set by the CPU is a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is inconsistent with the physical address of the network card, determining to forward the eighth signal; If the third target network adopts a high-availability seamless redundancy protocol, and the source physical address of the eighth signal is consistent with the physical address of the network card, it is determined not to forward the eighth signal.

8. The signal processing method according to claim 4, wherein: The method further comprises: If the first target network is the first network, buffering the first signal to instruct the central processor to obtain the first signal; If the second target network is the first network, the fifth signal is sent to the second target network.

9. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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