Backside illumination image sensor and method of manufacturing the same, electronic device

Abstract

The application relates to a back-illuminated image sensor preparation method, a back-illuminated image sensor and electronic equipment, which comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of first isolation structures extending in the substrate via a first surface of the substrate and arranged at intervals along a first direction parallel to the first surface; forming a first SiP layer on the first surface, and second isolation structures penetrating the first SiP layer along a second direction towards the substrate and connected with the first isolation structures; forming a groove between adjacent second isolation structures, and filling the groove with a SiAs material layer covering the top surfaces of the first SiP layer and the second isolation structures; forming third isolation structures connected with the second isolation structures in the SiAs material layer, and a plurality of second SiP layers distributed at intervals along the first direction between the third isolation structures; and the remaining SiAs material layer is used to form a SiAs layer. The method can simplify the process flow, increase the number of photo-generated carriers in the device, and improve the quantum efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a backside illuminated image sensor, a preparation method thereof and an electronic device. BACKGROUND

[0002] An image sensor is a photoelectric conversion device widely used in many fields such as consumer electronics, security monitoring, automotive electronics, and machine vision. According to the placement position of the metal line and the light receiving layer, it is divided into front-illuminated and back-illuminated. Among them, the backside illuminated (BSI) image sensor has higher sensitivity, better wiring layout, and allows high-speed recording, and is often used in fields with high requirements for image sensor pixel performance.

[0003] However, in today's deep submicron process, the traditional BSI front-end process needs to use high-energy ion implantation (IMP) to prepare a diode structure to form a pixel area, which may cause damage to the substrate surface. Non-uniform ion implantation will also cause signal crosstalk between different pixels, thereby hindering the further improvement of the performance of the BSI image sensor. SUMMARY

[0004] Therefore, it is necessary to provide a backside illuminated image sensor, a preparation method thereof and an electronic device to at least avoid signal crosstalk of the BSI image sensor and unnecessary damage caused by IMP.

[0005] In a first aspect, the present application provides a preparation method of a backside illuminated image sensor, comprising: providing a substrate, the substrate comprising a plurality of first isolation structures extending in the substrate through a first surface of the substrate and spaced apart along a first direction parallel to the first surface;

[0006] forming a first SiP layer on the first surface, and a second isolation structure penetrating the first SiP layer along a second direction towards the substrate and connected with the first isolation structure;

[0007] forming a trench between adjacent second isolation structures, and filling the trench with a SiAs material layer covering the top surface of the first SiP layer and the second isolation structure;

[0008] forming a third isolation structure connected with the second isolation structure in the SiAs material layer, and a plurality of second SiP layers spaced apart along the first direction between the third isolation structures; and the remaining SiAs material layer is used to form a SiAs layer;

[0009] wherein SiP represents silicon material doped with phosphorus P; and SiAs represents silicon material doped with arsenic As.

[0010] In the preparation method in the above embodiments, in order to improve the manufacturing efficiency, the preparation steps of the second and third isolation structures are interleaved in the process of preparing the stacked first SiP layer, second SiP layer and SiAs layer. By coordinating the preparation steps of different structures, the overall production process is optimized, so that the entire production process is more compact and efficient, and the front-end process is not affected during the process.

[0011] Based on the above preparation method, a plurality of stacked isolation structures are obtained, and the photoelectric material layers (i.e., the first SiP layer, the second SiP layer and the SiAs layer) arranged according to a predetermined rule between adjacent isolation structures are formed on the substrate to form a photoelectric diode structure. This effectively avoids unnecessary damage caused by high-energy ion implantation in traditional methods to form photoelectric diodes, reduces dark current caused by defects, and helps to improve the imaging clarity of the image sensor.

[0012] In some embodiments, forming the second isolation structure includes:

[0013] forming a first recess along the second direction through the first SiP layer, the first recess exposing part of the top surface of the first isolation structure;

[0014] epitaxially growing a first isolation material layer in the first recess;

[0015] removing the first isolation material layer whose top surface is higher than the first SiP layer, and the remaining first isolation material layer is used to constitute the second isolation structure.

[0016] In some embodiments, forming the third isolation structure includes:

[0017] forming a second recess along the second direction through the SiAs material layer, the second recess exposing the top surface of the second isolation structure;

[0018] forming a second isolation material layer filling the second recess by a spin coating process;

[0019] removing the second isolation material layer whose top surface is higher than the SiAs material layer, and the remaining second isolation material layer is used to constitute the third isolation structure.

[0020] In some embodiments, the SiAs layer includes:

[0021] a plurality of first SiAs layers are arranged one-to-one with a plurality of second SiP layers; and a second SiP layer is located directly above a first SiAs layer;

[0022] a plurality of second SiAs layers are alternately distributed between adjacent third isolation structures along the first direction with a plurality of second SiP layers.

[0023] In some embodiments, the first SiAs layer penetrates the first SiP layer along the second direction and extends into the substrate.

[0024] In some embodiments, the first isolation structure gradually increases in size along the first direction in a direction towards the substrate;

[0025] The second isolation structure gradually decreases in size along the first direction in a direction towards the substrate;

[0026] The third isolation structure is greater in size along the second direction than the second isolation structure is in size along the second direction.

[0027] In some embodiments, after forming the second SiP layer, the method further comprises:

[0028] forming a grating material layer covering the top surfaces of the second SiP layer, the second SiAs layer, and the third isolation structure;

[0029] removing part of the grating material layer to form gratings and third grooves arranged alternately along the first direction; the gratings are located directly above the third isolation structures arranged one-to-one;

[0030] forming, in the third grooves, a SiP cover layer and a filter layer stacked in a direction away from the substrate.

[0031] In a second aspect, the present application also provides a back-illuminated image sensor prepared by any of the above-mentioned methods, the back-illuminated image sensor comprising:

[0032] a substrate, the substrate comprising a plurality of first isolation structures extending through the substrate from a first surface of the substrate in a direction towards the substrate and arranged at intervals along a first direction parallel to the first surface;

[0033] a first SiP layer located on the first surface, comprising a second isolation structure and a first SiAs layer arranged alternately along the first direction, the second isolation structure being connected to the first isolation structure, the second isolation structure penetrating the first SiP layer along a second direction towards the substrate;

[0034] a plurality of third isolation structures arranged one-to-one with the second isolation structures;

[0035] a plurality of second SiAs layers arranged alternately with the second SiP layer along the first direction between adjacent third isolation structures; a second SiP layer is located directly above a first SiAs layer;

[0036] a plurality of gratings located directly above the third isolation structures;

[0037] a SiP cover layer located between adjacent gratings.

[0038] In the above embodiment, the physical shielding structure is formed by stacking the first isolation structure, the second isolation structure, and the third isolation structure through the pixel area of the back-illuminated image sensor, which can effectively avoid the diffusion and drift of charges into adjacent pixels, and the case of light diffusing to adjacent pixels, thereby inhibiting the adverse effects of optical and electrical crosstalk on the image clarity; the first SiP layer, the second SiP layer, the first SiAs layer, the second SiAs layer, and the SiP layer arranged between the adjacent isolation structures according to the preset rule form a pixel area with a cross-section in the shape of a waterfall, which can optimize the generation and separation process of carriers, increase the number of photo-generated carriers, reduce the recombination rate in the conversion process, and improve the photoelectric response efficiency.

[0039] In some embodiments, the substrate comprises a P-type doping element;

[0040] The size of the first isolation structure along the first direction gradually increases in the direction towards the substrate;

[0041] The size of the second isolation structure along the first direction gradually decreases in the direction towards the substrate;

[0042] The size of the third isolation structure along the second direction is greater than the size of the second isolation structure along the second direction.

[0043] In a third aspect, the present application also provides an electronic device comprising the back-illuminated image sensor prepared by the preparation method of any one of the above aspects; or the back-illuminated image sensor described in the above embodiments.

[0044] The electronic device equipped with the back-illuminated image sensor prepared by the preparation method of the present application can reduce equipment loss and maintenance cost, speed up research and production, and shorten the product marketing cycle, thanks to its simplified process flow. In addition, the dark current of the back-illuminated image sensor is reduced, the quantum efficiency is increased, the image noise is reduced, the light sensitivity is improved in low light environments, and the imaging is clearer.

[0045] The back-illuminated image sensor and the preparation method and the electronic device thereof in the embodiments of the present application have the following unexpected technical effects:

[0046] In the process of making the first SiP layer, the second SiP layer, and the SiAs layer of the stacked structure, the formation steps of the second and third isolation structures are introduced synchronously, so as to avoid the damage that may be caused by high-energy ion implantation while realizing the compactness and efficiency of the production process.

[0047] The regularly arranged optoelectronic material layers (i.e., the first SiP layer, the second SiP layer, the SiAs layer, and the SiP capping layer) and the substrate form a "waterfall-shaped" photodiode structure in the pixel region. This effectively optimizes the carrier transport process, increases the number of photogenerated carriers, and improves photoelectric response efficiency. The physical shielding structure that runs through the pixel region (i.e., the first isolation structure, the second isolation structure, and the third isolation structure) effectively suppresses the negative impact of crosstalk on imaging quality. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart of a back-illuminated image sensor fabrication method provided in one embodiment;

[0050] Figure 2a This is a schematic cross-sectional view of the structure obtained after forming an interlayer dielectric layer in step S24 of the preparation method provided in one embodiment;

[0051] Figure 2b This is a schematic cross-sectional view of the structure obtained after the initial substrate is thinned in step S26 of the preparation method provided in one embodiment;

[0052] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the first SiP layer in step S42 of the preparation method provided in one embodiment;

[0053] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming the first groove in step S44 of the preparation method provided in one embodiment;

[0054] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the first isolation material layer in step S46 of the preparation method provided in one embodiment;

[0055] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the second isolation structure in step S48 of the preparation method provided in one embodiment;

[0056] Figure 7 for Figure 6 A schematic diagram of the cross-section of the structure after the trench is formed;

[0057] Figure 8 for Figure 7 A schematic diagram of the cross-section of the structure obtained after the SiAs material layer is formed in the middle;

[0058] Figure 9 A cross-sectional view of the structure after forming the second groove in step S82 of the method provided in an embodiment;

[0059] Figure 10 A cross-sectional view of the structure after forming the third isolation structure in step S88 of the method provided in an embodiment;

[0060] Figure 11 A cross-sectional view of the structure after forming the second groove in step S810 of the method provided in an embodiment;

[0061] Figure 12 A cross-sectional view of the structure after forming the second SiP layer in step S812 of the method provided in an embodiment;

[0062] Figure 13 A cross-sectional view of the structure after forming the grid material layer in step S820 of the method provided in an embodiment; Figure 12

[0063] A cross-sectional view of the structure after forming the grid and the third groove in step S830 of the method provided in an embodiment; Figure 14 Figure 13 A cross-sectional view of the structure after forming the SiP cap layer in step S840 of the method provided in an embodiment;

[0064] Figure 15 Figure 14 A cross-sectional view of the structure after forming the optical filter in step S850 of the method provided in an embodiment;

[0065] Figure 16 A cross-sectional view of the structure after forming the optical filter in step S850 of the method provided in an embodiment; Figure 15

[0066] BRIEF DESCRIPTION OF THE DRAWINGS

[0067] 1, initial substrate; 10, substrate; 10a, first surface; 11, etching stop layer; 12, interlayer dielectric layer; 13, first SiP layer; 141, SiAs material layer; 14, SiAs layer; 14a, first SiAs layer; 14b, second SiAs layer; 15, second SiP layer; 16, SiP cap layer; 221, first isolation material layer; 21, first isolation structure; 22, second isolation structure; 23, third isolation structure; 31, first groove; 32, second groove; 33, third groove; 41, first trench; 42, second trench; 50, grid; 501, first grid material layer; 502, second grid material layer; 503, third grid material layer; 60, optical filter. DETAILED DESCRIPTION

[0068] ​​​For the purposes of the present application, the following terms are intended to have the meanings set forth below. The term "about" means approximately or nearly as understood by persons skilled in the art. For example, the term "about 90°" can mean in the range from 85° to 95°. The term "coupled" means directly or indirectly connected, linked, or associated, whether electrically, mechanically, or chemically, or any combination thereof. The term "coupled" does not require direct connection, linkage, or association, but rather means that the items connected, linked, or associated indirectly share some common element or feature.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0070] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a first

[0071] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0072] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0073] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implant in the region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application, unless otherwise defined herein.

[0074] In the embodiments of the present application, the substrate can include a first surface at the front side, and a back side opposite to the front side, i.e., a second surface. In the case of ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and a direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. A first direction and a third direction are defined in the top surface and the bottom surface direction of the substrate (i.e., the plane in which the substrate is located), and the first direction and the third direction intersect each other (e.g., perpendicular to each other). For example, the arrangement direction of the target isolation structure is the first direction, and the plane in which the substrate is located can be determined based on the first direction and the third direction. Among them, the first direction, the second direction and the third direction can be perpendicular to each other in pairs. In the embodiments of the present application, the first direction is defined as the Y-axis direction, the second direction is defined as the Z-axis direction, and the third direction is defined as the X-axis direction.

[0075] Referring to Figures 1-16 The present application provides a back-illuminated image sensor manufacturing method, comprising: steps S20-S80.

[0076] Step S20: providing a substrate 10, the substrate 10 includes a plurality of first isolation structures 21 extending in the substrate via a first surface of the substrate 10, and arranged at intervals along a first direction (OY direction) parallel to the first surface.

[0077] For example, the substrate 10 can be made of a semiconductor material, an insulating material, a conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the material of the substrate 10 includes but is not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductors or II / VI semiconductors. Alternatively, for example, the substrate 10 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon germanium on insulator. Therefore, the type of the substrate 10 should not limit the protection scope of the present disclosure. In the embodiments, the material of the substrate 10 includes silicon (Si).

[0078] For example, the material of the first isolation structure 21 can include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, etc. or a combination thereof.

[0079] Among them, the first isolation structure 21 is used to isolate electrons and light energy. For example, the cross-sectional shape of the first isolation structure 21 along the OY direction can include a right trapezoid, an inverted trapezoid, a rectangle, etc., or can also be a combination of right trapezoids, inverted trapezoids and rectangles. The embodiments of the present application only require that the first isolation structure 21 can isolate electrons and light energy. In addition, the embodiments of the present application do not make specific limitations on the distance between adjacent first isolation structures 21, which can be set according to actual needs.

[0080] Step S40: forming a first SiP layer 13 on the first surface, and penetrating the first SiP layer 13 along a second direction (ZO direction, i.e. the opposite direction of OZ direction) toward the substrate, and connecting the second isolation structure 22 with the first isolation structure 21.

[0081] For example, the second isolation structure 22 has the same cross-sectional shape as the first isolation structure 21 along the OY direction.

[0082] For example, the first SiP layer 13 is used to represent a silicon layer doped with phosphorus (P) ions, i.e. an N-type silicon layer.

[0083] Step S60: forming a trench between adjacent second isolation structures 22, and filling the trench with a SiAs material layer 141 covering the top surface of the first SiP layer 13 and the second isolation structure 22.

[0084] For example, the SiAs material layer 141 is used to represent a silicon layer doped with arsenic (As) ions, which is also an N-type silicon layer as the first SiP layer 13. The same logic applies to the SiP and SiAs layers in the subsequent embodiments, which will not be described in detail here.

[0085] Step S80: forming a third isolation structure 23 connected with the second isolation structure 22 in the SiAs material layer 141, and a plurality of second SiP layers 15 spaced apart along the first direction (OY direction) between the third isolation structures 23; the remaining SiAs material layer 141 is used to form a SiAs layer 14.

[0086] For example, the second SiP layer 15 is also a silicon layer doped with phosphorus (P) ions, but the doping concentration can be the same as or different from the doping concentration of the first SiP layer 13.

[0087] The structure of the back-illuminated image sensor obtained after steps S20-S80 can be referred to as Figure 16 Of course, in order to facilitate the understanding of the present application, Figure 16 a kind of example of back-illuminated image sensor prepared by the back-illuminated image sensor preparation method of the present application is given, and the back-illuminated image sensor prepared by the back-illuminated image sensor preparation method of the present application can also have other suitable examples, which are not limited by the present application.

[0088] In the above embodiment, the plurality of isolation structures (i.e., the second isolation structure 22 and the third isolation structure 23) arranged in the pixel region can be formed simultaneously in the process of forming the pixel region (i.e., the first SiP layer 13, the SiAs layer 14, and the second SiP layer 15). Adjusting the preparation sequence of the isolation structures and the pixel region can avoid unnecessary damage caused by implanting high-energy ions between adjacent isolation structures to form the photodiode, reduce the dark current in the pixel region, and help improve the imaging clarity of the image sensor. Since the second isolation structure 22 and the third isolation structure 23 penetrate the above-mentioned photodiode, the signal crosstalk between adjacent pixel regions is effectively reduced.

[0089] It should be understood that, although Figure 1 The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps in the flowchart can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0090] For the above steps, specific descriptions are made with reference to the accompanying drawings.

[0091] Please refer to Figure 2a and Figure 2b In some embodiments, step S20 includes steps S22-S26.

[0092] Step S22: providing an initial substrate 1, and forming first isolation structures 21 spaced apart along a first direction (OY direction) in the initial substrate 1.

[0093] For example, a P-type silicon wafer is used as a substrate wafer. In the front-end-of-line (FEOL) process, shallow trench isolation structures (STI) are formed in the initial substrate 1, which are spaced apart along the first direction (OY direction) and have a top surface flush with the top surface of the initial substrate 1, denoted as the first isolation structure 21.

[0094] The distance between the symmetry axes of two adjacent first isolation structures 21 is 500-700 nm, for example, 500 nm, 550 nm, 600 nm, 650 nm, or 700 nm, etc. In the above examples, the greater the spacing between two adjacent first isolation structures 21, the larger the pixel area of the BSI image sensor, i.e., the better the light sensing capability of the BSI image sensor. However, too large a spacing will result in excessively large pixels and reduced resolution. Therefore, when setting the distance between the symmetry axes of adjacent first isolation structures 21, the resolution and light sensing capability of the BSI should be considered in a balanced manner.

[0095] Step S24: Forming an etching stop layer 11 covering the first isolation structures 21 and an interlayer dielectric layer 12 covering the etching stop layer 11 on the initial substrate 1.

[0096] For example, referring to Figure 2a , first, an etching stop layer 11 is formed by a deposition process, then a metal is deposited to form a metal interconnection structure, and on this basis, an interlayer dielectric layer 12 is formed. Of course, this embodiment only represents one of the ways, the initial substrate 1 can also include other electrical structures, and the thickness of the etching stop layer 11 and the interlayer dielectric layer 12 is not limited, and can be adjusted according to the specific process requirements, but since it is not the focus of this embodiment, it will not be discussed here.

[0097] The etching stop layer 11 can be single-layer or multi-layer, and the material can include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, etc. or combinations thereof.

[0098] The interlayer dielectric layer 12 can be a silicon oxide layer.

[0099] Step S26: Performing a thinning process on the initial substrate 1 on the side away from the interlayer dielectric layer 12.

[0100] For example, referring to Figure 2b , the initial substrate 1 is flipped, and a chemical mechanical polishing (CMP) is used to thin and planarize the initial substrate 1, exposing the surface (i.e., the first surface 10a) of the first isolation structure 21 away from the interlayer dielectric layer 12. At this time, the remaining initial substrate 1 is used to constitute the substrate 10.

[0101] For example, referring to Figures 3-6 , in some embodiments, step S40 includes steps S42-S48.

[0102] Step S42: Forming a first SiP layer 13 on the first surface 10a.

[0103] For example, referring to Figure 3For example, the first SiP layer 13 is formed by epitaxial growth with a thickness of 20-30 nm. The epitaxial growth can avoid the problems of crystal structure damage, temperature rise and electric field effect caused by ion implantation, and can realize more accurate control of film thickness, and ensure the consistency and reliability of the structure.

[0104] For example, the thickness of the first SiP layer 13 can be 20 nm, 25 nm or 30 nm, etc.

[0105] Step S44: forming a first groove 31 penetrating the first SiP layer 13 along the second direction, the first groove 31 exposing part of the top surface of the first isolation structure 21.

[0106] Please refer to Figure 4 For example, a photoresist layer is coated on the top surface of the first SiP layer 13, and a series of steps such as exposure and development are performed to pattern the photoresist layer, and then a dry etching or wet etching method is used to form a shallow trench, which is referred to as the first groove 31. The first groove 31 is arranged corresponding to the first isolation structure 21, for example, one-to-one, that is, the center lines of the first groove 31 and the first isolation structure 21 in the depth direction are located on the same straight line.

[0107] Before the photolithography process, a layer of oxide layer can be deposited as an isolation layer to prevent damage to the first SiP layer 13 caused by etching, and to passivate the trench corner.

[0108] Step S46: epitaxially growing a first isolation material layer 221 in the first groove 31, wherein the top surface of the first isolation material layer 221 is not lower than the top surface of the first SiP layer 13.

[0109] For example, please refer to Figure 5 The first isolation material layer 221 with high quality is grown in the first groove 31 by epitaxial growth process.

[0110] The material of the first isolation material layer 221 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, etc. or a combination thereof.

[0111] Step S48: removing the first isolation material layer 221 whose top surface is higher than the first SiP layer 13, and the remaining first isolation material layer 221 is used to constitute the second isolation structure 22.

[0112] For example, please refer to Figure 6 The first isolation material layer 221 can be planarized by chemical mechanical polishing (CMP) process and removed from the first SiP layer 13, or any other planarization process, which should not be limited to one way here.

[0113] The remaining first isolation material layer 221 in the first groove 31 forms a shallow trench isolation structure, denoted as a second isolation structure 22, and is connected to the first isolation structure 21.

[0114] Referring to Figures 7-8 , step S60: forming a first trench 41 between adjacent second isolation structures 22, and filling the first trench 41 with a SiAs material layer 141 covering the top surface of the first SiP layer 13 and the second isolation structure 22. Further comprising:

[0115] Illustratively, referring to Figure 7 , after lithography, the first SiP layer 13 between adjacent second isolation structures 22 is etched to form a first trench 41 penetrating the first SiP layer 13 along the second direction (ZO direction). Then, referring to Figure 8 , a SiAs material layer 141 covering the top surface of the first SiP layer 13 and the second isolation structure 22 is formed by epitaxial growth.

[0116] Referring to Figures 9-12 , in some embodiments, step S80 comprises steps S82-S812.

[0117] Step S82: forming a second groove 32 penetrating the SiAs material layer 141 along the second direction (ZO direction), the second groove 32 exposing the top surface of the second isolation structure 22.

[0118] Illustratively, referring to Figure 9 , a deep trench, denoted as a second groove 32, is formed by lithography and etching. It should be noted that the second groove 32 is one-to-one arranged with the second isolation structure 22, and the width (dimension along the OY direction) is consistent with the width of the top surface of the second isolation structure 22, which means that the position of the second groove 32 can be defined based on the mask used to form the first groove 31, and the reuse of the mask can effectively reduce the process cost.

[0119] Step S84: forming a second isolation material layer (not shown) filling the second groove 32 by spin coating process.

[0120] Illustratively, then a liquid dielectric formed by mixing a solvent and silicon dioxide dielectric is coated in the second groove 32 by spin coating (Spin-On Glass, SOG) to form a second isolation material layer with a top surface not lower than the SiAs material layer 141. Due to the good flow performance of the liquid dielectric, it can effectively fill the second groove 32 with high aspect ratio, avoiding the problem of early closure of the pore corner and internal void defects in the traditional deposition method, and ensuring the isolation effect between pixels.

[0121] Step S88: removing the second isolation material layer higher than the SiAs material layer 141, and the remaining second isolation material layer is used to form the third isolation structure 23.

[0122] For example, referring to Figure 10 The second isolation material layer is planarized by a CMP process, and the top surface of the remaining second isolation material layer is flush with the top surface of the SiAs material layer 141, which is used to form a deep trench isolation structure, denoted as the third isolation structure 23.

[0123] In some embodiments, the first isolation structure 21 gradually increases in size along the first direction (OY direction) in a direction towards the substrate 10;

[0124] The second isolation structure 22 gradually decreases in size along the first direction (OY direction) in a direction towards the substrate;

[0125] The third isolation structure 23 has a size along the second direction (ZO direction) greater than that of the second isolation structure 22 along the second direction (ZO direction).

[0126] Specifically, the first isolation structure 21 and the second isolation structure 22 are both shallow trench isolation structures, and the third isolation structure 23 is a deep trench isolation structure. The shallow trench isolation structure is easier to manufacture than the deep trench isolation structure, and by manufacturing the first isolation structure 21, the second isolation structure 22 and the third isolation structure 23 in layers, a full physical shielding isolation region is formed through the pixel region.

[0127] Compared to manufacturing a deep trench isolation structure with a depth (size along the OZ direction) equivalent to that of the third isolation structure 23 in one step, the process is simple, and by providing a full physical shielding isolation region, the mutual crosstalk between light and electrons between the various light sensing regions is avoided, improving the display quality of the BSI image sensor based on this structure. Secondly, the design of the second isolation structure 22 gradually decreasing in width (size along the OY direction) can appropriately increase the light sensing area of the pixel region, improving the absorption and conversion efficiency of photons.

[0128] Step S810: forming a plurality of second trenches 42 spaced apart along the first direction (OY direction) in the SiAs material layer 141; a first trench 41 directly above includes a second trench 42.

[0129] For example, referring to Figure 11The SiAs material layer 141 between the adjacent third isolation structures 23 is removed based on a lithography and etching process to form the second groove 42. To reduce the process cost, the position of the second groove 42 can be defined on the top surface of the SiAs material layer 141 based on the same mask used to form the first groove 41, and in this case, the width (dimension along the OY direction) of the second groove 42 is the same as that of the first groove 41. Of course, other masks can also be used to define the second groove 42, as long as the center line of the second groove 42 is on the same line as that of the first groove 41. In this embodiment, the width of the first groove 41 is the same as that of the second groove 42, i.e., the same mask is used to form the two grooves.

[0130] In step S812, the second SiP layer 15 is formed in the second groove 42, and the remaining SiAs material layer 141 is used to form the SiAs layer 14.

[0131] For example, the second SiP layer 15 can be formed by a deposition process to fill the second groove 42, and then planarized to remove part of the second SiP layer 15 so that the top surface is flush with the top surface of the SiAs material layer 141, and the cross-sectional view of the obtained semiconductor structure is as shown in FIG. 8C. Figure 12

[0132] The first SiAs layer 14a is arranged one-to-one with the second SiP layer 15.

[0133] The second SiP layer 15 is located directly above the first SiAs layer 14a.

[0134] The second SiAs layer 14b is arranged alternately with the second SiP layer 15 along the first direction between the adjacent third isolation structures 23.

[0135] In another embodiment, the first SiAs layer 14a extends through the first SiP layer 13 along the second direction (ZO direction) and into the substrate 10.

[0136] Specifically, the first SiAs layer 14a and the first SiP layer 13 are both N-type and contact the P-type substrate 10 to form a double photodiode structure. Due to the difference in ionization energy between SiP and SiAs, compared with single doping, the non-uniform doping distribution helps to form a non-uniform electric field distribution in the pixel area, guiding the photo-generated carriers to move more efficiently to the collection area, reducing the recombination probability of the carriers in the generation and collection process. In addition, the first SiAs layer 14a extending into the substrate 10 increases the cross section of the PN junction interface, appropriately increases the junction capacitance, can store more charges formed by the photo-generated carriers, improves the efficiency of converting the optical signal into an electrical signal, and enhances the ability of the sensor to capture and respond to the optical signal.

[0137] Please refer to​Figures 13-16 In some embodiments, after forming the second SiP layer 15, further comprising:

[0138] Referring to Figure 13 a grating material layer is formed on the top surface of the second SiP layer 15, the second SiAs layer 14b and the third isolation structure 23 by a deposition method.

[0139] For example, the grating material layer includes a first grating material layer 501, a second grating material layer 502 and a third grating material layer 503, wherein the thickness of each grating material layer can be adjusted as needed without limitation.

[0140] The first grating material layer 501 includes but is not limited to one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxide nitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0141] The second grating material layer 502 includes but is not limited to titanium nitride (TiN).

[0142] The third grating material layer 503 includes but is not limited to cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), copper (Cu), aluminum (Al) and other metal materials.

[0143] In this embodiment, the material of the first grating material layer 501 is hafnium oxide (HfO2); the material of the second grating material layer 502 is titanium nitride (TiN); and the material of the third grating material layer is aluminum (Al).

[0144] Referring to Figure 14 part of the grating material layer is removed to form a grating 50 and a third groove 33 arranged alternately along the first direction (OY direction); the grating 50 is located directly above the one-to-one arranged third isolation structure 23.

[0145] For example, a patterned photoresist layer is used as a mask to define the position, shape and size of the grating 50, and then the grating material layer is etched to obtain the third groove 33 and the grating 50 arranged alternately along the OY direction. The grating 50 focuses light to the photosensitive area, increases the amount of light entering, and improves the photosensitive performance of the BSI image sensor.

[0146] In the above embodiment, the third groove 33 can be used to form the SiP cover layer 16 and the optical filter 60 at the same time, and by fully utilizing the structural characteristics of the back-illuminated image sensor, the difficulty of the preparation process of the multi-layer structure photodiode is reduced.

[0147] Referring to Figures 15-16 the SiP cover layer 16 and the optical filter 60 are sequentially formed in the third groove 33.

[0148] For example, the filter 60 includes, but is not limited to, a red filter, a yellow filter, a blue filter, etc., and three filters are arranged adjacent to each other as a pixel group. The color filter maintains high transmittance of a specific waveband, wherein the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves. In addition, the top of the filter is in a rounded arc shape, which is beneficial for light collection. Other microlens structures can also be used to meet the light collection requirements, and the application does not make specific limitations.

[0149] In the embodiment, the SiP cover layer 16, together with the second SiP layer 15 located directly below and the SiAs layer 14, i.e., the substrate 10, constitutes the pixel area of the back-illuminated image sensor of the application. The pixel area with different layer structures can increase the number of photo-generated carriers. In addition, the impurity level ionization energy of SiP and SiAs increases in turn, and the conductivity gradient after light excitation promotes the rapid separation and collection of photo-generated carriers in the pixel area, thereby improving the overall photoelectric conversion efficiency.

[0150] Referring to Figure 15 The application provides a back-illuminated image sensor prepared by the preparation method described in any one of the above embodiments, which comprises:

[0151] The substrate 10 comprises a plurality of first isolation structures 21 extending in the substrate 10 from the first surface of the substrate 10 towards the inside of the substrate 10 and arranged at intervals along a first direction parallel to the first surface;

[0152] The first SiP layer 13 is located on the first surface and comprises a plurality of second isolation structures 22 and first SiAs layers 14a alternately arranged along a second direction towards the substrate and penetrating the first SiP layer 13 along the first direction; the second isolation structures 22 are connected to the first isolation structures 21;

[0153] A plurality of third isolation structures 23 are arranged one-to-one with the second isolation structures 22;

[0154] A plurality of second SiAs layers 14b are alternately arranged with the second SiP layers 15 along the first direction between adjacent third isolation structures 23; a second SiP layer 15 is located directly above a first SiAs layer 14a;

[0155] A plurality of grids 50 are located directly above the third isolation structures 23;

[0156] The SiP cover layer 16 is located between adjacent grids 50.

[0157] By arranging a plurality of isolation structures in the pixel region, a photodiode array is obtained, the photogenerated carriers are prevented from penetrating between adjacent pixel regions, the probability of light diffusing to adjacent pixels is reduced, the negative effect of crosstalk on image clarity is effectively suppressed, and high-quality images are ensured.

[0158] In some embodiments, the substrate 10 comprises a P-type doped element;

[0159] The size of the first isolation structure 21 in the first direction gradually increases in the direction towards the substrate;

[0160] The size of the second isolation structure 22 in the first direction gradually decreases in the direction towards the substrate;

[0161] The size of the third isolation structure 23 in the second direction is greater than the size of the second isolation structure in the second direction.

[0162] In the above embodiments, under the premise of ensuring the isolation effect, the process difficulty of preparing a deep trench isolation structure is reduced by combining isolation structures of different depths. Meanwhile, by limiting the lateral size of the first isolation structure, the second isolation structure and the third isolation structure, the area of each pixel region is increased, and the image resolution is improved under the same chip size and pixel number.

[0163] In the above embodiments, the unexpected technical effects of the present application are:

[0164] In the process of manufacturing the first SiP layer, the second SiP layer and the SiAs layer of the stacked structure, the formation steps of the second and third isolation structures are introduced synchronously, so as to avoid the damage caused by high-energy ion implantation while realizing the compactness and efficiency of the production process.

[0165] The regularly arranged photoelectric material layers (i.e. the first SiP layer, the second SiP layer, the SiAs layer and the SiP cover layer) and the substrate form a “waterfall type” pixel region photodiode structure, which can effectively optimize the transmission process of the carriers, increase the number of photogenerated carriers, and improve the photoelectric response efficiency. The physical shielding structure (the first isolation structure, the second isolation structure and the third isolation structure) penetrating the pixel region effectively suppresses the negative effect of crosstalk on the imaging quality.

[0166] The technical features of the above embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0167] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: A substrate is provided, the substrate including a plurality of first isolation structures extending toward the substrate from a first surface of the substrate and spaced apart along a first direction parallel to the first surface; A first SiP layer is formed on the first surface, and a second isolation structure is formed through the first SiP layer along a second direction toward the substrate and connected to the first isolation structure. The second isolation structure is fabricated after the first SiP layer and is integrally formed; A first trench is formed between adjacent second isolation structures, and a SiAs material layer is formed to fill the first trench and cover the first SiP layer and the top surface of the second isolation structure. After forming a third isolation structure connected to the second isolation structure within the SiAs material layer, and a plurality of second trenches spaced apart between the third isolation structures along the first direction, a second SiP layer is formed within the second trenches; the remaining SiAs material layer is used to form a SiAs layer; wherein, when forming the second trench, the remaining SiAs material layer within the first trench is used to form a first SiAs layer, and the remaining SiAs material layer outside the second trench is used to form a second SiAs layer. A grid is formed on the top surface of the third isolation structure, and a SiP capping layer and a filter are sequentially stacked between the grids in a direction away from the substrate; SiP is used to characterize silicon materials doped with phosphorus (P); SiAs is used to characterize silicon materials doped with arsenic (As).

2. The preparation method according to claim 1, characterized in that, The formation of the second isolation structure includes: A first groove is formed that penetrates the first SiP layer along the second direction, and the first groove exposes a portion of the top surface of the first isolation structure; A first insulating material layer is grown both inside and outside the first groove; The first isolation material layer with its top surface above the first SiP layer is removed, and the remaining first isolation material layer is used to form the second isolation structure.

3. The preparation method according to claim 1, characterized in that, Forming the third isolation structure includes: A second groove is formed penetrating the SiAs material layer along the second direction, the second groove exposing at least a portion of the top surface of the second isolation structure; A second insulating material layer is formed by spin coating to at least fill the second groove; The second isolation material layer, whose top surface is higher than the SiAs material layer, is removed, and the remaining second isolation material layer is used to form the third isolation structure.

4. The preparation method according to claim 1, characterized in that, The SiAs layer includes: Multiple first SiAs layers are configured one-to-one with the multiple second SiP layers; The second SiP layer is located directly above the first SiAs layer; Multiple second SiAs layers and multiple second SiP layers are alternately distributed along the first direction between adjacent third isolation structures.

5. The preparation method according to claim 4, characterized in that, The first SiAs layer penetrates the first SiP layer along the second direction and extends into the substrate.

6. The preparation method according to any one of claims 1-5, characterized in that, The dimension of the first isolation structure gradually increases in the direction toward the substrate along the first direction; The dimensions of the second isolation structure gradually decrease along the first direction toward the substrate; The dimension of the third isolation structure along the second direction is greater than the dimension of the second isolation structure along the second direction.

7. The preparation method according to any one of claims 4-5, characterized in that, After forming the second SiP layer, the process also includes: A grid material layer is formed covering the second SiP layer, the second SiAs layer, and the top surface of the third isolation structure; A portion of the grille material layer is removed to form grilles and a third groove that are alternately arranged along the first direction; the grilles are located directly above the one-to-one third isolation structure; A SiP capping layer and a filter are sequentially formed in the third groove in a direction opposite to the substrate.

8. A back-illuminated image sensor, characterized in that, Includes a back-illuminated image sensor fabricated using the fabrication method according to any one of claims 1-7, wherein the back-illuminated image sensor comprises: A substrate, wherein the substrate includes a plurality of first isolation structures extending toward the interior of the substrate via a first surface of the substrate and spaced apart along a first direction parallel to the first surface; A first SiP layer is located on the first surface and includes a second isolation structure and a first SiAs layer that extend through the first SiP layer in a second direction toward the substrate and are alternately arranged in the first direction; the second isolation structure is connected to the first isolation structure. Multiple third isolation structures are configured one-to-one with the second isolation structure; Multiple second SiAs layers and second SiP layers are alternately arranged along the first direction between adjacent third isolation structures; a second SiP layer is located directly above a first SiAs layer. Multiple grilles are located directly above the third isolation structure; SiP capping layer is located between adjacent grids.

9. The back-illuminated image sensor according to claim 8, characterized in that, Includes at least one of the following features: The substrate contains P-type doped elements; The dimension of the first isolation structure gradually increases in the direction toward the substrate along the first direction; The dimensions of the second isolation structure gradually decrease along the first direction toward the substrate; The dimension of the third isolation structure along the second direction is greater than the dimension of the second isolation structure along the second direction.

10. An electronic device, characterized in that, include: A back-illuminated image sensor prepared by the preparation method according to any one of claims 1-7; or The back-illuminated image sensor as described in any one of claims 8 or 9.

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