Virtual machine computing resource dynamic allocation method and system based on PCIe card and storage medium

Abstract

The invention discloses a virtual machine computing resource dynamic allocation method and system based on a PCIe card and a storage medium, and belongs to the field of virtualization technology and hardware resource management.The method comprises the steps that the computing unit resource utilization rate of the PCIe card is monitored in real time through a hardware abstraction layer; dynamically generating a resource allocation scheme based on an improved auction algorithm, wherein the algorithm optimizes a resource quota through a time attenuation factor and a resource reuse penalty term; utilizing a programmable register remapping technology to distribute independent VF equipment for the virtual machine and establish a direct access channel; realizing interruption isolation between virtual functions through an interruption redirection controller; and during resource redistribution, atomic migration of a calculation task is completed by adopting a check point migration mechanism, and the atomic migration comprises context preloading and PCIe link layer retraining. According to the method, the problems of hardware resource distribution rigidness, insufficient isolation and migration service interruption in the prior art are solved, and fine-grained control and service lossless switching of the heterogeneous computing units are realized.

Description

Technical Field

[0001] The present invention relates to the fields of virtualization technology and computer hardware resource management, and specifically to a method, system, and storage medium for dynamically allocating computing resources for virtual machines based on PCIe cards. The method is particularly suitable for realizing efficient utilization and real-time adjustment of computing units of PCIe devices by virtual machines through hardware-level resource partitioning, dynamic register remapping, and interrupt isolation technologies. Background Art

[0002] In cloud computing and high-performance computing scenarios, virtual machines (VMs) are increasingly demanding dynamic allocation of hardware resources. Traditional VM resource allocation technologies primarily utilize software layers (such as hypervisors) to schedule common resources like CPUs and memory. However, for heterogeneous computing units like PCIe devices (such as GPUs, FPGAs, and AI accelerator cards), the following issues exist: 1. Rigid hardware resource allocation: Existing technologies often use static partitioning or software simulation (such as the basic SR-IOV function). These methods are unable to dynamically adjust physical resource quotas (such as memory bandwidth and DMA channels) based on VM load, resulting in low resource utilization. For example, when multiple VMs compete for GPU compute units, fixed resource allocation can lead to performance bottlenecks or idle resources.

[0003] 2. Inadequate interrupt and isolation: Traditional interrupt processing relies on virtual machine monitor (VMM) forwarding, which increases latency and makes it difficult to achieve strict isolation between virtual functions (VFs). Furthermore, the IOMMU-based address translation mechanism lacks support for fine-grained partitioning of PCIe device on-chip caches (such as L2 cache), potentially leading to security vulnerabilities or data conflicts.

[0004] 3. Business interruption during migration: Existing resource migration technologies (such as hot swapping) require pausing virtual machine tasks and reinitializing device contexts when adjusting PCIe device resources, making it difficult to ensure business continuity.

[0005] To address the above-mentioned issues, existing technologies have proposed several improvements. For example, Chinese patent CN106020933A proposes a resource scheduling method based on ultra-lightweight virtual machines. This method implements dynamic allocation and recovery of virtual machine resources through a resource prediction module and a task queuing module. Its core approach is to predict resource utilization using linear and quadratic fitting algorithms and prioritize resources according to SLA agreements. However, this method lacks hardware adaptability and only performs software-level scheduling for general resources such as CPUs and memory, without considering the resource isolation and dynamic allocation requirements of computing units in heterogeneous PCIe devices such as GPUs and FPGAs. Interrupt handling is inefficient, relying on the virtual machine monitor (VMM) to forward interrupt requests, resulting in insufficient isolation between virtual functions (VFs), making it difficult to meet the requirements of high-real-time scenarios. The migration mechanism is rigid, with resource recovery relying on static threshold judgment. The migration process requires pausing virtual machine tasks and reinitializing context, making lossless service switching impossible.

[0006] Chinese patent CN106681839 discloses a method for dynamic allocation of elastic computing. It selects overloaded physical hosts through a greedy algorithm and migrates virtual machines to low-load nodes based on a hotspot balancing formula. Its advantage is that it reduces contention for CPU and memory resources. However, it does not solve the problem of dynamic partitioning of physical resources of PCIe device computing units (such as AI accelerator cards) within a single host. It lacks hardware-level partitioning support for caches (such as L2 caches) on PCIe cards, which can easily lead to data conflicts.

[0007] Chinese patent CN114625544A discloses a memory balloon management method and device based on dynamic allocation of virtual machine business load. The method dynamically adjusts memory allocation by monitoring the virtual machine business throughput rate and uses the memory bubble mechanism to achieve resource reuse. However, the method has a narrow scope of application and only optimizes memory resources. It does not cover the dynamic allocation requirements of PCIe device computing units (such as GPU memory bandwidth and DMA channels), and cannot achieve register-level remapping and interrupt isolation of PCIe configuration space.

[0008] Therefore, there is an urgent need for a virtual machine resource allocation solution that can combine hardware-level resource partitioning, dynamic load awareness and lossless migration to improve the utilization, isolation and business continuity of heterogeneous computing resources. Summary of the Invention

[0009] In response to existing technical problems, the purpose of the present invention is to provide a method, system and storage medium for dynamic allocation of virtual machine computing resources based on PCIe cards, which realizes efficient utilization and real-time adjustment of PCIe device computing units by virtual machines through hardware-level resource partitioning, dynamic register remapping and interrupt isolation technology.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions: A method for dynamically allocating computing resources of virtual machines based on PCIe cards, comprising: Monitor resource usage of each computing unit on at least one PCIe card in real time through a hardware abstraction layer. The PCIe card is connected to a host machine through a PCIe switch. The resource usage includes computing unit temperature, cache occupancy, and video memory bandwidth. Based on a preset virtual machine resource allocation policy and monitored dynamic load data, a real-time allocation plan containing resource quotas and isolation parameters is generated. The resource allocation policy includes priority weights, physical resource segmentation granularity, and service quality levels. The real-time allocation plan is dynamically adjusted through an improved auction algorithm, which includes the introduction of a time decay factor and a resource reuse penalty term. The target PCIe card's computing unit is partitioned at the hardware level through programmable register remapping technology, an independent VF device is allocated to each virtual machine, and a direct access channel with the virtual machine's operating system is established; Dynamically adjust the BAR space mapping relationship corresponding to each virtual machine according to the real-time allocation plan, and implement interrupt isolation of virtual functions through the interrupt redirection controller; During resource reallocation, the business continuity of virtual machines is maintained through a checkpoint migration mechanism, including preloading context data in the target computing unit, using a double-buffer switching strategy to complete the atomic migration of computing tasks, and maintaining physical connection stability through PCIe link layer retraining.

[0011] Preferably, the hardware abstraction layer includes: A type adapter module for identifying the computing unit architecture type of heterogeneous PCIe devices, including GPU stream processors, FPGA logic units, and AI accelerator tensor cores; The virtualization agent module is deployed in the embedded controller of the PCIe card and is used to execute resource monitoring instructions and return extended monitoring data, wherein the extended monitoring data includes computing unit temperature and cache occupancy rate.

[0012] Preferably, the process of generating the real-time allocation plan specifically includes: Matching a preset resource template based on the virtual machine's service type, which defines the computing unit occupancy ratio, memory bandwidth threshold, and DMA channel allocation rules; When resource contention is detected, resource quotas are dynamically adjusted based on the improved auction algorithm, wherein a time decay factor is used to reduce the weight of historical resource occupancy, and a resource reuse penalty term is used to limit repeated allocation of the same physical resource.

[0013] Preferably, the hardware-level resource partitioning operation includes: Allocate an independent VF device to each virtual machine through PCIe configuration space rewriting technology; Divide the address window of the on-chip cache of the PCIe card to establish an L2 cache partition dedicated to the virtual machine.

[0014] Furthermore, the method further comprises: SR-IOV technology is used to create multiple physical function instances, and each instance is configured with an independent TC queue to isolate traffic priorities.

[0015] The present invention also provides a resource allocation system for implementing the method, comprising: The dynamic perception module is integrated into the host's PCIe root complex to collect real-time performance counter data from each VF device and analyze the TLP packet statistical traffic characteristics of the PCIe protocol layer; A policy engine module, deployed on the out-of-band management controller, includes a resource prediction model based on reinforcement learning and a dynamic priority calculator, which is used to generate weight coefficients based on virtual machine SLA agreements and historical load data; A reconfiguration execution module, including a programmable clock generator and a power management unit, for adjusting the operating frequency and supply voltage of the computing unit; The security isolation module adopts an IOMMU-based address translation protection mechanism, configures a dynamically updated access control list, and implements DMA access authentication by whitelist filtering of write operations to the PCIe configuration space.

[0016] Preferably, the dynamic perception module further includes: The temperature adaptive unit is directly connected to the thermal sensor on the PCIe card and triggers resource migration when overheating is detected.

[0017] Preferably, the safety isolation module further implements: PCIe ATS (Address Translation Services) is used to isolate the address space of virtual machines.

[0018] The present invention also provides a computer-readable storage medium storing instructions for executing the method, wherein when the instructions are executed by a processor: Implement hot-plug support for PCIe resources by modifying the device passthrough module of the virtual machine monitor, including dynamic loading and unloading of VF device drivers; The integrated resource topology discovery algorithm automatically identifies computing resource distribution by traversing the port registers of the multi-level PCIe switch architecture.

[0019] Due to the adoption of the above solution, the beneficial effects of the present invention are as follows: 1. Improved resource utilization: Through real-time monitoring of the hardware abstraction layer and an improved auction algorithm, fine-grained dynamic allocation of PCIe card computing units is achieved, increasing resource reuse by more than 30%; 2. Enhanced isolation: Hardware-level partitioning and interrupt redirection technologies reduce resource contention between virtual machines to less than 5%, ensuring the quality of service for high-priority tasks. 3. Lossless business switching: The checkpoint migration mechanism reduces business interruption time during resource reallocation to milliseconds, meeting the needs of highly sensitive scenarios such as financial transactions and real-time rendering. 4. Compatibility and scalability: Supports various heterogeneous PCIe devices such as GPUs, FPGAs, and AI accelerator cards, and can be adapted to different virtualization platforms (such as KVM and Xen). BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the overall architecture of the hardware system of the present invention. DETAILED DESCRIPTION

[0021] The technical solutions of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention. The embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0022] Example 1: Implementation of a dynamic resource allocation method based on a PCIe card This embodiment takes a method for dynamically allocating computing resources of virtual machines based on a PCIe card as an example, and describes the technical solution of the present invention in detail in combination with hardware deployment, algorithm implementation, and experimental verification.

[0023] 1. Hardware deployment and connection architecture like Figure 1 As shown, host machine 101 (configuration: Intel Xeon 8380 CPU 101a, 384GB memory 101b, Intel VT-d enabled in BIOS) is connected to Microchip Switchtec PSX PCIe switch 102 (supporting 16 downstream ports) via PCIe 4.0 root complex 101c. The following PCIe devices are connected to switch 102: GPU card 103: two NVIDIA A100 Tensor Core GPU cards (model GA100-800, PCIe 4.0 x16 interface), each with 108 streaming multiprocessors (SMs), each containing 64 CUDA cores; FPGA card 104: two Xilinx Alveo U280 FPGA cards (model XCU280-FSVC1517-2LV-c), each card including 1,228,800 programmable logic blocks (CLBs) and supporting SR-IOV technology (creating up to eight virtual functions (VFs)).

[0024] The host machine 101 runs KVM Hypervisor 109 (version 6.5) and is virtualized into four virtual machines (VM1-VM4). VM1 105 and VM2 106 are high-priority AI inference virtual machines (SLA level 5), while VM3 107 and VM4 108 are low-priority data analysis virtual machines (SLA level 3).

[0025] 2. Real-time monitoring of the hardware abstraction layer The hardware abstraction layer (HAL) is deployed in the kernel layer of the host 101, which includes the following modules: Type adaptation module: Identifies the device type (GPU / FPGA) by reading the PCIe card configuration space (offset address 0x00-0x0C) and parses device-specific registers to obtain computing unit information: For NVIDIA A100 GPU card 103, read the SM control register (address 0x1000) to obtain the number of SMs (108) and the number of CUDA cores per SM (64); For the Xilinx Alveo U280 FPGA card 104, read the CLB configuration register (address 0x2000) to obtain the total number of CLBs (1,228,800) and the number of logic cells in each CLB (4).

[0026] Virtualization agent module: DPU 103a embedded in the GPU card (Mellanox BlueField-2, model MT27800) accesses the monitoring registers (addresses 0x3000-0x3004) of the GPU card 103 through PCIe memory-mapped I / O (MMIO) and collects the following resource data every 50 ms: Stream processor temperature (register address 0x3000, range 0-100°C, threshold 85°C); L2 cache occupancy (register address 0x3001, range 0-100%, threshold 90%); Video memory bandwidth (register address 0x3002, unit: GB / s, baseline value: 550 GB / s).

[0027] At the same time, by parsing the transaction layer packets (TLPs) of the PCIe 4.0 protocol layer, the DMA channel traffic characteristics (number of requests per second and average data volume) of virtual machine VM1 105 are counted: Read the traffic monitoring register (address 0x4000) of the PCIe switch 102 to obtain the DMA request frequency (1,200 times / second) and average data size (4KB / time) of VM1 105; When the GPU temperature exceeds 80°C (close to the threshold of 85°C), resource migration to the FPGA card is triggered.

[0028] 3. Dynamic resource allocation strategy generation Match the preset resource template for the AI ​​inference virtual machine (such as VM1), as shown in Table 1: Table 1:

[0029] When the memory bandwidth utilization of VM1 105 reaches 90% (180 GB / s), the improved auction algorithm is called to dynamically adjust the memory bandwidth quota. The algorithm formula is:

[0030] in: α=0.85 (time decay factor, reducing historical occupancy weight); β=0.3 (resource reuse penalty, limiting duplicate allocation); Q(i,k−1): VM1 105’s memory bandwidth quota for the previous cycle (180 GB / s). Reuse count: The number of times the target video memory channel (channel 0) is repeatedly allocated by VM1 105 in the last 500ms (this time it is 2 times).

[0031] Calculated:

[0032] Therefore, the memory bandwidth quota of VM1 105 is adjusted to 182.4 GB / s (rounded up to 183 GB / s), and the number of multiplexing times of channel 0 is reset to 0.

[0033] 4. Hardware-level resource partitioning and isolation Using PCIe configuration space rewrite technology (offset address 0x200), virtual function VF1 110 is assigned to VM1 105, and its BAR space mapping is set to 0x10000000-0x18000000 (128MB of video memory). SR-IOV technology is used to create four physical function instances (PF0-PF3), and each PF is configured with independent traffic class (TC) queues: PF0 (high priority): TC1 queue weight 3, assigned to VM1 105; PF1 (high priority): TC1 queue weight 3, assigned to VM2 106; PF2 (low priority): TC0 queue weight 1, assigned to VM3 107; PF3 (low priority): TC0 queue weight 1, assigned to VM4 108.

[0034] The Intel VT-d controller maps the interrupt request of VF1 110 to the dedicated interrupt vector (IRQ48) of VM1 105, VF2 111 to IRQ49 of VM2 106, VF3 112 to IRQ50 of VM3 107, and VF4 113 to IRQ51 of VM4 108. At the same time, the IOMMU controller 101d sets a DMA access whitelist for each virtual machine: VM1 105: Only access to BAR space 0x10000000-0x18000000 is allowed; VM2 106: Only access to BAR space 0x20000000-0x28000000 is allowed; VM3 107 and VM4 108: mapped to 0x30000000-0x38000000 and 0x40000000-0x48000000, respectively.

[0035] 5. Checkpoint Migration and Business Continuity To migrate the computing tasks of VM1 105 from PF0 to PF1, perform the following steps: Checkpoint saving: Read the CUDA kernel registers (addresses 0x5000-0x5010) of VF1 110 and save the instruction pointer (PC=0x1000) and general registers (R0=0x1234, R1=0x5678) to the checkpoint file (storage path: / var / lib / kvm / checkpoints / vm1_001.bin).

[0036] Double buffered preloading: Primary buffer: mapped to the L2 cache partition of PF0 (address 0x8000-0xA000), storing the context of the currently running task; Backup buffer: mapped to the L2 cache partition of PF1 (address 0xB000-0xD000), preloaded with the checkpoint file content (PC=0x1000, R0=0x1234, R1=0x5678).

[0037] Atomic switch: Modify the page table entry of the host MMU and map the virtual address 0x1000 of VM1 105 to the backup buffer address 0xB000 (the original mapping is the primary buffer 0x8000). It takes 0.8ms.

[0038] Link retraining: Triggers the PCIe link layer state machine (LTSSM) to jump to the Recovery state, retrains the link rate (stabilized at 16GT / s), and verifies the bit error rate (≤ 1×10⁻¹²) to ensure data transmission reliability after migration.

[0039] 6. Experimental Verification In a test cluster consisting of two host machines (with the same configuration as above), 10 AI inference virtual machines (VM1-VM10) were deployed to compare the resource reuse rates of the solution proposed in this invention and the traditional SR-IOV static allocation solution (see Table 2): Table 2:

[0040] Experimental data show that the present invention significantly improves resource utilization and business continuity through an improved auction algorithm, hardware-level partitioning, and double-buffer switching strategy, verifying the feasibility of the technical effect.

[0041] Example 2: Resource Allocation System Deployment This embodiment uses a heterogeneous computing cluster in a cloud computing data center as a scenario to describe in detail the deployment architecture, module interaction, and key parameter configuration of the resource allocation system.

[0042] 1. System hardware architecture, hardware connection such as Figure 1 As shown: The cluster consists of two hosts (Host-01 and Host-02). Each host is configured as follows: CPU: Intel Xeon 8380 (28 cores, 56 threads, base frequency 2.3GHz, maximum turbo frequency 3.5GHz); Memory: 384GB DDR4-3200 (12 x 32GB); PCIe root complex: Intel C624 chipset, supporting PCIe 4.0 × 16 root ports; PCIe switch: Microchip Switchtec PSX 3140 (16 ports, supports PCIe 4.0×16, maximum bandwidth 256GB / s); Heterogeneous computing cards: 2 NVIDIA A100 GPU cards (GA100-800, PCIe 4.0×16, 40GB video memory); 2 Xilinx Alveo U280 FPGA cards (XCU280, PCIe 4.0×16, 32GB on-chip memory); Out-of-band management controller (BMC) 116: ASPEED AST2600, supporting IPMI 2.0 protocol.

[0043] Host 101 is connected to switch 102 via PCIe root complex 101c. Switch 102 has the following PCIe devices connected to it: GPU card 103: two NVIDIA A100 Tensor Core GPU cards (model GA100-800, PCIe 4.0 x16 interface), each with 108 streaming multiprocessors (SMs), each containing 64 CUDA cores; FPGA card 104: two Xilinx Alveo U280 FPGA cards (model XCU280-FSVC1517-2LV-c), each card including 1,228,800 programmable logic blocks (CLBs) and supporting SR-IOV technology (creating up to eight virtual functions (VFs)).

[0044] 2. Implementation of dynamic perception module The dynamic sensing module 114 is integrated into the PCIe root complex 101c of the host machine and implements real-time monitoring through the following submodules: 2.1 Performance Counter Collection Unit: By accessing the performance monitoring register (PMCR, address 0x0000_0400) of the PCIe device, the following data of the VF device is collected every 100ms: GPU card: instruction cycles (IPC), L2 cache hit rate (register address 0x0404), memory bandwidth utilization (address 0x0408); FPGA card: CLB utilization (address 0x0410), on-chip memory access latency (address 0x0414); For example, VM1's GPU IPC for VF1 is 1.2, its L2 cache hit rate is 92%, and its memory bandwidth utilization is 88% (close to the 90% threshold).

[0045] 2.2 TLP packet parsing unit: Monitor the traffic monitoring register of the PCIe switch (address 0x1C00), parse the transaction layer packet (TLP) type (such as read request, write request), source / destination address and data volume, and generate the virtual machine traffic feature table (Table 3): Table 3:

[0046] 2.3 Temperature adaptive unit: Directly connected to the GPU card's thermal sensor (model ADT7420, I2C address 0x48), it reads the temperature value (register address 0x00) every 200ms. When the GPU temperature is detected to be ≥85°C (threshold), it sends an "overheat migration" event to the policy engine module.

[0047] 3. Strategy engine module implementation The policy engine module 115 is deployed on the BMC 116 and includes the following core components: 3.1 Reinforcement Learning Prediction Model: The model input is the load data of the past 5 minutes (including the IPC, cache hit rate, temperature, and TLP frequency of the VF device) and the virtual machine SLA level (level 1-5, with level 5 being the highest); the output is the resource demand forecast value for the next 10 minutes (such as a 15% increase in GPU computing unit demand).

[0048] Model parameters: LSTM neural network with 256 hidden layer nodes and a learning rate of 0.001. Training data comes from the cluster's historical load log (2000 samples).

[0049] 3.2 Dynamic Priority Calculator: A weight coefficient is generated based on the SLA level and predicted demand (formula: weight = 0.7 × SLA level + 0.3 × predicted demand growth rate).

[0050] Example: VM1 (SLA = 5, predicted demand growth of 20%) weight = 0.7 × 5 + 0.3 × 20 = 3.5 + 6 = 9.5; VM2 (SLA = 3, predicted demand growth of 10%) weight = 0.7 × 3 + 0.3 × 10 = 2.1 + 3 = 5.1.

[0051] 4. Reconfiguration execution module implementation The reconfiguration execution module 117 is integrated into an embedded controller of a PCIe card (such as the BlueField-2 DPU of the NVIDIA A100), and includes: 4.1 Programmable Clock Generator: Adjust the compute unit frequency by writing to the clock control register (address 0x0800). For example, when VM1's GPU utilization is ≥ 85%, increase the SM frequency from 1.5 GHz to 1.8 GHz (register value adjusted from 0x100 to 0x120).

[0052] 4.2 Power Management Unit: Access the voltage regulator module (VRM) control register (address 0x0804) to dynamically adjust the supply voltage. For example, when the SM frequency increases, the voltage is adjusted from 1.0V to 1.1V (register value adjusted from 0x80 to 0x88) to ensure stability.

[0053] 5. Implementation of security isolation module The security isolation module 118 implements resource isolation through the following technologies: 5.1 IOMMU address translation protection: Configure the IOMMU page table entry (Table 3), map the guest physical address (GPA) of the virtual machine to the system physical address (SPA), and set the access permission (read / write) (Table 4): Table 4

[0054] 5.2 PCIe ATS Address Isolation: Enable the Address Translation Service (ATS) to map VM1's virtual address (VA=0x2000) to GPA=0x0000_2000, and then map it to SPA=0x1000_2000 through the IOMMU controller, ensuring that VM1 cannot access the address space of other virtual machines.

[0055] Example 3: Storage Medium Instruction Execution This embodiment is based on the QEMU-KVM virtualization platform to illustrate the specific execution process of instructions in the storage medium, focusing on the implementation details of PCIe resource hot plug support and resource topology discovery.

[0056] 1. PCIe resource hot-swap support The storage medium contains a modified QEMU-KVM device passthrough module (code path: drivers / pci / pci-stub.c), which adds a hotplug callback function vf_hotplug_cb to implement the following functions: 1.1 VF driver dynamic loading: When a VF needs to be allocated for VM1, call modprobe nvidia-vf.ko to load the VF driver, set the parameter vf_count to 4 (to create four VFs), and activate the VF device through echo 4> / sys / bus / pci / devices / 0000:01:00.0 / sriov_numvfs.

[0057] 1.2 VF driver dynamic unloading: When VM1 releases the VF, it calls rmmod nvidia-vf.ko to uninstall the driver and closes the VF device through echo 0> / sys / bus / pci / devices / 0000:01:00.0 / sriov_numvfs to release PCIe resources.

[0058] 2. Resource topology discovery algorithm The algorithm automatically identifies the distribution of computing resources by traversing the port registers of the PCIe switch (Microchip Switchtec PSX 3140, address space 0x0000_0000-0x0000_FFFF). The specific steps are as follows: 2.1 Root port enumeration: Read the port configuration register of the root complex (address 0x0000_0004) to obtain the number of root ports (two in this embodiment, at addresses 0x00 and 0x01).

[0059] 2.2 Switch cascade detection: Access the downstream device register of root port 0x00 (address 0x0000_0100), detect the MicrochipSwitchtec PSX switch (device ID 0x1100), and record its port number (16).

[0060] 2.3 Downstream device discovery: Traverse the device identification registers of switch ports 0x00-0x03 (address 0x0000_1000 + port number × 0x100): Port 0x00: device ID 0x10DE (NVIDIA), type is GPU card (model A100); Port 0x01: Device ID 0x10EE (Xilinx), type FPGA card (model U280); Ports 0x02-0x03: No device connected (status register value is 0x00).

[0061] 2.4 Topology output: Generate a resource distribution map in JSON format (example): { "root_ports": [ { "port_id": 0x00, "device_type": "switch", "vendor": "Microchip", "model": "Switchtec PSX 3140", "downstream_ports": [ { "port_id": 0x00, "device_type": "GPU", "vendor": "NVIDIA", "model": "A100"}, { "port_id": 0x01, "device_type": "FPGA", "vendor": "Xilinx", "model": "U280"} ] } ] } 3. Application of resource distribution map The scheduler (such as OpenStack Nova) allocates optimal computing resources to the newly created virtual machine (such as VM5) based on the resource distribution map: If VM5 is for AI inference tasks, select the idle VF of the GPU card (port 0x00); If VM5 is a real-time data processing task, select the idle VF of the FPGA card (port 0x01); Ensure resource allocation matches device type and load status to improve overall cluster efficiency.

Claims

1. A method for dynamically allocating computing resources of virtual machines based on PCIe cards, characterized in that: include: Monitor resource usage of each computing unit on at least one PCIe card in real time through a hardware abstraction layer. The PCIe card is connected to a host machine through a PCIe switch. The resource usage includes computing unit temperature, cache occupancy, and video memory bandwidth. Based on a preset virtual machine resource allocation policy and monitored dynamic load data, a real-time allocation plan containing resource quotas and isolation parameters is generated. The resource allocation policy includes priority weights, physical resource segmentation granularity, and service quality levels. The real-time allocation plan is dynamically adjusted through an improved auction algorithm, which includes the introduction of a time decay factor and a resource reuse penalty term. The target PCIe card's computing unit is partitioned at the hardware level through programmable register remapping technology, an independent VF device is allocated to each virtual machine, and a direct access channel with the virtual machine's operating system is established; Dynamically adjust the BAR space mapping relationship corresponding to each virtual machine according to the real-time allocation plan, and implement interrupt isolation of virtual functions through the interrupt redirection controller; During resource reallocation, the business continuity of virtual machines is maintained through a checkpoint migration mechanism, including preloading context data in the target computing unit, using a double-buffer switching strategy to complete the atomic migration of computing tasks, and maintaining physical connection stability through PCIe link layer retraining.

2. The method according to claim 1, characterized in that The hardware abstraction layer includes: A type adapter module for identifying the computing unit architecture type of heterogeneous PCIe devices, including GPU stream processors, FPGA logic units, and AI accelerator tensor cores; The virtualization agent module is deployed in the embedded controller of the PCIe card and is used to execute resource monitoring instructions and return extended monitoring data, wherein the extended monitoring data includes computing unit temperature and cache occupancy rate.

3. The method according to claim 1, characterized in that The generation process of the real-time allocation plan specifically includes: Matching a preset resource template based on the virtual machine's service type, which defines the computing unit occupancy ratio, memory bandwidth threshold, and DMA channel allocation rules; When resource contention is detected, resource quotas are dynamically adjusted based on the improved auction algorithm, wherein a time decay factor is used to reduce the weight of historical resource occupancy, and a resource reuse penalty term is used to limit repeated allocation of the same physical resource.

4. The method according to claim 1, wherein The hardware-level resource partitioning operation includes: An independent VF device is allocated to each virtual machine through PCIe configuration space rewriting technology; the address window of the on-chip cache of the PCIe card is divided to establish an L2 cache partition exclusive to the virtual machine.

5. The method according to claim 4, characterized in that Also includes: SR-IOV technology is used to create multiple physical function instances, and each instance is configured with an independent TC queue to isolate traffic priorities.

6. A resource allocation system for implementing the method according to any one of claims 1 to 5, characterized in that: include: The dynamic perception module is integrated into the host's PCIe root complex to collect real-time performance counter data from each VF device and analyze the TLP packet statistical traffic characteristics of the PCIe protocol layer; A policy engine module, deployed on the out-of-band management controller, includes a resource prediction model based on reinforcement learning and a dynamic priority calculator, which is used to generate weight coefficients based on virtual machine SLA agreements and historical load data; A reconfiguration execution module, including a programmable clock generator and a power management unit, for adjusting the operating frequency and supply voltage of the computing unit; The security isolation module adopts an IOMMU-based address translation protection mechanism, configures a dynamically updated access control list, and implements DMA access authentication by whitelist filtering of write operations to the PCIe configuration space.

7. The system according to claim 6, characterized in that The dynamic perception module also includes: The temperature adaptive unit is directly connected to the thermal sensor on the PCIe card and triggers resource migration when overheating is detected.

8. The system according to claim 6, wherein: The safety isolation module further implements: PCIe ATS (Address Translation Services) is used to isolate the address space of virtual machines.

9. A computer-readable storage medium storing instructions for executing the method according to any one of claims 1 to 5, characterized in that: When the instructions are executed by the processor: Implement hot-plug support for PCIe resources by modifying the device passthrough module of the virtual machine monitor, including dynamic loading and unloading of VF device drivers; The integrated resource topology discovery algorithm automatically identifies computing resource distribution by traversing the port registers of the multi-level PCIe switch architecture.

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