A method and system for automatic testing of mobile phone motherboard functions

Abstract

This invention discloses a method and system for automatic testing of mobile phone motherboard functions, belonging to the field of automated testing technology. The method includes: constructing a test knowledge graph based on the testing requirements of the mobile phone motherboard; loading the test knowledge graph onto the motherboard under test and generating an initial test sequence based on the dependencies in the test knowledge graph; the initial test sequence containing multiple test items to be executed; a digital shadow simulation process simulating the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items; if a hardware resource conflict is predicted during the simulation, a dynamic navigation instruction is generated; and the dynamic navigation instruction is sent to the execution layer to adjust the testing process of the motherboard under test in real time. This invention accelerates the simulation of the timing of unexecuted test items by synchronizing the physical test environment status to the simulation framework in real time through the digital shadow simulation process, and accurately detects the type and timing of future hardware resource conflicts.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology, and in particular to a method and system for automatically testing the functions of a mobile phone motherboard. Background Technology

[0002] In recent years, significant progress has been made in automated testing technology for mobile phone motherboards, particularly in the area of ​​test sequence optimization. Related technologies commonly employ knowledge graph modeling methods, analyzing circuit documentation and test specifications to extract functional test items and construct node-edge structure graphs to characterize electrical signal dependencies and hardware resource occupancy relationships. Initial test sequences are generated based on topology sorting algorithms, ensuring that the logical execution order of test items conforms to the circuit signal flow. Simultaneously, digital shadowing technology has been introduced into the test system, establishing a virtual simulation environment framework to replicate the physical hardware resource configuration and connection topology, simulating the testing process and rehearsing potential system behavior. These technologies integrate automated test equipment (ATE) and simulation mechanisms, improving the accuracy of test planning.

[0003] However, existing methods have a key flaw in the test sequence execution phase: a lack of real-time prediction and adaptive adjustment capabilities for dynamic hardware resource conflicts. After the initial sequence is generated, the test process relies on a static scheduling strategy. When multiple test items concurrently request the same non-shareable hardware resource, the system cannot predict conflicts and dynamically reschedule during execution, leading to test interruptions, resource lockouts, or timing disruptions, significantly increasing test failure rates and latency. This deficiency limits the robustness and efficiency of the test system, especially in complex motherboard testing scenarios. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a method for automatically testing the functions of a mobile phone motherboard, solving the problems of test sequence interruption and low efficiency caused by hardware resource conflicts in the automatic testing of mobile phone motherboard functions.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a method for automatically testing the functions of a mobile phone motherboard, comprising: constructing a test knowledge graph based on the test requirements of the mobile phone motherboard; loading the test knowledge graph onto the mobile phone motherboard under test, and generating an initial test sequence based on the dependencies in the test knowledge graph; the initial test sequence containing multiple test items to be executed; executing the initial test sequence on the mobile phone motherboard under test, and simultaneously initiating a digital shadow simulation process; the digital shadow simulation process simulating and simulating the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items; if a hardware resource conflict is predicted in the simulation, generating a dynamic navigation instruction; and sending the dynamic navigation instruction to the execution layer to adjust the test process of the mobile phone motherboard under test in real time.

[0008] As a preferred embodiment of the method for automatic testing of mobile phone motherboard functions according to the present invention, the testing requirements of the mobile phone motherboard refer to a set of test items for verifying various hardware functions of the mobile phone motherboard.

[0009] The specific steps for constructing the test knowledge graph are as follows.

[0010] Analyze the circuit documentation and test specifications of the mobile phone motherboard to extract functional test items;

[0011] Determine the hardware resources and electrical characteristics parameters when each functional test item is executed, and identify the dependencies between different functional test items;

[0012] The dependencies include electrical signal dependencies and hardware resource usage relationships;

[0013] Using graph modeling tools, functional test items are treated as nodes, and electrical signal dependencies and hardware resource usage relationships are treated as edges to construct a test knowledge graph.

[0014] In a preferred embodiment of the method for automatically testing the functions of a mobile phone motherboard as described in this invention, the step of generating an initial test sequence based on the dependencies in the test knowledge graph includes the following specific steps.

[0015] Read the nodes and dependencies of functional test items from the test knowledge graph;

[0016] The functional test items are sorted topologically based on the electrical signal dependencies, and the initial test sequence is output.

[0017] As a preferred embodiment of the method for automatic testing of mobile phone motherboard functions according to the present invention, the plurality of test items to be performed include power supply voltage load test, radio frequency signal transmission power test, baseband communication protocol consistency test, audio codec distortion test, and sensor accuracy calibration test.

[0018] As a preferred embodiment of the method for automatically testing the functions of a mobile phone motherboard according to the present invention, the digital shadow deduction process comprises the following specific steps.

[0019] The hardware resource configuration and connection topology of the physical test environment are replicated to establish a simulation environment framework;

[0020] In the simulation environment framework, the dependencies of the test knowledge graph are transformed into simulation logic rules, and the corresponding test stimulus generation algorithm and expected response judgment logic are injected into each functional test item node in the digital shadow inference process.

[0021] Initialize the simulation clock and state variables of the digital shadow simulation process, and establish a data synchronization channel between the digital shadow simulation process and the physical test environment.

[0022] In a preferred embodiment of the method for automatically testing the functions of a mobile phone motherboard according to the present invention, the specific steps of simulating and deducing the execution process of the initial test sequence are as follows:

[0023] The real-time execution status of functional test items in the physical test environment is obtained through the data synchronization channel;

[0024] The real-time execution state is mapped to the digital shadow simulation process to simulate the timing arrangement of unexecuted functional test items in the initial test sequence in a way that accelerates the simulation.

[0025] During the simulation process, the simulation status is analyzed to detect potential hardware resource conflicts at future points in time.

[0026] Record the types of hardware resource conflicts detected and their expected occurrence times.

[0027] As a preferred embodiment of the method for automatic testing of mobile phone motherboard functions described in this invention, the hardware resource conflict refers to an access conflict caused by multiple functional test items simultaneously requesting to use the same non-shareable physical resource.

[0028] In a preferred embodiment of the method for automatically testing the functions of a mobile phone motherboard according to the present invention, the specific process for generating dynamic navigation instructions is as follows:

[0029] Analyze the types and severity of hardware resource conflicts predicted by digital shadow simulation processes;

[0030] Based on the priority definition of functional test items in the test knowledge graph, a rescheduling strategy is formulated to generate dynamic navigation instructions that include adjustments to the execution order of functional test items and time offsets.

[0031] In a preferred embodiment of the method for automatically testing the functions of a mobile phone motherboard according to the present invention, the testing process of the mobile phone motherboard under test is adjusted in real time, and the specific process is as follows.

[0032] Analyze the execution order adjustment and time offset of functional test items contained in dynamic navigation instructions;

[0033] Pause the currently executing functional test item and save the corresponding intermediate state data; reallocate hardware resources and update the test task queue according to the dynamic navigation instructions.

[0034] The subsequent functional test items will continue to be executed according to the new functional test item execution order and time offset.

[0035] Secondly, this invention provides a system for automatically testing the functions of a mobile phone motherboard, comprising a knowledge graph construction module, a sequence generation module, a deduction execution module, a conflict prediction module, and a dynamic scheduling module. The knowledge graph construction module is used to construct a test knowledge graph based on the testing requirements of the mobile phone motherboard. The sequence generation module is used to load the test knowledge graph onto the mobile phone motherboard under test and generate an initial test sequence based on the dependencies in the test knowledge graph. The initial test sequence contains multiple test items to be executed. The deduction execution module is used to execute the initial test sequence on the mobile phone motherboard under test and simultaneously initiate a digital shadow deduction process. The digital shadow deduction process simulates the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items. The conflict prediction module is used to generate dynamic navigation instructions if hardware resource conflicts are predicted during the simulation. The dynamic scheduling module is used to send the dynamic navigation instructions to the execution layer to adjust the testing process of the mobile phone motherboard under test in real time.

[0036] The beneficial effects of this invention are as follows: By synchronizing the physical test environment status to the simulation framework in real time through the digital shadow simulation process, the timing arrangement of unexecuted test items is accelerated, and the types and occurrence times of future hardware resource conflicts are accurately detected; the digital shadow simulation process, based on the simulation logic rules of the test knowledge graph, including signal transmission rules and resource lock rules, simulates the execution process of the test sequence, identifies resource duplication conflicts or resource lock timeout conflicts, and generates detailed conflict reports; by seamlessly integrating conflict information to form dynamic navigation instructions, the order and time offset of test items can be adjusted in real time, avoiding actual conflicts and significantly improving test continuity, resource utilization efficiency, and overall test reliability. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of a method for automatically testing the functions of a mobile phone motherboard.

[0039] Figure 2 A module diagram of a system for automatically testing the functions of a mobile phone motherboard.

[0040] Figure 3 This is a flowchart of the digital shadow simulation process.

[0041] Figure 4 This is a flowchart of the dynamic navigation instruction execution process. Detailed Implementation

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0044] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0045] Reference Figures 1-4 As one embodiment of the present invention, this embodiment provides a method for automatically testing the functions of a mobile phone motherboard, including the following steps:

[0046] S1: Construct a test knowledge graph based on the testing requirements of the mobile phone motherboard; the testing requirements of the mobile phone motherboard refer to the set of test items that verify the various hardware functions of the mobile phone motherboard.

[0047] S1.1: Analyze the circuit documentation and test specifications of the mobile phone motherboard to extract functional test items.

[0048] Specifically, the circuit documentation and test specification documents are scanned line by line to identify the test items explicitly marked in the documents. Each test item represents an independent hardware function verification task; for example, power supply voltage load test, RF signal transmit power test, baseband communication protocol conformance test, audio codec distortion test, and sensor accuracy calibration test.

[0049] The process of extracting functional test items includes recording the test item names, test objectives, and test scope from the circuit documentation and test specification documents into a structured list of functional test items.

[0050] S1.2: Determine the hardware resources and electrical characteristics parameters when each functional test item is executed, and identify the dependencies between different functional test items; the dependencies include electrical signal dependencies and hardware resource occupancy relationships.

[0051] Specifically, for each functional test item in the list of functional test items, consult the circuit documentation of the mobile phone motherboard to locate the hardware resources involved in the functional test item (such as power management chip, RF transceiver, baseband processor, audio codec chip or sensor interface), and record the unique identifier of the hardware resource.

[0052] Read the electrical characteristic parameters of the functional test items from the circuit documentation; the electrical characteristic parameters include the operating voltage range, current consumption, signal frequency, and impedance matching value.

[0053] Furthermore, each pair of functional test items in the functional test item list is compared one by one to identify dependent operations; specifically, electrical signal dependencies are determined by analyzing the signal flow diagram in the circuit documentation: for example, if the output signal of one functional test item is the input signal of another functional test item, it is marked as an electrical signal dependency.

[0054] Hardware resource occupancy is determined by checking the usage status of hardware resources: for example, if multiple functional test items simultaneously request access to the same physical hardware resource (such as a shared bus or interface), it is marked as a hardware resource occupancy relationship.

[0055] Record dependencies as relation pairs. For example, functional test item A and functional test item B have an electrical signal dependency, or functional test item C and functional test item D have a hardware resource usage relationship.

[0056] S1.3: Use graph modeling tools to construct a test knowledge graph by treating functional test items as nodes and electrical signal dependencies and hardware resource usage relationships as edges.

[0057] Specifically, launch a graph modeling tool (such as Neo4j or a similar tool) and create a new graph project;

[0058] In the interface of the graph modeling tool, add a node for each functional test item in the list of functional test items; set attributes for each node, including the functional test item name, hardware resource list, and electrical characteristic parameters;

[0059] Based on the dependency list, add edges one by one in the graph modeling tool. Edges relating to electrical signals are labeled "Electrical Signal Dependency," and edges relating to hardware resource usage are labeled "Hardware Resource Usage." Each edge connects two functional test item nodes.

[0060] Execute the graph construction command in the graph modeling tool to integrate all nodes and edges into a directed graph structure, and verify the integrity and consistency of the graph: check whether all functional test item nodes have been added, whether all dependency edges are correctly connected, whether there are no isolated nodes or erroneous edges, and output the test knowledge graph data structure.

[0061] It should be noted that the test knowledge graph data structure stores functional test item nodes, dependency edges, and attributes in graph form, which are used for the generation of subsequent initial test sequences.

[0062] S2: Load the test knowledge graph for the motherboard of the mobile phone under test, and generate the initial test sequence based on the dependencies in the test knowledge graph.

[0063] S2.1: Read the nodes and dependencies of functional test items from the test knowledge graph.

[0064] Specifically, open the test knowledge graph data structure stored in the computer's memory.

[0065] The test knowledge graph data structure contains multiple functional test item nodes. Each node has attributes (including functional test item name, hardware resource list, and electrical characteristic parameters) as well as edges connecting the nodes, with each edge having attributes (including edge type and weight).

[0066] Traverse all nodes of the test knowledge graph and extract the name and attributes of each functional test item; traverse all edges of the test knowledge graph and extract the source node, target node, edge type (electrical signal dependency or hardware resource usage relationship) and weight value of each edge.

[0067] S2.2: Sort the functional test items according to the electrical signal dependencies and output the initial test sequence.

[0068] Specifically, filter out all entries with edge type "electrical signal dependency" from the dependency list;

[0069] A directed graph is constructed using the list of functional test item nodes as the vertex set and the electrical signal dependency edges as directed edges. The directed graph nodes represent all functional test items in the list of functional test item nodes, and the edges represent electrical signal dependencies. A topological sorting algorithm (using Kahn's algorithm) is applied to process the directed graph.

[0070] The specific steps for processing a directed graph are as follows: initialize a queue and calculate the in-degree of each functional test item node (the in-degree is defined as the number of electrical signal dependency edges pointing to the corresponding node).

[0071] Add all functional test item nodes with an in-degree of 0 to the queue; remove the corresponding functional test item node from the queue and add the node to the initial test sequence; update the in-degree of all neighboring nodes pointed to by electrical signal dependency edges originating from the node (decrease the in-degree value); if the in-degree of a neighboring node becomes 0, add the neighboring node to the queue until the queue is empty, and output the initial test sequence.

[0072] It should be noted that the sorting process ensures the logical correctness of the execution order of functional test items based on electrical signal dependencies, and does not involve hardware resource occupancy relationships. The initial test sequence is an ordered list of functional test items; the list of functional test items contains multiple test items to be executed, such as power supply voltage load test, RF signal transmit power test, baseband communication protocol conformance test, audio codec distortion test, and sensor accuracy calibration test.

[0073] Better yet, by using topological sorting based on electrical signal dependencies, the shortcomings of existing linear test sequences that do not match the logic of hardware signal flow are overcome, so that the execution order of functional test items accurately follows the signal transmission path of the circuit design.

[0074] S3: Execute the initial test sequence on the motherboard of the mobile phone under test, and start the digital shadow simulation process at the same time; the digital shadow simulation process simulates and simulates the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items.

[0075] S3.1: Replicate the hardware resource configuration and connection topology of the physical test environment to establish a simulation environment framework.

[0076] Specifically, open the configuration file of the physical test environment. The configuration file records the physical connection relationships and parameter configurations of all hardware resources (such as power management chip, RF transceiver and baseband processor) of the motherboard of the phone under test.

[0077] A simulation environment framework is created in computer memory by copying the hardware resource identifiers, connection interface types (such as I²C bus, SPI interface), and resource attributes (such as address range, clock frequency) from the configuration file into the simulation environment framework. Creating the simulation environment framework in computer memory involves allocating storage space for the data structure by calling standard memory allocation functions (such as malloc or new) and filling the data fields according to the hardware resource configuration and connection topology of the physical test environment.

[0078] The simulation environment framework is stored in the form of a topology graph, where nodes are hardware resources and edges represent physical connections. For example, the power management chip node is connected to the baseband processor node via a "power supply bus" edge, and the RF transceiver node is connected to the baseband processor node via an "antenna interface" edge.

[0079] S3.2: In the simulation environment framework, the dependencies of the test knowledge graph are transformed into simulation logic rules, and the corresponding test stimulus generation algorithm and expected response judgment logic are injected into each functional test item node in the digital shadow inference process.

[0080] Specifically, functional test item nodes and their dependencies are read from the test knowledge graph, and corresponding simulation logic rules are created for each functional test item node in the simulation environment framework.

[0081] The simulation logic rules include signal transmission rules and resource locking rules. Specifically: Electrical signal dependencies are converted into signal transmission rules: for example, if the output signal of functional test item A is the input of functional test item B, then the signal transmission rule is defined as "functional test item B must receive the output signal value of functional test item A before starting." Hardware resource occupancy relationships are converted into resource locking rules: for example, if functional test item C and functional test item D share the same hardware resource, then the resource locking rule is defined as "when functional test item C occupies the resource, functional test item D must wait for the resource to be released."

[0082] Furthermore, electrical characteristic parameters are associated with each functional test item node, and an excitation generation algorithm is written based on these electrical characteristic parameters.

[0083] Specifically, the electrical characteristic parameters of the hardware resources corresponding to the functional test items, as defined in the circuit document, are extracted from the test knowledge graph; these electrical characteristic parameters are bound to the attributes of the functional test item nodes to form structured data; and an excitation generation algorithm is written based on these electrical characteristic parameters.

[0084] The specific implementation of the excitation generation algorithm is as follows: For power supply test items, the excitation generation algorithm outputs increasing or decreasing voltage signals in stages according to the voltage range; for radio frequency test items, the excitation generation algorithm generates modulation signals for the corresponding frequency band according to the frequency range; for digital signal test items, the excitation generation algorithm generates standard communication frames according to the protocol specifications; for analog signal test items, the excitation generation algorithm outputs test waveforms with specific amplitudes according to impedance requirements.

[0085] It is important to note that all excitation generation algorithms must be run under the boundary conditions defined by the electrical characteristic parameters to ensure that the generated test excitations can cover both normal operating conditions and trigger extreme conditions, thereby verifying whether the hardware functions meet the design specifications.

[0086] For each functional test item node, a test standard is associated with it, and the expected response judgment logic is written. Specifically, for each functional test item node, the corresponding test standard is extracted from the test specification document, conditional judgment statements are written based on the definition value of the test standard, and the expected response judgment logic is embedded in the expected response verification process of the corresponding functional test item node in the digital shadow simulation process.

[0087] S3.3: Initialize the simulation clock and state variables of the digital shadow simulation process, and establish a data synchronization channel between the digital shadow simulation process and the physical test environment.

[0088] Set the start time of the digital shadow simulation process, and align the time step with the actual test time unit of the physical test environment; set the initial state for all hardware resources in the simulation environment framework, and set the initial state for all functional test items;

[0089] A bidirectional communication interface is created between the control software of the digital shadow simulation process and the physical test environment, and the data transmission format is defined. Specifically, a network connection is established between the computer hosting the digital shadow simulation process and the control host of the physical test environment, and bidirectional data transmission is achieved using standard network communication protocols.

[0090] Among them, the digital shadow simulation process serves as the server port for the client to actively connect to the physical test environment control software, and both parties agree to use a lightweight data exchange format to encapsulate the transmitted content.

[0091] The lightweight data exchange format consists of two parts: a message header and a message body. The message header defines the data type and timestamp of the transmitted data. The message body organizes the data according to predefined fields such as the execution status of functional test items and hardware resource usage. The communication interface implements a heartbeat mechanism to maintain connection stability and sets up a data buffer to handle instantaneous traffic fluctuations. During transmission, a verification mechanism is used to ensure data integrity. After either party sends a status update, it must wait for the receiver to return an acknowledgment signal before continuing subsequent operations. In the event of a communication failure, a reconnection mechanism is automatically triggered to restore data synchronization.

[0092] S3.4: Obtain the real-time execution status of functional test items in the physical test environment through the data synchronization channel.

[0093] Specifically, it continuously receives status update messages sent by the physical test environment through the data synchronization channel.

[0094] When the physical test environment begins executing the functional test items in the initial test sequence, the message content is parsed to extract the functional test item name, execution progress, and hardware resources used.

[0095] The parsed functional test item names, execution progress, and hardware resources used are integrated into structured data by timestamps to generate a real-time snapshot of the physical test environment.

[0096] S3.5: Map the real-time execution state to the digital shadow simulation process to simulate the timing arrangement of unexecuted functional test items in the initial test sequence in a way that accelerates the simulation.

[0097] Specifically, based on the real-time status snapshot of the physical test environment, update the status of the corresponding functional test item nodes in the digital shadow simulation process, as well as the occupancy status of hardware resources;

[0098] Based on the current simulation clock, skip the actual time consumed by the executed functional test items, and directly deduce the startup sequence of the unexecuted functional test items (such as RF signal transmit power test) according to the simulation logic rules:

[0099] It should be noted that if the RF signal transmit power test requires the output signal of the power supply voltage load test, the RF signal transmit power test will be started after the power supply voltage load test is completed.

[0100] During the simulation process, the test stimulus generation algorithm for RF signal transmit power testing (e.g., "generate 2.4GHz carrier signal") needs to be called to advance the test progress according to the simulation clock step.

[0101] S3.6: Analyze the simulation status during the simulation process, detect potential hardware resource conflicts at future time points, and record the detected hardware resource conflict types and expected occurrence times; hardware resource conflict refers to the access conflict caused by multiple functional test items simultaneously requesting to use the same non-shareable physical resource.

[0102] Specifically, check whether multiple functional test items request to occupy the same non-shareable hardware resource (such as the baseband processor) within the same time period.

[0103] It should be noted that hardware resource conflict types include resource duplication conflicts (such as two test items requesting the baseband processor at the same time) and resource lock timeout conflicts (such as a test item waiting indefinitely because the resource is occupied).

[0104] Record the names of the hardware resources involved in the conflict, the names of the conflicting functional test items, and the expected time of occurrence as a hardware resource conflict report list.

[0105] The superior method is to synchronize the physical test environment with the virtual simulation environment in real time through digital shadow simulation. By accelerating the simulation to predict the future test status, it achieves early warning and proactive avoidance of test resource conflicts compared to the post-event conflict detection method.

[0106] S4: If a hardware resource conflict is predicted during the simulation, a dynamic navigation command is generated.

[0107] S4.1: Analyze the types and severity of hardware resource conflicts predicted by the digital shadow simulation process.

[0108] Specifically, the hardware resource conflict report list is read. If multiple functional test items occupy the same hardware resource for an overlapping period of time, it is marked as "resource duplication conflict"; if a functional test item cannot start because the resource is occupied for a long time, it is marked as "resource lock timeout conflict".

[0109] The calculation calculates the percentage of overlapping time in resource duplication conflicts. The severity of resource lock timeout conflicts is directly related to the priority of functional test items. Priority definitions are stored in the functional test item node attributes of the test knowledge graph. The output is a conflict analysis table, which includes conflict type, related functional test item name, conflict severity value, and expected occurrence time.

[0110] S4.2: Based on the priority definition of functional test items in the test knowledge graph, formulate a rescheduling strategy and generate dynamic navigation instructions that include adjustments to the execution order and time offsets of functional test items.

[0111] Specifically, the priority attribute value of each functional test item node is obtained from the test knowledge graph;

[0112] Compare the priorities of conflicting functional test items in the conflict analysis table, retain the functional test items with higher priority and execute them at the original time; postpone the functional test items with lower priority by the sum of the conflict overlap time and the safety margin; based on the postponement amount, specify the start time offset value for each functional test item that needs to be postponed.

[0113] The safety margin is determined based on the minimum stable switching time of the hardware resources; the minimum stable switching time is obtained by measuring the shortest stable interval time of the target hardware resources during multiple state switching processes (such as occupation, release and reoccupation).

[0114] Example: If the baseband communication protocol conformance test (priority 2) and the sensor accuracy calibration test (priority 3) overlap by 20ms starting from T=120ms, and the safety margin is 5ms, then the sensor accuracy calibration test will be delayed until T=120ms+20ms+5ms=145ms to start.

[0115] For functional test items waiting for resources, insert an active release instruction. If a high-priority functional test item times out while occupying resources, force release the resources after the current test step is completed, and skip the blocking steps of low-priority functional test items that depend on the resources.

[0116] Skipped low-priority functional test items are moved to the end of the test sequence, and the start time is recalculated. The order of conflicting functional test items in the initial test sequence is rearranged. Example: If there is a resource conflict between the baseband communication protocol conformance test (priority 2) and the sensor accuracy calibration test (priority 3), the sensor accuracy calibration test will be adjusted to be executed after the baseband communication protocol conformance test.

[0117] The superior approach, which dynamically calculates the optimal adjustment scheme based on the priority attributes and stable resource switching time of the test knowledge graph, significantly improves hardware resource utilization compared to existing fixed priority scheduling algorithms.

[0118] S5: Sends dynamic navigation commands to the execution layer to adjust the test process of the motherboard under test in real time.

[0119] S5.1: Analyze the execution order adjustment and time offset of the functional test items contained in the dynamic navigation instructions.

[0120] Specifically, the function test item execution order adjustment instruction is read to identify the name of the function test item whose position needs to be adjusted and its new position in the initial test sequence; the time offset instruction is read to extract the name and time offset of each affected function test item.

[0121] S5.2: Pause the currently executing functional test item and save the corresponding intermediate state data, reallocate hardware resources according to the dynamic navigation instructions and update the test task queue.

[0122] Specifically, based on the name of the functional test item that needs to be adjusted immediately as indicated in the dynamic navigation command, a pause command is sent to the control interface of the physical test environment to immediately interrupt the currently executing functional test item;

[0123] Read the execution progress of the current functional test item, record the hardware resource status occupied by the functional test item, and store all incomplete operation step data and generated test results;

[0124] Release all hardware resources currently occupied by the paused functional test item, adjust the resource allocation strategy according to the dynamic navigation instructions, and specifically create a new test task queue data structure: arrange the functional test items according to the new order in the parsed instruction operation table (e.g., move the sensor accuracy calibration test to the fifth position); add a time offset to each functional test item; add the paused functional test item to the queue and mark it as "to be resumed".

[0125] S5.3: Continue executing subsequent functional test items according to the new functional test item execution order and time offset.

[0126] Specifically, the next functional test item to be executed is read from the updated test task queue;

[0127] If the functional test item is a previously paused test item (such as baseband communication protocol conformance test), reload the intermediate state data of the functional test item; reallocate hardware resources (such as re-occupying the baseband processor) and continue executing the unfinished operation steps from the saved breakpoint;

[0128] If it is a new feature test item that has not been executed before, initialize the corresponding feature test item according to the new startup time; allocate the required hardware resources, and start the test process from the beginning.

[0129] This embodiment also provides a system for automatically testing the functions of a mobile phone motherboard, including: a knowledge graph construction module, a sequence generation module, a deduction execution module, a conflict prediction module, and a dynamic scheduling module; the knowledge graph construction module is used to construct a test knowledge graph according to the test requirements of the mobile phone motherboard; the sequence generation module is used to load the test knowledge graph for the mobile phone motherboard under test and generate an initial test sequence according to the dependencies in the test knowledge graph; the initial test sequence contains multiple test items to be executed; the deduction execution module is used to execute the initial test sequence for the mobile phone motherboard under test and simultaneously start a digital shadow deduction process; the digital shadow deduction process simulates the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items; the conflict prediction module is used to generate dynamic navigation instructions if hardware resource conflicts are predicted in the simulation deduction; the dynamic scheduling module is used to send the dynamic navigation instructions to the execution layer to adjust the test process of the mobile phone motherboard under test in real time.

[0130] This embodiment also provides a computer device applicable to the method of automatically testing the functions of a mobile phone motherboard, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the method of automatically testing the functions of a mobile phone motherboard as proposed in the above embodiment.

[0131] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0132] This embodiment also provides a storage medium storing a computer program. When executed by a processor, the program implements the method for automatically testing the functions of a mobile phone motherboard as described in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0133] In summary, this invention synchronizes the physical test environment status to the simulation framework in real time through a digital shadow simulation process, accelerating the timing arrangement of unexecuted test items and accurately detecting the types and timing of future hardware resource conflicts. The digital shadow simulation process, based on simulation logic rules of a test knowledge graph, including signal transmission rules and resource lock rules, simulates the execution of test sequences, identifies resource duplication conflicts or resource lock timeout conflicts, and generates detailed conflict reports. By seamlessly integrating conflict information to form dynamic navigation instructions, it enables real-time adjustment of the test item order and time offset, avoiding actual conflicts and significantly improving test continuity, resource utilization efficiency, and overall test reliability.

[0134] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for automatically testing the functions of a mobile phone motherboard, characterized in that: include, Based on the testing requirements of mobile phone motherboards, a testing knowledge graph is constructed; Load the test knowledge graph into the motherboard of the mobile phone under test, and generate the initial test sequence based on the dependencies in the test knowledge graph; The initial test sequence contains multiple test items to be executed; The initial test sequence is executed on the motherboard of the mobile phone under test, and the digital shadow simulation process is started simultaneously. The digital shadow simulation process simulates and simulates the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items. If hardware resource conflicts are predicted during simulation, dynamic navigation instructions are generated. Dynamic navigation commands are sent to the execution layer to adjust the testing process of the motherboard of the mobile phone under test in real time.

2. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The testing requirements for the mobile phone motherboard refer to the set of test items that verify the various hardware functions of the mobile phone motherboard. The specific steps for constructing the test knowledge graph are as follows. Analyze the circuit documentation and test specifications of the mobile phone motherboard to extract functional test items; Determine the hardware resources and electrical characteristics parameters when each functional test item is executed, and identify the dependencies between different functional test items; The dependencies include electrical signal dependencies and hardware resource usage relationships; Using graph modeling tools, functional test items are treated as nodes, and electrical signal dependencies and hardware resource usage relationships are treated as edges to construct a test knowledge graph.

3. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The specific steps for generating the initial test sequence based on the dependencies in the test knowledge graph are as follows. Read the nodes and dependencies of functional test items from the test knowledge graph; The functional test items are sorted topologically based on the electrical signal dependencies, and the initial test sequence is output.

4. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The multiple tests to be performed include power supply voltage load test, radio frequency signal transmission power test, baseband communication protocol conformance test, audio codec distortion test, and sensor accuracy calibration test.

5. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The specific steps of the digital shadow simulation process are as follows: The hardware resource configuration and connection topology of the physical test environment are replicated to establish a simulation environment framework; In the simulation environment framework, the dependencies of the test knowledge graph are transformed into simulation logic rules, and the corresponding test stimulus generation algorithm and expected response judgment logic are injected into each functional test item node in the digital shadow inference process. Initialize the simulation clock and state variables of the digital shadow simulation process, and establish a data synchronization channel between the digital shadow simulation process and the physical test environment.

6. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The execution process of the simulated initial test sequence is as follows: The real-time execution status of functional test items in the physical test environment is obtained through the data synchronization channel; The real-time execution state is mapped to the digital shadow simulation process to simulate the timing arrangement of unexecuted functional test items in the initial test sequence in a way that accelerates the simulation. During the simulation process, the simulation status is analyzed to detect potential hardware resource conflicts at future points in time. Record the types of hardware resource conflicts detected and their expected occurrence times.

7. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The hardware resource conflict refers to an access conflict caused by multiple functional test items simultaneously requesting to use the same non-shareable physical resource.

8. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The specific process for generating dynamic navigation instructions is as follows. Analyze the types and severity of hardware resource conflicts predicted by digital shadow simulation processes; Based on the priority definition of functional test items in the test knowledge graph, a rescheduling strategy is formulated to generate dynamic navigation instructions that include adjustments to the execution order of functional test items and time offsets.

9. The method for automatically testing the functions of a mobile phone motherboard as described in claim 1, characterized in that: The testing process for the motherboard of the mobile phone under test is adjusted in real time, and the specific process is as follows. Analyze the execution order adjustment and time offset of functional test items contained in dynamic navigation instructions; Pause the currently executing functional test item and save the corresponding intermediate state data; reallocate hardware resources and update the test task queue according to the dynamic navigation instructions. The subsequent functional test items will continue to be executed according to the new functional test item execution order and time offset.

10. A system for automatically testing the functions of a mobile phone motherboard, based on the method for automatically testing the functions of a mobile phone motherboard according to any one of claims 1 to 9, characterized in that: It includes a graph construction module, a sequence generation module, a deduction execution module, a conflict prediction module, and a dynamic scheduling module; The graph construction module is used to construct a test knowledge graph based on the test requirements of the mobile phone motherboard. The sequence generation module is used to load a test knowledge graph onto the motherboard of the mobile phone under test, and generate an initial test sequence based on the dependencies in the test knowledge graph. The initial test sequence contains multiple test items to be executed; The simulation execution module is used to execute the initial test sequence on the motherboard of the mobile phone under test, and at the same time start the digital shadow simulation process. The digital shadow simulation process simulates and simulates the execution process of the initial test sequence based on the test knowledge graph and the real-time execution status of all current test items. The conflict prediction module is used to generate dynamic navigation instructions if a hardware resource conflict is predicted in the simulation. The dynamic scheduling module is used to send dynamic navigation instructions to the execution layer to adjust the testing process of the motherboard of the mobile phone under test in real time.

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