A slave device interrupt wake-up method and system based on SPI protocol, a chip, a computer-readable storage medium, and an electronic device.

Abstract

This invention belongs to the field of communication interface technology and discloses a slave device interrupt wake-up method and system, chip, computer-readable storage medium, and electronic device based on the SPI protocol. The method achieves active wake-up of the master device by multiplexing SPI bus signal lines: when the slave device needs to transmit data, it controls any two signal lines to be pulled low simultaneously as an interrupt signal; the master device detects this signal and initiates an interrupt arbitration process; the interrupt arbitration has two modes: in the interrupt signal mode including the CS signal line, arbitration is based on the state of each slave device's CS line, and when a slave device's CS line is high, it is determined to be the interrupt source; in the interrupt signal mode without the CS signal line, the interrupt source is determined by calculating the duty cycle. This invention eliminates the need for additional GPIO pins, solving the problem that slave devices cannot actively initiate communication in the traditional SPI protocol, reducing hardware complexity and wiring costs.

Description

Technical Field

[0001] This invention belongs to the field of communication interface technology, specifically relating to a slave device interrupt wake-up method and system, chip, computer-readable storage medium, and electronic device based on the SPI protocol. Background Technology

[0002] SPI (Serial Peripheral Interface), proposed by Motorola, is a synchronous, full-duplex, master-slave serial communication protocol widely used for data exchange between microcontrollers and peripheral devices (such as FLASH memory, sensors, ADCs, etc.). Its standard architecture includes four types of signal lines (such as...). Figure 1 As shown): SCK (Serial Clock): Clock signal generated by the master device, controlling the data transmission timing; MOSI (Master Out Slave In): Channel for the master device to send data to the slave device; MISO (Master In Slave Out): Channel for the slave device to send data to the master device; CS (Chip Select): Chip select signal controlled by the master device, enabling the target slave device.

[0003] The current SPI communication protocol is essentially a master-driven communication mode, making it impossible for slave devices to initiate transmissions spontaneously. If a slave device needs to transmit data, most current designs rely on GPIO interrupts to notify the master device. This increases the complexity of hardware design and wiring, and further exacerbates the shortage of GPIO pin resources due to their limited availability.

[0004] With the proliferation of smart devices, highly integrated SoC chips serve as the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; highly integrated SoC chips are ubiquitous. The ultimate goal is to achieve low power consumption.

[0005] These types of chips heavily rely on efficient peripheral communication mechanisms, and SPI, as a commonly used interface, directly impacts system power consumption and integration density due to its GPIO resource consumption. Therefore, achieving low power consumption necessitates optimizing the SPI communication architecture and reducing reliance on additional pins.

[0006] Therefore, in order to meet the need for active communication by the slave device, this invention proposes a slave device interrupt wake-up solution based on the SPI protocol, so as to enable the slave device to wake up the master device and notify the master device without consuming extra GPIO pins. Summary of the Invention

[0007] The purpose of this invention is to propose a slave device interrupt wake-up method and system, chip, computer-readable storage medium, and electronic device based on the SPI protocol, so as to solve the problem that the slave device cannot spontaneously perform data communication.

[0008] This invention provides a slave device interrupt wake-up method based on the SPI protocol. This method is applied to one master device and multiple slave devices. When a slave device needs to transmit data to the master device, it performs at least the following steps:

[0009] S1: The slave device sends an interrupt signal to the master device;

[0010] S2: When the aforementioned master device detects an interrupt signal, it initiates the interrupt arbitration process;

[0011] S3: Based on the above interrupt arbitration result, it is determined that the interrupt signal was issued by the above slave device, thereby enabling the slave device to autonomously transmit data to the master device;

[0012] The SPI bus includes four pins: SCK, CS, MISO, and MOSI. The interrupt signal is generated by a combination of two of these four pins. Based on whether it includes the CS pin, the interrupt signal is divided into interrupt signals with CS signal line design and interrupt signals without CS signal line design.

[0013] The interrupt signal including the CS signal line design has a signal line combination including any one of the following: SCK and CS, CS and MISO, CS and MOSI; while the interrupt signal without the CS signal line design has a signal line combination including any one of the following: SCK and MISO, SCK and MOSI, MISO and MOSI.

[0014] When the master device recognizes that both signal lines that generate the interrupt signal in the above combination are simultaneously pulled low, it determines that the master device has detected an interrupt signal and realizes the interrupt wake-up of the master device.

[0015] As described above, in the SPI protocol-based slave device interrupt wake-up method, when an interrupt signal is issued by a combination signal line including a CS signal line, the interrupt arbitration process is as follows: determine which slave device issued the interrupt signal based on the state of the CS signal line; the judgment rule is: analyze the state of the CS signal line of each slave device, and when the CS signal line of a certain slave device is in a low state, it is determined that the interrupt signal was issued by that slave device.

[0016] As described above, in the SPI protocol-based slave device interrupt wake-up method, when the interrupt signal is issued by a combination signal line other than the CS signal line, the interrupt arbitration will be performed by introducing a duty cycle to determine which slave device issued the interrupt signal.

[0017] As described above, in the SPI protocol-based slave device interrupt wake-up method, when an interrupt signal is emitted from the SCK and MISO signal lines, interrupt arbitration is performed by introducing a duty cycle to determine which slave device emitted the interrupt signal. When a slave device sends an in-band interrupt signal, the specific interrupt arbitration process is as follows:

[0018] S21: Start the timer to start counting;

[0019] S22: When MISO goes high, record time1;

[0020] S23: When SCK goes high, the timer stops counting and records the time time2;

[0021] S24: Calculate the duty cycle using time1 and time2 The calculation formula is:

[0022] ;

[0023] S25: Based on calculations Interruption arbitration is performed to determine which slave device issued the interrupt signal.

[0024] As described above, in the SPI protocol-based slave device interrupt wake-up method, in S25, based on the calculation...

[0025] Calculated To interrupt arbitration, the following steps are involved:

[0026] S251: Each slave device in the plurality of slave devices is pre-numbered, denoted as i, where, N is the total number of slave devices; then a predetermined value is set for each of the above slave devices. , ;

[0027] S252: Based on calculations , and compare it with the aforementioned preset value If a comparison is made, = Then determine the The corresponding number;

[0028] S253: Based on the numbering obtained above, the numbering of multiple slave devices is matched to determine which slave device issued the interrupt signal, thus completing the interrupt arbitration process.

[0029] As described above, the slave device interrupt wake-up method based on the SPI protocol further includes the following steps in S3: SCK is kept low throughout the entire interrupt signal generation process, while the CS signal line is pulled high at a certain moment. When SCK is pulled high, the entire interrupt signal generation ends. When the CS signal line changes from a high state to a low state, data transmission based on the SPI protocol is performed.

[0030] The present invention also provides a slave device interrupt wake-up system based on the SPI protocol. The system includes a master device and multiple slave devices, and the master device and the multiple slave devices are connected by SCK, CS, MISO and MOSI pins. When one of the multiple slave devices needs to autonomously transmit data to the master device, the above-mentioned slave device interrupt wake-up method based on the SPI protocol is executed.

[0031] The present invention also provides a chip, which includes at least one processor and a communication interface.

[0032] The communication interface is coupled to the at least one processor, which is used to run computer programs or instructions to implement the above-described slave device interrupt wake-up method based on the SPI protocol.

[0033] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by the processor of an electronic device, causes the electronic device to perform the above-described slave device interrupt wake-up method based on the SPI protocol.

[0034] The present invention also provides an electronic device, including one or more processors; a storage device for storing one or more computer programs; when the one or more computer programs are executed by the one or more processors, the electronic device implements the above-described slave device interrupt wake-up method based on the SPI protocol.

[0035] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0036] This invention provides a slave device interrupt wake-up method and system, chip, computer-readable storage medium, and electronic device based on the SPI protocol. The method achieves active wake-up of the master device by multiplexing SPI bus signal lines: when the slave device needs to transmit data, it controls any two signal lines to be pulled low simultaneously as an interrupt signal; the master device detects this signal and initiates an interrupt arbitration process; interrupt arbitration has two modes: in the interrupt signal mode including the CS signal line, arbitration is based on the CS line status of each slave device, and when a slave device's CS line is low, it is determined to be the interrupt source; in the interrupt signal mode without the CS signal line, taking SCK and MISO as examples, the interrupt source is determined by calculating the duty cycle of the time difference between MISO pulling high and SCK pulling high and the total duration. This invention eliminates the need for additional GPIO pins, solving the problem that slave devices cannot actively initiate communication in the traditional SPI protocol, reducing hardware complexity and wiring costs. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the SPI bus hardware framework according to an embodiment of this application;

[0038] Figure 2 This is a schematic diagram illustrating interrupt wake-up using SCK and CS according to an embodiment of this application;

[0039] Figure 3 This is a schematic diagram illustrating interrupt wake-up using SCK and MISO according to an embodiment of this application;

[0040] Figure 4 This is a flowchart illustrating the interruption of arbitration using duty cycle according to an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure of a chip according to an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the structure of a computer-readable storage medium according to an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0044] The present invention will be described in detail below through embodiments.

[0045] The following description, in conjunction with the accompanying drawings, details the specific solutions provided by the present invention for the SPI protocol-based slave device interrupt wake-up method and system, chip, computer-readable storage medium, and electronic device.

[0046] Example 1:

[0047] Please see Figure 1 This is a bus hardware framework diagram of the SPI provided in the embodiments of this application. Figure 1 The diagram illustrates the data communication process based on SPI.

[0048] SPI (Serial Peripheral Interface) is a synchronous serial interface technology proposed by Motorola. This bus system enables serial communication and data exchange between microcontroller units (MCUs) and various peripheral devices (such as FLASH RAM, A / D converters, network controllers, and other MCUs). SPI features high speed, full-duplex operation, and synchronous transmission.

[0049] As attached Figure 1 As shown, the SPI bus uses a ring topology, and its timing logic is relatively simple. Its core lies in the bidirectional shift register between the master and slave devices, controlled by the clock signal (SCK), to complete data exchange. The basic principle of SPI data transmission requires at least four signal lines (which can be reduced to three lines in unidirectional transmission mode). All devices based on the SPI protocol include the following standard signal lines:

[0050] SDI (Serial Data Input): Data input line

[0051] SDO (Serial Data Output): Data output line

[0052] SCK (Serial Clock): Clock signal line

[0053] CS (Chip Select): Chip select signal line

[0054] The chip select signal (CS) is used to control the enable state of the target device. Operation on the device is only valid when the CS signal reaches a preset enable level (high or low). This mechanism allows multiple SPI devices to be connected to the same bus.

[0055] SPI employs a bit-by-bit serial data transmission method, with the clock signal (SCK) providing a synchronization timing reference. Both the data output (SDO) and input (SDI) operate under the drive of the clock pulse: the output data level switches on the rising or falling edge of the clock and is sampled and read by the receiver on the immediately following falling or rising edge; the input data sampling follows the same principle. Therefore, an 8-bit data unit can be transmitted in at least 8 complete clock cycles (including one rising edge and one falling edge).

[0056] The timing process is illustrated using the transmission of the binary sequence 10101010 (most significant bit first) as an example. Data transmission is configured to latch the output on the rising edge of the clock and sample the input on the falling edge: At the first rising edge, the most significant bit (1) is output through the SDO line; on the subsequent falling edge, the input level on the SDI line is latched into the receive register. This process repeats cyclically. After eight complete clock cycles, the initial data in the master and slave device shift registers are swapped, marking the end of a complete SPI data transmission cycle.

[0057] To avoid increasing the complexity of hardware design and wiring, and to avoid occupying GPIO pin resources, this invention proposes a solution for SPI protocol interrupt wake-up. It only requires any two SPI signal lines, such as SCK & CS, SCK & MISO, or SCK & MOSI, to enable the slave device to wake up the master device and notify the master, without consuming additional GPIO pins. Specifically, MISO (Master In Slave Out) is simply the master-in, slave-out signal line; and MOSI (Master Out Slave In) is simply the master-out, slave-in signal line.

[0058] Example 2:

[0059] Please see Figure 2 This is a schematic diagram illustrating the use of SCK and CS to implement interrupt wake-up according to an embodiment of this application. Figure 2 As shown, interrupt arbitration is performed using SCK and CS in the SPI bus to achieve active communication from the slave device. The following diagram illustrates using SCK and CS as interrupt signals to solve the interrupt wake-up solution based on the SPI communication protocol.

[0060] The SPI protocol-based slave device interrupt wake-up method is applied to one master device and multiple slave devices. When a slave device needs to transmit data to the master device, the following steps are executed:

[0061] S1: The slave device sends an interrupt signal to the master device;

[0062] It should be noted that the SPI bus includes four pins: SCK, CS, MISO, and MOSI. The interrupt signal can be generated by any combination of two signal lines in the SPI. Depending on whether the CS signal line is used, interrupt signals can be categorized as those with and without a CS signal line. Interrupt signals with a CS signal line include combinations such as SCK&CS, CS&MISO, and CS&MOSI; interrupt signals without a CS signal line include combinations such as SCK&MISO, SCK&MOSI, and MISO&MOSI. In this embodiment, the slave device controls the levels of the SCK and CS pins, simultaneously pulling SCK and CS low as an interrupt signal, which is then sent to the master device.

[0063] S2: When the aforementioned master device detects an interrupt signal, it initiates the interrupt arbitration process;

[0064] It should be noted that: as attached Figure 2 As shown, SCK and CS are used as interrupt signals for judgment. When the master device detects that SCK and CS are both pulled low, it detects an interrupt signal and wakes up the master device from the interrupt. At this time, the master device initiates the interrupt arbitration process. The slave device corresponding to the low CS signal line becomes the interrupt source, meaning the interrupt signal is issued by that slave device to prepare for subsequent data transmission. During the entire interrupt signal generation process, SCK needs to remain low, while the CS signal line is pulled high at a certain moment. When SCK goes high, the entire interrupt signal generation process ends.

[0065] When SCK & CS are used as interrupt signals, since they include the CS signal line, the corresponding interrupt arbitration determines which slave device issued the interrupt signal based on the state of the CS signal line. The judgment rule is: analyze the state of the CS signal lines of each slave device; when the CS signal line of a certain slave device is pulled low, it is determined that the interrupt signal was issued by that slave device; combined with the appendix... Figure 2 As shown, when the CS signal line of the slave device is pulled low again, data transmission based on the SPI protocol is performed.

[0066] S3: Based on the above interrupt arbitration result, it is determined that the interrupt signal was issued by the above slave device, thereby enabling the slave device to autonomously transmit data to the master device.

[0067] It should be noted that after the interrupt arbitration is completed based on the above step S2, that is, the interrupt arbitration result is obtained, the interrupt source is determined, and thus it is determined which slave device issued the interrupt signal, thereby determining that the slave device actively wakes up the master device to realize data transmission between the two.

[0068] This embodiment provides a slave device interrupt wake-up method based on the SPI protocol. This method enables the slave device to actively wake up the master device by multiplexing SPI bus signal lines: when the slave device needs to transmit data, it controls any two signal lines to be pulled low simultaneously as an interrupt signal; the master device detects this signal and initiates an interrupt arbitration process; the interrupt arbitration mode is: in SCK-CS mode, arbitration is based on the CS line status of each slave device, and when a slave device's CS line is low, it is determined to be the interrupt source. This invention eliminates the need for additional GPIO pins, solving the problem that slave devices cannot actively initiate communication in the traditional SPI protocol, reducing hardware complexity and wiring costs.

[0069] Example 3:

[0070] Please see Figure 3-4 These are, respectively, a schematic diagram of interrupt wake-up using SCK&MISO and a flowchart of interrupt arbitration using duty cycle, provided in the embodiments of this application.

[0071] like Figure 3 As shown, the SCK & MISO signal lines in the SPI bus are used to generate an interrupt signal, and it is assumed that SCK and MISO are pulled low at the same time to interrupt the wake-up of the master device.

[0072] Because interrupt signal determination uses a non-CS signal line design, it's impossible to determine which slave device sent the interrupt signal using the CS signal line. Therefore, for interrupt signals using a non-CS signal line design, the interrupt arbitration rule is as follows: A duty cycle is pre-defined for each device. The master device detects different duty cycles to determine the corresponding slave device. In this case, interrupt arbitration is performed by introducing the duty cycle to determine which slave device sent the interrupt signal. When a slave device sends an in-band interrupt signal, the interrupt arbitration process is as follows:

[0073] S21: Start the timer to start counting;

[0074] S22: When MISO goes high, record time1;

[0075] S23: When SCK goes high, the timer stops counting and records the time time2;

[0076] S24: Calculate the duty cycle using time1 and time2 The calculation formula is:

[0077] ;

[0078] S25: Based on calculations Interruption arbitration is performed to determine which slave device issued the interrupt signal.

[0079] It should be noted that: using duty cycle to distinguish which slave device issued the interrupt signal involves the following steps:

[0080] S251: Each slave device in the plurality of slave devices is pre-numbered, denoted as i, where, N is the total number of slave devices; then a predetermined value is set for each of the above slave devices. , ;

[0081] S252: Based on calculations , and compare it with the aforementioned preset value If a comparison is made, = Then determine the The corresponding number;

[0082] S253: Based on the numbering obtained above, the numbering of multiple devices is matched to determine that the interrupt signal was issued by a slave device, thus completing the interrupt arbitration process.

[0083] Furthermore, for in-band interrupt signals, this refers to utilizing the existing communication channel itself to transmit control or management signals (such as interrupt requests) within the communication protocol and hardware design, rather than creating an additional independent channel. Its core characteristics are: 1. Multiplexing of data channels: Control signals and data share the same set of physical signal lines (such as SCK and MISO in SPI); 2. No need for additional pins: Avoiding the addition of dedicated control lines such as GPIO, saving hardware resources. (See attached...) Figure 3 The specific implementation of the "in-band interrupt" is as follows: 1. Signal line selection: The interrupt signal is transmitted using the existing SCK and MISO signal lines of the SPI protocol (instead of additional GPIO); 2. Triggering method: The slave device sends an interrupt request (i.e., "in-band interrupt signal") by simultaneously pulling SCK and MISO low; 3. Master device detection: The master device monitors the SCK & MISO levels, and if it detects that they are pulled low at the same time, it determines that it is an interrupt request and wakes up the master device.

[0084] Based on the above-described arbitration interruption process, assuming a master device and three slave devices numbered 1, 2, and 3, the three slave devices are pre-set with predetermined values ​​as follows: =0.2、 =0.4、 =0.6; if calculated according to the duty cycle formula... =0.4, then = If the interrupt signal is determined to be issued by slave device number 2, then based on the above interrupt arbitration result, it is determined that the slave device autonomously transmits data to the master device.

[0085] Furthermore, the solution for using the SCK & MOSI signal lines to implement SPI-based slave device interrupt wake-up is essentially the same as the interrupt judgment and arbitration method using the SCK & MISO signal lines in Embodiment 3 above. In this scenario, the arbitration process is consistent with the SCK & MISO mode: the slave device simultaneously pulls SCK & MOSI low to trigger an interrupt, and the master device calculates the duty cycle by detecting the time difference between MOSI going high and SCK going high, matching the pre-allocated... The value determines the interrupt source. The advantage of using SCK & MOSI as interrupt signals is that in systems where chip select signal CS resources are scarce or wiring needs to be simplified, this solution provides an alternative path. It is especially suitable for scenarios where the master device needs to connect a large number of slave devices, has strong scalability, and does not require additional signal lines.

[0086] This invention provides a slave device interrupt wake-up method based on the SPI protocol. This method enables a slave device to actively wake up a master device by reusing either the SCK&MOSI or SCK&MISO signal lines in the SPI bus: when the slave device needs to transmit data, it controls both signal lines to be pulled low simultaneously as an interrupt signal; the master device detects this signal and initiates an interrupt arbitration process; in SCK-MISO mode, the interrupt arbitration determines the interrupt source by calculating the duty cycle of the time difference between MISO high and SCK high (time2-time1) and the total duration time2. This invention eliminates the need for additional GPIO pins, solving the problem of slave devices being unable to actively initiate communication in the traditional SPI protocol, thus reducing hardware complexity and wiring costs. Furthermore, the SCK&MOSI and SCK&MISO modes share the same duty cycle calculation process and arbitration rules, eliminating the need for the master device to distinguish signal line types, reducing implementation complexity; simultaneously, different predetermined values ​​are pre-allocated... Distinguish between slave devices and support dynamically expanding the number of slave devices (only unique allocation is required). (Value), thereby avoiding the complex process of hardware modification.

[0087] Example 4:

[0088] The present invention also provides a slave device interrupt wake-up system based on the SPI protocol. The system includes a master device and multiple slave devices, and the master device and multiple slave devices are connected by SCK, CS, MISO and MOSI pins. When one of the multiple slave devices needs to autonomously transmit data to the master device, the slave device interrupt wake-up method based on the SPI protocol provided in the above embodiment is executed.

[0089] Example 5:

[0090] like Figure 5The diagram shown is a schematic representation of a chip structure provided in an embodiment of this application. The chip 5000 includes one or more processors 5100 and a communication interface 5300. The communication interface 5300 is coupled to the at least one processor 5100, which is used to run computer programs or instructions to implement the slave device interrupt wake-up method based on the SPI protocol as described in the above embodiment.

[0091] Preferably, the memory 5400 stores the following elements: executable modules or data structures, or subsets thereof, or extended sets thereof.

[0092] In this embodiment, memory 5400 may include read-only memory and random access memory, and provides instructions and data to processor 5100. A portion of memory 5400 may also include non-volatile random access memory (NVRAM).

[0093] In this embodiment, the memory 5400, the communication interface 5300, and the memory 5400 are coupled together via a bus system 5200. The bus system 5200 includes a data bus, and may also include a power bus, a control bus, and a status signal bus, etc. For ease of description, in... Figure 5 The general labeled all buses as Bus System 5200.

[0094] The methods described in the embodiments of this application can be applied to, or implemented by, the processor 5100. The processor 5100 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the hardware of the processor 5100 or by instructions in software form. The processor 5100 may be a general-purpose processor (e.g., a microprocessor or conventional processor), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates, transistor logic devices, or discrete hardware components. The processor 5100 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention.

[0095] Example 6:

[0096] See appendix Figure 6This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention, such as... Figure 6 As shown, a computer-readable storage medium 6000 stores program code 6100 for executing the method steps according to the present invention. When executed by a processor, the program code 6100 for executing the method steps according to the present invention implements the SPI protocol-based slave device interrupt wake-up method as described above. The SPI protocol-based slave device interrupt wake-up method has been described in detail above and will not be repeated here.

[0097] The methods described in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. The computer-readable medium 6000 may include computer storage media and communication media, and may also include any medium capable of transferring a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0098] As one possible design, computer-readable medium 6000 may include compact disc read-only memory (CD ROM), RAM, ROM, EEPROM, or other optical disc storage; computer-readable medium may include disk storage or other disk storage devices. Furthermore, any connecting cable may also be appropriately referred to as computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers.

[0099] Example 7:

[0100] See Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application, such as... Figure 7 As shown, the electronic device 7000 includes a memory 7100, a processor 7200, and a computer program stored in the memory 7100 and executable by the processor, wherein the processor 7200 executes... Figure 6When the program code 6100 stored in the computer-readable storage medium 6000 is executed to perform the steps of the method according to the present invention, it can realize the slave device interrupt wake-up method based on the SPI protocol. The slave device interrupt wake-up method based on the SPI protocol has been described in detail above and will not be repeated here.

[0101] The memory 7100 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory 7100 has storage space 7300 for storing program code 6100 for executing the method steps according to the invention, which is used to perform any of the method steps described above. The program code 6100 for executing the method steps according to the invention can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, CDs, memory cards, or floppy disks. Such computer program products are typically, for example... Figure 7 The computer-readable storage medium is described above. A computer device may include multiple processors, each of which may be a single-core (single CPU) processor or a multi-core (multi CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0102] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0103] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0104] The above are preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made to the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A slave device interrupt wake-up method based on the SPI protocol, applicable to one master device and multiple slave devices, wherein when a slave device needs to transmit data to the master device, at least the following steps are performed: S1: A slave device sends an interrupt signal to the master device; S2: When the master device detects an interrupt signal, it initiates an interrupt arbitration process; S3: Based on the above interrupt arbitration result, it is determined that the interrupt signal was issued by the above slave device, thereby enabling the slave device to autonomously transmit data to the master device; The SPI bus includes four pins: SCK, CS, MISO, and MOSI. The interrupt signal is generated by a combination of two of these four pins. Based on whether it includes the CS pin, the interrupt signal is divided into interrupt signals with CS signal line design and interrupt signals without CS signal line design. in, The interrupt signal including the CS signal line design has a signal line combination including any one of the following: SCK and CS, CS and MISO, CS and MOSI; while the interrupt signal not including the CS signal line design has a signal line combination including any one of the following: SCK and MISO, SCK and MOSI, MISO and MOSI. When the master device detects that both signal lines of the above-mentioned combination interrupt signal are simultaneously pulled low, it determines that the master device has detected an interrupt signal and realizes interrupt wake-up of the master device; when the interrupt signal is issued by a combination signal line including the CS signal line, the interrupt arbitration process is as follows: determine which slave device issued the interrupt signal based on the state of the CS signal line; the judgment rule is: analyze the state of the CS signal line of each slave device, and when the CS signal line of a certain slave device is pulled low, it is determined that the interrupt signal was issued by that slave device; When an interrupt signal is issued by a combination signal line that is not a CS signal line, the interrupt arbitration will be performed by introducing a duty cycle to determine which slave device issued the interrupt signal. When the interrupt signal in a non-CS signal line design is issued by SCK and MISO, the specific interrupt arbitration process after a slave device sends an in-band interrupt signal is as follows: S21: Start the timer to start counting; S22: When MISO goes high, record time1; S23: When SCK goes high, the timer stops counting and records the time time2; S24: Calculate the duty cycle using time1 and time2 The calculation formula is: ； S25: Based on calculations Interruption arbitration is performed to determine which slave device issued the interrupt signal.

2. The slave device interrupt wake-up method based on the SPI protocol according to claim 1, characterized in that, In S25 above, based on the calculated To interrupt arbitration, the following steps are involved: S251: Each slave device in the plurality of slave devices is pre-numbered, denoted as i, where, N is the total number of slave devices; then a predetermined value is set for each of the above slave devices. , ; S252: Based on calculations Compare it with the aforementioned predetermined value If a comparison is made, = Then determine the predetermined value. The corresponding number; S253: Based on the numbering obtained above, the numbering of multiple slave devices is matched to determine which slave device issued the interrupt signal, thus completing the interrupt arbitration process.

3. The slave device interrupt wake-up method based on the SPI protocol according to claim 1, characterized in that, The above-mentioned S3 also includes: SCK remains low throughout the entire interrupt signal generation process, while the CS signal line is pulled high at a certain moment. When SCK is pulled high, the entire interrupt signal generation ends; when the CS signal line changes from a high state to a low state, data transmission based on the SPI protocol is performed.

4. A slave device interrupt wake-up system based on the SPI protocol, the system comprising a master device and multiple slave devices, wherein the master device and the multiple slave devices are connected by SCK, CS, MISO, and MOSI pins; when one of the multiple slave devices needs to autonomously transmit data to the master device, the slave device interrupt wake-up method based on the SPI protocol as described in any one of claims 1-3 is executed.

5. A chip, characterized in that, The chip includes at least one processor and a communication interface, wherein the communication interface is coupled to the at least one processor, and the at least one processor is used to run computer programs or instructions to implement the slave device interrupt wake-up method based on the SPI protocol as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by the processor of the electronic device, causes the electronic device to perform the slave device interrupt wake-up method based on the SPI protocol as described in any one of claims 1-3.

7. An electronic device, characterized in that, It includes one or more processors; a storage device for storing one or more computer programs; and when the one or more computer programs are executed by the one or more processors, the electronic device implements the slave device interrupt wake-up method based on the SPI protocol as described in any one of claims 1-3.

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