Serial bus switching system, method and electronic device

Abstract

This application discloses a serial bus switching system, method, and electronic device, relating to the field of electronic technology. The serial bus switching system includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, expanders, several multiplexers, and several PCIe devices. The controller's first output is connected to the switch's input via a two-wire serial bus. The switch's output is connected to the first input of each of the multiplexers and expanders. The multiplexers' outputs are connected one-to-one to the inputs of each of the PCIe devices. The controller's second output is connected to the second input of each of the multiplexers and expanders via a three-wire serial bus. The expanders' outputs are connected to the third input of each of the multiplexers. This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a serial bus switching system, method and electronic device. Background Technology

[0002] In current technological practices, motherboards have deeply integrated I3C (Improved Inter-Integrated Circuit) into the memory temperature monitoring and fault diagnosis link, significantly improving the real-time data acquisition efficiency of high-frequency memory. At the same time, manufacturers have supported the expansion of a single host port to 16 slave devices (such as temperature sensors and voltage monitoring ICs), effectively breaking through the physical capacitance limitations of the I2C (Inter-Integrated Circuit) bus and meeting the requirements of rack-level monitoring.

[0003] The PCIe 6.0 specification is the first to require devices to support the I3C management interface, marking a new stage in technological collaboration: this technology innovatively reuses the original I2C physical pins, enabling devices that support the I3C protocol to be backward compatible with the I2C management mode, thus protecting existing hardware investments.

[0004] The new generation of motherboards natively integrates a high-speed peripheral interconnect (PCIe) device management channel for I3C, enabling fine-grained power consumption control and real-time status diagnosis of high-speed devices such as network cards, RAID cards, and graphics processing units (GPUs). The increased I3C speed also improves the information exchange efficiency between the Baseboard Management Controller (BMC) and PCIe (PCI Express) devices. In addition, the in-band interrupt and hot-join characteristics of the I3C link can significantly optimize the asynchronous event response mechanism of PCIe devices, reducing system interrupt latency by more than 30%. However, in the design of the new generation of motherboards, how to achieve compatibility with existing PCIe 5.0 adapter cards (Risers) and manage PCIe devices through the I3C link at a lower cost is a new technical challenge. Summary of the Invention

[0005] This application provides a serial bus switching system, method, and electronic device. The serial bus switching system includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, an expander, several multiplexers, and several pluggable devices. The controller's first output is connected to the switch's input via a two-wire serial bus. The switch's output is connected to the first input of several multiplexers and expanders, respectively. The outputs of the multiple multiplexers are connected one-to-one to the inputs of several pluggable devices. The controller's second output is connected to the second input of several multiplexers and expanders via a three-wire serial bus. The expander's output is connected to the third input of several multiplexers, respectively. The expander receives the presence information of the three-wire serial bus, and the multiplexers control the link signal type accessed by the controller to the pluggable devices. This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

[0006] This application provides a serial bus switching system, which includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, an expander, several multiplexers, and several pluggable devices.

[0007] The controller's first output is connected to the switch's input via a two-wire serial bus. The switch's output is connected to the first input of several multiplexers and expanders, and the multiple multiplexers' outputs are connected to the inputs of several pluggable devices one by one.

[0008] The second output of the controller is connected to the second input of several multiplexers and expanders via a three-wire serial bus, and the output of the expander is connected to the third input of several multiplexers.

[0009] The extender is used to receive the presence information of the three-wire serial bus, and the multiplexer is used to control the link signal type for the controller to access plugged-in devices.

[0010] This application also provides a serial bus switching method, applied to a controller in a serial bus switching system, the method comprising:

[0011] The controller obtains the presence information of the three-wire serial bus through the extender;

[0012] In response to the presence of three-wire serial bus information, it is determined whether each plug-in device supports the three-wire serial bus link signal; where the plug-in device is a PCIe device.

[0013] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement a serial bus switching method, the method comprising:

[0015] The controller obtains the presence information of the three-wire serial bus through the extender;

[0016] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0017] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0018] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of a serial bus switching method, the method comprising:

[0019] The controller obtains the presence information of the three-wire serial bus through the extender;

[0020] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0021] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0022] This application also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of a serial bus switching method, the method comprising:

[0023] The controller obtains the presence information of the three-wire serial bus through the extender;

[0024] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0025] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0026] This application provides a method that includes the controller acquiring the presence information of the three-wire serial bus via an extender; in response to the presence of the three-wire serial bus information, determining whether each PCIe device supports the three-wire serial bus link signal; and switching the link signal type for the controller's access to the PCIe device via a multiplexer based on the determination result. This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

[0027] This application proposes a new generation of motherboard platform and PCIe 6.0 adapter card management topology and related circuit design, realizing the management of the I3C protocol by the PCIe 6.0 adapter card and improving transmission efficiency. Compared with related technologies, it uses a low-cost multiplexer (MUX) and saves development costs compared with existing I3C hub solutions. At the same time, it can reuse PCIe 5.0 adapter cards developed for existing platforms, further saving costs and improving product continuity. Attached Figure Description

[0028] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 Circuit diagram of related technical solution 1 provided in the embodiments of this application;

[0030] Figure 2 Circuit diagram of related technical solution 2 provided in the embodiments of this application;

[0031] Figure 3 This is a first flowchart of a serial bus switching method provided in an embodiment of this application;

[0032] Figure 4 This is a second flowchart of a serial bus switching method provided in an embodiment of this application;

[0033] Figure 5 This is a structural diagram of a serial bus switching system provided in an embodiment of this application;

[0034] Figure 6 Exemplary systems provided for embodiments of this application that can be used to implement the various embodiments of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0036] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0037] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] As a revolutionary alternative to the I2C bus, the I3C bus achieves three major technological breakthroughs: a leap in speed (up to 12.5Mbps), dynamic power consumption optimization, and multi-branch topology expansion. These breakthroughs precisely meet the stringent requirements of the server industry for high-density sensor monitoring, improved energy efficiency, and system reliability. Although it still faces challenges in the short term regarding compatibility with traditional I2C devices and protocol stack adaptation, with the DDR5 memory standard fully adopting the I3C protocol as its management interface, and the gradual implementation of controller solutions from leading manufacturers, the I3C bus protocol is rapidly establishing itself as the core bus standard for next-generation server management.

[0039] Among them, the I3C bus protocol increases the speed from 1M / s of the I2C bus to 12.5M / s (this is the speed under the PCIE specification; the actual I2C bus reaches a maximum of 3.4M / s, while the I3C bus can reach 120M / s), and is backward compatible with I2C devices.

[0040] like Figure 1 As shown, related technical solution 1 is a solution and circuit design for managing a motherboard and PCIe 5.0 adapter card. The motherboard's BMC is connected to the motherboard's I2C connector via an I2C link, and connected to the adapter card's (Riser) I2C connector via a cable. An I2C switch is first connected to the adapter card (Riser). The I2C switch expands multiple I2C links to devices Slot0, Slot1, and devices such as the memory FRU and sensor on the adapter card (Riser).

[0041] However, the drawback of related technical solution 1 is that when the circuit supports PCIe 6.0, the bus connected to the PCIe device by related technical solution 1 is only the I2C bus, that is, it can only work in I2C mode, and cannot take advantage of the higher speed of the I3C bus and the efficient management advantages such as in-band interrupts.

[0042] like Figure 2As shown, related technical solution 2 is a motherboard and adapter card Riser design that supports PCIe 6.0 devices. The I3C bus used for PCIe device management is integrated into the onboard input / output connectors (MCIO) of the motherboard for high-speed connection. For example, if the motherboard has 16 connector MCIOs, the controller BMC needs to split two I3C buses to two 8-channel hubs (I3CHUB). Each hub I3C HUB expands 8 I3C buses, for a total of 16 I3C buses to each connector MCIO of the motherboard, and then connects to the adapter card Riser via cables, and finally transmits to each PCIe device slot.

[0043] Compared with related technical solution 1, the I3C management topology can remove the I2C switch and cancel the connection to the PCIe slot.

[0044] However, the disadvantages of related technical solution 2 are:

[0045] 1. The motherboard uses two 8-channel I3C hubs. Because the hubs integrate protocol conversion and level conversion functions, their cost is relatively high.

[0046] 2.16 I3C links to each connector MCIO result in high complexity of motherboard layout routing;

[0047] 3. Because the connector's MCIO pin definition includes I3C pins, it is incompatible with the previous generation PCIe 5.0 adapter card. A new PCIe 6.0 adapter card riser needs to be developed, and the PCIe 5.0 adapter card riser needs to be modified, which increases development costs.

[0048] An I3C hub is a hub or bridge device based on the I3C (Improved Inter-Integrated Circuit) bus protocol. It enables I3C bus expansion, and a common hub can expand one I3C link to four or eight links. Since the I3C link needs to be backward compatible with I2C, the hub also needs to perform protocol conversion and level conversion functions.

[0049] "MCIO15" refers to a dedicated onboard input / output connector used to connect modules such as M.2 NVMe SSDs, U.2 interface hard drives, or OCP network cards.

[0050] Embodiments of this application provide a serial bus switching method, such as... Figure 3 As shown, the method is applied to the controller in a serial bus switching system, and the method includes:

[0051] The controller obtains the presence information of the three-wire serial bus through the extender;

[0052] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0053] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0054] Understandably, this application addresses the motherboard's need to support the management of PCIe 6.0 adapter cards, is less expensive than existing solutions, and is compatible with the original PCIe 5.0 version adapter card Riser.

[0055] Embodiments of this application provide a serial bus switching method, such as... Figure 3 As shown, the method is applied to the controller in a serial bus switching system, and the method includes:

[0056] Step S01: Detect the two-wire serial bus (I2C) link channel between the controller and the switch;

[0057] The two-wire serial bus link between the controller and the switch is tested, including:

[0058] Obtain the power supply voltage of the two-wire serial bus connector and verify the range of the power supply voltage of the two-wire serial bus connector.

[0059] Power off the two-wire serial bus link and obtain the resistance of the serial data line to the power supply voltage and the resistance of the serial clock line to the power supply voltage.

[0060] Determine whether the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage are within the first threshold (1kΩ ~ 10kΩ);

[0061] If yes, the two-wire serial bus link channel signal is normal; if not, the two-wire serial bus link needs maintenance.

[0062] Obtain the total capacitance of the two-wire serial bus link channel, where the total capacitance of the two-wire serial bus link channel is the sum of the capacitance of the controller and the switch, the capacitance of several two-wire serial bus connectors, and the capacitance of the two-wire serial bus link traces.

[0063] If the total capacitance of the two-wire serial bus link channel is less than or equal to the first preset value (400pF), then the two-wire serial bus link channel signal is determined to be normal.

[0064] The parameters of the two-wire serial bus link signal waveform are verified, including the high-level voltage, rise time, and clock frequency.

[0065] Specifically, after BMC determines the I2C channel access adapter card Riser, it measures the power supply voltage of the I2C device (connector) (such as 3.3V or 5V) to ensure it is within the allowable range (±5%).

[0066] After power is off, measure the resistance of the serial data line SDA (Serial Data Line) and the serial clock line SCL (Serial Clock Line) to the power supply voltage VCC. The normal value is between 1kΩ and 10kΩ.

[0067] Calculate the total capacitance of the I2C bus (input capacitance of all devices + parasitic capacitance of traces); the I2C specification requires the total capacitance to be ≤ 400pF, otherwise the signal rise time will exceed the limit;

[0068] Finally, use an oscilloscope to observe the I2C channel signal waveform and test the key parameters.

[0069] In step S02, the controller obtains the presence information of the three-wire serial bus (I3C) through the extender.

[0070] Understandably, the I3C cable level signal information of the IO expander on the adapter card Riser is read first. The presence or absence of the I3C bus cable is then determined based on the I3C cable level signal information. For example, if the I3C cable level signal is 0, the I3C bus cable is not present; if the I3C cable level signal is 1, the I3C bus cable is present.

[0071] At the same time, the presence information of the three-wire serial bus (I3C) can also be read through the I / O pins of the motherboard controller to determine whether the I3C bus cable is in place.

[0072] Step S03: In response to the presence of three-wire serial bus information, determine whether each PCIe device supports the three-wire serial bus link signal.

[0073] Specifically, if the I3C bus information is available, the motherboard and controller BMC have the capability to support the I3C bus. It is necessary to confirm whether the PCIe devices of the adapter card support the I3C signal. The BMC first controls the IO expander to select the multiplexers MUX0 and MUX1 to the I2C path, and accesses each PCIe device through the I2C link. The PCIe 6.0 version adapter card specification is used to confirm whether the PCIe devices support the I3C link.

[0074] In step S031, in response to the absence of three-wire serial bus information, the link selection signals of several multiplexers are output as two-wire serial bus signals through the expander, and communication is carried out between all multiplexers and the corresponding PCIe devices through the two-wire serial bus.

[0075] Specifically, if the I3C cable information is not available, the PCIE device slot is managed using the I2C bus. The BMC controls the IO expander to output the channel selection signals of multiplexers MUX0 and MUX1 as I2C signals, thus connecting both multiplexers MUX0 and MUX1 to the I2C channel. At this time, the management topology and scheme are the same as the PCIE 5.0 adapter card management method.

[0076] Step S032: The link selection signals of all multiplexers are output as two-wire serial bus signals through the expander, and communication is carried out between each multiplexer and the corresponding PCIe device through the two-wire serial bus.

[0077] Test the pins or connector interface of any PCIe device to determine whether the pins of any PCIe device include serial data line and serial clock line pins;

[0078] Since the PCIe device has serial data line and serial clock line pins, the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage are determined.

[0079] Determine the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage, including:

[0080] If the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage are both within the first threshold, then the PCIe device supports a three-wire serial bus link signal.

[0081] The serial data line and serial clock line pins of any PCIe device can be tested using a logic analyzer.

[0082] Determine whether the serial data line and serial clock line pins of the PCIe device include dynamic address allocation signals, and determine whether the data format of the serial data line and serial clock line pin data line signals of the PCIe device conforms to the three-wire serial bus frame structure.

[0083] If the serial data line and serial clock line pins of a PCIe device include dynamic address allocation signals and the data format of the serial data line and serial clock line pin data line signals of the PCIe device conforms to the three-wire serial bus frame structure, then the PCIe device supports three-wire serial bus link signals.

[0084] Specifically, if an SDA / SCL pin is found in the interface of a PCIe device (especially a U.2 SSD, OCP NIC, or EDSFF), and the pull-up resistor is measured to be 1.5kΩ to 3.3kΩ, it indicates that the PCIe device supports the I3C link for high-speed management communication.

[0085] Use a logic analyzer to capture the DAA (Dynamic Address Allocation) process of a PCIe device to confirm whether it includes I3C protocol behavior.

[0086] Step S04: Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0087] Specifically, to determine if a PCIe device supports I3C mode: The host and the PCIe device initially operate in I2C mode. The host accesses the I2C address of a device and monitors whether the PCIe device responds. If it does not respond, the device only supports I2C mode, and the host maintains I2C mode accordingly. If the device responds, the host accesses the address again after a period of time. If the device does not respond, it indicates that the device supports I3C mode, and both the host and the PCIe device are configured to I3C mode. If the device still responds on the second access to the address, the PCIe device only supports I2C mode, and the host should remain in I2C mode.

[0088] Step S041: When the PCIe device supports a three-wire serial bus link signal, the link selection signal of the multiplexer corresponding to the PCIe device is output as a three-wire serial bus signal through the expander, and communication is carried out between the PCIe device and the corresponding multiplexer through the three-wire serial bus.

[0089] When a PCIe device does not support a three-wire serial bus link signal, the link selection signal of the multiplexer corresponding to the PCIe device is output as a two-wire serial bus signal through the expander, and communication between the PCIe device and the corresponding multiplexer is carried out through the two-wire serial bus.

[0090] Specifically, if a PCIe device supports I3C mode, the BMC controls the SEL signal of the corresponding multiplexer (MUX) to allow the BMC to access the PCIe device via the I3C link; if a PCIe device does not support I3C mode, the multiplexer (MUX) continues to maintain the selected channel I2C link, and the BMC uses the I2C link to manage the PCIe device.

[0091] Step S05: The serial bus switching system also includes several fans. In response to the sensor measuring the temperature of the adapter card being greater than the second preset value (70°C), the serial bus switching system is optimized.

[0092] Optimize the serial bus switching system, including:

[0093] The controller sends adjustment commands to the fan interface to increase the speed of the plurality of fans;

[0094] In response to the fan speed being greater than the second threshold, a power adjustment command is sent to the power interface to reduce the supply voltage or current.

[0095] In response to the supply voltage being less than a third threshold, the communication rates of the three-wire serial bus link and the two-wire serial bus link are optimized.

[0096] If the temperature measured by the sensor on the adapter card is greater than a third preset value, a thermal shutdown mechanism is triggered to cut off the power supply to the adapter card, wherein the third preset value is greater than the second preset value.

[0097] Specifically, one or more small fans are added near the adapter board to dissipate heat from the adapter board;

[0098] The controller can control the fan speed via the fan FAN interface. When the adapter card temperature rises, the BMC can increase the fan speed to increase airflow and thus reduce the temperature.

[0099] The controller can dynamically adjust the fan speed based on temperature sensor data to achieve more efficient heat dissipation. In response to the fan speed exceeding a second threshold (the specific value of the second threshold needs to be determined based on factors such as fan specifications, system thermal design, and expected noise levels; if the maximum fan speed is 5000 RPM, the second threshold may be set to 4000 RPM or lower), the controller can manage the power supply via the DC-CON interface. During off-peak load periods, the controller can reduce the supply voltage or current to decrease power consumption and heat generation.

[0100] In response to the supply voltage being less than a third threshold (which may be set to 3.0V if the minimum voltage for normal system operation is 3.3V), the communication rates of the three-wire serial bus link and the two-wire serial bus link are optimized: for example, by selecting an appropriate clock frequency, shortening the length of the SPI signal line, reducing signal reflection and delay, using differential pair traces or shielding layers to reduce electromagnetic interference, and in long-distance transmission or high-speed applications, adding appropriate terminating resistors at the receiving end to reduce signal reflection and improve signal quality, reduce unnecessary waiting time and delay, and improve data transmission efficiency.

[0101] If the adapter card temperature exceeds the third preset value (80°C), the controller can trigger the thermal shutdown mechanism, cutting off the power supply to the adapter card via a control signal to prevent hardware damage.

[0102] The intelligent temperature control algorithm based on sensor temperature data adjusts the fan speed according to the real-time temperature; the BMC controller enables remote temperature monitoring and management, records temperature data regularly, analyzes heat-generating components, and performs targeted optimizations.

[0103] Develop corresponding software to monitor the circuit in real time, and immediately alarm and take measures when abnormalities are detected.

[0104] Optimizing circuit design involves comprehensive consideration of multiple aspects, including power management, signal integrity, heat dissipation design, hardware selection, and software control; these measures effectively improve the performance and stability of the circuit.

[0105] Here, as Figure 4 As shown, the Riser design of this application connects the I3C and I2C links to the PCIE device via a multiplexer (MUX). The I2C link is used to perform the initial interaction with the PCIE 6.0 adapter card to confirm whether the PCIE device supports PCIE 6.0. In this application's solution, the I3C link always operates in I3C mode, without the need for downgrading through an I3C hub. A low-cost MUX solution can be used to manage the I3C link.

[0106] The motherboard adds an I3C header. The number of I3C links depends on the number of PCIe 6.0 adapter cards supported by the system. Compared to connecting each connector MCIO on the motherboard to I3C signals, it saves on expansion chip costs and motherboard routing complexity, and does not change the definition of the connector MCIO pins, so it can be compatible with the original PCIe 5.0 adapter card mode.

[0107] This application proposes a new generation of motherboard platform and PCIe 6.0 version adapter card collaborative management architecture, which realizes efficient I3C link management of PCIe 6.0 devices through circuit topology design:

[0108] Through the physical link of the motherboard's BMC → I3C connector → Riser adapter card, combined with the MUX multiplexer selection array controlled by the IO expander, the link management protocol of the PCIe device is dynamically adapted:

[0109] Intelligent dual-mode switching process initiated based on I3C cable in-situ detection;

[0110] Supports I3C / I2C management by channel switching based on PCIe device capabilities (only one I3C channel is selected for a single multiplexer MUX).

[0111] Maintain compatibility with legacy devices by keeping the I2C channel as the basic management bus;

[0112] At the same time, it achieves dual cost advantages compared to related technical solutions:

[0113] Component cost: Replacing the highly integrated I3C hub with a low-cost multiplexer MUX reduces the circuit's BOM cost.

[0114] Compatibility cost: The connector MCIO pin definitions are fully retained, enabling plug-and-play reuse of PCIe 5.0 adapter cards and avoiding platform redesign.

[0115] In addition, determining whether each PCIe device supports a three-wire serial bus link signal also includes:

[0116] The BMC boots in I2C mode and sends address 0x01 to any PCIe device; address 0x01 is a detection signal for the PCIe device's ability to support I3C.

[0117] Determine whether a PCIe device supports I3C mode based on its response.

[0118] If no PCIe device responds to address 0x01, the BMC continues to operate in I2C mode and does not enable I3C mode.

[0119] If a PCIe device responds with address 0x01, it indicates that at least one I3C-capable device exists, and the I3C bus upgrade process begins.

[0120] The BMC continues to broadcast other I2C addresses (such as 0x10, 0x20, etc.) in I2C mode.

[0121] I3C-capable devices no longer respond to other I2C addresses;

[0122] If other devices still respond to other I2C addresses, then all of them are I2C devices;

[0123] If the BMC sends address 0x01 again, the I3C device will no longer respond to the ACK and will internally switch the I / O voltage level to I3C mode.

[0124] The BMC initiates the I3C bus characteristic sequence; it sends the ENTDAA (Enter Dynamic Address Assignment) command.

[0125] When the DAA (Dynamic Address Assignment) command is initiated, the I3C device responds with its static address or pin-based ID, and the BMC assigns a unique dynamic address to the I3C device.

[0126] When an I3C device obtains a dynamic address, normal communication is possible.

[0127] Specifically, address 1 (0x01) is disabled in the I2C specification, and I2C devices will not respond to this address. This address is used to determine whether the device supports the I3C bus.

[0128] 1. The BMC broadcasts address 1 using I2C mode and voltage. If there is no response, it broadcasts other I2C addresses. If there is a response, it confirms that the PCIe card supports I2C mode.

[0129] 2. The BMC uses I2C mode and voltage broadcast address 1. If there is a response, the device will not use I2C mode to respond to the communication at that address again in this process.

[0130] The BMC continues to broadcast other I2C addresses using I2C mode and voltage. If there is no response, it determines that the device is operating in I3C mode.

[0131] BMC broadcasts address 1 again in I2C mode. The device does not respond, but after receiving this transmission, it needs to adjust the voltage of the operating mode to I3C mode.

[0132] The BMC broadcasts address 1 in I3C mode via the I3C link. The device responds, and the handshake between the two parties is successful. Then the PCIe device can work in I3C mode.

[0133] Here, by using the I2C reserved address 0x01 as a "capability detection signal", we can achieve: lossless detection of I3C bus support capabilities; smooth upgrade from I2C bus to I3C bus; and compatibility with pure I2C devices.

[0134] The serial bus switching method provided in this application embodiment can be improved and optimized in several ways without departing from the technical solution of this application, and these improvements and optimizations should also be considered within the protection scope of this application.

[0135] The beneficial effects of the technical solutions provided in this application are:

[0136] This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

[0137] This application proposes a new generation of motherboard platform and PCIe 6.0 adapter card management topology and related circuit design, realizing the management of the I3C protocol by the PCIe 6.0 adapter card and improving transmission efficiency. Compared with related technologies, it uses a low-cost multiplexer (MUX) and saves development costs compared with existing I3C hub solutions. At the same time, it can reuse PCIe 5.0 adapter cards developed for existing platforms, further saving costs and improving product continuity.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0139] Embodiments of this application also provide a serial bus switching system, such as Figure 5 As shown, the serial bus switching system includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, expanders, several multiplexers, and several PCIe devices.

[0140] The controller's first output is connected to the switch's input via a two-wire serial bus. The switch's output is connected to the first input of several multiplexers and expanders, and the multiple multiplexers' outputs are connected to the inputs of several PCIe devices one by one.

[0141] The second output of the controller is connected to the second input of several multiplexers and expanders via a three-wire serial bus, and the output of the expander is connected to the third input of several multiplexers.

[0142] The extender is used to receive the presence information of the three-wire serial bus, and the multiplexer is used to control the type of link signal that the controller uses to access PCIe devices.

[0143] The controller is used to obtain the presence information of the three-wire serial bus through the extender;

[0144] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0145] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0146] In one embodiment, the adapter card also includes a storage unit and a sensor.

[0147] The storage unit is used to store the operating information of the serial bus switching circuit;

[0148] The sensor is used to detect the temperature of the adapter card.

[0149] In one embodiment, the serial bus switching system further includes several two-wire serial bus connectors and several three-wire serial bus connectors.

[0150] Several two-wire serial bus connectors are connected between the controller and the switch;

[0151] Several three-wire serial bus connectors are connected between the controller and the expander.

[0152] Specifically, such as Figure 5 The diagram shows the motherboard and adapter card riser design of this application, which supports PCIe 6.0 device management:

[0153] The motherboard's BMC connects to the I3C connector via an I3C link, and then connects to the PCIe 6.0 version adapter card Riser via a cable;

[0154] The Riser adapter is designed to provide a management interface for each device's slot that supports both I2C and I3C links. The slot is then selected by a multiplexer (MUX) and provided to the device.

[0155] The Riser topology of the adapter card adds an IO expander, which outputs the strobe signals of each multiplexer (MUX) and receives the presence information of the I3C cable.

[0156] The I3C connector on the adapter card Riser connects to each multiplexer MUX. The multiplexer MUX is controlled by the expander IO. The multiplexer MUX is used to control the link signal type that the controller accesses the PCIe device.

[0157] Among them, Field Replaceable Unit refers to an independent hardware module or memory that can be quickly disassembled and replaced on-site (such as at the customer site, computer room, base station, etc.) when the equipment fails, without having to return it to the factory for repair. Here, Field Replaceable Unit refers to storage unit.

[0158] PCIe SLOT (Peripheral Component Interconnect Express Slot) is a high-speed expansion slot on a computer motherboard used to install various high-performance hardware expansion cards;

[0159] An I / O expander is an electronic device or integrated circuit (IC) used to expand the number of input / output pins of a microcontroller (MCU), processor, or host chip.

[0160] A PCIE Riser (PCIE Extension Riser) is a circuit board or cable assembly used to extend or adapt PCIE slots, primarily for changing the connection method and physical location between PCIE devices (such as graphics cards, NVMe SSDs, etc.) and the motherboard.

[0161] The beneficial effects of the technical solutions provided in this application are:

[0162] This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

[0163] This application proposes a new generation of motherboard platform and PCIe 6.0 adapter card management topology and related circuit design, realizing the management of the I3C protocol by the PCIe 6.0 adapter card and improving transmission efficiency. Compared with related technologies, it uses a low-cost multiplexer (MUX) and saves development costs compared with existing I3C hub solutions. At the same time, it can reuse PCIe 5.0 adapter cards developed for existing platforms, further saving costs and improving product continuity.

[0164] For a description of the features in the embodiment corresponding to the serial bus switching circuit, please refer to the relevant description of the embodiment corresponding to the serial bus switching method, which will not be repeated here.

[0165] Embodiments of this application also provide an electronic device, which includes a serial bus switching system. The serial bus switching system includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, an expander, several multiplexers, and several PCIe devices.

[0166] The controller's first output is connected to the switch's input via a two-wire serial bus. The switch's output is connected to the first input of several multiplexers and expanders, and the multiple multiplexers' outputs are connected to the inputs of several PCIe devices one by one.

[0167] The second output of the controller is connected to the second input of several multiplexers and expanders via a three-wire serial bus, and the output of the expander is connected to the third input of several multiplexers.

[0168] The extender is used to receive the presence information of the three-wire serial bus, and the multiplexer is used to control the type of link signal the controller uses to access PCIe devices.

[0169] Embodiments of this application also provide an electronic device, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the serial bus switching method embodiments, the method including:

[0170] The controller obtains the presence information of the three-wire serial bus through the extender;

[0171] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0172] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0173] like Figure 6 As shown, embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the serial bus switching method embodiments at runtime, the method including:

[0174] The controller obtains the presence information of the three-wire serial bus through the extender;

[0175] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0176] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0177] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0178] Embodiments of this application also provide a computer program product, which includes a computer program. When executed by a processor, the computer program implements the steps in the serial bus switching method embodiment, the method including:

[0179] The controller obtains the presence information of the three-wire serial bus through the extender;

[0180] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0181] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0182] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps in the serial bus switching method embodiment, the method including:

[0183] The controller obtains the presence information of the three-wire serial bus through the extender;

[0184] In response to the presence of three-wire serial bus information, a determination is made as to whether each PCIe device supports three-wire serial bus link signals;

[0185] Based on the judgment result, the link signal type for the controller to access the PCIe device is switched using a multiplexer.

[0186] This application is compatible with existing PCIe 5.0 adapter cards, enabling controller management of I3C links at a lower cost.

[0187] This application proposes a new generation of motherboard platform and PCIe 6.0 adapter card management topology and related circuit design, realizing the management of the I3C protocol by the PCIe 6.0 adapter card and improving transmission efficiency. Compared with related technologies, it uses a low-cost multiplexer (MUX) and saves development costs compared with existing I3C hub solutions. At the same time, it can reuse PCIe 5.0 adapter cards developed for existing platforms, further saving costs and improving product continuity.

[0188] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0189] The serial bus switching system, method, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A serial bus switching system, characterized in that, The serial bus switching system includes a motherboard and an adapter card. The motherboard includes a controller, and the adapter card includes a switch, an expander, several multiplexers, and several pluggable devices. The first output terminal of the controller is connected to the input terminal of the switch via a two-wire serial bus. The output terminal of the switch is connected to the first input terminal of the plurality of multiplexers and the expander, respectively. The output terminals of the plurality of multiplexers are connected to the input terminals of the plurality of pluggable devices one by one. The second output terminal of the controller is connected to the second input terminals of the plurality of multiplexers and the expander respectively via a three-wire serial bus, and the output terminal of the expander is connected to the third input terminal of the plurality of multiplexers respectively. The extender is used to receive the presence information of the three-wire serial bus, and the multiplexer is used to control the link signal type of the controller accessing the plug-in device.

2. The serial bus switching system according to claim 1, characterized in that, The adapter card also includes a storage unit and a sensor. The storage unit is used to store log information of the serial bus switching circuit; The sensor is used to detect the temperature of the adapter card.

3. The serial bus switching system according to claim 1, characterized in that, The serial bus switching system also includes several two-wire serial bus connectors and several three-wire serial bus connectors. The plurality of two-wire serial bus connectors are connected between the controller and the switch; The plurality of three-wire serial bus connectors are connected between the controller and the extender.

4. A serial bus switching method, applied to a controller in the serial bus switching system as described in claim 1, characterized in that, The method includes: The controller obtains the presence information of the three-wire serial bus through the extender; In response to the presence of the three-wire serial bus information, a determination is made as to whether each plug-in device supports the three-wire serial bus link signal, wherein the plug-in device is a PCIe device; Based on the judgment result, the multiplexer switches the link signal type for the controller to access the PCIe device.

5. The serial bus switching method according to claim 4, characterized in that, Before obtaining the presence information of the three-wire serial bus through the extender, the process includes: The two-wire serial bus link channel between the controller and the switch is detected; The detection of the two-wire serial bus link channel between the controller and the switch includes: Obtain the power supply voltage of the two-wire serial bus connector and verify the range of the power supply voltage of the two-wire serial bus connector. Power off the two-wire serial bus link and obtain the resistance of the serial data line to the power supply voltage and the resistance of the serial clock line to the power supply voltage. Determine whether the resistance of the serial data line to the power supply voltage and the resistance of the serial clock line to the power supply voltage are within the first threshold. If yes, the two-wire serial bus link channel signal is normal; if not, the two-wire serial bus link needs maintenance. Obtain the total capacitance of the two-wire serial bus link channel, wherein the total capacitance of the two-wire serial bus link channel is the sum of the capacitance of the controller and the switch, the capacitance of several two-wire serial bus connectors, and the capacitance of the two-wire serial bus link traces; If the total capacitance of the two-wire serial bus link channel is less than or equal to a first preset value, then the two-wire serial bus link channel signal is determined to be normal. The parameters of the two-wire serial bus link signal waveform are verified, including the high-level voltage, rise time, and clock frequency.

6. The serial bus switching method according to claim 4, characterized in that, The method includes: In response to the absence of the three-wire serial bus information, the link selection signals of the multiplexers are output as two-wire serial bus signals through the expander, and communication is carried out between all multiplexers and the corresponding PCIe devices through the two-wire serial bus.

7. The serial bus switching method according to claim 4, characterized in that, Determine whether each PCIe device supports a three-wire serial bus link signal, including: The expander outputs the link selection signals of all multiplexers as two-wire serial bus signals, and communication is carried out between each multiplexer and the corresponding PCIe device through the two-wire serial bus. Test the pins or connector interface of any PCIe device to determine whether the pins of any PCIe device include serial data line and serial clock line pins; In response to the fact that the PCIe device has serial data line and serial clock line pins, the resistance of the serial data line to the power supply voltage and the resistance of the serial clock line to the power supply voltage are determined. The determination of the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage includes: If the resistance of the serial data line to the supply voltage and the resistance of the serial clock line to the supply voltage are both within a first threshold, then the PCIe device supports a three-wire serial bus link signal. Test the serial data line and serial clock line pins of any PCIe device; Determine whether the serial data line and serial clock line pins of the PCIe device include dynamic address allocation signals, and determine whether the data format of the serial data line and serial clock line pin data line signals of the PCIe device conforms to the three-wire serial bus frame structure. In response to the fact that the serial data line and serial clock line pins of the PCIe device include dynamic address allocation signals and the data format of the serial data line and serial clock line pin data line signals of the PCIe device conforms to the three-wire serial bus frame structure, then the PCIe device supports three-wire serial bus link signals.

8. The serial bus switching method according to claim 4, characterized in that, The step of switching the link signal type of the controller accessing the PCIe device through the multiplexer based on the judgment result includes: When the PCIe device supports a three-wire serial bus link signal, the link selection signal of the multiplexer corresponding to the PCIe device is output as a three-wire serial bus signal through the expander, and communication is carried out between the PCIe device and the corresponding multiplexer through the three-wire serial bus. When the PCIe device does not support a three-wire serial bus link signal, the link selection signal of the multiplexer corresponding to the PCIe device is output as a two-wire serial bus signal through the expander, and communication between the PCIe device and the corresponding multiplexer is carried out through the two-wire serial bus.

9. The serial bus switching method according to claim 4, characterized in that, The serial bus switching system also includes several fans. After switching the link signal type for the controller accessing the PCIe device via the multiplexer based on the judgment result, the system further includes: If the temperature measured by the sensor for the adapter card is greater than a second preset value, the serial bus switching system is optimized. The optimization of the serial bus switching system includes: The controller sends adjustment commands to the fan interface to increase the speed of the plurality of fans; In response to the fan speed being greater than the second threshold, a power adjustment command is sent to the power interface to reduce the supply voltage or current. In response to the supply voltage being less than a third threshold, the communication rates of the three-wire serial bus link and the two-wire serial bus link are optimized. If the temperature measured by the sensor on the adapter card is greater than a third preset value, a thermal shutdown mechanism is triggered to cut off the power supply to the adapter card, wherein the third preset value is greater than the second preset value.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the serial bus switching method as described in any one of claims 4 to 9 when executing the computer program.

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