Full-pipeline single-path delay feedback FFT (Fast Fourier Transform) hardware architecture capable of simply addressing twiddle factors

Abstract

The invention discloses a full-pipeline single-path delay feedback structure fast Fourier transform calculation unit capable of simply addressing twiddle factors, which comprises SDF modules at all levels, twiddle factor read-out modules corresponding to the SDF modules, and a three-real-number complex multiplier of a pipeline structure. According to the twiddle factor reading module provided by the invention, orderly input of twiddle factors can be realized only by using three either-or data selectors, a synchronous counter and a synchronous ROM (Read Only Memory) and depending on two control signals; although the three-real-number and complex-number multiplier of the pipeline structure sacrifices the data throughput, the power consumption is greatly reduced, and meanwhile, it is ensured that the proposed FFT calculation unit is of a full pipeline architecture, so that no interval exists between two adjacent continuous output periods.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly to a fully-pipelined single-path delayed feedback fast Fourier transform (FFT) hardware architecture capable of easily addressing twiddle factors. Background Art

[0002] The single-path delay feedback architecture is a basic implementation of the Fast Fourier Transform (FFT). It is typically used in low-power, low-resource scenarios with minimal output latency and data throughput requirements. Its characteristic is that input data passes through each processing unit in a fixed order, allowing the butterfly computing units at each level to be reused, reducing hardware resource consumption.

[0003] Existing implementations of single-path delay feedback structures rely on a single ROM and complex addressing circuitry to achieve the ordered input of twiddle factors. This typically involves counting the input data at each stage and using complex combinational logic to determine the addresses where the required twiddle factors are stored. This approach requires complex combinational logic and requires redesigning the addressing circuitry every time the number of FFT points increases, making it unsuitable for portable and configurable IP cores. Furthermore, potential race conditions in the combinational circuitry must be considered. Furthermore, the complex multiplication involved in single-path delay feedback presents challenges in ensuring that complex multiplication is implemented without disrupting the single-path data flow.

[0004] Therefore, based on the technical route of using ROM to implement the input of rotation factors, how to optimize the layout of the addressing circuit and ROM module to minimize the use of complex combinational logic circuits, avoid cumbersome timing constraints, and implement complex multiplication with low power consumption without destroying the pipeline structure of the single-path delay feedback structure has become an urgent problem that technicians in this field need to solve. Summary of the Invention

[0005] The problems to be solved by the present invention are: how to propose a rotation factor readout circuit that can realize the orderly input of the rotation factors with a simple structure while minimizing the analysis of timing issues; and how to design a complex multiplier with a pipeline structure that has low resource consumption and low power consumption.

[0006] To address the aforementioned issues, the present invention proposes a fully pipelined, single-path delayed feedback FFT hardware architecture (using an 8-point FFT calculation as an example) that allows for simple addressing of twiddle factors. The architecture comprises a first-stage single-path delayed feedback (SDF) module, a second-stage single-path delayed feedback (SDF) module, a third-stage single-path delayed feedback (SDF) module, twiddle factor readout modules corresponding to each stage, and three real-complex multipliers within each SDF module. The first-stage single-path delayed feedback module serves as the first-stage input for time-domain data, with its output serving as the input for the second stage. Similarly, the third-stage SDF module serves as the input for the second-stage output. The third-stage SDF module can assume that its twiddle factor input is always 1, eliminating the need for a complex multiplier or ROM module. Each twiddle factor readout module uses the output flag signal of the previous-stage SDF module and the select signal of the data selector within the current-stage SDF module as control signals. When both are high, the address counter within the ROM module begins to increment, achieving orderly input of twiddle factors without the need for complex combinational logic. The SDF submodules at each level use delay registers to perform delayed feedback operations to obtain the correct combination of operation data. The three real-complex multipliers adopt a pipeline structure, dividing complex multiplication into three stages to avoid complex multiplication operations destroying the pipeline structure.

[0007] Furthermore, the twiddle factor readout circuit is located next to the SDF submodule at each stage (except the last), simplifying the addressing circuit while also reducing delays caused by transmission lines. The circuit includes a counter, a two-to-one data selector, and a ROM module. The counter begins self-incrementing under the control of the previous stage output flag signal IN_VAL and the MUX selection signal SEL within the current stage SDF submodule, thereby sequentially addressing the twiddle factors stored in the ROM. The ROM module reads the twiddle factors stored at the corresponding address under the drive of the clock signal. The data selector MUX1 controls the reset terminal RST (active low) of the counter based on the MUX selection signal SEL within the SDF. MUX2 and MUX3 are nested, selecting corresponding outputs based on different control signals.

[0008] Each SDF submodule includes an adder, subtractor, and multiplier, along with a delay register bank for delay feedback. Two data selectors exchange data between ports under the control of the SEL signal. Depending on the SEL signal, the result of a subtraction operation on port A or A and C is selected and input to port B via a MUX. The data from port B is then delayed by the delay register bank and fed to port C. The data from port D is derived from the result of the addition operation on port C or A and C. The SEL signal level inversion is implemented using a counter. For the first-level SDF module of the eight-point DIF-FFT, a counter with a bit width of 3 is defined to count the input data, with the most significant bit serving as the selection signal for the data selector within the SDF module. The multiplier within the SDF module is a three-real-complex multiplier. To preserve the single-path data flow structure of the SDF architecture, the complex multiplier is pipelined using registers. This fully pipelined structure ensures that the FFT calculation unit only experiences a first output delay for continuous input.

[0009] The basic principle of the twiddle factor readout circuit is that the control signal SEL controls the reset port RST (active low) of the synchronous counter. When SEL is high, the counter increments on the rising edge of the clock without being reset. When SEL is low, the counter resets and remains at 0. MUX2 and MUX3 are nested, selecting the corresponding output based on the states of SEL and IN_VAL. When both SEL and IN_VAL are high, the ROM module's output port OUT is enabled. When only IN_VAL is high, a 1 is output. If neither of these conditions is met, a 0 is output.

[0010] The first-level SDF submodule of the 8-point FFT calculation unit of the single-path delayed feedback architecture sequentially inputs the time domain data at port A. The flip timing of SEL is shown in the figure. In the first four clock cycles, the SEL signal is low, the data of port A is transmitted to port B, and the data of port C is selected to port D. In the next four clock cycles, the SEL signal is reversed to a high level. At this time, the data of port C is the data four clock cycles ago, and the data of port D is A+C. The delay register inside the SDF module not only includes the register group required for the data delay from port B to port C, but also needs to perform a delay operation on the rotation factor. According to the timing relationship diagram, the rotation factor is input at the same time as the input data of port A, but its action time is after four clock cycles. According to the rotation factor The delay operation diagram is as follows. The delay is realized with the help of a shift register group, whose width is the data bit width and depth is the delay length.

[0011] The pipelined three-real-complex multiplier decomposes the three-real-complex multiplication operation into three stages, each implemented in three clock cycles. The first clock cycle performs the addition and subtraction of the real and imaginary parts of the input data: AB, CD, and C+D. The second clock cycle performs the multiplication operations: (AB)×D, (CD)×A, and (C+D)×B. Registers are used to delay the inputs A, B, and D in the first clock cycle so that they can participate in the multiplication operation in the second clock cycle. In the third clock cycle, the multiplier outputs are combined and added to obtain the real and imaginary parts E and F, respectively.

[0012] The present invention proposes a fully-pipelined, single-path delayed feedback FFT hardware architecture capable of simple addressing of twiddle factors. The technical effects of the architecture are as follows: a counter controlled only by the SEL and IN_VAL signals is used to generate the addressing addresses of the twiddle factors, thereby avoiding complex combinational logic and timing issues; two nested MUXs are used to select the output of a ROM module, further avoiding the need for complex addressing circuit design; and a pipelined three-real-complex multiplier is used to avoid disrupting the single-path data flow characteristic of the SDF architecture, thereby making the SDF architecture fully pipelined. In the case of continuous input in the time domain, only the first output delay occurs, and there is no gap between adjacent output cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The single-path delayed feedback FFT hardware architecture proposed by the present invention can easily address the rotation factors; Figure 2 The rotation factor readout circuit proposed in the present invention; Figure 3 The first-level SDF module timing diagram of the DIF-FFT calculation unit of the 8-point SDF architecture; Figure 4 This is the ideal theoretical timing diagram for the first-level ROM; Figure 5 This is the waveform simulation diagram of the first-level ROM; Figure 6 Schematic diagram of using shift registers to delay the rotation factors within the first-level SDF module; Figure 7 The block diagram of the pipeline structure of three real multipliers; Figure 8 Power consumption analysis of the three real multiplier complex multiplier of the proposed pipeline structure.

[0014] Figure 9 Power consumption analysis of a complex multiplier implemented directly based on complex multiplication theory Figure 10Output timing diagram of the 256-point FFT calculation unit of the proposed architecture; Figure 11 This is the power consumption analysis diagram of the 256-point FFT calculation unit of the proposed architecture at an operating frequency of 31.25MHz; DETAILED DESCRIPTION The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0015] The single-path delayed feedback FFT hardware architecture proposed in this invention can easily address the rotation factors. Taking the implementation of 8-point FFT calculation as an example, the specific circuit is as follows: Figure 1 As shown, it includes three levels of SDF sub-modules and rotation factor readout circuits corresponding to each level of SDF sub-modules, wherein each level of SDF sub-modules is only used to illustrate the working principle of each level of rotation factor readout circuit and does not involve the technical innovation of the present invention.

[0016] Since the address self-incrementing rotation factor readout circuit proposed in the present invention serves the SDF sub-modules at all levels, the basic calculation principles and characteristics of the SDF architecture are briefly described, as follows: Figure 1 The single-path delayed feedback architecture was proposed to save hardware resources. The single-path structure ensures that each level of decomposition only requires a corresponding butterfly unit. Input data passes through each level of processing unit in a fixed order, and the final output is a result. This allows the butterfly units at each level to be reused, and there is no need to consider complex timing synchronization issues. Delay registers are used to delay the input data to obtain the correct input data combination for the butterfly calculation.

[0017] like Figure 1 As shown, the rotation factor readout circuits at each level The Read Circuit is configured next to the corresponding SDF module. However, in the existing technical solution, all SDF modules read the twiddle factors from one ROM, that is, the ROM module is shared.

[0018] The structure of each level of rotation factor readout circuit is as follows Figure 2As shown, the system includes data selectors MUX1, MUX2, and MUX3, a counter, and a ROM. The selected counter is composed of a T flip-flop that is valid on the rising edge of the clock, and its reset control port RST is valid at a low level. The data selector MUX1 controls the reset operation of the counter based on the data selector valid signal SEL in the SDF module. When SEL is high, the reset operation is not performed, otherwise the counter is reset. The ROM module that stores the rotation factor uses the counting state of the counter to address the rotation factor and outputs it on the rising edge of the clock. The nested data selectors MUX2 and MUX3 select the output of the ROM. When SEL and IN_VAL (IN_VAL is the output flag signal Out_Flag of the previous SDF module) are both high, the output port OUT of the ROM is selected. When only IN_VAL is high, the output rotation factor is 1. When neither of the above two states is met, the output of the rotation factor is 0.

[0019] according to Figure 3 The timing diagram of the first-level SDF module analyzes why the above-mentioned rotation factor readout module can only rely on the two signals SEL and IN_VAL to address the rotation factor. Figure 3 As shown, when the first frame data is input, the input data valid signal IN_VAL is always high. When IN_VAL is high but the data selection signal inside the SDF module is When it is high, it can be considered that the rotation factor is always input 1; when IN_VAL and When all are high, the rotation factors begin to be input in order, and the address count shown in the previous paragraph also starts to increase to match the address of the corresponding rotation factor; when the above conditions are not met, in order to prevent the output of the circuit from being in an indeterminate state, the input rotation factor is considered to be 0.

[0020] according to Figure 3 A timing problem involved in the simulation analysis of the rotation factor readout circuit is analyzed. The valid signal of the data selector in the SDF module is realized by counting the input data. The state of SEL is the highest bit of the output state of the counter, and the counting of the input data is also driven by the rising edge of the clock, which means that at a certain moment T0, SEL flips to a high level. SEL needs to be transmitted to the rotation factor readout circuit via a transmission line as a control signal, but in the Verilog language, the delay caused by the transmission line cannot be reflected, which will cause the counter to start counting at the rising edge of the moment T0, which will eventually cause the rotation factor input to be misplaced. In order to ensure the timing of the functional simulation and the actual circuit Figure 3 The theoretical timing shown in the figure is that a buffer is introduced during the design to artificially delay the SEL signal transmitted to the ROM module. The simulation waveform after layout and routing is shown in the figure below. Figure 5 As shown, Figure 4The theoretical timing diagram shown is exactly the same.

[0021] Since the single-path delay feedback structure has strict requirements on the timing consistency of data flow, the delay operation in the SDF module is now supplemented. The delay operation diagram of the rotation factor in the first-level SDF module is as follows: Figure 6 As shown in the figure, a shift register group is defined with a width equal to the data bit width and a depth equal to the delay length. The data to be delayed is shifted forward in sequence under the drive of the clock signal. The highest bit of the shift register group is the rotation factor after the delay.

[0022] The principle and implementation of the proposed pipeline structure three real multiplier are analyzed. If the data involved in the complex multiplication operation is X 1 =X 1 _Real+X 1 _Im ( X 1 _Real, X 1 _Im Denoted as A, B respectively), = _Real+ _Im ( _Real, _Im C and D respectively), then the real part of the output Y_Real Imaginary part Y_Im They can be expressed as:

[0023]

[0024] The structural block diagram of the three real-complex multiplier is as follows Figure 7 As shown in Figure 1, based on the basic idea of ​​the pipeline structure, the above process can be decomposed into three stages, each of which is implemented by one clock cycle. The first stage performs addition and subtraction operations - 、 、 And the real / imaginary parts involved in the multiplication operation 、 、 Stored in the register, used to participate in the multiplication operation in the second clock cycle; the second stage performs the multiplication operation. When the second clock rising edge arrives, the input data stored in the register is taken out and multiplied with the addition and subtraction results of the first stage. 、 、 The third stage combines the multiplication results of the second stage to obtain the real and imaginary parts of the final output: 、 .

[0025] When the above process is implemented using the four-real number multiplication theory (i.e., the basic complex number multiplication theory), it can be expressed as follows:

[0026]

[0027] contrast Figure 8 and Figure 9 A power consumption comparison analysis of a three-real complex multiplier and a four-real complex multiplier was conducted. Because the three-real multiplier divides the complex multiplication operation into three stages, its output signal rate is significantly lower than that of the four-real multiplier, significantly reducing I / O power consumption. Clearly, the three-real multiplier is more suitable for single-path delayed feedback architectures that require lower data throughput but are characterized by resource conservation and low power consumption.

[0028] In some specific application scenarios, the number of FFT calculation points is selected as 256 points, which is composed of an 8-level cascade of SDF modules. The timing analysis and power consumption analysis of the proposed single-path delayed feedback FFT hardware architecture with simple addressable rotation factors are first performed.

[0029] Figure 10 The output timing relationship of each level of SDF module under this implementation structure is demonstrated. It can be seen that due to the use of a pipelined three-real multiplier, the FFT calculation unit is a fully pipelined structure. When multiple sets of data are continuously input, continuous output can be achieved after the initial output delay (that is, there is no gap between adjacent output cycles).

[0030] Figure 11 The power consumption analysis results of the 256-point FFT calculation unit with the features of the present invention using the power report function of Vivado are presented. The results show that at an operating frequency of 31.25 MHz, the dynamic power consumption of the calculation unit is only 0.205 W.

Claims

1. A fully pipelined, single-path delayed feedback FFT hardware architecture with simple addressing of twiddle factors, comprising basic units for single-path delayed feedback at each level, twiddle factor readout circuits at each level, and a pipelined three-real multiplier. The twiddle factor readout circuits at each level rely solely on the output flag signal of the previous-stage SDF module and the selection signal of the current-stage data selector to achieve orderly addressing and output of the twiddle factors. The pipelined three-real multiplier divides the complex multiplication operation into three stages, allowing the FFT calculation unit to maintain a fully pipelined structure while reducing dynamic power consumption at the expense of data throughput. Compared to basic complex multiplication, this implementation better matches the low power and low resource consumption characteristics of a single-path delayed feedback structure.

2. A fully pipelined single-path delayed feedback FFT hardware architecture with simple addressable twiddle factors according to claim 1, characterized in that: A rotation factor readout circuit is configured for each level of SDF module, that is, each level of SDF module does not need to share a ROM, which simplifies the design of the ROM addressing circuit, reduces the delay caused by the transmission line, and avoids the use of complex combinational logic.

3. The fully pipelined single-path delayed feedback FFT hardware architecture with simple addressable twiddle factors according to claim 1, wherein: The twiddle factor readout circuit includes data selectors MUX1, MUX2, MUX3, a counter, and a ROM. The selected counter is composed of a T flip-flop that is valid on the rising edge of the clock, and its reset control port RST is valid at a low level. Data selector MUX1 controls the counter's reset operation based on the data selector valid signal SEL in the SDF module. When SEL is high, the reset operation is not performed; otherwise, the counter is reset. The ROM module that stores the twiddle factors uses the counter's count state to address the twiddle factors and outputs them on the rising edge of the clock. The nested data selectors MUX2 and MUX3 select the ROM output. When SEL and IN_VAL (IN_VAL is the output flag signal Out_Flag of the previous SDF module) are both high, the ROM output port OUT is selected. When only IN_VAL is high, the output twiddle factor is 1. When neither of these two conditions is met, the output of the twiddle factor is 0.

4. The fully pipelined single-path delayed feedback FFT hardware architecture with simple addressable twiddle factors according to claim 1, wherein: The pipeline structure of the three-real multiplier consists of a register, an adder, and a multiplier. It divides the multiplication of two complex numbers into three stages. The first stage performs addition and subtraction operations: (AB), (CD), (C+D), and stores the real / imaginary A, B, and D involved in the second stage multiplication operation in the register for participating in the multiplication operation in the second clock cycle. The second stage performs multiplication. On the second rising clock edge, the input data stored in the register is retrieved and multiplied with the addition and subtraction results from the first stage: (AB) × D, (CD) × A, (C + D) × B. The third stage combines the multiplication results from the second extreme to produce the final output: (AB) × D + (CD) × A, and (AB) × D + (C + D) × B. The pipelined three-real multiplier reduces power consumption (dynamic power consumption of the four-real multiplier is 0.422W, while the dynamic power consumption of the three-real multiplier is only 0.127W) at the expense of a lower I / O output rate (the I / O output rate is 22.091Mtr / s at 31.25MHz, while the signal rate of the four-real multiplier output port is 63.436Mtr / s).

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