Fast Fourier transform optimal scaling vector analysis method and device

Abstract

The invention discloses a fast Fourier transform optimal scaling vector analysis method and device, relates to the field of digital signal processing, and solves the problems of low design efficiency, difficulty in global optimization and the like caused by search space index explosion, large quantization and saturation error coupling effect estimation deviation and dependence on manual parameter adjustment in the prior art. According to the technical scheme, the method comprises the steps that a joint power model of quantization errors and saturation errors is established, and overall error power is accurately calculated; the search space is compressed step by step based on a dynamic programming algorithm, only a branch with the minimum accumulative error is reserved for a path with the same zooming frequency, and the search space is reduced from an exponential level to a linear level; an optimal scaling vector and hardware parameters are automatically generated, and a traditional trial and error process is replaced; according to the method, in the FFT design, the overall error power is greatly reduced, hardware resource occupation is reduced, the parameter generation time is compressed from the hour level to the second level, and global optimal balance of precision and efficiency is achieved.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and more particularly to a fast Fourier transform optimal scaling vector analysis method and device. Background Art

[0002] The Fast Fourier Transform (FFT), a core algorithm in digital signal processing and a fast implementation of the Discrete Fourier Transform (DFT), is widely used for spectrum analysis and signal processing in fields such as radar, communications, and image processing. The classic Cooley-Tukey FFT algorithm uses a divide-and-conquer recursive approach to decompose a long-sequence DFT into a cascade of shorter DFTs, significantly reducing computational complexity and enabling efficient deployment in very large-scale integrated circuits (VLSI).

[0003] Existing technical solutions use a predefined fixed scaling factor (e.g., a fixed scaling of 1 / 2 per level) in hardware implementation to prevent signal overflow. Parameters such as quantization bit width and saturation threshold are manually adjusted through a large number of simulation experiments, and quantization error or saturation error is independently optimized. The following defects exist: 1) Search space exponential explosion: For N-point FFT (levels ), the number of scaling factor combinations is indivual( is the number of selectable scaling factors at each level), traditional exhaustive methods cannot meet the needs of large-scale FFT design; 2) Incomplete error estimation: Existing models only consider the single impact of quantization error or saturation error, ignoring the coupling effect between the two, resulting in excessive deviation in error power estimation; 3) Reliance on experience-based parameter adjustment: Automated parameter generation methods lack theoretical guidance, resulting in long design cycles (for example, a 2048-point FFT requires hundreds of simulation iterations), and it is difficult to ensure the optimal balance between accuracy and hardware resources.

[0004] Therefore, how to research and design a fast Fourier transform optimal scaling vector analysis method and device that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the Invention

[0005] In order to address the deficiencies in the prior art, the purpose of the present invention is to provide a fast Fourier transform optimal scaling vector analysis method and device. By establishing a joint power model of quantization error (uniform distribution) and saturation error (truncated normal distribution), the defect of the prior art that only optimizes a single error source leads to large error estimation deviation is solved, and the error power estimation accuracy is greatly improved; an efficient search algorithm based on dynamic programming is used to construct a scaling path step by step, and at each level, only the branch with the smallest cumulative total error is retained for nodes with the same scaling times, thereby generating an optimal path, compressing the search space, and solving the problem of the traditional method that global optimization cannot be achieved due to the exponential explosion of the search space; hardware parameter generation is guided by a theoretical model to realize an automated design closed loop, reduce most of the simulation parameter adjustment times, and ensure that the total error power of the output signal is globally minimized.

[0006] In a first aspect, a fast Fourier transform optimal scaling vector analysis method is provided, comprising the following steps:

[0007] For each level of the FFT architecture in the FFT hardware module, the quantization error power and the saturation error power are calculated based on the input signal power of the FFT architecture, and the error powers of all FFT architectures are accumulated level by level to obtain the overall error power of the FFT hardware module;

[0008] With the goal of minimizing the overall error power, the search space is compressed step by step based on a dynamic programming algorithm, and only the scaling vector nodes with the minimum cumulative error power are retained under the same scaling times to generate a search path set;

[0009] An optimal path is selected from the search path set for backtracking to obtain an optimal scaling vector, and the optimal scaling vector is configured in the FFT hardware module.

[0010] Furthermore, the architecture of the FFT hardware module includes a butterfly operation unit, a twiddle factor multiplication unit, a saturation operation unit and a quantization unit;

[0011] The quantization unit implements a scaling operation by adjusting a bit width offset, and the scaling factor is an integer power of 1 / 2.

[0012] Furthermore, it is characterized in that the quantization error power is calculated based on a uniform distribution assumption.

[0013] Furthermore, the saturation error power is calculated based on the assumption that the FFT input signal obeys a normal distribution with a mean of 0.

[0014] Furthermore, the calculation of the overall error power of the FFT hardware module includes:

[0015] Adding the quantization error power and the saturation error power of each level of the FFT architecture to obtain a total error power of each level;

[0016] The product of the total error power of each stage and the error propagation coefficient of each stage is linearly superimposed to obtain the overall error power of the FFT hardware module.

[0017] Furthermore, the stepwise compression of the search space based on the dynamic programming algorithm includes:

[0018] Starting from the first-level FFT architecture, the cumulative error power of each node is recorded. The cumulative error power is the linear summation of the quantization error power and the saturation error power accumulated from the first level to the current level.

[0019] For nodes with the same scaling times, only the node with the smallest cumulative error power is retained, and the next level branch is generated based on the node;

[0020] The node expansion and pruning of all levels are completed iteratively step by step, reducing the search space complexity from exponential to linear.

[0021] Furthermore, the method further comprises:

[0022] During the dynamic programming search process, if the quantization error power or the saturation error power of a node at a certain level exceeds a corresponding preset threshold value, the subsequent path search of the corresponding node is terminated.

[0023] Furthermore, the generation of the search path set satisfies a scaling constraint, and the optimal path finally selected is the path with the minimum overall error power in the set.

[0024] In a second aspect, a digital signal processing device is provided, wherein the device includes at least one FFT hardware module for implementing a fast Fourier transform optimal scaling vector analysis method as described in any one of the first aspects.

[0025] In a third aspect, a signal receiving device is provided, wherein the device includes at least one digital signal processing device and a channel decoding module for implementing the second aspect.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. The present invention provides a fast Fourier transform optimal scaling vector analysis method. By establishing a composite error power model, this method achieves the coordinated optimization of quantization error (uniform distribution) and saturation error (truncated normal distribution). The method introduces an error propagation coefficient at each stage to strengthen the weight of the influence of the previous stage error on the final output, ensuring the global optimality of the early scaling strategy. The method also models the dynamic evolution of the signal variance at each stage to ensure the physical accuracy of the error propagation link. According to actual measurement results, this method significantly improves the total error power estimation accuracy compared to traditional empirical schemes, while reducing LUT resource usage and power consumption in FPGAs.

[0028] 2. This invention uses a highly efficient search algorithm based on dynamic programming to construct a scaling path step by step. At each level, for nodes with the same scaling number, only the branch with the smallest cumulative error is retained to generate the optimal path. This solves the problem of traditional methods being unable to find the optimal solution globally due to an exponential explosion in the search space (for example, the number of scaling combinations for a 2048-point FFT reaches over 4 million). It compresses the search time complexity from O(ML) to O(L) (for example, the calculation of a 2048-point FFT is reduced from hours to seconds), and supports large-scale FFT hardware parameter generation without sacrificing global optimality.

[0029] 3. This invention constructs a parameter generation framework based on a theoretical model. It uses an error model and dynamic programming to directly output the optimal scaling vector, quantization bit width, and saturation threshold parameters. This transforms the traditional trial-and-error process, which relies on manual experience, into a deterministic mathematical optimization problem, achieving a closed-loop mapping with hardware. This approach significantly reduces the number of simulation parameter adjustments and ensures the global minimization of the total error power of the output signal, significantly shortening the design cycle of the FFT hardware solution. The calculation results can be verified through Monte Carlo simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0031] Figure 1 is a schematic diagram of a signal processing device according to an embodiment of the present invention;

[0032] Figure 2 1 is a diagram of the hardware implementation architecture of the i-th level FFT in an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of fixed-point numbers and quantization errors in an embodiment of the present invention;

[0034] Figure 4 is a probability distribution diagram of quantization error in an embodiment of the present invention;

[0035] Figure 5is a diagram showing the influence of different saturation thresholds on the probability density of normal distribution in an embodiment of the present invention;

[0036] Figure 6 1 is a schematic diagram of the FFT scaling vector principle in an embodiment of the present invention;

[0037] Figure 7 1 is a schematic diagram of a scaling vector search method after compressing the search space in an embodiment of the present invention;

[0038] Figure 8 This is a conceptual block diagram of the FFT optimal scaling vector search method in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0040] Embodiment: A fast Fourier transform optimal scaling vector analysis method comprises the following steps:

[0041] S1: For each level of the FFT hardware module, the quantization error power and saturation error power are calculated based on the input signal power of the level, and the error power of all levels is accumulated level by level to generate the overall error power of the FFT hardware module;

[0042] S2: With the goal of minimizing the overall error power, the search space is compressed step by step based on the dynamic programming algorithm. Only the scaling vector nodes with the minimum cumulative error power are retained under the same scaling times to generate a set of search paths.

[0043] S3: Select the optimal path from the search path set for backtracking to obtain the optimal scaling vector, and configure the optimal scaling vector in the FFT hardware module.

[0044] refer to Figure 1 The FFT algorithm has a variety of application scenarios. Taking the receiving end baseband digital signal processing module in the communication system as an example to illustrate the application background of the present invention, considering the FFT hardware module in the communication system, the FFT algorithm used therein is given in matrix form as follows:

[0045]

[0046] The FFT algorithm can be decomposed into Level, in formula (1) and Represent the rotation factor matrix and butterfly operation matrix of the i-th level FFT respectively, and It is a matrix used to adjust the order of calculation results and will not affect the accuracy of the calculation results. is a column vector consisting of the input signals of the FFT hardware module in the communication system, It is a column vector composed of the output signals of the FFT hardware module in the communication system.

[0047] In hardware implementation, floating-point numbers must be quantized into fixed-point numbers. Due to the finite word length effect, quantization operations will introduce quantization errors. Furthermore, due to hardware bit width limitations, overflow may occur during addition operations. FFT is an extremely computationally intensive algorithm, involving numerous addition and multiplication operations. This causes quantization errors and overflow-related miscalculations to propagate throughout the FFT calculation, ultimately resulting in erroneous results.

[0048] When performing each addition calculation on fixed-point numbers, expanding the result can prevent overflow, but this incurs additional computational area overhead. For FFT algorithms, which have a very high density of multiplication and addition operations, the bit width increases with each FFT stage. If all the results are expanded, the additional computational area overhead is enormous. To avoid the additional area overhead of expanding the result while ensuring relatively accurate calculation results, saturation and scaling are used to reduce overflow errors at the expense of a certain level of computational precision.

[0049] refer to Figure 2 The structure of the i-th level FFT includes functional units such as butterfly unit, rotation factor multiplication, saturation operation, quantization operation, etc. The present invention creatively introduces the calculation error caused by saturation into the error estimation of FFT, so the overall calculation error of FFT is It can be written as:

[0050]

[0051] in, is the error introduced by the saturation operation in the hardware implementation of the i-th level FFT architecture, is the error introduced by the quantization operation in the hardware implementation of the i-th level FFT architecture, and They represent the rotation factor matrix and butterfly operation matrix of the j-th level FFT architecture respectively, and L is the total number of levels of FFT hardware modules.

[0052] refer to Figure 3 For fixed-point numbers, it is usually considered to be equal to the sum of floating-point numbers and errors. Therefore, the error is considered as noise, and the power is used to measure the impact of the error on the system accuracy. Therefore, the overall error power of FFT is for:

[0053]

[0054] Among them, in formula (3) represents the trace of the matrix, represents the mean, represents the overall FFT calculation error proposed by formula (2), L is the total number of FFT hardware modules, is the error introduced by the saturation operation in the hardware implementation of the i-th level FFT architecture, is the error introduced by the quantization operation in the hardware implementation of the i-th level FFT architecture.

[0055] Due to saturation error and quantization error are independent of each other, so:

[0056]

[0057] In formula (4) is the saturation error power at level i in the FFT hardware module, is the quantization error power of the i-th level in the FFT hardware module, and L is the total number of levels in the FFT hardware module.

[0058] refer to Figure 4 When using the Round truncation method, It can be considered as a random variable that obeys a uniform distribution. Assuming that its quantization bit width is B and the number of times it is scaled by 1 / 2 is n, then according to the variance formula of the uniform distribution, the power of the quantization error is:

[0059]

[0060] in, is the real number quantization error power calculation formula, B is the quantization bit width, and n is the number of scaling times.

[0061] For complex data, it is:

[0062]

[0063] in, is the calculation formula for the complex quantization error power, is the real number quantization error power calculation formula, B is the quantization bit width, and n is the number of scaling times.

[0064] refer to Figure 5, the probability density of a normally distributed signal will change after passing through different saturation thresholds. When the saturation threshold is relatively loose, it can be considered that the probability density is still approximately normally distributed. When the saturation threshold is more aggressive, the saturated data no longer obeys the normal distribution. For a certain level of FFT architecture, assuming that the input signals of this level are independent and have a mean of 0, and a variance of The data of the output signal of this level theoretically obeys the normal distribution with a mean of 0 and a variance of However, since the saturation operation will reduce the data beyond the current characterization range, some power will be lost. The power transferred from this stage to the next stage needs to be corrected for this part of the power. The saturation threshold is set to , then the lost power for:

[0065]

[0066]

[0067] Therefore, the output power of this stage for:

[0068]

[0069] The saturation operation will cause power loss. The power error MSE caused by this part of the lost power is the power of the saturation error. for:

[0070]

[0071]

[0072] Explain the symbols involved in equations (7), (8), and (9). is the input signal of the i-th level in the FFT hardware module and obeys the normal distribution, is the probability density distribution function of the input signal, is the saturation threshold, It represents the power loss value caused by saturation operation of the i-th level FFT architecture. is the actual output power value of the i-th level FFT architecture after removing the power loss value, is the power value of the saturation error, is the variance of the output signal, is the power of the saturation error.

[0073] When the data is scaled, the data of the output signal of this level theoretically obeys the mean of 0 and the variance of The normal distribution of , the analysis method remains unchanged, only in the calculation of formula (7), (8), (9), substitute Perform calculations.

[0074] In summary, the overall error power estimation method of FFT is as follows: according to the quantization bit width, saturation threshold and scaling conditions, the corresponding data is substituted into equations (6) to (9) respectively, and the results are substituted into equation (4).

[0075] refer to Figure 6 , for an N-point FFT, there are Level FFT architecture, assuming that there are M scaling factors, so the scaling vector has a total of In FFT calculations, the scaling vector greatly affects the accuracy of the FFT results. As the number of FFT points and the types of scaling factors increase, the search space for scaling vectors grows exponentially, making the exhaustive search method unsuitable for high-point FFTs. Therefore, the scaling vector is usually chosen based on empirical values.

[0076] The present invention provides an FFT scaling vector search method based on the overall error power given by formula (4), introduces the idea of ​​dynamic programming into the search method, and reduces the computational complexity.

[0077] According to equations (6) and (9), the overall FFT error power is obtained by summing the quantization error power and saturation error power of each level. When the overall error power is minimum, the calculation accuracy of FFT is the highest. Therefore, the minimum value of the overall error power is set to To search for the target.

[0078] refer to Figure 7 , for an FFT hardware module, starting from the first-level FFT architecture, calculate and record the error power of each node , according to formula (6), when the scaling times are equal, the quantization error power If the two sets of scaling vectors have the same scaling levels, then the output power of the FFT architecture is similar. To select the nodes that need to be recorded, according to formula (4), only keep The smallest scaling vector, that is, when When, if , then the scaling vector is retained , otherwise keep the scaling vector ,in 、 Indicates the scaling factor corresponding to the i-th level FFT structure in the scaling vector.

[0079] It is not necessary to record all nodes during the search process. For all nodes with the same scaling times, only the node with the smallest cumulative error power is retained and expanded downward, thereby expanding the exponential search space. Compress the search space to a linear level In addition, according to equations (6) and (9), as the number of scaling increases, the quantization error power Will increase, saturation error power will decrease, so two error power thresholds can be set , which further reduces the search space. or When , the part and the corresponding extended node are no longer searched, so after completing the entire search process, traverse from the final searched node to the root node from bottom to top, and the value of each node is the value of the i-th level of the optimal scaling vector. Further, all node values ​​are sorted to obtain the optimal scaling vector .

[0080] refer to Figure 8 , shows the conceptual block diagram of the Fast Fourier Transform optimal scaling vector search method, by setting the parameters of the FFT hardware module in the system, including the saturation threshold, the number of scaling factors , quantization bit width , input signal power Etc., the optimal scaling vector for the current design can be calculated in advance , thereby guiding the hardware design of the FFT hardware module and shortening the design process.

[0081] Working principle: The present invention accurately calculates the overall error power of FFT by establishing a joint power model of quantization error (uniform distribution) and saturation error (truncated normal distribution), thus solving the defect of existing technologies that only optimize a single error source, resulting in large error estimation deviations, and greatly improving the accuracy of error power estimation; based on an efficient search algorithm for dynamic programming, a scaling path is constructed step by step. At each level, only the branch with the smallest cumulative total error is retained for nodes with the same number of scaling times, thereby generating the optimal path and compressing the search space. This solves the problem of traditional methods that are unable to globally optimize due to the exponential explosion of the search space; hardware parameter generation is guided by theoretical models to achieve an automated design closed loop, reducing most of the simulation parameter adjustment times and ensuring that the total error power of the output signal is globally minimized.

[0082] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0084] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0086] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fast Fourier transform optimal scaling vector analysis method, characterized in that: The following steps are involved: For each level of the FFT architecture in the FFT hardware module, the quantization error power and the saturation error power are calculated based on the input signal power of the FFT architecture, and the error powers of all FFT architectures are accumulated level by level to obtain the overall error power of the FFT hardware module; With the goal of minimizing the overall error power, the search space is compressed step by step based on a dynamic programming algorithm, and only the scaling vector nodes with the minimum cumulative error power are retained under the same scaling times to generate a search path set; An optimal path is selected from the search path set for backtracking to obtain an optimal scaling vector, and the optimal scaling vector is configured in the FFT hardware module.

2. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The architecture of the FFT hardware module includes a butterfly operation unit, a twiddle factor multiplication unit, a saturation operation unit and a quantization unit; The quantization unit implements a scaling operation by adjusting a bit width offset, and the scaling factor is an integer power of 1 / 2.

3. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The quantization error power is calculated based on a uniform distribution assumption.

4. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The saturation error power is calculated based on the assumption that the FFT input signal obeys a normal distribution with a mean of 0.

5. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The calculation of the overall error power of the FFT hardware module includes: Adding the quantization error power and the saturation error power of each level of the FFT architecture to obtain a total error power of each level; The product of the total error power of each stage and the error propagation coefficient of each stage is linearly superimposed to obtain the overall error power of the FFT hardware module.

6. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The step-by-step compression of the search space based on the dynamic programming algorithm includes: Starting from the first-level FFT architecture, record the cumulative error power of each node, which is the linear summation of the quantization error power and the saturation error power accumulated from the first level to the current level; For nodes with the same scaling times, only the node with the smallest cumulative error power is retained, and the next level branch is generated based on the node; The node expansion and pruning of all levels are completed iteratively step by step, reducing the search space complexity from exponential to linear.

7. The fast Fourier transform optimal scaling vector analysis method according to claim 6, characterized in that: The method further includes: During the dynamic programming search process, if the quantization error power or the saturation error power of a node at a certain level exceeds a corresponding preset threshold value, the subsequent path search of the corresponding node is terminated.

8. The fast Fourier transform optimal scaling vector analysis method according to claim 1, characterized in that: The generation of the search path set satisfies a scaling constraint, and the optimal path finally selected is the path with the minimum overall error power in the set.

9. A digital signal processing device, characterized in that: The device comprises at least one FFT hardware module according to any one of claims 1-8.

10. A signal receiving device, characterized in that: The device comprises at least one digital signal processing device as claimed in claim 9 and a channel decoding module.

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