Clustering method and system based on multi-bit trigger

Abstract

The invention provides a clustering method and system based on a multi-bit trigger, and solves the problems that an existing multi-bit trigger optimization method is insufficient in time sequence optimization capability and does not support trigger clustering in a multi-clock source scene. Firstly, according to an input netlist, chip coordinates and selectable trigger list information, under the constraint that clustered triggers must belong to the same clock network, a multi-bit trigger cluster is generated through an improved mean shift clustering algorithm. And then de-clustering and refining optimization are performed on the multi-bit trigger in combination with a feasible region de-clustering mechanism and a trigger replacement strategy driven by a time sequence, so that comprehensive optimization of the area, the power consumption and the time sequence performance is realized.

Description

Technical Field

[0001] The present invention proposes a clustering method and system based on multi-bit triggers, and relates to the field of computers. Background Art

[0002] Traditional single-bit flip-flops (SBFFs) waste wiring resources and increase power consumption due to independent layout, while multi-bit flip-flops (MBFFs) significantly reduce area and dynamic power consumption by sharing clock and power networks. However, existing MBFF optimization methods have the following issues: insufficient timing optimization capabilities and inability to effectively handle flip-flop clustering in scenarios with multiple clock sources, a common scenario in industrial samples. Summary of the Invention

[0003] In light of this, and to address the issues of suboptimal trigger clustering results, insufficient timing optimization capabilities, and a lack of consideration for trigger clustering in scenarios with multiple clock sources, the present invention proposes a clustering method and system based on multi-bit triggers. This method balances area, power consumption, and timing costs at advanced process nodes, achieving multi-objective balanced optimization. To address the gaps and shortcomings of the existing technology, the present invention proposes a clustering method and system based on multi-bit triggers.

[0004] The present invention proposes a clustering method and system based on multi-bit triggers, including the following contents:

[0005] A clustering method based on multi-bit triggers includes first generating multi-bit trigger clusters using an improved mean-shift clustering algorithm; then declustering the multi-bit triggers by combining a feasible region declustering mechanism and a timing-driven trigger relocation strategy; wherein the clustering method based on multi-bit triggers includes the following steps:

[0006] Step S1: collecting a list of multi-bit triggers as input information for multi-bit trigger clustering; clustering the multi-bit triggers using an R-tree and improved mean-shift clustering method;

[0007] Step S2: re-clustering the multi-bit triggers using a probabilistic framework;

[0008] Step S3: declustering the multi-bit triggers;

[0009] Step S4: Partially clustering the multi-bit triggers that are incompatible with clustering;

[0010] Step S5: Use timing to drive the multi-bit trigger to reposition.

[0011] Furthermore, step S1 includes the following contents:

[0012] Step S11: Collect a list of multi-bit triggers as input information for multi-bit trigger clustering; wherein the expression of the multi-bit trigger list is F = {f1, ..., f N}, where f1,…,f N Represents a single multi-bit flip-flop;

[0013] Each multi-bit flip-flop includes a delay D(f i ), area A(f i ), power consumption P(f i ), properties and standard cell libraries,

[0014] The coordinates of each multi-bit trigger P i =(x i ,y i ), the pin of each multi-bit trigger includes initial timing information.

[0015] Step S12: constructing an R-tree for storing multi-bit triggers, including first traversing all multi-bit triggers and inserting the position of each multi-bit trigger into the R-tree;

[0016] Step S13: Collecting K neighbors; wherein the process of collecting K neighbors includes querying the R-tree to obtain the K nearest multi-bit triggers of the current multi-bit trigger, and then filtering the set of multi-bit triggers by retaining only the multi-bit triggers whose distance is less than a specified distance upper limit;

[0017] Step S14: Next, determine whether the number of neighbors of the current multi-bit trigger is 1. If so, the multi-bit trigger does not move; if not, set the multi-bit trigger bandwidth, including the following:

[0018] h i =min(h max ,||x i -x i，M ||)

[0019] where h i is the bandwidth of the i-th multi-bit trigger, h max is the maximum allowable displacement, ||x i -x i，M || is the distance from the trigger to the farthest neighbor;

[0020] Step S15: Sort the neighbors by distance; after locating the neighbors of all multi-bit triggers, traverse all multi-bit triggers to perform displacement iteration.

[0021] Furthermore, step S1 also includes the following contents:

[0022] Step S16: Determine whether the current multi-bit trigger flag is immovable. If so, skip the current trigger. Otherwise, move the multi-bit trigger according to the following formula:

[0023]

[0024] Among them, t represents the current iteration number, j represents the multi-bit trigger traversed, and x i represents the initial position of the multi-bit trigger before it starts moving, y is the position of the trigger after moving, h is the maximum distance each trigger can move, d represents the current density construction of d-dimensional data, and function g is the gradient of the Gaussian kernel function;

[0025] Step S17: According to the formula Determine whether the displacement is less than the threshold, where is the new position of the multi-bit flip-flop j, is the original position of the multi-bit flip-flop j, is the displacement of the multi-bit trigger j, δ is the threshold;

[0026] Step S18: Further, if the displacement is less than the threshold, the multi-bit trigger is marked as completed, otherwise the displacement is continued to be calculated until the displacement of the multi-bit trigger j is less than the threshold;

[0027] Step S19: When all multi-bit triggers have completed the contents of step S11 to step S18, each multi-bit trigger is traversed in order according to the coordinates and clustered in sequence.

[0028] Furthermore, step S2 includes the following contents:

[0029] Step S21: define each multi-bit trigger to belong to a corresponding clock network, where the clock network c k ∈C=c1,…,c M};

[0030] Define cluster set Γ={γ1,…,γ K}, where clustering

[0031] Define cluster γ j The probability of being plundered is in

[0032] Step S22: generating a probability based on the distance between each multi-bit trigger, including the following:

[0033] Defining triggers The probability of being robbed based on distance is:

[0034]

[0035] Among them, μ s =centroid(γ s ) is the target cluster γ s The center of mass of the multi-bit trigger is d(·), d(·) is the Euclidean distance, σ is the strength of the control space correlation, is the average distance of the multi-bit trigger to the nearest multi-bit trigger, and α is the direct factor that controls the size of this probability, that is, the closer the trigger is, the greater the probability of being plundered;

[0036] Step S23: For each multi-bit trigger that forms a cluster, γ y = {y}, and determine its nearest multi-bit trigger x∈γ x ; Based on the above probability, choose whether y will plunder x into its cluster y.

[0037] Furthermore, step S2 also includes the following contents:

[0038] Step S24: According to step S21, step S22 and step S32, a re-clustering process is implemented, including the following contents:

[0039] S241: merging adjacent flip-flops of the same clock network based on a probability mechanism, including based on a defined probability of being plundered clusters and a probability generated based on distance, wherein a merging criterion includes merging if the probability generated based on distance is less than a threshold and the probability of being plundered clusters is less than a threshold;

[0040] S242: Clustering and splitting based on the same clock network constraints, including the following:

[0041] Perform in-place decomposition for hybrid clock network clusters, including the following:

[0042]

[0043] Among them, Γ refers to the set of all clusters, γ j represents a cluster in the set,

[0044] Furthermore, define in Indicates that a cluster γ j Decompose into a set of k small clusters containing the same clock network; the coordinates of each cluster of simultaneous clock networks are determined by the centroid of all triggers belonging to the same network in the original cluster;

[0045] Furthermore, the re-clustering centroid calculation formula is:

[0046]

[0047] in Is a new subcluster The coordinates of the center of mass, is the number of triggers in the subcluster, coord(f) is the coordinate of trigger f;

[0048] S243: The same probabilistic mechanism re-merges adjacent triggers, including the following:

[0049] The small clustering set is performed according to the re-clustering centroid calculation formula defined in step S242 The merge after splitting will optimize the new sub-cluster that appears in step S242 Further optimize area and timing.

[0050] Furthermore, step S3 includes the following contents:

[0051] Step S31: Define a multi-bit trigger f i The center coordinate is c i =(x i ,y i ), define the multi-bit trigger pin coordinates p i,k =(x i,k ,y i,k ), define the pin timing margin as S(p i,k ), connection direction vector

[0052] Step S32: Generate a rectangle at the center of the multi-bit trigger, whose initial size is the minimum bounding box between the trigger pin and the connected fan-in / fan-out pins; the calculation formula of the rectangle is:

[0053]

[0054] Among them, w i is the width of the rectangle, h i is the height of the rectangle, p i,k is the pin coordinate, c i is the center coordinate of the multi-bit trigger, ||p i,k -c i || is the distance between the two, Represents the initial rectangle generated;

[0055] Step S33: traverse the pins of each multi-bit trigger and adjust the size and coordinates of the rectangle according to the direction, distance and slack of the connected fan-out and fan-in pins. The calculation formula includes the following:

[0056] When S(p i,k )<0, that is, when the margin is negative, the rectangular coordinates of each multi-bit trigger pin connected are moved in the direction of the displacement: Δrk =|S(p i,k )|·v i,k , where Δr k is the displacement of the multi-bit trigger, |S(p i,k )| is the time margin of the multi-bit trigger, v i,k is the direction vector of the multi-bit trigger;

[0057] When S(p i,k )>0, that is, positive margin, the size of the rectangle is expanded in the opposite direction of the connected multi-bit flip-flop pins. The size adjustment includes the following:

[0058]

[0059] where Δw k is the change in the width of the rectangle, Δh k is the change in the height of the rectangle, S(p i,k ) is its time margin, β is the proportional factor, |v x | is the length of the vector in the x-axis direction, |v y |The vector is the length in the y-axis direction.

[0060] Step S34: define the F region update function as:

[0061]

[0062] in Indicates adjusting the size of the rectangle along the specified direction. the new coordinates of the rectangle's center, is the old coordinate of the center of the rectangle, Δr k is the rectangular displacement, is the new size of the rectangle, is the old size of the rectangle, Δw k is the change in the width of the rectangle, Δh k The change in the height of the rectangle is used to guide the size expansion or coordinate movement of the F region through the F region update function;

[0063] Step S35: After the F region update function is obtained, since the original multi-bit trigger set is F={f1,…,f N}, the original cluster set is Γ={γ1,…,γ K}, where clustering Updated multi-bit flip-flop f i The F region is The intersection area set is I = {R i ∩R j |i≠j};

[0064] The intersection area is determined by the formula: Area(R a ∩R b )>0After calculating the F area of ​​each multi-bit trigger and its intersection area, traverse the intersection area in reverse order of area size, and divide these clusters into the cluster sets corresponding to the intersection area to ensure that they are placed in the area with optimal timing. Finally, check whether the original cluster point still has trigger allocation and falls in any intersection area. If so, retain the cluster.

[0065] Furthermore, step S4 includes the following contents:

[0066] Step S41: First, filter out incompatible multi-bit flip-flop clusters, including multi-bit flip-flops for which no matching one exists in the cell library of the specified bit size;

[0067] Step S42: Split the incompatible multi-bit trigger clusters and sort them by position from smallest to largest bit number;

[0068] Step S43: Design a cost function for regenerating a compatible multi-bit flip-flop cluster, wherein the cost function includes the following:

[0069]

[0070] Where x represents a candidate multi-bit flip-flop; HPWL represents the total semi-perimeter wire length, HPWL(n) represents the total semi-perimeter wire length of the network connected to x, and OriHPWL(n') represents the total semi-perimeter wire length connected to the original multi-bit flip-flop before clustering; Delay(x), Power(x), Area(x), Bit(x) represent the delay, power consumption, area, and number of bits of the multi-bit flip-flop x, while Delay(i), Power(i), Area(i), Bit(i) correspond to the delay, power consumption, area, and number of bits of each flip-flop in cluster c; α, β, γ, and δ represent the cost factors of wire length, power consumption, area, and number of bits, respectively.

[0071] Furthermore, step S5 includes the following contents:

[0072] Step S51: relocate the multi-bit trigger to optimize the timing condition of the pin, wherein a single multi-bit trigger f i The original coordinates are defined as Critical pins are defined as pins where the timing margin of each pin is less than a specified threshold, and the maximum allowed displacement is defined as D max , the original network minimum bounding box is defined as B net =[x min , x max ]×[y min ,y max];

[0073] Step S52: For each multi-bit flip-flop, check its key pins and obtain the bounding boxes formed by the fan-in and fan-out pins respectively; wherein the fan-in area bounding box calculation formula includes the following:

[0074]

[0075] The fan-out area bounding box calculation formula includes the following:

[0076]

[0077] in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates;

[0078] in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates;

[0079] in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates;

[0080] in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates;

[0081] Step S53: When there is a valid fan-in bounding box, the center of the single multi-bit flip-flop is aligned to the nearest point of the box; otherwise, it is aligned to the nearest point of the fan-out box. The calculation formula is:

[0082]

[0083] The displacement from the original position does not exceed the maximum allowable displacement distance, that is,

[0084] Step S54: While moving, ensure that the multi-bit trigger does not exceed the minimum bounding box area of ​​the original network; if the signal delay of the multi-bit trigger is not reduced after repositioning, the multi-bit trigger will be restored to its original position.

[0085] According to the second aspect of the present invention, a clustering system based on multi-bit triggers includes an electronic device, wherein the electronic device includes a memory, a processor, and a computer program stored in the memory and runnable on the processor, and is characterized in that when the processor executes the computer program, it implements a clustering method based on multi-bit triggers as described in any one of the present invention.

[0086] According to the third aspect of the present invention, a clustering system based on multi-bit triggers includes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and is characterized in that when the computer program is executed by a processor, it implements a clustering method based on multi-bit triggers as described in any one of the present inventions.

[0087] The present invention has the following advantages:

[0088] This invention addresses the problems of existing multi-bit trigger optimization methods, such as suboptimal trigger clustering results, insufficient timing optimization capabilities, and inability to support trigger clustering in multiple clock source scenarios, by innovating clustering methods. By employing a mean-shift-based clustering processor, clusters with reasonable initial solutions can be generated in both multi-clock and single-clock environments. Furthermore, a feasible region-based multi-bit trigger declustering and timing-driven relocation algorithm further optimizes area utilization, timing, and power consumption. Statistical results demonstrate that the overall algorithm outperforms the most advanced mean-shift algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 This is a flow chart of a clustering method and system based on multi-bit triggers in the present invention.

[0090] Figure 2 It is a flow chart of the clustering method using improved mean shift in the present invention.

[0091] Figure 3 It is a pseudo code diagram of the mean shift algorithm framework of the present invention.

[0092] Figure 4 It is a schematic diagram of split clustering in probability-based re-clustering in the present invention.

[0093] Figure 5 It is a schematic diagram of the process of modifying the F region in the present invention.

[0094] Figure 6 It is a schematic diagram of clustering division in the present invention.

[0095] Figure 7 This is a schematic diagram of the cost function in the present invention. DETAILED DESCRIPTION

[0096] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0097] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0098] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application; as used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form, and it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or their combinations.

[0099] A clustering method based on multi-bit triggers includes first generating multi-bit trigger clusters using an improved mean-shift clustering algorithm; then declustering the multi-bit triggers by combining a feasible region declustering mechanism and a timing-driven trigger relocation strategy; wherein the clustering method based on multi-bit triggers includes the following steps:

[0100] Step S1: collecting a list of multi-bit triggers as input information for multi-bit trigger clustering; clustering the multi-bit triggers using an R-tree and improved mean-shift clustering method;

[0101] Step S2: re-clustering the multi-bit triggers using a probabilistic framework;

[0102] Step S3: declustering the multi-bit triggers;

[0103] Step S4: Partially clustering the multi-bit triggers that are incompatible with clustering;

[0104] Step S5: Use timing to drive the multi-bit trigger to reposition.

[0105] Furthermore, step S1 includes the following contents:

[0106] Step S11: Collect a list of multi-bit triggers as input information for multi-bit trigger clustering; wherein the expression of the multi-bit trigger list is F = {f1, ..., f N}, where f1,…,f N Represents a single multi-bit flip-flop;

[0107] Each multi-bit flip-flop includes a delay D(f i ), area A(f i ), power consumption P(f i), properties and standard cell libraries,

[0108] The coordinates of each multi-bit trigger P i =(x i ,y i ), the pin of each multi-bit trigger includes initial timing information.

[0109] Step S12: constructing an R-tree for storing multi-bit triggers, including first traversing all multi-bit triggers and inserting the position of each multi-bit trigger into the R-tree;

[0110] Step S13: Collecting K neighbors; wherein the process of collecting K neighbors includes querying the R-tree to obtain the K nearest multi-bit triggers of the current multi-bit trigger, and then filtering the set of multi-bit triggers by retaining only the multi-bit triggers whose distance is less than a specified distance upper limit;

[0111] Step S14: Next, determine whether the number of neighbors of the current multi-bit trigger is 1. If so, the multi-bit trigger does not move; if not, set the multi-bit trigger bandwidth, including the following:

[0112] h i =min(h max , ‖x i -x i，M ‖)

[0113] where h i is the bandwidth of the i-th multi-bit trigger, h max is the maximum allowable displacement, ||x i -x i，M || is the distance from the trigger to the farthest neighbor;

[0114] Step S15: Sort the neighbors by distance; after locating the neighbors of all multi-bit triggers, traverse all multi-bit triggers to perform displacement iteration.

[0115] Furthermore, step S1 also includes the following contents:

[0116] Step S16: Determine whether the current multi-bit trigger flag is immovable. If so, skip the current trigger. Otherwise, move the multi-bit trigger according to the following formula:

[0117]

[0118] Among them, t represents the current iteration number, j represents the multi-bit trigger traversed, and x irepresents the initial position of the multi-bit trigger before it starts moving, y is the position of the trigger after moving, h is the maximum distance each trigger can move, d represents the current density construction of d-dimensional data, and function g is the gradient of the Gaussian kernel function;

[0119] Step S17: According to the formula Determine whether the displacement is less than the threshold, where is the new position of the multi-bit flip-flop j, is the original position of the multi-bit flip-flop j, is the displacement of the multi-bit trigger j, δ is the threshold;

[0120] Step S18: Further, if the displacement is less than the threshold, the multi-bit trigger is marked as completed, otherwise the displacement is continued to be calculated until the displacement of the multi-bit trigger j is less than the threshold;

[0121] Step S19: When all multi-bit triggers have completed the contents of step S11 to step S18, each multi-bit trigger is traversed in order according to the coordinates and clustered in sequence.

[0122] Furthermore, step S2 includes the following contents:

[0123] Step S21: define each multi-bit trigger to belong to a corresponding clock network, where the clock network c k ∈C=c1,…,c M};

[0124] Define cluster set Γ={γ1,…,γ K}, where clustering

[0125] Define cluster γ j The probability of being plundered is in

[0126] Step S22: generating a probability based on the distance between each multi-bit trigger, including the following:

[0127] Defining triggers The probability of being robbed based on distance is:

[0128]

[0129] Among them, μ s =centroid(γ s ) is the target cluster γ sThe center of mass of the multi-bit trigger is d(·), d(·) is the Euclidean distance, σ is the strength of the control space correlation, is the average distance of the multi-bit trigger to the nearest multi-bit trigger, and α is the direct factor that controls the size of this probability, that is, the closer the trigger is, the greater the probability of being plundered;

[0130] Step S23: For each multi-bit trigger that forms a cluster, γ y = {y}, and determine its nearest multi-bit trigger x∈γ x ; Based on the above probability, choose whether y will plunder x into its cluster y.

[0131] Furthermore, step S2 also includes the following contents:

[0132] Step S24: According to step S21, step S22 and step S32, a re-clustering process is implemented, including the following contents:

[0133] S241: merging adjacent flip-flops of the same clock network based on a probability mechanism, including based on a defined probability of being plundered clusters and a probability generated based on distance, wherein a merging criterion includes merging if the probability generated based on distance is less than a threshold and the probability of being plundered clusters is less than a threshold;

[0134] S242: Clustering and splitting based on the same clock network constraints, including the following:

[0135] Perform in-place decomposition for hybrid clock network clusters, including the following:

[0136]

[0137] Among them, Γ refers to the set of all clusters, γ j represents a cluster in the set,

[0138] Furthermore, define in Indicates that a cluster γ j Decompose into a set of k small clusters containing the same clock network; the coordinates of each cluster of simultaneous clock networks are determined by the centroid of all triggers belonging to the same network in the original cluster;

[0139] Furthermore, the re-clustering centroid calculation formula is:

[0140]

[0141] in Is a new subcluster The coordinates of the center of mass, is the number of triggers in the subcluster, coord(f) is the coordinate of trigger f;

[0142] S243: The same probabilistic mechanism re-merges adjacent triggers, including the following:

[0143] The small clustering set is performed according to the re-clustering centroid calculation formula defined in step S242 The merge after splitting will optimize the new sub-cluster that appears in step S242 Further optimize area and timing.

[0144] Furthermore, step S3 includes the following contents:

[0145] Step S31: Define a multi-bit trigger f i The center coordinate is c i =(x i ,y i ), define the multi-bit trigger pin coordinates p i,k =(x i,k ,y i,k ), define the pin timing margin as S(p i,k ), connection direction vector

[0146] Step S32: Generate a rectangle at the center of the multi-bit trigger, whose initial size is the minimum bounding box between the trigger pin and the connected fan-in / fan-out pins; the calculation formula of the rectangle is:

[0147]

[0148] Among them, w i is the width of the rectangle, h i is the height of the rectangle, p i,k is the pin coordinate, c i is the center coordinate of the multi-bit trigger, ||p i,k -c i || is the distance between the two, Represents the initial rectangle generated;

[0149] Step S33: traverse the pins of each multi-bit trigger and adjust the size and coordinates of the rectangle according to the direction, distance and slack of the connected fan-out and fan-in pins. The calculation formula includes the following:

[0150] When S(p i,k )<0, that is, when the margin is negative, the rectangular coordinates of each multi-bit trigger pin connected are moved in the direction of the displacement: Δr k =|S(p i,k )|·v i,k , where Δr k is the displacement of the multi-bit trigger, |S(p i,k)| is the time margin of the multi-bit trigger, v i,k is the direction vector of the multi-bit trigger;

[0151] When S(p i,k )>0, that is, positive margin, the size of the rectangle is expanded in the opposite direction of the connected multi-bit flip-flop pins. The size adjustment includes the following:

[0152]

[0153] where Δw k is the change in the width of the rectangle, Δh k is the change in the height of the rectangle, S(p i,k ) is its time margin, β is the proportional factor, |v x | is the length of the vector in the x-axis direction, |v y |The vector is the length in the y-axis direction.

[0154] Step S34: define the F region update function as:

[0155]

[0156] in Indicates adjusting the size of the rectangle along the specified direction. the new coordinates of the rectangle's center, is the old coordinate of the center of the rectangle, Δr k is the rectangular displacement, is the new size of the rectangle, is the old size of the rectangle, Δw k is the change in the width of the rectangle, Δh k The change in the height of the rectangle is used to guide the size expansion or coordinate movement of the F region through the F region update function;

[0157] Step S35: After the F region update function is obtained, since the original multi-bit trigger set is F={f1,…,f N}, the original cluster set is Γ={γ1,…,γ K}, where clustering Updated multi-bit flip-flop f i The F region is The intersection area set is I = {R i ∩R j |i≠j};

[0158] The intersection area is determined by the formula: Area(R a ∩R b)>0After calculating the F area of ​​each multi-bit trigger and its intersection area, traverse the intersection area in reverse order of area size, and divide these clusters into the cluster sets corresponding to the intersection area to ensure that they are placed in the area with optimal timing. Finally, check whether the original cluster point still has trigger allocation and falls in any intersection area. If so, retain the cluster.

[0159] Furthermore, step S4 includes the following contents:

[0160] Step S41: First, filter out incompatible multi-bit flip-flop clusters, including multi-bit flip-flops for which no matching one exists in the cell library of the specified bit size;

[0161] Step S42: Split the incompatible multi-bit trigger clusters and sort them by position from smallest to largest bit number;

[0162] Step S43: Design a cost function for regenerating a compatible multi-bit flip-flop cluster, wherein the cost function includes the following:

[0163]

[0164] Where x represents a candidate multi-bit flip-flop; HPWL represents the total semi-perimeter wire length, HPWL(n) represents the total semi-perimeter wire length of the network connected to x, and OriHPWL(n') represents the total semi-perimeter wire length connected to the original multi-bit flip-flop before clustering; Delay(x), Power(x), Area(x), Bit(x) represent the delay, power consumption, area, and number of bits of the multi-bit flip-flop x, while Delay(i), Power(i), Area(i), Bit(i) correspond to the delay, power consumption, area, and number of bits of each flip-flop in cluster c; α, β, γ, and δ represent the cost factors of wire length, power consumption, area, and number of bits, respectively.

[0165] Furthermore, step S5 includes the following contents:

[0166] Step S51: relocate the multi-bit trigger to optimize the timing condition of the pin, wherein a single multi-bit trigger f i The original coordinates are defined as Critical pins are defined as pins where the timing margin of each pin is less than a specified threshold, and the maximum allowed displacement is defined as D max , the original network minimum bounding box is defined as B net =[x min , x max ]×[y min ,y max ];

[0167] Step S52: For each multi-bit flip-flop, check its key pins and obtain the bounding boxes formed by the fan-in and fan-out pins respectively; wherein the fan-in area bounding box calculation formula includes the following:

[0168]

[0169] The fan-out area bounding box calculation formula includes the following:

[0170]

[0171] in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates;

[0172] in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates;

[0173] in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates;

[0174] in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates;

[0175] Step S53: When there is a valid fan-in bounding box, the center of the single multi-bit flip-flop is aligned to the nearest point of the box; otherwise, it is aligned to the nearest point of the fan-out box. The calculation formula is:

[0176]

[0177] The displacement from the original position does not exceed the maximum allowable displacement distance, that is,

[0178] Step S54: While moving, ensure that the multi-bit trigger does not exceed the minimum bounding box area of ​​the original network; if the signal delay of the multi-bit trigger is not reduced after repositioning, the multi-bit trigger will be restored to its original position.

[0179] According to the second aspect of the present invention, a clustering system based on multi-bit triggers includes an electronic device, wherein the electronic device includes a memory, a processor, and a computer program stored in the memory and runnable on the processor, and is characterized in that when the processor executes the computer program, it implements a clustering method based on multi-bit triggers as described in any one of the present invention.

[0180] According to the third aspect of the present invention, a clustering system based on multi-bit triggers includes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and is characterized in that when the computer program is executed by a processor, it implements a clustering method based on multi-bit triggers as described in any one of the present inventions.

[0181] In addition to the above, the present invention also provides the following embodiments:

[0182] In one embodiment of the present invention, a clustering method and system based on multi-bit triggers is as follows: Figure 1 shown.

[0183] In one embodiment of the present invention, the flowchart of the clustering method using the improved mean shift in step S1 is as follows: Figure 2 shown.

[0184] In one embodiment of the present invention, in step S19, when all multi-bit triggers have completed the contents of steps S11 to S18, each multi-bit trigger is traversed in the order of coordinates and clustered in sequence. At the same time, in order to alleviate the problem that the mean shift algorithm cannot assign different probability weights to triggers with different clock networks, the present invention adds additional weight parameters to the original equation, balances the mutual influence between triggers with different clock networks, and promotes the clustering of triggers with the same clock network, thereby forming a more reasonable initial solution. The pseudo code of the mean shift algorithm framework is as follows: Figure 3 shown.

[0185] In one embodiment of the present invention, the schematic diagram of the split clustering in the probability-based re-clustering in step S2 is as follows: Figure 4 As shown, flip-flops with the same stripes belong to the same cluster, and flip-flops with the same color belong to the same clock network. After the first re-clustering is completed, each cluster will be split into multiple clusters with consistent internal clock networks based on the clock network constraints and re-clustered.

[0186] In one embodiment of the present invention, the detailed modification rules and the process of creating the final modified F region in step S3 are as follows: Figure 5 shown. Figure 5 The orange pins represent fan-out pins, and the green pins represent fan-in pins. The numbers indicate the pin margin. Figure 5 Figure (a) shows that the initial F region is created based on the shortest connection length of the trigger pins. Figure 5 Figure (b) shows that the black pin is a fan-out pin with negative margin, causing the F region to move leftward and upward. Figure 5Figure (c) shows that another fan-out pin with negative margin will move the F region to the left and downward. Figure 5 Figure (d) shows that a fan-out pin with positive margin will expand the F region to the left and upward, opposite to the connection direction of the pin.

[0187] In one embodiment of the present invention, in step S4, the intersection area is determined by the formula: Area(R a ∩R b )>0, after calculating the F area of ​​each trigger and its intersection area, traverse the intersection area in reverse order of area size, and divide these clusters into the cluster sets corresponding to the intersection area to ensure that they are placed in the area with the best timing. Finally, check whether the original cluster point still has a trigger allocation and falls in any intersection area. If so, retain the cluster. The final process is as follows Figure 6 shown. Figure 6 The red dots represent the original clusters, the green dots represent the newly generated clusters, the blue rectangles are the triggers, and the red boundaries are the F-regions of the flipped units. Figure 6 Figure (a) shows the intersection determined based on the greedy algorithm, excluding the green area because its area is smaller than other areas. Figure 6 (b) shows that the clusters are moved to the nearest red region boundary and redistributed. Figure 6 Figure (c) shows that if the clusters lie within intersecting F regions, some triggers may separate while others remain.

[0188] In one embodiment of the present invention, step S42: split incompatible multi-bit trigger clusters and sort them by position according to the number of bits from small to large; for example, a 5-bit cluster K can be split into a set of 1+2+2-bit triggers {a, b, c}. If the average heights of 1-bit and 2-bit triggers are h1 and h2 respectively, then

[0189] y a =h k ,y b =h k +h1,y c =h k +h1+j2.

[0190] In one embodiment of the present invention, in step S43, x represents a candidate multi-bit flip-flop; HPWL represents the total half-perimeter wire length, HPWL(n) represents the total half-perimeter wire length HPWL of the network connected to x, and OriHPWL(n') represents the HPWL connected to the original multi-bit flip-flop before clustering. Delay(x), Power(x), Area(x), Bit(x) represent the delay, power consumption, area, and number of bits of the multi-bit flip-flop x, while Delay(i), Power(i), Area(i), Bit(i) correspond to the delay, power consumption, area, and number of bits of each flip-flop in cluster c; α, β, γ, and δ represent the cost factors for wire length, power consumption, area, and number of bits, respectively, with default settings of 1.5, 2.3, 5.0, and 1.0. The total cost after clustering is calculated using the denominator reflecting the properties of the original cluster and the numerator summing the properties of the split cluster.

[0191] In one embodiment of the present invention, Figure 7 The process of step S43 is shown in Figure 2. For incompatible clusters, it is necessary to determine whether the loss is lower when splitting into multiple small bit clusters or replacing them with higher bit triggers. For compatible clusters, it is only necessary to select the best available trigger corresponding to the bit.

[0192] In one embodiment of the present invention, in terms of area, power consumption, TNS and CPU time, the algorithm of the present invention reduces the area by 5.2%, optimizes the power consumption by 7.4%, and significantly improves TNS compared to the existing mean-shift MBFF clustering algorithm, while shortening the running time by 13.3%. Compared with the mean-shift algorithm (without trigger relocation) with the declustering strategy proposed in the present invention, the algorithm of the present invention can achieve an 11.2% time optimization without sacrificing area and power consumption. Specifically, since the layout generated by the algorithm of the present invention is more evenly distributed, the algorithm of the present invention also achieves a total running time acceleration of 3.1%. Overall, the experimental results show that the algorithm of the present invention is both effective and efficient for the optimization problem it solves.

[0193] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions and effects do not exceed the scope of the technical solution of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A clustering method based on multi-bit triggers, characterized in that: First, multi-bit trigger clusters are generated using an improved mean-shift clustering algorithm; then, the multi-bit triggers are declustered by combining a feasible region declustering mechanism and a timing-driven trigger relocation strategy; wherein the multi-bit trigger-based clustering method comprises the following steps: Step S1: collecting a list of multi-bit triggers as input information for multi-bit trigger clustering; clustering the multi-bit triggers using an R-tree and improved mean-shift clustering method; Step S2: re-clustering the multi-bit triggers using a probabilistic framework; Step S3: declustering the multi-bit triggers; Step S4: Partially clustering the multi-bit triggers that are incompatible with clustering; Step S5: Use timing to drive the multi-bit trigger to reposition.

2. A clustering method based on multi-bit triggers according to claim 1, characterized in that: Step S1 includes the following contents: Step S11: Collect a list of multi-bit triggers as input information for multi-bit trigger clustering; The expression of the multi-bit trigger list is F={f1,…,f N }, where f1,…,f N Represents a single multi-bit flip-flop; Each multi-bit flip-flop includes a delay D(f i ), area A(f i ), power consumption P(f i ), properties and standard cell libraries, The coordinates of each multi-bit trigger P i =(x i ,y i ), the pins of each multi-bit flip-flop include initial timing information; Step S12: constructing an R-tree for storing multi-bit triggers, including first traversing all multi-bit triggers and inserting the position of each multi-bit trigger into the R-tree; Step S13: Collecting K neighbors; wherein the process of collecting K neighbors includes querying the R-tree to obtain the K nearest multi-bit triggers of the current multi-bit trigger, and then filtering the set of multi-bit triggers by retaining only the multi-bit triggers whose distance is less than a specified distance upper limit; Step S14: Then determine whether the number of neighbors of the current multi-bit trigger is 1. If so, the multi-bit trigger does not move; if not, set the multi-bit trigger bandwidth. Includes the following: h i =min(h max ,||x i -x i，M ||) where h i is the bandwidth of the i-th multi-bit trigger, h max is the maximum allowable displacement, ||x i -x i，M || is the distance from the trigger to the farthest neighbor; Step S15: Sort the neighbors by distance; after locating the neighbors of all multi-bit triggers, traverse all multi-bit triggers to perform displacement iteration.

3. The clustering method based on multi-bit triggers according to claim 2, characterized in that: Step S1 also includes the following: Step S16: Determine whether the current multi-bit trigger flag is immovable. If so, skip the current trigger. Otherwise, move the multi-bit trigger according to the following formula: Among them, t represents the current iteration number, j represents the multi-bit trigger traversed, and x i represents the initial position of the multi-bit trigger before it starts moving, y is the position of the trigger after moving, h is the maximum distance each trigger can move, d represents the current density construction of d-dimensional data, and function g is the gradient of the Gaussian kernel function; Step S17: According to the formula Determine whether the displacement is less than the threshold, where is the new position of the multi-bit flip-flop j, is the original position of the multi-bit flip-flop j, is the displacement of the multi-bit trigger j, δ is the threshold; Step S18: Further, if the displacement is less than the threshold, the multi-bit trigger is marked as completed, otherwise the displacement is continued to be calculated until the displacement of the multi-bit trigger j is less than the threshold; Step S19: When all multi-bit triggers have completed the contents of step S11 to step S18, each multi-bit trigger is traversed in order according to the coordinates and clustered in sequence.

4. The clustering method based on multi-bit triggers according to claim 3, characterized in that: Step S2 includes the following contents: Step S21: define each multi-bit trigger to belong to a corresponding clock network, where the clock network c k ∈C={c1,…,c M }; Define cluster set Γ={γ1,…,γ K }, where clustering Define cluster γ j The probability of being plundered is in Step S22: generating a probability based on the distance between each multi-bit trigger, including the following: Defining triggers The probability of being robbed based on distance is: Among them, μ s =centroid(γ s ) is the target cluster γ s The center of mass of the multi-bit trigger is d(·), d(·) is the Euclidean distance, σ is the strength of the control space correlation, is the average distance of the multi-bit trigger to the nearest multi-bit trigger, and α is the direct factor that controls the size of this probability, that is, the closer the trigger is, the greater the probability of being plundered; Step S23: For each multi-bit trigger that forms a cluster, γ y = {y}, and determine its nearest multi-bit trigger x∈γ x ; Based on the above probability, choose whether y will plunder x into its cluster y.

5. The clustering method based on multi-bit triggers according to claim 4, characterized in that: Step S2 also includes the following: Step S24: According to step S21, step S22 and step S32, a re-clustering process is implemented, including the following contents: S241: merging adjacent flip-flops of the same clock network based on a probability mechanism, including based on a defined probability of being plundered clusters and a probability generated based on distance, wherein a merging criterion includes merging if the probability generated based on distance is less than a threshold and the probability of being plundered clusters is less than a threshold; S242: Clustering and splitting based on the same clock network constraints, including the following: Perform in-place decomposition for hybrid clock network clusters, including the following: Among them, Γ refers to the set of all clusters, γ j represents a cluster in the set, Furthermore, define in Indicates that a cluster γ j Decompose into a set of k small clusters containing the same clock network; the coordinates of each cluster of simultaneous clock networks are determined by the centroid of all triggers belonging to the same network in the original cluster; Furthermore, the re-clustering centroid calculation formula is: in Is a new subcluster The coordinates of the center of mass, is the number of triggers in the subcluster, coord(f) is the coordinate of trigger f; S243: The same probabilistic mechanism re-merges adjacent triggers, including the following: The small clustering set is performed according to the re-clustering centroid calculation formula defined in step S242 The merge after splitting will optimize the new sub-cluster that appears in step S242 Further optimize area and timing.

6. The clustering method based on multi-bit triggers according to claim 5, characterized in that: Step S3 includes the following contents: Step S31: Define a multi-bit trigger f i The center coordinate is c i =(x i ,y i ), define the multi-bit trigger pin coordinates p i,k =(x i,k ,y i,k ), define the pin timing margin as S(p i,k ), connection direction vector Step S32: Generate a rectangle at the center of the multi-bit trigger, whose initial size is the minimum bounding box between the trigger pin and the connected fan-in / fan-out pins; the calculation formula of the rectangle is: Among them, w i is the width of the rectangle, h i is the height of the rectangle, p i,k is the pin coordinate, c i is the center coordinate of the multi-bit trigger, ||p i,k -c i || is the distance between the two, Represents the initial rectangle generated; Step S33: traverse the pins of each multi-bit trigger and adjust the size and coordinates of the rectangle according to the direction, distance and slack of the connected fan-out and fan-in pins. The calculation formula includes the following: When S(p i,k )<0, that is, when the margin is negative, the rectangular coordinates of each multi-bit trigger pin connected are moved in the direction of the displacement: Δr k =|S(p i,k )|·v i,k , where Δr k is the displacement of the multi-bit trigger, |S(p i,k )| is the time margin of the multi-bit trigger, v i,k is the direction vector of the multi-bit trigger; When S(p i,k )>0, that is, when the margin is positive, the size of the rectangle is extended in the opposite direction of the connected multi-bit trigger pin, and its size adjustment amount Includes the following: where Δw k is the change in the width of the rectangle, Δh k is the change in the height of the rectangle, S(p i,k ) is its time margin, β is the proportional factor, |v x | is the length of the vector in the x-axis direction, |v y |Vector is the length in the y-axis direction; Step S34: define the F region update function as: Where ⊕ means adjusting the size of the rectangle along the specified direction. the new coordinates of the rectangle's center, is the old coordinate of the center of the rectangle, Δr k is the rectangular displacement, is the new size of the rectangle, is the old size of the rectangle, Δw k is the change in the width of the rectangle, Δh k The change in the height of the rectangle is used to guide the size expansion or coordinate movement of the F region through the F region update function; Step S35: After the F region update function is obtained, since the original multi-bit trigger set is F={f1,…,f N }, the original cluster set is Γ={γ1,…,γ K }, where clustering Updated multi-bit flip-flop f i The F region is The intersection area set is I = {R i ∩R j |i≠j}; The intersection area is determined by the formula: Area(R a ∩R b )>0After calculating the F area of ​​each multi-bit trigger and its intersection area, traverse the intersection area in reverse order of area size, and divide these clusters into the cluster sets corresponding to the intersection area to ensure that they are placed in the area with optimal timing. Finally, check whether the original cluster point still has trigger allocation and falls in any intersection area. If so, retain the cluster.

7. The clustering method based on multi-bit triggers according to claim 6, characterized in that: Step S4 includes the following contents: Step S41: First, filter out incompatible multi-bit flip-flop clusters, including multi-bit flip-flops for which no matching one exists in the cell library of the specified bit size; Step S42: Split the incompatible multi-bit trigger clusters and sort them by position from smallest to largest bit number; Step S43: Design a cost function for regenerating a compatible multi-bit flip-flop cluster, wherein the cost function includes the following: Where x represents a candidate multi-bit flip-flop; HPWL represents the total semi-perimeter wire length, HPWL(n) represents the total semi-perimeter wire length of the network connected to x, and OriHPWL(n') represents the total semi-perimeter wire length connected to the original multi-bit flip-flop before clustering; Delay(x), Power(x), Area(x), Bit(x) represent the delay, power consumption, area, and number of bits of the multi-bit flip-flop x, while Delay(i), Power(i), Area(i), Bit(i) correspond to the delay, power consumption, area, and number of bits of each flip-flop in cluster c; α, β, γ, and δ represent the cost factors of wire length, power consumption, area, and number of bits, respectively.

8. The clustering method based on multi-bit triggers according to claim 7, characterized in that: Step S5 includes the following contents: Step S51: relocate the multi-bit trigger to optimize the timing condition of the pin, wherein a single multi-bit trigger f i The original coordinates are defined as Critical pins are defined as pins where the timing margin of each pin is less than a specified threshold, and the maximum allowed displacement is defined as D max , the original network minimum bounding box is defined as B net =[x min , x max ]×y min ,y max ]; Step S52: For each multi-bit flip-flop, check its key pins and obtain the bounding boxes formed by the fan-in and fan-out pins respectively; wherein the fan-in area bounding box calculation formula includes the following: The fan-out area bounding box calculation formula includes the following: in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates; in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates; in, Represents the minimum value of the input network bounding box coordinates, Indicates the minimum value of the output network bounding box coordinates; in, Indicates the maximum value of the input network bounding box coordinates, Indicates the maximum value of the output network bounding box coordinates; Step S53: When there is a valid fan-in bounding box, the center of the single multi-bit flip-flop is aligned to the nearest point of the box; otherwise, it is aligned to the nearest point of the fan-out box. The calculation formula is: The displacement from the original position does not exceed the maximum allowable displacement distance, that is, Step S54: While moving, ensure that the multi-bit trigger does not exceed the minimum bounding box area of ​​the original network; if the signal delay of the multi-bit trigger is not reduced after repositioning, the multi-bit trigger will be restored to its original position.

9. A clustering system based on a multi-bit trigger, comprising an electronic device, wherein the electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the processor implements the clustering method based on multi-bit triggers as described in any one of claims 1 to 8.

10. A clustering system based on a multi-bit trigger, comprising a computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the computer program implements a clustering method based on multi-bit triggers as claimed in any one of claims 1 to 8.

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