PCB layout design verification method, system, device and medium

Abstract

This invention relates to the field of PCB layout design technology, specifically providing a PCB layout design verification method, system, device, and medium, comprising: extracting design intent from design requirement text using natural language processing technology; querying design constraint parameters from a pre-constructed knowledge graph based on the design intent; generating dynamic verification rules according to the design constraint parameters; applying the dynamic verification rules using a rule engine to verify the design parameters in the PCB layout, and outputting the verification results. This invention improves verification efficiency and reduces the rework rate caused by missing constraints.

Description

Technical Field

[0001] This invention belongs to the field of layout design technology, specifically relating to a PCB layout design verification method, system, device, and medium. Background Technology

[0002] In the PCB design field, traditional verification methods heavily rely on designers manually interpreting requirements documents and configuring EDA tool rules, resulting in significant efficiency bottlenecks and error risks. With the increasing complexity of high-speed circuits, the electrical constraints, physical rules, and manufacturing requirements implicit in design requirements are growing exponentially, making it easy to miss key parameters (such as impedance tolerance and equal-length matching tolerance) during manual extraction. While existing automated verification systems can perform basic DRC checks, they lack a deep understanding of the design intent described in natural language, and their static rule bases cannot dynamically adapt to changing process constraints and manufacturer capabilities. Especially in high-density interconnect board design, the rework rate due to incomplete constraint extraction or rule conflicts can reach as high as 34%. Therefore, a technical solution integrating semantic parsing and dynamic rule generation is urgently needed to achieve closed-loop optimization across the entire process from design requirements to verification execution. Summary of the Invention

[0003] In view of the above-mentioned shortcomings of the prior art, the present invention provides a PCB layout design verification method, system, device and medium to solve the above-mentioned technical problems.

[0004] In a first aspect, the present invention provides a PCB layout design verification method, comprising:

[0005] Utilize natural language processing technology to extract design intent from design requirement texts;

[0006] Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph;

[0007] Dynamic verification rules are generated based on the design constraint parameters;

[0008] The dynamic verification rules are applied using the rule engine to verify the design parameters in the PCB layout and output the verification results.

[0009] In an optional implementation, the method further includes:

[0010] A multimodal input interface is constructed, which supports mixed Chinese and English text input and input of annotation text and graphic markers.

[0011] In an optional implementation, based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including:

[0012] Modal processing is performed on the intermediate representation output by the multimodal interface, which includes word segmentation of text data and feature extraction of image annotation data;

[0013] A PCB-specific dictionary is introduced, which includes several core terms. A term weighting enhancement mechanism is used to improve the priority of professional terms in semantic recognition.

[0014] Based on the dictionary, a parse tree is constructed from the modal processing results of dependency parsing to identify subject-verb-object and attributive-adverb-complement grammatical structures; ternary relations are extracted from the parse tree, and the ternary relations include constraint object, constraint type, and constraint value.

[0015] In an optional implementation, based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including:

[0016] Based on the constraint objects and constraint types in the ternary relation, the corresponding standard constraint values ​​and the associated triples of the ternary relation are queried from the pre-built knowledge graph;

[0017] Verify the rationality of the constraint values ​​in the ternary relation based on the standard constraint values ​​found in the query;

[0018] Design constraint parameters will be generated based on the verified ternary relationships and associated triples.

[0019] In an optional implementation, the method further includes:

[0020] The design requirement text is processed using the BERT-base model, which contains a 12-layer Transformer encoder and outputs a 768-dimensional general semantic feature vector.

[0021] Domain feature mapping is achieved by injecting PCB knowledge graph, and the weight allocation of domain-specific associations is strengthened by relational attention mechanism. The knowledge graph contains at least 5,000 entities and 8,000 relations, covering components, signal types and process parameters.

[0022] The classifier and regressor are connected in parallel to identify the constraint type and extract the constraint parameters. The output of the constraint type identification includes three main categories: electrical, physical and manufacturing, and their subcategories. After extracting the constraint parameters, the output is a triplet of target value, tolerance range and applicable object.

[0023] In an optional implementation, generating dynamic verification rules based on the design constraint parameters includes:

[0024] Construct a manufacturability index matrix, which includes the following dimensions:

[0025] The index categories cover geometric parameters, electrical parameters, and process parameters. Geometric parameters include line width, line spacing, and aperture; electrical parameters include impedance tolerance and current carrying capacity; and process parameters include minimum pad spacing and solder mask bridge width.

[0026] The calculation formula is a quantitative model built based on physical principles and process characteristics;

[0027] Design values ​​are the initial constraint values ​​extracted from the design intent identification results.

[0028] Manufacturer capabilities, specifically the process limits retrieved from the manufacturing knowledge base;

[0029] Safety margin, a percentage factor set according to the product reliability level;

[0030] Compare the design value with the manufacturer's capability; mark the design value as an infeasible constraint when it exceeds the manufacturer's capability.

[0031] For infeasible constraints, the adjustment value is calculated based on the safety margin model: Adjustment value = Vendor capability × (1 + Safety margin);

[0032] If the adjusted value does not exceed the manufacturer's capacity limit, the original design value is replaced; otherwise, a negotiation request is generated, and the final design value is negotiated through a priority-based conflict resolution mechanism.

[0033] If the design value does not exceed the manufacturer's energy capacity, the original design value is retained.

[0034] In an optional implementation, the final design value is negotiated through a priority-based conflict resolution mechanism, including:

[0035] The constraint rules are divided into three levels according to their importance: safety-related rules are high priority, function-related rules are medium priority, and process-related rules are low priority.

[0036] For conflicting rules RuleA and RuleB, if RuleA has a higher priority than RuleB, then RuleA is retained; if RuleB has a higher priority than RuleA, then RuleB is retained; if the priorities are the same, then the rules are merged and the intersection of the parameters is taken.

[0037] Secondly, the present invention provides a PCB layout design verification system, comprising:

[0038] The intent extraction module is used to extract design intent from design requirement texts using natural language processing technology.

[0039] The constraint query module is used to query design constraint parameters from a pre-built knowledge graph based on the design intent;

[0040] The rule generation module is used to generate dynamic verification rules based on the design constraint parameters;

[0041] The verification execution module is used to apply the dynamic verification rules through the rule engine to verify the design parameters in the PCB layout and output the verification results.

[0042] Thirdly, a device is provided, comprising:

[0043] Memory, used to store PCB layout design verification programs;

[0044] A processor is configured to implement the steps of the PCB layout design verification method as provided in the first aspect when executing the PCB layout design verification program.

[0045] Fourthly, a computer-readable medium is provided, on which a PCB layout design verification program is stored, wherein when the PCB layout design verification program is executed by a processor, the steps of the PCB layout design verification method provided in the first aspect are implemented.

[0046] The beneficial effects of this invention are that the PCB layout design verification method, system, equipment, and medium provided by this invention significantly improve the accuracy and completeness of design intent extraction through the synergistic effect of natural language processing and knowledge graphs, avoiding constraint omissions (such as impedance tolerance and equal length matching deviations) caused by manual interpretation. The dynamic verification rule engine breaks through the limitations of traditional static rule bases, adapting in real time to changes in manufacturer process capabilities and resolving rule conflicts in high-density interconnect designs. Actual testing shows that in high-speed PCB designs with 6 or more layers, verification efficiency is improved by 60%, and the rework rate due to missing constraints is reduced by 34%. Simultaneously, the structured verification result output accelerates the design iteration loop. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention.

[0049] Figure 2 This is a schematic block diagram of a system according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the structure of a device provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0053] The PCB layout design verification method provided in this embodiment of the invention is executed by a computer device, and correspondingly, the PCB layout design verification system runs in the computer device.

[0054] Figure 1 This is a schematic flowchart illustrating a method according to an embodiment of the present invention. Wherein, Figure 1 The executing entity can be a PCB layout design verification system. Depending on different requirements, the order of the steps in this flowchart can be changed, and some steps can be omitted.

[0055] like Figure 1 As shown, the method includes:

[0056] S1. Use natural language processing technology to extract design intent from design requirement text;

[0057] S2. Based on the design intent, query the design constraint parameters from the pre-built knowledge graph;

[0058] S3. Generate dynamic verification rules based on the design constraint parameters;

[0059] S4. Using the rule engine, apply the dynamic verification rules to verify the design parameters in the PCB layout and output the verification results.

[0060] In one embodiment of the present invention, based on step S1, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0061] First, a multimodal input interface is constructed, which supports mixed Chinese and English text input and input of annotation text and graphic markers.

[0062] The multimodal input interface is designed to break the limitations of a single input format, adapt to the expression habits of designers in different design scenarios, and improve the flexibility and convenience of inputting design requirements. This interface primarily supports two core formats: mixed Chinese and English text input, and annotation text and graphic markup input.

[0063] For mixed Chinese and English text input, the interface employs a Unicode-based character set processing mechanism, simultaneously supporting multiple character formats including Simplified Chinese, Traditional Chinese, and English. To address potential semantic ambiguity in mixed Chinese and English input, the interface integrates a bilingual semantic alignment model. This model, trained on a large corpus of parallel Chinese and English texts, accurately identifies the correspondence between Chinese and English words in the input text, thereby improving the accuracy of semantic understanding. For example, when inputting mixed Chinese and English text such as "the impedance of the USB differential line needs to be controlled at 90Ω±10%", the interface can accurately understand the relationship between "USB differential line" and "impedance control," as well as the specific numerical range expressed by "90Ω±10%".

[0064] For inputting annotation text and graphic markers, the interface employs a combined approach of image recognition and text extraction. For images containing annotation text, the text region is first located using a deep learning-based object detection algorithm (such as YOLOv5), and then the annotation text is extracted from the text region using optical character recognition (OCR) technology (such as Tesseract). Simultaneously, for graphic markers, the interface uses computer vision algorithms such as edge detection and contour extraction to identify the shape, size, and position of the graphic, and associates this information with the extracted annotation text. For example, in a PCB design drawing containing conductor width markings, the interface can accurately identify the graphic outline of the marked conductor, extract the adjacent "4mil" annotation text, and establish a correspondence between the two, thereby understanding the conductor width constraint requirements.

[0065] S101. Perform modal processing on the intermediate representation output by the multimodal interface, wherein the modal processing includes word segmentation of text data and feature extraction of image annotation data.

[0066] Modal processing is a process of selectively processing the intermediate representation output from a multimodal interface, with the aim of providing high-quality input data for subsequent semantic analysis. This process mainly includes word segmentation of text data and feature extraction from image annotation data.

[0067] In terms of word segmentation of text data, for Chinese text, a word segmentation model combining bidirectional long short-term memory network (BiLSTM) and conditional random field (CRF) is adopted. Through the training of a large number of Chinese word segmentation corpora, this model can accurately identify word boundaries in Chinese text and solve common ambiguity problems in Chinese word segmentation (such as multiple word segmentation methods for "It's raining. Do you want to stay? I don't mind staying or leaving"). For English text, a basic word segmentation method based on spaces and punctuation marks is adopted, and combined with stemming technology (such as the Porter stemming algorithm), to restore English words to their stem forms, reduce the variant forms of vocabulary, and improve the efficiency of subsequent processing. For example, for the English text "impedancecontrolisrequiredforthehigh-speedsignals", after word segmentation, we get "impedance", "control", "is", "required", "for", "the", "high-speed", "signals", and after stemming, "required" is restored to "require".

[0068] For feature extraction of image annotation data, a convolutional neural network (CNN) is adopted as the basic model. First, the image annotation data is standardized, uniformly adjusted to a fixed size (such as 224×224 pixels), and grayscaled and normalized to eliminate the influence of image size and brightness differences on feature extraction. Then, a pre-trained CNN model (such as VGG16) is used to extract features from the processed image. Through the alternating action of multiple convolutional layers and pooling layers, this model can extract local and global features in the image. For example, for a graphic marker representing the wire spacing, the CNN model can extract edge features of the wire, size features of the spacing, etc., and these features will provide important bases for subsequent semantic association.

[0069] S102. Introduce a PCB professional field dictionary, which includes multiple core terms, and enhance the priority of professional vocabulary in semantic recognition through a term weight enhancement mechanism.

[0070] The introduction of the PCB professional field dictionary is a key step to improve the accuracy of semantic recognition. This dictionary contains a large number of core terms related to PCB design, covering multiple aspects such as electrical parameters, physical constraints, and process requirements. Through the term weight enhancement mechanism, the priority of these professional vocabulary in semantic recognition can be enhanced, enabling the system to pay more attention to the key information in design requirements.

[0071] The dictionary was built using a semi-automated approach. First, keywords were extracted from a large amount of textual data, including PCB design documents, technical manuals, and standards (using algorithms such as TF-IDF and TextRank), to initially identify potential technical terms. Then, domain experts reviewed and revised these terms, removing irrelevant terms, adding missing terms, and accurately defining and classifying each term. Currently, the dictionary contains over 3200 core terms, such as "impedance," "differential line," "minimum trace width," and "pad."

[0072] The terminology weighting enhancement mechanism determines the weight value of each term based on its importance and frequency in the PCB design field. Terms that frequently appear in design requirements and have a significant impact on the design results (such as "impedance control" and "signal integrity") are assigned higher weight values; while less important or generic terms are assigned lower weight values. During semantic recognition, the system adjusts its focus on different terms based on their weight values; terms with higher weight values ​​have a greater influence on semantic analysis. For example, when both "impedance" and "wire" appear in the input text, the system will prioritize the constraint information related to "impedance" because it has a higher weight value.

[0073] S103. Based on the dictionary, construct a syntax parse tree based on the modal processing results of dependency parsing, and identify subject-verb-object and attributive-adverb-complement grammatical structures; extract ternary relations from the syntax parse tree, wherein the ternary relations include constraint object, constraint type, and constraint value.

[0074] Dependency parsing employs a graph-based dependency parsing algorithm. This algorithm treats each word in a sentence as a node, calculates the dependency probabilities between words, constructs a dependency relationship network, and thus determines the sentence's grammatical structure. During the construction of the parse tree, the system references terminology information from a PCB-specific dictionary, specially marking and processing technical terms to improve the accuracy of grammatical structure recognition. For example, for the sentence "USB differential lines require 90Ω±10% impedance control," dependency parsing identifies "USB differential lines" as the subject (constraint object), "requires" as the predicate, "impedance control" as the object (constraint type), and "90Ω±10%" as the modifier (constraint value), thereby constructing a clear parse tree.

[0075] When extracting ternary relations from the parse tree, the system employs a combination of rule-based and machine learning methods. First, based on a pre-defined rule template, potential ternary relations are initially extracted from the parse tree. For example, when a grammatical structure of "subject + verb + object + modifier" is identified, the subject is attempted as the constraint object, the object as the constraint type, and the modifier as the constraint value. Then, a machine learning classifier (such as Support Vector Machine, SVM) is used to verify and correct the initially extracted ternary relations, removing erroneous ternary relations and supplementing any missing ones. This method accurately extracts constraint information from design requirements; for example, extracting a ternary relation like (USB differential line, impedance control, 90Ω±10%) from the example above provides structured data support for subsequent constraint generation.

[0076] In one embodiment of the present invention, based on step S2, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0077] S201. Based on the constraint objects and constraint types in the ternary relation, query the corresponding standard constraint values ​​and the associated triples of the ternary relation from the pre-constructed knowledge graph.

[0078] Based on the constraint objects (such as "USB differential line") and constraint types (such as "impedance control") extracted from ternary relations, the system achieves related information retrieval with the help of a pre-built PCB domain knowledge graph. This knowledge graph adopts a semantic network model and constructs a domain knowledge system covering design, process, and electrical performance through a triple structure of entities, relations, and attributes.

[0079] The core components of the knowledge graph consist of three layers: the entity layer covers more than 800 types of PCB design-related entities, such as components, signal networks, and physical parameters. Each entity is assigned a unique identifier and attribute set. For example, "USB differential line" includes more than 20 attributes such as characteristic impedance, transmission rate, and line width range; the relationship layer defines more than 150 types of relationships between entities, including subordinate relationships (such as "USB differential line belongs to high-speed signal network"), constraint relationships (such as "impedance control depends on line width and dielectric thickness"), and influence relationships (such as "increased dielectric constant will reduce characteristic impedance"); and the rule layer stores more than 1,000 domain rules, which describe the constraint rules between parameters in the form of logical propositions, such as "when the signal frequency exceeds 1GHz, impedance control must be performed".

[0080] The query process employs a bidirectional reasoning strategy: forward reasoning starts with the constraint object and type, extracting directly related standard constraint values ​​through semantic query language, such as obtaining the standard value "90Ω±10%" from the association between "USB differential line" and "impedance control"; backward reasoning utilizes a rule engine to mine implicitly related triples, for example, deriving auxiliary constraints such as "line width not less than 8mil" and "medium thickness of 4mil" from "impedance control". To improve query efficiency, the knowledge graph adopts a distributed indexing architecture, storing entities in partitions according to domain categories, keeping the query response time for millions of triples within 200 milliseconds.

[0081] S202. Verify the rationality of the constraint values ​​in the ternary relation based on the standard constraint values ​​found in the query.

[0082] For the constraint values ​​in the ternary relationship, the system implements multi-dimensional rationality verification through a three-level verification architecture to ensure that they comply with design specifications and manufacturing feasibility.

[0083] Basic threshold verification is the first step in the validation process. A preliminary judgment is made by calculating the deviation rate between the user-input constraint value and the standard constraint value obtained from the knowledge graph query. The deviation rate calculation formula is: Deviation Rate = |User Value - Standard Value| / Standard Tolerance Range × 100%. Based on the deviation rate, three intervals are defined: Deviation Rate ≤ 30% is the safe zone, directly judged as reasonable; 30% < Deviation Rate ≤ 80% is the warning zone, marked as "Needs Attention"; Deviation Rate > 80% is the danger zone, initially judged as unreasonable.

[0084] Context consistency verification is used to validate the fit between constraint values ​​and the design context. The system analyzes the design scenario in which the constraint values ​​are located by combining the associated triplet. For example, when the user inputs "USB differential line impedance = 75Ω" (standard value is 90Ω), if the associated triplet contains the constraint "transmission rate = 1.5Gbps" (USB 2.0 low speed mode), the deviation rate weight is adjusted appropriately to avoid misjudgment due to special scenarios.

[0085] Manufacturing feasibility verification verifies whether the constraint values ​​are within the actual production capacity range by calling the manufacturer's capability database interface. The system matches the corresponding manufacturer's process parameters, such as minimum linewidth and impedance control accuracy, based on the design requirements, and calculates whether the constraint values ​​are within the manufacturer's safe range (considering a 20% safety margin). For example, if the manufacturer's minimum linewidth capability is 3 mil, and the user-input linewidth constraint value is 2.5 mil, then it is determined to be infeasible.

[0086] The verification results are presented as confidence scores (0-100 points), and are calculated by weighting the results of the three levels of verification. The basic threshold accounts for 60%, context consistency accounts for 25%, and manufacturing feasibility accounts for 15%, which provides a quantitative basis for the subsequent generation of constraint parameters.

[0087] S203. Design constraint parameters will be generated based on the verified ternary relationships and associated triples.

[0088] The validated ternary relations and association triples are transformed into a structured set of design constraint parameters through a multi-source information fusion strategy, realizing the transformation from semantic information to executable rules.

[0089] The parameter structuring adopts a semantically enhanced description format, including core fields such as constraint identifier, target object, parameter type, nominal value, tolerance range, and confidence score, along with associated constraint information. For example, the constraint parameter set for "USB differential line impedance control" not only includes the main constraint "90Ω±10%" but also incorporates associated constraints such as "line width 8mil" and "spacing 6mil," and clearly indicates the source of each parameter (such as knowledge graph query results or inference generation).

[0090] Constraint fusion is achieved by constructing a constraint dependency graph, with primary constraints (such as impedance) as root nodes and related constraints (such as linewidth and dielectric thickness) as child nodes. The mutual information entropy between nodes is calculated to determine the weight coefficients, and child nodes with a weight greater than 0.6 are included in the final constraint set. This mechanism ensures the completeness and correlation of constraint parameters, avoiding design defects caused by the omission of a single parameter.

[0091] To achieve end-to-end traceability, the generated constraint parameters are accompanied by complete traceability information, including the original input ID, knowledge graph query logs, verification process records, and generation timestamps. This information is stored in blockchain format to ensure the immutability of the constraint parameters and meet the compliance requirements of high-end fields such as aerospace.

[0092] The generated constraint parameter set can be directly imported into mainstream EDA tools (such as Allegro and PADS), achieving seamless integration of design constraints through standardized interfaces. Testing showed a 98.7% import success rate and an average conversion time of less than 1.2 seconds, significantly improving the deployment efficiency of design constraints.

[0093] In one embodiment of the present invention, based on step S3, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0094] S301. Construct a manufacturability index matrix, the matrix comprising the following dimensions:

[0095] The index categories cover geometric parameters, electrical parameters, and process parameters. Geometric parameters include line width, line spacing, and aperture; electrical parameters include impedance tolerance and current carrying capacity; and process parameters include minimum pad spacing and solder mask bridge width.

[0096] The calculation formula is a quantitative model built based on physical principles and process characteristics;

[0097] Design values ​​are the initial constraint values ​​extracted from the design intent identification results.

[0098] Manufacturer capabilities, specifically the process limits retrieved from the manufacturing knowledge base;

[0099] Safety margin, a percentage factor set according to the product reliability level;

[0100] S302. Compare the design value with the manufacturer's capability. When the design value exceeds the manufacturer's capability, mark it as an infeasible constraint.

[0101] S303. For infeasible constraints, calculate the adjustment value based on the safety margin model: Adjustment value = Vendor capability × (1 + Safety margin);

[0102] S304. If the adjusted value does not exceed the manufacturer's capability limit, the original design value is replaced; otherwise, a negotiation request is generated, and the final design value is negotiated through a priority-based conflict resolution mechanism.

[0103] The constraint rules are divided into three levels according to their importance: safety-related rules are high priority, function-related rules are medium priority, and process-related rules are low priority.

[0104] For conflicting rules RuleA and RuleB, if RuleA has a higher priority than RuleB, then RuleA is retained; if RuleB has a higher priority than RuleA, then RuleB is retained; if the priorities are the same, then the rules are merged and the intersection of the parameters is taken.

[0105] S305. If the design value does not exceed the manufacturer's feasible energy constraints, the original design value shall be retained.

[0106] For example, the minimum linewidth calculation for a consumer-grade product: the calculated current carrying capacity is 2.5 mil, the etching compensation is 1 mil, so the initial design value = 3.5 mil; the manufacturer's minimum linewidth capability is 3 mil, with a safety margin of 20%, then the final constraint value = 3 mil × (1 - 20%) = 2.4 mil. Since the design value 3.5 mil > 2.4 mil, 3.5 mil is taken as the final constraint. This matrix achieves dynamic matching between design requirements and manufacturing capabilities through quantitative analysis, significantly reducing the number of design iterations.

[0107] S306. Convert the adjusted constraints into a DRC format (such as Allegro's ".drf" file) that can be recognized by EDA tools, including information such as rule type (Width, Spacing), applicable objects (nets, layers), and threshold range.

[0108] In one example, the dynamic rule generation process includes:

[0109] The designer input a temporary constraint via natural language: "Critical signals need a spacing of 20 mils."

[0110] NLP engine real-time parsing: Extracting constraint elements {"spacing":{"nets":["CLK",""],"value":20}} through semantic understanding architecture ("" represents all other networks).

[0111] Feasibility verification: The rule base calls the current stackup data (e.g., the surface layer is 1oz copper, FR4 material) and queries the manufacturer's minimum pitch capability for this layer to find that it is 18mil.

[0112] Feedback and rule generation: The GUI displays the verification results in real time ("The current layer allows a minimum of 18mil, and 20mil meets the requirements"), and generates temporary spacing rules, which are then added to the DRC rule set.

[0113] In one embodiment of the present invention, based on step S4, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0114] The dynamic verification rules are applied using the rule engine to verify the design parameters in the PCB layout and output the verification results.

[0115] The application process of dynamic verification rules in PCB layout parameter verification is reflected in a closed-loop process of "parameter extraction - rule matching - logic execution - result feedback".

[0116] During the parameter extraction phase, the original parameters of the layout design are obtained in real time through the CAD interface, including geometric parameters (line width, spacing, aperture, etc.), electrical parameters (impedance value, signal frequency, voltage level, etc.), and physical parameters (dielectric thickness, copper foil thickness, etc.). To ensure parameter accuracy, the system adopts a "real-time sampling + cache update" mechanism: high-frequency sampling (10 times / second) is performed on dynamically modified areas (such as the network segment being wired by the designer), while an incremental update strategy is used for static areas (sampling is triggered only when parameters change), which reduces system resource consumption and ensures the real-time nature of verification.

[0117] The rule matching stage is achieved through precise mapping between parameter characteristics and rule conditions. For example, for the "high-speed differential line impedance verification rule," the system first extracts parameters such as the linewidth (W), spacing (S), and dielectric thickness (H) of the differential line pair. Then, it matches the conditional expression "when the frequency > 1 GHz, the characteristic impedance should meet 90Ω ± 10%" in the rule base. The system then verifies the deviation between the actual impedance value and the constraint range using an impedance calculation model (e.g., based on the microstrip line formula Z = 87 / √(εr + 1.41) × ln(5.98H / (0.8W + S))). For rules containing fuzzy conditions (e.g., "sufficient heat dissipation space should be reserved around high-power devices"), the system introduces fuzzy logic reasoning to quantify "sufficient space" as "no metal obstruction within a radius of 1.5 times the device package size," achieving quantitative verification of qualitative rules.

[0118] During the logic execution phase, corresponding verification actions are triggered based on the rule matching results, including compliance determination (e.g., "pass / fail"), deviation calculation (e.g., "the deviation rate between the actual line width of 2.5mil and the constraint value of 3mil is 16.7%), and auxiliary suggestion generation (e.g., "adjust the line width to 3.2mil to meet the safety margin"). For related parameter verification (e.g., "the aspect ratio of aperture to plate thickness ≤ 8:1"), the execution engine supports multi-parameter joint calculation, and achieves collaborative verification of cross-type parameters by constructing a parameter relationship model (e.g., aspect ratio = plate thickness / aperture).

[0119] The results feedback phase employs a tiered alert mechanism: minor deviations (e.g., deviation rate < 5%) are only logged; moderate deviations (5% ≤ deviation rate < 15%) trigger a yellow alert and provide optimization suggestions; severe deviations (deviation rate ≥ 15%) trigger a red alert and suspend the design tool's save operation, forcing designers to make corrections. Simultaneously, the system supports retrospective querying of verification results, enabling end-to-end traceability of "design parameters - verification rules - result records" by associating design version numbers with rule version numbers, facilitating design review and problem localization.

[0120] Based on the above embodiments, in order to further improve the semantic recognition accuracy of the method provided in the above embodiments, and as an implementable approach, the following semantic recognition method is used to directly extract constraint parameters from the design requirement text.

[0121] The design requirement text is processed using the BERT-base model, which contains a 12-layer Transformer encoder and outputs a 768-dimensional general semantic feature vector.

[0122] Domain feature mapping is achieved by injecting PCB knowledge graph, and the weight allocation of domain-specific associations is strengthened by relational attention mechanism. The knowledge graph contains at least 5,000 entities and 8,000 relations, covering components, signal types and process parameters.

[0123] The classifier and regressor are connected in parallel to identify the constraint type and extract the constraint parameters. The output of the constraint type identification includes three main categories: electrical, physical and manufacturing, and their subcategories. After extracting the constraint parameters, the output is a triplet of target value, tolerance range and applicable object.

[0124] In some embodiments, the PCB layout design verification system may include multiple functional modules composed of computer program segments. The computer programs for each program segment in the PCB layout design verification system may be stored in the memory of a computer device and executed by at least one processor to perform (see details). Figure 1 (Description) Function for PCB layout design verification.

[0125] In this embodiment, the PCB layout design verification system can be divided into multiple functional modules based on its functions, such as... Figure 2 As shown. The module referred to in this invention is a series of computer program segments that can be executed by at least one processor and perform a fixed function, and is stored in memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0126] The intent extraction module is used to extract design intent from design requirement texts using natural language processing technology.

[0127] The constraint query module is used to query design constraint parameters from a pre-built knowledge graph based on the design intent;

[0128] The rule generation module is used to generate dynamic verification rules based on the design constraint parameters;

[0129] The verification execution module is used to apply the dynamic verification rules through the rule engine to verify the design parameters in the PCB layout and output the verification results.

[0130] Figure 3The PCB layout design verification method provided in the embodiments of this application can be applied to devices. Those skilled in the art will understand that the device structures involved in the embodiments of this invention do not constitute a limitation on the device. A device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, the device includes, but is not limited to, laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0131] The device 300 may include a processor 310, a memory 320, and a communication unit 330. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figure does not constitute a limitation of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0132] The memory 320 can be used to store execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the device 300 is able to perform some or all of the steps in the above method embodiments.

[0133] The processor 310 serves as the control center of the storage device, connecting various parts of the electronic device via various interfaces and lines. It executes software programs and / or modules stored in the memory 320, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 310 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0134] The communication unit 330 is used to establish a communication channel, enabling the storage device to communicate with other devices. It can receive user data sent by other devices or send user data to other devices.

[0135] The present invention also provides a computer medium, wherein the computer medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0136] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a medium such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other medium capable of storing program code. It includes several instructions to cause a computer device (which may be a personal computer, a server, or a second device, network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0137] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0138] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0139] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0140] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0141] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A PCB layout design verification method, characterized in that, include: Utilize natural language processing technology to extract design intent from design requirement texts; Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph; Dynamic verification rules are generated based on the design constraint parameters; The dynamic verification rules are applied using the rule engine to verify the design parameters in the PCB layout and output the verification results. Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including: Modal processing is performed on the intermediate representation output by the multimodal interface, which includes word segmentation of text data and feature extraction of image annotation data; A PCB-specific dictionary is introduced, which includes several core terms. A term weighting enhancement mechanism is used to improve the priority of professional terms in semantic recognition. Based on the dictionary, a parse tree is constructed using the modal processing results of dependency parsing to identify subject-verb-object and attributive-adverbial-complement grammatical structures; ternary relations are extracted from the parse tree, and the ternary relations include constraint object, constraint type, and constraint value. Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including: Based on the constraint objects and constraint types in the ternary relation, the corresponding standard constraint values ​​and the associated triples of the ternary relation are queried from the pre-built knowledge graph; Verify the rationality of the constraint values ​​in the ternary relation based on the standard constraint values ​​found in the query; Design constraint parameters will be generated based on the verified ternary relationships and associated triples; Also includes: The design requirement text is processed using the BERT-base model, which contains a 12-layer Transformer encoder and outputs a 768-dimensional general semantic feature vector. Domain feature mapping is achieved by injecting PCB knowledge graph, and the weight allocation of domain-specific associations is strengthened by relational attention mechanism. The knowledge graph contains at least 5,000 entities and 8,000 relations, covering components, signal types and process parameters. The system utilizes a parallel-connected classifier and regressor to identify constraint types and extract constraint parameters. The output of constraint type identification includes three main categories: electrical, physical, and manufacturing, along with their respective subcategories. After extracting constraint parameters, the system outputs a triplet containing the target value, tolerance range, and applicable objects. Generate dynamic verification rules based on the design constraint parameters, including: Construct a manufacturability index matrix, which includes the following dimensions: The index categories cover geometric parameters, electrical parameters, and process parameters. Geometric parameters include line width, line spacing, and aperture; electrical parameters include impedance tolerance and current carrying capacity; and process parameters include minimum pad spacing and solder mask bridge width. The calculation formula is a quantitative model built based on physical principles and process characteristics; Design values ​​are the initial constraint values ​​extracted from the design intent identification results. Manufacturer capabilities, specifically the process limits retrieved from the manufacturing knowledge base; Safety margin, a percentage factor set according to the product reliability level; Compare the design value with the manufacturer's capability; mark the design value as an infeasible constraint when it exceeds the manufacturer's capability. For infeasible constraints, the adjustment value is calculated based on the safety margin model: Adjustment value = Vendor capability × (1 + Safety margin); If the adjusted value does not exceed the manufacturer's capacity limit, the original design value is replaced; otherwise, a negotiation request is generated, and the final design value is negotiated through a priority-based conflict resolution mechanism. For feasible constraints where the design values ​​do not exceed the manufacturer's capabilities, the original design values ​​should be retained.

2. The method according to claim 1, characterized in that, The method further includes: A multimodal input interface is constructed, which supports mixed Chinese and English text input and input of annotation text and graphic markers.

3. The method according to claim 1, characterized in that, The final design value is negotiated through a priority-based conflict resolution mechanism, including: The constraint rules are divided into three levels according to their importance: safety-related rules are high priority, function-related rules are medium priority, and process-related rules are low priority. For conflicting rules RuleA and RuleB, if RuleA has a higher priority than RuleB, then RuleA is retained; if RuleB has a higher priority than RuleA, then RuleB is retained; if the priorities are the same, then the rules are merged and the intersection of their parameters is taken.

4. A PCB layout design verification system, characterized in that, include: The intent extraction module is used to extract design intent from design requirement texts using natural language processing technology. The constraint query module is used to query design constraint parameters from a pre-built knowledge graph based on the design intent; The rule generation module is used to generate dynamic verification rules based on the design constraint parameters; The verification execution module is used to apply the dynamic verification rules through the rule engine to verify the design parameters in the PCB layout and output the verification results. Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including: Modal processing is performed on the intermediate representation output by the multimodal interface, which includes word segmentation of text data and feature extraction of image annotation data; A PCB-specific dictionary is introduced, which includes several core terms. A term weighting enhancement mechanism is used to improve the priority of professional terms in semantic recognition. Based on the dictionary, a parse tree is constructed using the modal processing results of dependency parsing to identify subject-verb-object and attributive-adverbial-complement grammatical structures; ternary relations are extracted from the parse tree, and the ternary relations include constraint object, constraint type, and constraint value. Based on the design intent, design constraint parameters are queried from a pre-built knowledge graph, including: Based on the constraint objects and constraint types in the ternary relation, the corresponding standard constraint values ​​and the associated triples of the ternary relation are queried from the pre-built knowledge graph; Verify the rationality of the constraint values ​​in the ternary relation based on the standard constraint values ​​found in the query; Design constraint parameters will be generated based on the verified ternary relationships and associated triples; Also includes: The design requirement text is processed using the BERT-base model, which contains a 12-layer Transformer encoder and outputs a 768-dimensional general semantic feature vector. Domain feature mapping is achieved by injecting PCB knowledge graph, and the weight allocation of domain-specific associations is strengthened by relational attention mechanism. The knowledge graph contains at least 5,000 entities and 8,000 relations, covering components, signal types and process parameters. The system utilizes a parallel-connected classifier and regressor to identify constraint types and extract constraint parameters. The output of constraint type identification includes three main categories: electrical, physical, and manufacturing, along with their respective subcategories. After extracting constraint parameters, the system outputs a triplet containing the target value, tolerance range, and applicable objects. Generate dynamic verification rules based on the design constraint parameters, including: Construct a manufacturability index matrix, which includes the following dimensions: The index categories cover geometric parameters, electrical parameters, and process parameters. Geometric parameters include line width, line spacing, and aperture; electrical parameters include impedance tolerance and current carrying capacity; and process parameters include minimum pad spacing and solder mask bridge width. The calculation formula is a quantitative model built based on physical principles and process characteristics; Design values ​​are the initial constraint values ​​extracted from the design intent identification results. Manufacturer capabilities, specifically the process limits retrieved from the manufacturing knowledge base; Safety margin, a percentage factor set according to the product reliability level; Compare the design value with the manufacturer's capability; mark the design value as an infeasible constraint when it exceeds the manufacturer's capability. For infeasible constraints, the adjustment value is calculated based on the safety margin model: Adjustment value = Vendor capability × (1 + Safety margin); If the adjusted value does not exceed the manufacturer's capacity limit, the original design value is replaced; otherwise, a negotiation request is generated, and the final design value is negotiated through a priority-based conflict resolution mechanism. For feasible constraints where the design values ​​do not exceed the manufacturer's capabilities, the original design values ​​should be retained.

5. A PCB layout design verification device, characterized in that, include: Memory, used to store PCB layout design verification programs; A processor is configured to implement the steps of the PCB layout design verification method as described in any one of claims 1-3 when executing the PCB layout design verification program.

6. A computer-readable medium storing a computer program, characterized in that, The readable medium stores a PCB layout design verification program, which, when executed by a processor, implements the steps of the PCB layout design verification method as described in any one of claims 1-3.

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