Selector-only memory and memory system

Abstract

The invention provides a selector-only memory and a memory system. The selector-only memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array; the memory cell array includes a plurality of memory cells, and the peripheral circuit is configured to apply a read pulse to a conductive line coupled to a target memory cell of the plurality of memory cells to perform a read operation on the target memory cell; the width of the rising edge and / or the falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a selector-only memory and a memory system. Background Art

[0002] To bridge the performance gap between dynamic random access memory (DRAM) and NAND flash memory, the industry has proposed a new storage medium technology, storage class memory (SCM). SCM is a non-volatile storage medium between DRAM and NAND flash memory, meaning stored information is not lost after a power outage. Its access latency is generally less than 1 microsecond, promising improvements to current computing architectures and applications, breaking through bottlenecks in computer system performance. Mainstream SCM media include phase-change memory (PCM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FeRAM). However, as the performance requirements for computer systems continue to increase, memory devices, including SCM, and their systems still have significant room for improvement.

[0003] Currently, SCM is being proposed as a bridge between DRAM and SSDs to improve current storage architectures. SCM needs to be significantly faster than NAND and offer excellent non-volatility. Among several emerging SCM storage technologies, phase-change memory is the most mature, with 3D XPoint showing the greatest promise, offering high capacity, high speed, non-volatility, and excellent cycling performance.

[0004] Recently, research on high-capacity non-volatile memory technologies to mitigate the weaknesses of 3D XPoint memory has become increasingly active. A new type of non-volatile memory has been proposed: "Selector Only Memory (SOM)," "Self-Selecting Memory (SSM)," or "Single-chalcogenide XPoint (SXM)" technology. SOM differs from 3D XPoint memory (and similar 3D cross-point memories) in that, while it uses a similar three-dimensional structure to 3D XPoint, its OTS material serves as both the gate and the memory. SOM memory offers advantages such as simple structure, high scalability, fast SET / RESET speeds, long cycle life, vertical stackability, and the absence of thermally induced write crosstalk. It is a promising non-volatile memory with significant advantages in applications such as Compute Express Link (CXL) and High Bandwidth Memory (HBM). Summary of the Invention

[0005] In a first aspect, an embodiment of the present disclosure provides a selector-only memory, which includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory cells, and the peripheral circuit is configured to: apply a read pulse to a conductive line coupled to a target memory cell among the plurality of memory cells to perform a read operation on the target memory cell; the width of the rising edge and / or falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse.

[0006] In an optional embodiment, the width of the plateau of the read pulse is greater than or equal to 10% of the total width of the read pulse, and the width of the rising edge or falling edge of the read pulse is less than or equal to 90% of the total width of the read pulse.

[0007] In an optional embodiment, the width of the rising edge and the falling edge of the read pulse are both greater than 15% of the total width of the read pulse, and both are less than 40% of the total width of the read pulse.

[0008] In an optional embodiment, the total width of the read pulse is greater than or equal to 50 ns, and the width of the rising edge and / or falling edge is greater than or equal to 20 ns.

[0009] In an optional implementation, the rising edge and / or the falling edge of the read pulse is an inclined straight line.

[0010] In an optional embodiment, the read pulse has a step-like rising edge and / or falling edge; the number of steps of the rising edge and / or falling edge of the read pulse is N, and N is an integer greater than or equal to 1.

[0011] In an optional implementation, the width of a single step of the rising edge and / or the falling edge of the read pulse is less than or equal to 25% of the total width of the read pulse.

[0012] In an optional embodiment, the multiple memory cells are configured to have a first memory state and a second memory state, the threshold voltage of the memory cell having the first memory state is less than the threshold voltage of the memory cell having the second memory state; the voltage value of the first step of the rising edge of the read pulse is greater than a first preset value; the first preset value is the median value corresponding to the threshold voltage distribution of the memory cell having the first memory state, or the first preset value is the average threshold voltage corresponding to the threshold voltage distribution of the memory cell having the first memory state.

[0013] In an optional embodiment, the multiple memory cells are configured to have a first memory state and a second memory state, the threshold voltage of the memory cell having the first memory state is less than the threshold voltage of the memory cell having the second memory state; the voltage value of the first step of the falling edge of the read pulse is less than a second preset value; and the second preset value is the median value or average value corresponding to the retention voltage distribution of the memory cell having the first memory state.

[0014] In a second aspect, an embodiment of the present disclosure further provides a memory system comprising: at least one selector-only memory as described in any of the above-mentioned embodiments; and a memory controller coupled to the selector-only memory and configured to control the selector-only memory.

[0015] In the embodiment of the present disclosure, during a read operation on a target memory cell, the width of the rising edge and / or falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse. The embodiment of the present disclosure increases the width of the rising edge / falling edge of the read pulse so that the rising edge / falling edge has a larger width, thereby effectively suppressing the overshoot / reverse overshoot of the source meter output waveform, thereby reducing the surge current in the selector memory only, thereby effectively increasing the read cycle life. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of an exemplary system provided in accordance with an embodiment of the present disclosure;

[0017] Figure 2A schematic diagram of the structure of a selector-only memory provided in an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of the structure of a storage unit in a selector-only memory provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the current-voltage relationship of different memory states of a selector-only memory provided by an embodiment of the present disclosure;

[0020] Figure 5 Schematic diagram of the threshold voltage distribution of the set state and reset state of the selector memory provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 6 Schematic diagram of the read crosstalk test pulse waveform provided by the embodiment of the present disclosure Figure 1 ;

[0022] Figure 7 A schematic diagram of the read life under a conventional test method for only selector storage provided in an embodiment of the present disclosure;

[0023] Figure 8 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 2 ;

[0024] Figure 9 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 3 ;

[0025] Figure 10 for Figure 9 The read pulse applied in a Figure 9 Schematic diagram of the respective source meter output waveforms under the read pulse applied in b;

[0026] Figure 11 A schematic diagram of read life under read pulses with different rising edge widths provided by an embodiment of the present disclosure;

[0027] Figure 12 Schematic diagram of the threshold voltage distribution of the set state and reset state of the selector memory provided in the embodiment of the present disclosure Figure 2 ;

[0028] Figure 13 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 4 ;

[0029] Figure 14 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 5 ;

[0030] Figure 15A flowchart of a method for operating a selector-only memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0033] In the drawings, like reference numerals refer to like elements throughout.

[0034] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] like Figure 1 As shown, an embodiment of the present disclosure shows an exemplary system 100, which may include a host 101 and a memory system 102. The exemplary system 100 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 104; the host 101 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The memory system 102 includes a memory controller 103 and a memory device 104 coupled to the memory controller 103.

[0037] Exemplarily, the memory controller 103 can communicate with an external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0038] The memory device may include selector-only memory. Figure 2 FIG. 1 shows a schematic diagram of the structure of a selector memory only. Figure 2As shown, only the selector memory 201 includes a memory cell array 202 and a peripheral circuit 203 coupled to the memory cell array 202. The memory cell array 202 and the peripheral circuit 203 can be integrated on the same or different dies, which allows a wider bus and a higher operating speed. The memory cell array 202 may include a plurality of memory cells. The peripheral circuit 203 may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory device. For example, the peripheral circuit may include control logic, a data buffer, a decoder (the decoder may also be called a decoder), a driver, and a read-write circuit, etc. When the control logic receives a read-write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage generated from the driver to the corresponding word line (WL, Word Line) and bit line (BL, Bit Line) based on the decoded address to implement a data read operation or a write operation, and communicate with the external (for example) through the data buffer. Figure 1 For example, after receiving the read operation or write operation command and address data, the control logic can determine the selected word line and selected bit line corresponding to the selected memory cell (target memory cell) among the multiple memory cells under the action of the decoder. For example, the memory cell can be controlled by a row decoder and a column decoder. Specifically, the row decoder can receive a row address from the memory controller and activate the appropriate word line based on the received row address. The column decoder can receive a column address from the memory controller and activate the appropriate bit line, and can activate the memory cell at the intersection of the word line and the bit line.

[0039] like Figure 2 As shown, the memory cell array 202 may include a plurality of memory cells 206 arranged in rows and columns, wherein the plurality of memory cells 206 arranged in rows are coupled to the same word line 204, and the plurality of memory cells 206 arranged in columns are coupled to the same bit line 205. To operate the memory cell array 202, a word line voltage may be applied to the word line to which the target phase-change memory cell is coupled, and a bit line voltage may be applied to the bit line to which the target phase-change memory cell is coupled.

[0040] In some embodiments, as Figure 3 As shown, the storage unit 206 of the selector memory only includes a first electrode layer 301 , a functional layer 302 , and a second electrode layer 303 stacked and arranged along the Z-axis direction.

[0041] In the embodiment of the present disclosure, the first electrode layer 301 can be connected to one of a word line and a bit line, and the second electrode layer 303 can be connected to the other of the word line and the bit line. For example, the first electrode layer 301 is connected to the word line, and the second electrode layer 303 is connected to the bit line; or the first electrode layer 301 is connected to the bit line, and the second electrode layer 303 is connected to the word line.

[0042] In the embodiment of the present disclosure, the functional layer 302 has both storage and gating functions, and the material of the functional layer 302 is a dual-function material (DFM). Exemplarily, the material of the functional layer 302 may include any appropriate bidirectional threshold switch (OTS) material, which may include a chalcogenide alloy, such as germanium (Ge), arsenic (As) and selenium (Se) and their compounds; the first electrode layer 301 and the second electrode layer 303 may be the same material or different materials, and the materials of the first electrode layer 301 and the second electrode layer 303 include but are not limited to copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and its compounds, conductive doped semiconductors, etc.

[0043] In some embodiments, only in the selector memory, during the write operation, each memory cell can be programmed to store two memory states represented as logic "1" (low resistance state, Set state) and logic "0" (high resistance state, Reset state). Among them, a positive pulse is applied to the target memory cell to cause the elements in the OTS material to achieve forward migration or positive polarization. This process is called the Set process, or the Set operation. A reverse pulse (or negative pulse) is applied to the target memory cell to cause the elements in the OTS material to achieve reverse migration or reverse polarization. This process is called the Reset process, or the Reset operation. In some embodiments, more than two memory states can be stored in the selector memory only, which will not be described in detail here.

[0044] Figure 4 Schematic diagram of the current-voltage relationship of different memory states of the selector-only memory. The selector-only memory uses OTS material as the storage medium. There are two memory states: Set state and Reset state. The two memory states are distinguished according to the difference in threshold voltage Vth between the two memory states. For example, Figure 5 As shown, the voltage difference between the Set state threshold voltage Vth1 and the Reset state threshold voltage Vth2 is ΔVt(Vth2-Vth1). During reading, a read voltage Vread between Vth1 and Vth2 is applied, and the current value is read to distinguish the two memory states: the low current is the Reset state, and the high current is the Set state. Therefore, the threshold voltage difference (ΔVt) between the two memory states determines the size of the selector-only memory's operating window (Read-Write Margin, RWM). The read voltage Vread can be between Vth1 and Vth2 to distinguish the two memory states of the memory cell.

[0045] In the write operation, the direction of the current (pulse) during the Set process can be positive or negative, and the direction of the current (pulse) during the Reset process can be positive or negative, but the directions of the current (pulse) during the Set process and the Reset process are opposite. Figure 5 During the Set process, the current (pulse) flows from word line 204 to bit line 205, which is a positive pulse (①). During the Reset process, the current (pulse) flows from bit line 205 to word line 204, which is a negative pulse (②). It can also be understood that the direction of the current in the same memory cell varies when performing different write operations. Furthermore, during a read operation, the direction of the current applied to the selected memory cell can be either positive or negative; however, it should be understood that the direction of the read current remains constant across multiple read operations. In other words, the direction of the current (pulse) during a read operation may be the same as or different from the direction of the current (pulse) during a write operation. However, when the directions are different and the applied voltage reaches the threshold transition voltage of the OTS material, the resistance of the Set state OTS material decreases, and a large overshoot transient current (i.e., overshoot (inrush) current) exists in the circuit, which can easily cause the state of the memory cell to flip from the Set state to the Reset state; or, the overshoot transient current in the circuit itself in the Reset state is too large, causing the memory cell state to flip, causing the memory cell to change from the Reset state to the Set state; thereby causing bit errors in the memory cell, reducing the read performance and reliability of the memory device. For example, the read voltage / current direction is the same as that of the Set state, but opposite to that of the Reset state. The read operation may cause the Reset state to flip (especially after repeated readings), thereby affecting the reliability of the data.

[0046] Figure 6 Schematic diagram of the read crosstalk test pulse waveform provided by the embodiment of the present disclosure Figure 1 .like Figure 6 As shown, after pre-processing by applying positive pulses and negative pulses to the word line or bit line coupled to the target memory cell, the target memory cell is repeatedly written and read multiple times, and the number of read repetitions is, for example, 1 to 1E7. Then, the state of the device is read to detect whether a bit flip occurs. Figure 7 A diagram of the read life under the conventional test method is stored for only the selector, such as Figure 7 As shown, the read life of the Reset state of the selector-only memory is very low, and some even flip to the Set state after being read 1-10 times; therefore, reducing the read crosstalk of the selector-only memory and improving its read life are issues that need to be urgently addressed in the selector-only memory.

[0047] An embodiment of the present disclosure provides a selector-only memory, which includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes multiple memory cells, and the peripheral circuit is configured to: apply a read pulse to a conductive line coupled to a target memory cell among the multiple memory cells to perform a read operation on the target memory cell; the width of the rising edge and / or falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse.

[0048] The width of the rising edge and / or falling edge of the read pulse here is greater than or equal to 10% of the total width of the read pulse, including: 1. Only the width of the rising edge of the read pulse is greater than or equal to 10% of the total width of the read pulse; 2. Only the width of the falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse; 3. Both the width of the rising edge and the width of the falling edge of the read pulse are greater than or equal to 10% of the total width of the read pulse.

[0049] In the embodiment of the present disclosure, during a read operation on a target memory cell, the width of the rising edge and / or falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse. The embodiment of the present disclosure increases the width of the rising edge / falling edge of the read pulse so that the rising edge / falling edge has a larger width, thereby effectively suppressing the overshoot / reverse overshoot of the source meter output waveform, thereby reducing the surge current in the selector memory only, thereby effectively increasing the read cycle life.

[0050] In the above embodiment, the conductive line can be a bit line or a word line, that is, the read pulse can be applied to the word line coupled to the target memory cell or to the bit line coupled to the target memory cell.

[0051] Figure 8 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 2 .like Figure 8 As shown, Figure 8 The width of the rising edge of the pulse read in b is Figure 8 The width of the rising edge of the pulse read in a is large. Figure 8 The width of the falling edge of the reading pulse in b is greater than Figure 8 The width of the falling edge of the read pulse in a is large. In the embodiment of the present disclosure, by increasing the width of the rising edge / falling edge of the read pulse, the rising edge / falling edge has a larger width, which can effectively increase the read cycle life.

[0052] In the embodiment of the present disclosure, the width of the rising edge can be understood as follows Figure 8The width t1 is the width from the start of the pulse application to the start of the target plateau. The width of the falling edge can be understood as the width from the end of the plateau to the pulse dropping to 0.

[0053] In some embodiments, the width of the plateau of the read pulse is greater than or equal to 10% of the total width of the read pulse, and the width of the rising edge or falling edge of the read pulse is less than or equal to 90% of the total width of the read pulse.

[0054] In the embodiment of the present disclosure, by reducing the ratio of the width of the plateau period of the read pulse to the total width of the read pulse and increasing the ratio of the width of the rising edge and / or falling edge of the read pulse to the total width of the read pulse, the overshoot / reverse overshoot of the source meter output waveform is effectively suppressed, thereby reducing the surge current in the selector memory only, thereby effectively increasing the read cycle life.

[0055] In some embodiments, the widths of the rising edge and the falling edge of the read pulse are both greater than 15% of the total width of the read pulse, and both are less than 40% of the total width of the read pulse.

[0056] In the disclosed embodiment, only the proportion of the width of the rising edge of the read pulse in the total width of the read pulse can be increased, or only the proportion of the width of the falling edge of the read pulse in the total width of the read pulse can be increased, or the proportion of the width of both the rising and falling edges in the total width of the read pulse can be increased at the same time.

[0057] It can be understood that, when the proportion of the width of the rising edge and the falling edge in the total width of the read pulse is increased at the same time, by increasing the proportion of the width of the rising edge of the read pulse in the total width of the read pulse, the read pulse has a wider rising edge, reducing the voltage / current overshoot of the system, thereby reducing the crosstalk of the read to the Reset state, and by increasing the proportion of the width of the falling edge of the read pulse in the total width of the read pulse, the read pulse has a wider falling edge, which can reduce the reverse overshoot current during pulse unloading, thereby reducing the read crosstalk phenomenon of the read to the Set state.

[0058] Figure 9 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 3 .like Figure 9 As shown in FIG, after the programming operation, multiple read operations are performed on the target memory cell by applying read pulses with different rising edge widths. Figure 9 As shown, after a programming operation is performed on a target memory cell by applying a set pulse and a reset pulse, a read pulse with different rising edge widths is applied to the target memory cell. Figure 9 The width of the rising edge of the read pulse applied in a is less than Figure 9The width of the rising edge of the read pulse applied in b, Figure 9 In a and Figure 9 The pulse sizes of the plateau phases of the read pulses applied in b can be equal, Figure 9 In a and Figure 9 The width of the falling edge of the read pulse applied in b can be equal. For example, Figure 9 The width of the rising edge of the read pulse applied in a is 10ns, Figure 9 The width of the rising edge of the read pulse applied in b is 30ns. After applying the corresponding read pulse, a pulse Rd_tri is applied to read the threshold transition voltage of the device. Figure 10 for Figure 9 The read pulse applied in a Figure 9 Schematic diagram of the source meter output waveform under the reading pulse applied in b. Figure 10 As shown, when the width of the rising edge of the read pulse increases from 10ns to 30ns, the overshoot voltage of the pulse basically disappears. Therefore, the increase in the width of the rising edge of the read pulse can reduce the overshoot current in the selector memory only, thereby improving the read life of the Reset state.

[0059] Figure 11 Schematic diagram of read life under read pulses with different rising edge widths. Figure 11 In the embodiment shown, the total width of the read pulses under the read pulses with different rising edge widths can be equal, and the pulse sizes of the plateau periods of the read pulses applied under the read pulses with different rising edge widths can be equal. Figure 11 As shown in Figure 3, when the width of the read pulse rising edge increases from 8ns to 30ns, the read cycle life is improved by about 10,000 times.

[0060] In the embodiment of the present disclosure, only the width of the rising edge of the read pulse may be increased, or only the width of the falling edge of the read pulse may be increased, or both the width of the rising edge and the width of the falling edge of the read pulse may be increased.

[0061] It is understood that in the disclosed embodiments, by increasing the width of the rising edge of the read pulse, the read pulse has a larger rising edge, reducing the system's inherent voltage / current overshoot, thereby reducing read crosstalk to the Reset state. Simultaneously, the read pulse has a wider falling edge, reducing reverse overshoot current during pulse unloading, thereby reducing read crosstalk to the Set state.

[0062] In some embodiments, the total width of the read pulse is greater than or equal to 50 ns, and the width of the rising edge and / or the falling edge is greater than or equal to 20 ns.

[0063] It should be noted that the above embodiment is illustrated by taking the total width of the read pulse greater than or equal to 50ns and the width of the rising edge and / or falling edge greater than or equal to 20ns as an example, but the embodiments of the present disclosure are not limited thereto.

[0064] In some embodiments, as Figure 8 As shown in b, the rising edge and / or falling edge of the read pulse is an inclined straight line.

[0065] In the embodiment of the present disclosure, the rising edge and the falling edge of the read pulse may both be an inclined straight line, or one of the rising edge and the falling edge of the read pulse may be an inclined straight line.

[0066] When both the rising and falling edges of the read pulse are inclined straight lines, the total width of the read pulse can be, for example, less than or equal to 100 ns. When the total width of the read pulse is less than or equal to 100 ns, the width of the rising or falling edge can be less than or equal to 50 ns. Specifically, the total width of the read pulse is 100 ns, and the width of the rising or falling edge is 20 ns, 30 ns, or 40 ns.

[0067] The total width of the read pulse may also be, for example, greater than 100 ns and less than or equal to 300 ns. Specifically, when the total width of the read pulse is 200 ns, the widths of the rising edge / falling edge are 20 ns, 40 ns, 60 ns, 80 ns, etc.; when the total width of the read pulse is 300 ns, the widths of the rising edge / falling edge are 30 ns, 50 ns, 70 ns, 90 ns, 110 ns, 130 ns, etc.

[0068] In the embodiment of the present disclosure, the total width of the read pulse can be understood as follows: Figure 8 As shown, the width t2 from the start of the pulse application to the pulse dropping to 0.

[0069] It can be understood that the total width of the read pulse can be controlled within a certain range, and the width of the rising edge of the read pulse can also be controlled within a certain range, so that the total width of the read pulse can be controlled within a certain range, so that only the selector memory has a smaller read delay, thereby improving the reading efficiency.

[0070] It should be noted that the upper limits of the rising and falling edges given in the above embodiments are merely examples and are not intended to limit the upper limits of the rising and falling edges in the embodiments of the present disclosure. Furthermore, the upper limits of the total width of the read pulse given in the above embodiments are merely examples and are not intended to limit the upper limit of the total width of the read pulse in the embodiments of the present disclosure. In practical applications, the widths of the rising and falling edges of the read pulses can be reasonably set based on both read cycle life and read latency, ensuring that read latency is minimized while maintaining an acceptable range for read crosstalk from the selector memory.

[0071] In some embodiments, the multiple memory cells are configured to have a first memory state and a second memory state, the threshold voltage of the memory cell having the first memory state is less than the threshold voltage of the memory cell having the second memory state; the read pulse is a voltage pulse; the voltage magnitude of the plateau period of the read pulse is greater than the maximum threshold voltage corresponding to the threshold voltage distribution of the memory cell having the first memory state, and is less than the minimum threshold voltage corresponding to the threshold voltage distribution of the memory cell having the second memory state.

[0072] like Figure 12 As shown, the memory cell in the first memory state (set state) corresponds to the first threshold voltage distribution, and the memory cell in the second memory state (reset state) corresponds to the second threshold voltage distribution, and the threshold voltage of the first threshold voltage distribution is lower than the threshold voltage of the second threshold voltage distribution. In some embodiments, as Figure 12 As shown, during a read operation, the selector-only memory can obtain data in the memory cell by applying a read voltage Vread between the threshold voltages of the set state and the reset state to the word line or the bit line coupled to the memory cell.

[0073] It is understood that the read pulse in the embodiment of the present disclosure may be a voltage pulse. When the read pulse is a voltage pulse, such as Figure 12 As shown, the voltage of the plateau period of the read pulse is greater than the maximum threshold voltage of the first threshold voltage distribution and less than the minimum threshold voltage of the second threshold voltage distribution, that is, it is between the first threshold voltage distribution and the second threshold voltage distribution.

[0074] In some embodiments, the multiple memory cells are configured to have a first memory state and a second memory state, the threshold voltage of the memory cell having the first memory state is less than the threshold voltage of the memory cell having the second memory state; the read pulse is a current pulse, and the current size of the plateau period of the read pulse is 10μA to 80μA.

[0075] It is understandable that the read pulse in the embodiment of the present disclosure may also be a current pulse. When the read pulse is a current pulse, the current magnitude during the plateau period of the read pulse needs to be maintained within a certain range so that the data in the storage unit can be read.

[0076] Figure 13 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 4 ; Figure 14 The pulse waveform provided in the embodiment of the present disclosure is shown as follows: Figure 5 .

[0077] In some embodiments, as Figure 13 as well as Figure 14 As shown, the read pulse has a step-like rising edge and / or falling edge; the number of steps of the rising edge and / or falling edge of the read pulse is N, and N is an integer greater than or equal to 1.

[0078] It can be understood that by making the read pulse have a step-like rising edge / falling edge, the voltage / current overshoot of the system can be reduced by increasing the voltage / current rising time, thereby reducing the read crosstalk phenomenon.

[0079] In the embodiments of the present disclosure, the read pulse has a step-like rising edge and / or falling edge. The read pulse may have only a step-like rising edge, or may have only a step-like falling edge, or may have both a step-like rising edge and a step-like falling edge. When the read pulse has both a step-like rising edge and a step-like falling edge, the number of steps on the rising edge may be equal to or different from the number of steps on the falling edge.

[0080] In some embodiments, a width of a single step of a rising edge / falling edge of the read pulse is less than or equal to 25% of a total width of the read pulse.

[0081] In some embodiments, the width of a single step of the rising edge / falling edge of the read pulse is between 10ns and 50ns, and the total width of the read pulse is less than or equal to a third preset value; the third preset value ranges from 200ns to 300ns.

[0082] In the embodiment of the present disclosure, when the read pulse has a step-like rising edge / falling edge, the width of a single step can be understood as follows: Figure 13 As shown, the width t3 between the start of the pulse rise in the step and the end of the plateau period of the step.

[0083] It is understandable that the width of the rising edge of the read pulse is also controlled within a certain range, so that the total width of the read pulse needs to be controlled within a certain range, so that only the selector memory has a smaller read delay, thereby improving the reading efficiency.

[0084] In the embodiment of the present disclosure, the number of steps of the rising edge / falling edge of the read pulse is N, where N is an integer greater than or equal to 1, that is, the number of steps of the rising edge / falling edge of the read pulse can be 1 or more. Figure 13 As shown in FIG, the number of steps of the rising edge / falling edge of the read pulse is 1; Figure 14 As shown, the number of steps of the rising edge / falling edge of the read pulse is 2.

[0085] In some embodiments, the voltage value of the first step of the rising edge of the read pulse is greater than a first preset value; the first preset value is the median value corresponding to the threshold voltage distribution of the storage unit having the first memory state, or the first preset value is the average threshold voltage corresponding to the threshold voltage distribution of the storage unit having the first memory state.

[0086] like Figure 13 as well as Figure 14 As shown, the voltage value V1 of the first step of the rising edge of the read pulse is greater than the first preset value Vth_S, which can reduce the impact of the read process on the Reset state.

[0087] In some embodiments, the voltage value of the first step of the falling edge of the read pulse is less than a second preset value; the second preset value is a median value or an average value corresponding to the retention voltage distribution of the memory cells having the first memory state.

[0088] like Figure 13 as well as Figure 14 As shown, the voltage value V2 of the first step of the falling edge of the read pulse is less than the second preset value Vh, where Vh is the median value or average value corresponding to the holding voltage distribution of the storage unit having the first memory state. This can reduce the reverse overcharge voltage / current generated during the reading process and reduce the crosstalk of the reading process to the Set state.

[0089] In some embodiments, the first preset value Vth_S is greater than the second preset value Vh.

[0090] Based on a concept similar to the above-mentioned selector-only memory, the present disclosure also provides a memory system, comprising: at least one selector-only memory in any of the above-mentioned embodiments; a memory controller, the memory controller being coupled to the selector-only memory and configured to control the selector-only memory.

[0091] The memory system in the above embodiment can refer to Figure 1 For the sake of brevity, the related descriptions are not repeated here.

[0092] Based on a concept similar to the above-mentioned selector-only memory, the present disclosure further provides an operating method of a selector-only memory, wherein the selector-only memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory cells, such as Figure 15 As shown, the operating method includes the following steps: Step S10: applying a read pulse to a conductive line coupled to a target memory cell among the multiple memory cells to perform a read operation on the target memory cell; the width of the rising edge and / or falling edge of the read pulse is greater than or equal to 10% of the total width of the read pulse.

[0093] The operation method of the selector memory only has been described in detail in the corresponding embodiment of the selector memory only side, and will not be repeated here for the sake of simplicity.

[0094] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0095] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0096] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A selector-only memory, characterized in that The selector-only memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory cells, and the peripheral circuit is configured to: A read pulse is applied to a conductive line coupled to a target memory cell among the plurality of memory cells to perform a read operation on the target memory cell; a width of a rising edge and / or a falling edge of the read pulse is greater than or equal to 10% of a total width of the read pulse.

2. The selector-only memory according to claim 1, wherein The width of the plateau of the read pulse is greater than or equal to 10% of the total width of the read pulse, and the width of the rising edge or the falling edge of the read pulse is less than or equal to 90% of the total width of the read pulse.

3. The selector-only memory according to claim 2, wherein: The width of the rising edge and the falling edge of the read pulse are both greater than 15% of the total width of the read pulse, and both are less than 40% of the total width of the read pulse.

4. The selector-only memory according to any one of claims 1 to 3, wherein: The total width of the read pulse is greater than or equal to 50 ns, and the width of the rising edge and / or the falling edge is greater than or equal to 20 ns.

5. The selector-only memory according to claim 1, wherein The rising edge and / or the falling edge of the read pulse is an inclined straight line.

6. The selector-only memory according to claim 1, wherein The read pulse has a step-like rising edge and / or falling edge; the number of steps of the rising edge and / or falling edge of the read pulse is N, and N is an integer greater than or equal to 1.

7. The selector-only memory according to claim 6, wherein: The width of a single step of a rising edge / falling edge of the read pulse is less than or equal to 25% of the total width of the read pulse.

8. The selector-only memory according to claim 7, wherein: The plurality of memory cells are configured to have a first memory state and a second memory state, a threshold voltage of a memory cell having the first memory state is lower than a threshold voltage of a memory cell having the second memory state; a voltage value of a first step of a rising edge of the read pulse is greater than a first preset value; The first preset value is a median value corresponding to a threshold voltage distribution of memory cells having the first memory state, or the first preset value is an average threshold voltage corresponding to a threshold voltage distribution of memory cells having the first memory state.

9. The selector-only memory according to claim 7, wherein: The multiple memory cells are configured to have a first memory state and a second memory state, the threshold voltage of the memory cell with the first memory state is lower than the threshold voltage of the memory cell with the second memory state; the voltage value of the first step of the falling edge of the read pulse is lower than a second preset value; the second preset value is the median value or average value corresponding to the retention voltage distribution of the memory cell with the first memory state.

10. A memory system, characterized in that: include: At least one selector-only memory according to any one of claims 1 to 9; A memory controller is coupled to the selector-only memory and configured to control the selector-only memory.

Images