Memory device

Abstract

A memory device is provided including a memory cell array including a first memory cell coupled to a first word line and a second memory cell coupled to a second word line; and a word line driver coupled to the memory cell array and configured to drive the first word line and the second word line using a word line signal having a pulse. A leading edge of a pulse of the wordline signal applied to the first wordline is delayed relative to a wordline signal applied to the second wordline.

Claims

1. A memory device comprising: A memory cell array includes a first memory cell coupled to a first word line and a second memory cell coupled to a second word line; as well as A word line driver is coupled to the memory cell array and configured to drive the first word line and the second word line using a word line signal having a pulse of a word line signal, wherein a leading edge of the pulse of the word line signal applied to the first word line is delayed relative to a leading edge of the pulse of the word line signal applied to the second word line.

2. The memory device of claim 1, wherein the pulse of the word line signal has a width, and the width of the pulse of the word line signal applied to the first word line is shorter than that of the word line signal applied to the second word line.

3. The memory device of claim 1 , further comprising a clock generator configured to generate an internal clock signal having a variable pulse width, the variable pulse width of the internal clock signal being varied by changing a timing of a leading edge of the internal clock signal according to a row address.

4. A memory device comprising a first memory cell, configured to perform a read operation on the first memory cell, wherein a pulse of a word line signal for reading the first memory cell has a leading edge, and a timing of the leading edge depends on a row address of the first memory cell.

5. The memory device of claim 4 , further comprising: a second storage unit; as well as a sense amplifier array configured to read data from the first memory cell and the second memory cell, wherein: The first memory cell is coupled to a first word line; The second storage unit is coupled to a second word line; The distance between the first word line and the sense amplifier array is a first distance; The distance between the second word line and the sense amplifier array is a second distance, and the second distance is greater than the first distance; The pulse of the word line signal has a width, and Compared with the word line signal applied to the first word line, the pulse width of the word line signal applied to the second word line is larger.

6. The memory device of claim 5 , further comprising a clock generator configured to generate an internal clock signal, the clock generator being configured to receive an address signal representing a row address of the first memory cell and an address signal representing a row address of the second memory cell, and to generate the internal clock signal having a pulse, wherein a leading edge of the pulse of the internal clock signal is delayed according to the row address corresponding to the first memory cell relative to the row address corresponding to the second memory cell.

7. The memory device of claim 4 , further comprising: A memory cell array includes the first memory cell and a second memory cell, and a word line driver coupled to the memory cell array, wherein: The first memory cell is coupled to a first word line; The second storage unit is coupled to a second word line; The word line driver is configured to drive the first word line and the second word line using the word line signal, and A leading edge of a pulse of the word line signal applied to the first word line is delayed relative to the word line signal applied to the second word line.

8. A method of operating a memory, comprising: Generating a first word line signal and applying the first word line signal to a first memory cell in a memory cell array, wherein the first word line signal has a first word line signal pulse and a first word line signal pulse width; as well as generating a second word line signal and applying the second word line signal to a second memory cell in the memory cell array, wherein the second word line signal has a second word line signal pulse and a second word line signal pulse width; The operation of generating the first word line signal includes delaying a leading edge of the first word line signal pulse relative to a leading edge of the second word line signal pulse.

9. The method of claim 8, further comprising reading data from the first memory cell and the second memory cell using a sense amplifier array, wherein: The distance between the first word line and the sense amplifier array is a first distance; The distance between the second word line and the sense amplifier array is a second distance; The first distance is smaller than the second distance; The operation of reading data from the first storage unit and the second storage unit includes: ending a reading operation on the first storage unit after a first elapsed time, and ending a reading operation on the second storage unit after a second elapsed time, wherein the first elapsed time is shorter than the second elapsed time.

10. The method of claim 8, further comprising generating an internal clock signal having an internal clock signal pulse, the operation of generating the internal clock signal comprising: Changing the time of a leading edge of the internal clock signal pulse according to a row address of the first memory cell and a row address of the second memory cell; The operation of changing the leading edge of the internal clock signal pulse includes: delaying the leading edge of the internal clock signal pulse for the row address corresponding to the first storage unit relative to the row address corresponding to the second storage unit.

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