Storage and calculation integrated chip and operation method thereof

Abstract

The invention discloses a storage and calculation integrated chip and an operation method thereof, and belongs to the technical field of semiconductors. The storage and calculation integrated chip comprises two complementary storage and calculation integrated arrays and m processing modules; each storage and calculation integrated array comprises at least one memory, m storage and calculation word lines and n shared bit lines which are distributed in m rows and n rows; the m rows of memories are connected with the m storage word lines in a one-to-one correspondence manner, and the n rows of memories are connected with the n shared bit lines in a one-to-one correspondence manner; the storage and calculation word lines in the first storage and calculation integrated array and the second storage and calculation integrated array are in one-to-one correspondence to form m pairs of complementary storage and calculation word lines, and the shared bit lines in the first storage and calculation integrated array and the second storage and calculation integrated array are in one-to-one correspondence to form n pairs of complementary shared bit lines. The memories in the first storage and calculation integrated array and the second storage and calculation integrated array are in one-to-one correspondence to form at least one pair of complementary memories; and the m pairs of complementary storage word lines are connected with the m processing modules in a one-to-one correspondence manner. Positive and negative weight calculation can be completed at a time, and the calculation time is shortened.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a storage and computing integrated chip and an operating method thereof. Background Art

[0002] With the continuous evolution of process nodes, the traditional von Neumann architecture faces increasingly severe "memory wall" and "power wall" problems. Memory bandwidth has struggled to keep pace with the growth of computing power density, severely hindering system performance. Furthermore, the frequent data transfer between storage and computing creates unacceptable power consumption and heat dissipation issues. To address these memory bandwidth and energy efficiency challenges, integrated computing and storage technology has been proposed. This technology utilizes novel non-volatile memory (eNVM) such as resistive random access memory (RRAM) to construct an array, simultaneously performing data storage and computation locally. This eliminates data transfer and alleviates both the "memory wall" and "power wall" issues. For example, a p*q integrated computing and storage array is constructed with p bit lines and q word lines. At the intersection of each bit line and word line, a two-terminal memory device is connected. The conductance of this memory device is continuously variable, representing different values. The conductance value is pre-programmed into each memory device. During computation, the input is applied as a voltage to each bit line. The product of the voltage on the bit line and the conductance in the memory device is then injected into the word line as a current, completing a multiplication operation. The currents generated by multiple bit lines converge on a single word line, where the current equals the sum of the currents from the individual memory devices on that word line, completing an addition operation. This converged current enters an analog-to-digital converter (ADC), where it is converted into a value that can be processed by digital circuits and then output. This technique of performing multiplication and addition using analog rather than digital calculations is called memory-computation-integrated technology, and the array that implements this technique is called a memory-computation-integrated array.

[0003] Related art integrated storage and computation arrays use a single bitline for data input, meaning they only input the data itself, not its complementary data. This type of integrated storage and computation array, when performing calculations involving negative weights, requires two separate inputs for both positive and negative weights, doubling the computation time. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a storage and computing integrated chip and an operating method thereof, which can complete the positive and negative weight calculations in one go, reducing the calculation time.

[0005] In a first aspect, the present application provides a memory-computing integrated chip, comprising two complementary memory-computing integrated arrays and m processing modules, wherein the memory-computing integrated array comprises at least one memory, m memory-computing word lines, and n shared bit lines, where m≥1 and n≥1;

[0006] The at least one memory is distributed in m rows and n lines, the m rows of memory are connected to the m storage and calculation word lines in a one-to-one correspondence, and the n rows of memory are connected to the n shared bit lines in a one-to-one correspondence;

[0007] The two integrated storage and computing arrays include a first integrated storage and computing array and a second integrated storage and computing array. The m storage and computing word lines in the first integrated storage and computing array correspond one-to-one with the m storage and computing word lines in the second integrated storage and computing array to form m pairs of complementary storage and computing word lines. The n shared bit lines in the first integrated storage and computing array correspond one-to-one with the n shared bit lines in the second integrated storage and computing array to form n pairs of complementary shared bit lines. The at least one memory in the first integrated storage and computing array corresponds one-to-one with the at least one memory in the second integrated storage and computing array to form at least one pair of complementary memories.

[0008] The m pairs of complementary storage word lines are connected to the m processing modules in a one-to-one correspondence. The processing modules are used to perform calculations on the two currents of the corresponding pair of complementary storage word lines and output calculation results.

[0009] According to the storage and computing integrated chip of the present application, by setting two complementary storage and computing integrated arrays, the storage and computing word lines in the two storage and computing integrated arrays constitute complementary storage and computing word lines, the shared bit lines in the two storage and computing integrated arrays constitute complementary shared bit lines, and the memories in the two storage and computing integrated arrays constitute complementary memories. By applying a 0V voltage to one of the complementary shared bit lines and applying a target voltage to the other shared bit line, the two currents of each pair of complementary storage and computing word lines are processed by the processing module, and the positive and negative weight calculations can be completed at one time without inputting data twice, thereby effectively reducing the calculation time.

[0010] According to one embodiment of the present application, the memory-computing integrated chip further includes a dynamic random access memory (DRAM) array, the DRAM array includes a plurality of bit lines, and every two bit lines of the plurality of bit lines constitute a pair of complementary bit lines;

[0011] The n pairs of complementary bit lines are connected to the n pairs of complementary shared bit lines in a one-to-one correspondence.

[0012] According to one embodiment of the present application, the integrated storage and computing chip further includes n gating modules, and the multiple pairs of complementary bit lines formed by the multiple bit lines are divided into n groups of bit lines, each group of bit lines includes k pairs of complementary bit lines, and k≥2;

[0013] The n groups of bit lines are connected to the input ends of the n gating modules in a one-to-one correspondence, the n pairs of complementary shared bit lines are connected to the output ends of the n gating modules in a one-to-one correspondence, and the gating module is used to select a pair of complementary bit lines from the corresponding k pairs of complementary bit lines and connect them to the corresponding pair of complementary shared bit lines.

[0014] According to one embodiment of the present application, the gating module includes two gating units;

[0015] The two bit lines in each pair of complementary bit lines are respectively connected to the input ends of the two gating units in the corresponding gating module, and the two shared bit lines in each pair of complementary shared bit lines are respectively connected to the output ends of the two gating units in the corresponding gating module.

[0016] According to one embodiment of the present application, the integrated storage and computing chip further includes a substrate;

[0017] The DRAM array and the integrated storage and computing array are located on opposite sides of the substrate, the gating module and the integrated storage and computing array are located on the same side of the substrate, and the bit lines in the DRAM array pass through the substrate and are connected to the corresponding gating modules.

[0018] According to one embodiment of the present application, the integrated storage and computing chip further includes a substrate, and the integrated storage and computing array is located on one side of the substrate;

[0019] The integrated storage and computing array includes at least one stack structure spaced apart along a first direction, the stack structure including a memory layer and a word line layer distributed along the first direction, wherein the first direction is parallel to the substrate;

[0020] The word line layer includes a plurality of storage and calculation word lines spaced apart along a second direction, and the storage and calculation word lines extend along a third direction, the second direction is perpendicular to the substrate, the third direction is parallel to the substrate, and the third direction is perpendicular to the first direction;

[0021] The memory layer includes a plurality of memories distributed in multiple rows and columns, the multiple rows of memories in the memory layer are distributed along the second direction and are connected one-to-one with the multiple storage and calculation word lines in the word line layer; the multiple columns of memories in the memory layer are distributed along the third direction, the multiple columns of memories in the at least one stack structure constitute multiple rows of memories distributed along the third direction, and the multiple shared bit lines are distributed at intervals along the third direction and are connected one-to-one with the multiple rows of memories.

[0022] According to one embodiment of the present application, the memory layer includes two memory sub-layers distributed along the first direction, and the word line layer is located between the two memory sub-layers.

[0023] According to one embodiment of the present application, the stack structure includes two memory layers and two word line layers distributed along the first direction, and the two word line layers are located between the two memory layers.

[0024] According to one embodiment of the present application, the shared bit line includes a first line segment and a second line segment;

[0025] The at least one stack structure is provided with the first line segment extending along the first direction; each memory layer is provided with a second line segment on a side away from the word line layer, the second line segment extending along the second direction and connected to the first line segment.

[0026] According to one embodiment of the present application, the shared bit line includes a third line segment, a fourth line segment, and a fifth line segment;

[0027] Each stack structure is provided with the third line segment extending along the first direction, the substrate is provided with the fourth line segment extending along the first direction, and each memory layer is provided with the fifth line segment on the side away from the word line layer. The fifth line segment extends along the second direction and is respectively connected to the third line segment and the fourth line segment.

[0028] According to one embodiment of the present application, the two integrated storage and computing arrays are arranged in a mirror-symmetrical manner.

[0029] In a second aspect, the present application provides an operating method for a storage-computing integrated chip, which is applied to the storage-computing integrated chip described in the first aspect above, and the method includes:

[0030] Set the value stored in each memory;

[0031] Applying voltages to each shared bit line and each storage word line, wherein the voltage applied to one shared bit line in each pair of complementary shared bit lines is 0V and the voltage applied to the other shared bit line is the target voltage;

[0032] The two currents of a corresponding pair of complementary storage and calculation word lines are acquired through each processing module, and the two currents of the corresponding pair of complementary storage and calculation word lines are processed to obtain a calculation result.

[0033] According to one embodiment of the present application, the numerical value stored in each memory in the first integrated memory and computing array is set to a real numerical value, the numerical value stored in each memory in the second integrated memory and computing array is set to a target value, the voltage applied to each memory and computing word line is 0V, or the voltage applied to each memory and computing word line is the target voltage, and the operation processing includes calculating the difference between the two currents of a corresponding pair of complementary memory and computing word lines.

[0034] According to one embodiment of the present application, the numerical value stored in each memory in the first integrated memory and computing array is set to a real numerical value, the numerical value stored in each memory in the second integrated memory array is set to the numerical value stored in its complementary memory, the voltage applied to each memory and computing word line is half of the target voltage, and the operation processing includes calculating the difference between the two currents of a corresponding pair of complementary memory and computing word lines.

[0035] According to one embodiment of the present application, the voltage applied to each storage and computing word line in the first storage and computing integrated array is 0V, the voltage applied to each storage and computing word line in the second storage and computing integrated array is the target voltage, and the calculation processing includes calculating the sum of two currents of a corresponding pair of complementary storage and computing word lines;

[0036] The setting of the values ​​stored in each memory includes:

[0037] Obtain the value to be stored in each pair of complementary memories;

[0038] If the value to be stored in a pair of complementary memories is 0, the values ​​stored in the pair of complementary memories are both set to high impedance;

[0039] If the value to be stored in a pair of complementary memories is a positive value, the value stored in the memory located in the first memory-computing integrated array in the pair of complementary memories is set to the positive value, and the value stored in the memory located in the second memory-computing integrated array is set to high impedance;

[0040] If the value to be stored in a pair of complementary memories is a negative value, the value stored in the memory located in the first storage and computing integrated array in the pair of complementary memories is set to high impedance, and the value stored in the memory located in the second storage and computing integrated array is set to the negative value.

[0041] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0042] By setting up two complementary storage-computing integrated arrays, the storage-computing word lines in the two storage-computing integrated arrays constitute complementary storage-computing word lines, the shared bit lines in the two storage-computing integrated arrays constitute complementary shared bit lines, and the memories in the two storage-computing integrated arrays constitute complementary memories. By applying a 0V voltage to one of the complementary shared bit lines and applying a target voltage to the other shared bit line, positive and negative weight calculations can be completed at one time without the need to input data twice, effectively reducing calculation time.

[0043] Furthermore, the complementary bit lines in the DRAM array are connected to the complementary shared bit lines in the integrated storage and computing array, and the DRAM array and the integrated storage and computing array are located on opposite sides of the substrate, making the distance between the DRAM array and the integrated storage and computing array close, greatly reducing the delay and power consumption of data moving from the DRAM array to the integrated storage and computing array;

[0044] Furthermore, the memories in the memory-computing integrated array are distributed in a direction parallel to the substrate and stacked in a direction perpendicular to the substrate to form a three-dimensional memory-computing integrated array, thereby increasing the number of devices per unit area and thus improving the device density.

[0045] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0047] Figure 1 This is a circuit diagram of a storage and computing integrated chip provided in an embodiment of the present application;

[0048] Figure 2 This is a partial circuit diagram of the storage and computing integrated chip provided in an embodiment of the present application;

[0049] Figure 3 This is a schematic diagram of the structure of the storage and computing integrated chip provided in an embodiment of the present application;

[0050] Figure 4 This is one of the structural diagrams of the stack structure and shared bit lines in the storage and computing integrated chip provided in the embodiment of the present application;

[0051] Figure 5 This is the second structural diagram of the stack structure and shared bit lines in the storage and computing integrated chip provided in the embodiment of the present application;

[0052] Figure 6 This is the third structural diagram of the stack structure and shared bit lines in the storage and computing integrated chip provided in the embodiment of the present application;

[0053] Figure 7 It is a flow chart of the operating method of the storage and computing integrated chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0054] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0055] The following describes the storage and computing integrated chip and its operation method provided by the embodiments of the present application with reference to the accompanying drawings.

[0056] Figure 1 This is a circuit schematic diagram of the storage and computing integrated chip provided in an embodiment of the present application.

[0057] like Figure 1As shown, the memory-computing integrated chip provided in the embodiment of the present application includes two complementary memory-computing integrated arrays and m processing modules 20. The two complementary memory-computing integrated arrays have the same structure. Each memory-computing integrated array includes at least one memory 11, m memory-computing word lines and n shared bit lines, m ≥ 1, n ≥ 1. At least one memory in each memory-computing integrated array is distributed in m rows and n rows, and the m rows of memory are connected to the m memory-computing word lines in a one-to-one correspondence, and the n rows of memory are connected to the n shared bit lines in a one-to-one correspondence. Among them, the memory may include a non-volatile memory such as a resistive random access memory.

[0058] Among them, the two integrated storage and computing arrays include a first integrated storage and computing array 10a and a second integrated storage and computing array 10b. The first integrated storage and computing array 10a includes m*n memories 11t, m storage and computing word lines W1t, ..., Wmt and n shared bit lines B1t, ..., Bnt. The m*n memories 11t are distributed in m rows and n rows, and each row of memories 11t can be distributed in a column or in an array. Each row of memories 11t is connected to a corresponding storage and computing word line, and the m rows of memories 11t are connected to the m storage and computing word lines W1t, ..., Wmt in a one-to-one correspondence. Each row of memories 11t is connected to a corresponding shared bit line, and the n rows of memories 11t are connected to the n shared bit lines B1t, ..., Bnt in a one-to-one correspondence.

[0059] The second integrated memory and computation array 10b includes m*n memories 11c, m memory and computation word lines W1c, ..., Wmc, and n shared bit lines B1c, ..., Bnc. The m*n memories 11c are arranged in m rows and n rows, and each row of memories 11c can be arranged in a column or in an array. Each row of memories 11c is connected to a corresponding memory and computation word line, and m rows of memories 11c are connected to the m memory and computation word lines W1c, ..., Wmc in a one-to-one correspondence. Each row of memories 11c is connected to a corresponding shared bit line, and n rows of memories 11c are connected to the n shared bit lines B1c, ..., Bnc in a one-to-one correspondence.

[0060] The n shared bit lines B1t, ..., Bnt in the first integrated memory and computing array 10a correspond one-to-one with the n shared bit lines B1c, ..., Bnc in the second integrated memory and computing array 10b to form n pairs of complementary shared bit lines. That is, shared bit line B1t and shared bit line B1c form a pair of complementary shared bit lines, shared bit line B2t and shared bit line B2c form a pair of complementary shared bit lines, and so on, shared bit line Bnt and shared bit line Bnc form a pair of complementary shared bit lines. In each pair of complementary shared bit lines, one shared bit line has a voltage of 0V, and the other shared bit line has a voltage of the target voltage VDD.

[0061] The m storage and computing word lines W1t, ..., Wmt in the first integrated storage and computing array 10a correspond one-to-one with the m storage and computing word lines W1c, ..., Wmc in the second integrated storage and computing array 10b to form m pairs of complementary storage and computing word lines. That is, storage and computing word line W1t and storage and computing word line W1c form a pair of complementary storage and computing word lines, storage and computing word line W2t and storage and computing word line W2c form a pair of complementary storage and computing word lines, and so on, storage and computing word line Wmt and storage and computing word line Wmc form a pair of complementary storage and computing word lines. The voltage of each storage and computing word line can be 0V, VDD, or VDD / 2.

[0062] At least one memory 11t in the first integrated memory and computing array 10a corresponds to at least one memory 11c in the second integrated memory and computing array 10b, forming at least one pair of complementary memories. The two memories defined by each pair of complementary memory and computing word lines and each pair of complementary shared bit lines form a pair of complementary memories, thereby forming m*n pairs of complementary memories.

[0063] The m pairs of complementary storage word lines are connected to the m processing modules 20 in a one-to-one correspondence. The processing modules 20 are used to perform calculations on the two currents of the corresponding pair of complementary storage word lines and output calculation results.

[0064] The two storage and calculation word lines in each pair of complementary storage and calculation word lines are connected to a corresponding processing module 20. For example, storage and calculation word line W1t and storage and calculation word line W1c are respectively connected to the first processing module 20, storage and calculation word line W2t and storage and calculation word line W2c are respectively connected to the second processing module 20, and so on, storage and calculation word line Wnt and storage and calculation word line Wnc are respectively connected to the nth processing module 20.

[0065] The two current signals of each pair of complementary storage word lines are simultaneously used by the corresponding processing module 20. Each pair of processing modules 20 performs operations on the two current signals of the corresponding pair of complementary storage word lines to obtain an operation result.

[0066] In some embodiments, the processing module 20 may include an analog-to-digital conversion module. The current of the storage word line is an analog signal, and the calculation result output by the processing module 20 is a digital signal. The processing module 20 may first perform calculation processing on the two currents of the corresponding pair of complementary storage word lines, then perform analog-to-digital conversion on the processing result, and output the calculation result. The processing module 20 may also first perform analog-to-digital conversion on the two currents of the corresponding pair of complementary storage word lines, then perform calculation processing on the conversion result, and output the calculation result.

[0067] It should be noted that the voltages of the storage and computing word lines and the functions of the processing modules 20 are different in different storage and computing integrated methods.

[0068] In this embodiment, two complementary storage and computing arrays are set up, the storage and computing word lines in the two storage and computing arrays constitute complementary storage and computing word lines, the shared bit lines in the two storage and computing arrays constitute complementary shared bit lines, and the memories in the two storage and computing arrays constitute complementary memories. By applying a 0V voltage to one of the complementary shared bit lines and applying a target voltage to the other shared bit line, the two currents of each pair of complementary storage and computing word lines are processed by the processing module, and the positive and negative weight calculations can be completed at one time without inputting data twice, thereby effectively reducing the calculation time.

[0069] In some embodiments, as Figure 2 As shown, the storage and computing integrated chip also includes a dynamic random access memory DRAM array 30, and the DRAM array 30 includes multiple bit lines B111, B112, ..., B1k1, B1k2, ..., Bnk1, Bnk2. Every two bit lines in the multiple bit lines B111, B112, ..., Bnk1, Bnk2 constitute a pair of complementary bit lines, that is, bit lines B111 and B112 constitute a pair of complementary bit lines, bit lines B1k1 and B1k2 constitute a pair of complementary bit lines, and so on, bit lines Bnk1 and Bnk2 constitute a pair of complementary bit lines, thereby constituting n*k pairs of complementary bit lines, k≥1.

[0070] When k = 1, DRAM array 30 includes n pairs of complementary bit lines, each of which is connected to n pairs of complementary shared bit lines in a one-to-one correspondence. When k > 1, DRAM array 30 includes n*k pairs of complementary bit lines, with n pairs of complementary bit lines selected from the n*k pairs of complementary bit lines and connected to n pairs of complementary shared bit lines in a one-to-one correspondence. The n pairs of complementary bit lines in DRAM array 30 provide input data to the n pairs of complementary shared bit lines.

[0071] This embodiment integrates the DRAM array 30 and the storage-computing integrated array into one chip, reducing the delay and power consumption of moving data from the DRAM array to the storage-computing integrated array.

[0072] In some embodiments, as Figure 2 As shown, the integrated storage and computing chip further includes n gating modules 40. When k ≥ 2, the multiple pairs of complementary bit lines formed by the plurality of bit lines are divided into n groups of bit lines, each group of bit lines including k pairs of complementary bit lines. The n groups of bit lines are connected to the inputs of the n gating modules 40 in a one-to-one correspondence, and the n pairs of complementary shared bit lines are connected to the outputs of the n gating modules 40 in a one-to-one correspondence. The gating modules 40 are configured to select a pair of complementary bit lines from the corresponding k pairs of complementary bit lines and connect them to the corresponding pair of complementary shared bit lines.

[0073] For example, bit lines B111, B112, ..., B1k1, and B1k2 in DRAM array 30 form a group of bit lines, which includes k pairs of complementary bit lines. Bit lines B111, B112, ..., B1k1, and B1k2 are each connected to the input of a gating module 40, and a pair of complementary shared bit lines B1t and B1c are each connected to the output of the gating module 40. Based on a control signal, the gating module 40 selects a pair of complementary bit lines from the k pairs of complementary bit lines and connects them to the pair of complementary shared bit lines B1t and B1c. Each of the N gating modules 40 selects n pairs of complementary bit lines and connects them to the n pairs of complementary shared bit lines in a one-to-one correspondence.

[0074] The structure of the gating module 40 is not specifically limited.

[0075] In some embodiments, the gating module 40 includes two gating units, the two bit lines in each pair of complementary bit lines are respectively connected to the input ends of the two gating units in the corresponding gating module 40, and the two shared bit lines in each pair of complementary shared bit lines are respectively connected to the output ends of the two gating units in the corresponding gating module 40.

[0076] Each group of bit lines is connected to the input of a gating module 40, one bit line in each pair of complementary bit lines in the group of bit lines is connected to a gating unit in the gating module 40, and the other bit line in each pair of complementary bit lines in the group of bit lines is connected to another gating unit in the gating module 40. Each pair of complementary shared bit lines is connected to the output of a gating module 40, one shared bit line in the pair of complementary shared bit lines is connected to a gating unit in the gating module 40, and the other shared bit line in the pair of complementary shared bit lines is connected to another gating unit in the gating module 40.

[0077] For example, the gating module 40 includes a first gating unit and a second gating unit, and bit lines B111, B112, ..., B1k1, and B1k2 are connected to the input end of the gating module 40, wherein bit lines B111, ..., and B1k1 are connected to the input end of the first gating unit of the gating module 40, and bit lines B112, ..., and B1k2 are connected to the input end of the second gating unit of the gating module 40. A shared bit line B1t is connected to the output end of the first gating unit of the gating module 40, and a shared bit line B1c is connected to the output end of the second gating unit of the gating module 40.

[0078] The first gating unit selects a bit line (e.g., bit line B111) from bit lines B111, ..., B1k1 based on a control signal and connects it to the shared bit line B1t. The second gating unit selects a bit line (e.g., bit line B112) from bit lines B112, ..., B1k2 based on a control signal and connects it to the shared bit line B1c. The bit line selected by the first gating unit and the bit line selected by the second gating unit form a pair of complementary bit lines.

[0079] In some embodiments, as Figure 3 As shown, the integrated storage and computing chip further includes a substrate 50, and the DRAM array 30 and the integrated storage and computing array are located on opposite sides of the substrate 50. The substrate 50 may include a silicon wafer, the DRAM array 30 may be located on the front side of the substrate 50, and the first integrated storage and computing array 10a and the second integrated storage and computing array 10b are both located on the back side of the substrate 50.

[0080] When k=1, n pairs of complementary bit lines in the DRAM array 30 penetrate the substrate 50 and are connected to n pairs of complementary shared bit lines in a one-to-one correspondence.

[0081] In the case of k≥2, such as Figure 3 As shown, the gating module 40 and the integrated storage and computing array are located on the same side of the substrate 50. Each gating module 40 includes two gating units 41. The gating units 41, the first integrated storage and computing array 10a and the second integrated storage and computing array 10b are located on the back side of the substrate 50.

[0082] The bit lines in the DRAM array 30 extend through the substrate 50 and connect to corresponding gating modules 40. The two gating units 41 in each gating module 40 are respectively configured to correspond to the first integrated memory and computing array 10a and the second integrated memory and computing array 10b. This ensures that n gating units 41 in the n gating modules 40 correspond to the first integrated memory and computing array 10a, and the remaining n gating units 41 in the n gating modules 40 correspond to the second integrated memory and computing array 10b. Each bit line BL in the DRAM array 30 extends through the substrate 50 and connects to the input of the corresponding gating unit 41.

[0083] In this embodiment, the DRAM array 30 and the storage and computing integrated array are located on opposite sides of the substrate 50, so that the DRAM array 30 and the storage and computing integrated array are very close in physical space, greatly reducing the delay and power consumption of moving data from the DRAM array 30 to the storage and computing integrated array.

[0084] In some embodiments, as Figure 3 As shown, the 2n gating units 41 in the n gating modules 40 are sequentially distributed along the third direction Z, the first integrated storage and computing array 10a and the second integrated storage and computing array 10b are sequentially distributed along the third direction Z, the first integrated storage and computing array 10a and the corresponding n gating units 41 are spaced apart along the first direction X, and the second integrated storage and computing array 10b and the corresponding n gating units 42 are spaced apart along the first direction X. The first direction X is parallel to the substrate 50, the third direction Z is parallel to the substrate 50, and the third direction Z is perpendicular to the first direction X.

[0085] The k*n bit lines BL (i.e., B111, B121, ..., B1k1, B211, B221, ..., Bnk1) in the DRAM array 30 are arranged corresponding to the first integrated storage and computing array 10a, and the k*n bit lines BL corresponding to the first integrated storage and computing array 10a pass through the substrate 50 and are connected to the corresponding n selection units 42 (each k bit lines BL is connected to one selection unit 42), and the n selection units 42 corresponding to the first integrated storage and computing array 10a are located between the corresponding k*n bit lines BL and the first integrated storage and computing array 10a. The remaining k*n bit lines BL (i.e., B112, B122, ..., B1k2, B212, B222, ..., Bnk2) in the DRAM array 30 are arranged corresponding to the second integrated storage and computing array 10b, and the k*n bit lines BL corresponding to the second integrated storage and computing array 10b pass through the substrate 50 and are connected to the corresponding n selection units 42 (each k bit lines BL is connected to one selection unit 42), and the n selection units 42 corresponding to the second integrated storage and computing array 10b are located between the corresponding k*n bit lines BL and the second integrated storage and computing array 10b.

[0086] In some embodiments, in each integrated storage and computing array (such as the first integrated storage and computing array 10a), multiple rows of memories 11t can be distributed along a third direction Z. The memories 11t in each row of memories can be distributed along a first direction X, or along a second direction Y, or in an array along both the first direction X and the second direction Y. The memories 11t in each row of memories are distributed along the third direction Z. The structure of the second integrated storage and computing array 10b is the same as that of the first integrated storage and computing array 10a and will not be described in detail here.

[0087] The memories in the storage and computing integrated array in this embodiment can be stacked to form a three-dimensional storage and computing integrated array. Compared with the two-dimensional storage and computing integrated array, more memories can be set up in the same area, that is, the number of devices per unit area is increased, thereby improving the device density.

[0088] In some embodiments, as Figure 3 As shown, the integrated storage and computing chip also includes a substrate 50, and the integrated storage and computing array is located on one side of the substrate 50, that is, the first integrated storage and computing array 10a and the second integrated storage and computing array 10b are located on the same side of the substrate 50.

[0089] The integrated storage and computing array includes at least one stack structure 60 spaced apart along a first direction X. The stack structure 60 includes a memory layer 61 and a word line layer 62 distributed along the first direction X. The memory layer 61 can be located on one side of the word line layer 62 along the first direction X, or on both sides of the word line layer 62 along the first direction X.

[0090] The number of stack structures 60 can be set according to actual needs. Different stack structures 60 can have the same structure.

[0091] The word line layer 62 includes a plurality of storage and computing word lines W spaced apart along a second direction Y, and the storage and computing word lines W extend along a third direction Z. The second direction Y is perpendicular to the substrate 50, that is, the second direction Y, the third direction Z, and the first direction X are mutually perpendicular. The number of storage and computing word lines W in the word line layer 62 can be set according to actual needs. Different word line layers 62 can have the same structure, that is, the number of storage and computing word lines W in different word line layers 62 can be the same.

[0092] In some embodiments, the word line layer 62 may further include an insulating layer, and the plurality of storage word lines W in the word line layer 62 are separated by the insulating layer.

[0093] Memory layer 61 includes multiple memories arranged in multiple rows and columns. The multiple rows of memories in memory layer 61 are arranged along a second direction Y, and the multiple memories in each row are arranged along a first direction X. The multiple rows of memories in memory layer 61 are connected one-to-one with the multiple memory word lines W in word line layer 62. The multiple columns of memories in memory layer 61 are arranged along a third direction Z, and the multiple memories in each column are arranged along the second direction Y. The multiple columns of memories in at least one stack structure 60 form multiple rows of memories arranged along the third direction Z. The multiple memories in at least one stack structure 60 located in the same plane (a plane perpendicular to the third direction Z) form a row of memories, thereby forming multiple rows of memories arranged along the third direction Z. Multiple shared bit lines B are arranged at intervals along the third direction Z and are connected one-to-one with the multiple rows of memories. Each shared bit line B extends in the direction of a corresponding row of memories to connect to each memory in the corresponding row of memories.

[0094] For example Figure 3 As shown, the integrated storage and computing array includes two stack structures 60 spaced apart along a first direction X and three shared bit lines B spaced apart along a third direction Z. The word line layer 62 in each stack structure 60 includes four storage and computing word lines W, and the memory layer 61 in each stack structure 60 includes twelve memories distributed in four rows and three columns. The four rows of memories in each stack structure 60 are connected one-to-one with the four storage and computing word lines W. The multiple memories located in the same plane (a plane perpendicular to the third direction Z) in the two stack structures 60 constitute a row of memories, thereby constituting three rows of memories. The three rows of memories are connected one-to-one with the three shared bit lines B.

[0095] In the first integrated storage and computing array 10a, the multiple storage and computing word lines W in the multiple word line layers 62 include m storage and computing word lines W1t,...,Wmt, the multiple memories in the multiple memory layers 61 include m*n memories 11t, and the multiple shared bit lines B include n shared bit lines B1t,...,Bnt.

[0096] In the second integrated storage and computing array 10b, the multiple storage and computing word lines W in the multiple word line layers 62 include m storage and computing word lines W1c,...,Wmc, the multiple memories in the multiple memory layers 61 include m*n memories 11c, and the multiple shared bit lines B include n shared bit lines B1c,...,Bnc.

[0097] In this embodiment, the multiple storage and computing word lines W in the word line layer 62 can be distributed along the second direction Y, and the multiple memories 11 in the memory layer 61 can be stacked along the second direction Y, thereby forming a three-dimensional storage and computing integrated array, increasing the number of devices per unit area and improving device density.

[0098] In some embodiments, as Figure 3 and Figure 4 As shown, the memory layer 61 includes two memory sub-layers 611 distributed along a first direction X, and the word line layer 62 is located between the two memory sub-layers 611. Each memory 61 in the memory layer 61 has two memory sub-layers 611. The word line layer 62 is located between the two memory sub-layers 611 and contacts the two memory sub-layers 611 respectively. Each storage word line W in the word line layer 62 is located between the two storage sub-layers 611 of a row of memories in the memory layer 61 and contacts the two storage sub-layers 611 of the row of memories, so that each storage word line W is connected to a corresponding row of memories.

[0099] In some embodiments, as Figure 5 and Figure 6 As shown, the stack structure 60 includes two memory layers 61 and two word line layers 62 distributed along a first direction X, with the two word line layers 62 located between the two memory layers 61. The two word line layers 62 are respectively arranged corresponding to the two memory layers 61, each word line layer 62 is in contact with its corresponding memory layer 61, and each storage and calculation word line W in each word line layer 62 is in contact with a row of memories in the corresponding memory layer 61, so that each storage and calculation word line W in each word line layer 62 is connected to a row of memories in the corresponding memory layer 61. The two word line layers 62 are in contact, and the storage and calculation word lines W in the two word line layers 62 are separated by an insulating layer.

[0100] In some embodiments, as Figure 3 and Figure 5 As shown, the shared bit line B includes a first line segment Ba and a second line segment Bb. The first line segment Ba is provided on at least one stack structure 60 and extends along a first direction X. A second line segment Bb is provided on a side of each memory layer 61 facing away from the word line layer 62. The second line segment Bb extends along a second direction Y and is connected to the first line segment Ba.

[0101] The distance between adjacent stack structures 60 is small, for example, the distance between adjacent stack structures 60 may be the thickness of the shared bit line B. The outer film layer of each stack structure 60 along the first direction X is a memory layer 61, for example Figure 3 As shown, the word line layer 62 is located between two memory sub-layers 611, for example Figure 4 As shown, two word line layers 62 are located between two memory layers 61. Each stack structure 60 is provided with a second line segment Bb extending along the second direction Y on both sides along the first direction X. Adjacent stack structures 60 can share one second line segment Bb. At least one stack structure 60 is provided with a first line segment Ba extending along the first direction X. The first line segment Ba is connected to the second line segments Bb on both sides of each stack structure 60, thereby forming a continuous shared bit line B. Furthermore, the first line segment Ba and the second line segment Bb are located in the same plane (a plane perpendicular to the third direction Z) as the corresponding row of memories, so that the shared bit line B is connected to each memory cell in the corresponding row of memories.

[0102] In addition, the shared bit line B may further include a sixth line segment Bc, which is located on the substrate 50 between the gating unit 41 and the stack structure 60 disposed closest to the gating unit 41. The sixth line segment Bc extends along the first direction X and is respectively connected to the output end of the gating unit 41 and the second line segment Bb disposed closest to the gating unit 41, so that the shared bit line B is respectively connected to the corresponding gating unit 41 and the corresponding row of memories.

[0103] In this embodiment, the distance between the stack structures 60 is small, which reduces the device occupied area and further improves the device density.

[0104] In some embodiments, as Figure 4 and Figure 6 As shown, the shared bit line B includes a third line segment Bd, a fourth line segment Be, and a fifth line segment Bf. Each stack structure 60 is provided with a third line segment Bd extending along the first direction X. The substrate 50 is provided with a fourth line segment Be extending along the first direction X. A fifth line segment Bf is provided on the side of each memory layer 61 facing away from the word line layer 62. The fifth line segment Bf extends along the second direction Y and is connected to the third line segment Bd and the fourth line segment Be, respectively.

[0105] The distance between adjacent stack structures 60 is relatively large, for example, the distance between adjacent stack structures 60 may be greater than twice the thickness of the shared bit line B. The outer film layer of each stack structure 60 along the first direction X is a memory layer 61, for example Figure 4 As shown, the word line layer 62 is located between two memory sub-layers 611, for example Figure 6As shown, two word line layers 62 are located between two memory layers 61. Each stack structure 60 is provided with a fifth line segment Bf extending along the second direction Y on both sides along the first direction X. Each stack structure 60 is provided with a third line segment Bd extending along the first direction X, and the third line segment Bd is connected to the fifth line segments Bf on both sides of the stack structure 60. A fourth line segment Be extending along the first direction X is provided on the substrate 50 between adjacent stack structures 60, and the fourth line segment Be is connected to adjacent fifth line segments Bf in adjacent stack structures 60, thereby forming a continuous shared bit line B. Furthermore, the third line segment Bd, the fourth line segment Be, and the fifth line segment Bf are located in the same plane (a plane perpendicular to the third direction Z) as the corresponding row of memories, so that the shared bit line B is connected to each memory cell in the corresponding row of memories.

[0106] In addition, a fourth line segment Be is provided on the substrate 50 between the gating unit 41 and the stack structure 60 arranged closest to the gating unit 41. The fourth line segment Be extends along the first direction X and is respectively connected to the output end of the gating unit 41 and the fifth line segment Bf arranged closest to the gating unit 41, so that the shared bit line B is respectively connected to the corresponding gating unit 41 and the corresponding row of memories.

[0107] In this embodiment, the distance between the stack structures 60 is relatively large, which can reduce interference between devices.

[0108] In some embodiments, the two integrated storage and computing arrays are arranged in a mirror-symmetrical manner.

[0109] It should be noted that Figure 3 Only one of the two integrated storage and computing arrays and its corresponding gating unit is shown, and the other integrated storage and computing array and its corresponding gating unit are shown. Figure 3 The array structure of the storage-computing integrated array shown is mirror-symmetrical and logically consistent. The two storage-computing integrated arrays, namely the first storage-computing integrated array 10a and the second storage-computing integrated array 10b, can be distributed along the third direction Z, and the first storage-computing integrated array 10a and the second storage-computing integrated array 10b are arranged in mirror-symmetrical configuration and logically consistent.

[0110] The storage and computing word lines in the first storage and computing integrated array 10a and the second storage and computing integrated array 10b that are arranged in a mirror-symmetrical manner constitute a pair of complementary storage and computing word lines, the shared bit lines in the first storage and computing integrated array 10a and the second storage and computing integrated array 10b that are arranged in a mirror-symmetrical manner constitute a pair of complementary shared bit lines, and the memories in the first storage and computing integrated array 10a and the second storage and computing integrated array 10b that are arranged in a mirror-symmetrical manner constitute a pair of complementary memories.

[0111] The processing module 20 can be disposed between the two integrated memory and computing arrays, and each pair of complementary memory and computing word lines can extend along the first direction X to the corresponding processing module 20 to connect with the corresponding processing module 20. The processing module 20 can also be disposed in other locations, as long as each pair of complementary memory and computing word lines is connected to one processing module 20, and this is not specifically limited here.

[0112] In this embodiment, the two integrated storage and computing arrays are arranged in a mirror-symmetrical manner, which can offset the common-mode noise between the two arrays.

[0113] In summary, according to the storage and computing integrated chip provided by the embodiment of the present application, by setting up two complementary storage and computing integrated arrays, the storage and computing word lines in the two storage and computing integrated arrays constitute complementary storage and computing word lines, the shared bit lines in the two storage and computing integrated arrays constitute complementary shared bit lines, and the memories in the two storage and computing integrated arrays constitute complementary memories. By applying a 0V voltage to one of the complementary shared bit lines and applying a target voltage to the other shared bit line, the positive and negative weight calculations can be completed at one time without the need to input data twice, thereby effectively reducing the calculation time. Moreover, the complementary bit lines in the DRAM array are correspondingly connected to the complementary shared bit lines in the storage and computing integrated array, and the DRAM array and the storage and computing integrated array are located on opposite sides of the substrate, so that the distance between the DRAM array and the storage and computing integrated array is close, greatly reducing the delay and power consumption overhead of moving data from the DRAM array to the storage and computing integrated array. Moreover, the memories in the storage and computing integrated array are distributed in a direction parallel to the substrate and are stacked in a direction perpendicular to the substrate to form a three-dimensional storage and computing integrated array, thereby increasing the number of devices per unit area and thus increasing the device density.

[0114] Correspondingly, an embodiment of the present application also provides an operating method of a storage and computing integrated chip, which can be applied to the storage and computing integrated chip in the above embodiment.

[0115] like Figure 7 As shown, the operating method of the storage and computing integrated chip provided in the embodiment of the present application includes steps 110 to 130.

[0116] Step 110: Set the values ​​stored in each memory.

[0117] Combine Figure 1 As shown, the values ​​stored in each memory 11t in the first integrated storage and computing array 10a and each memory 11c in the second integrated storage and computing array 10b are set respectively.

[0118] Step 120 : Apply voltage to each shared bit line and each storage word line. The voltage applied to one shared bit line in each pair of complementary shared bit lines is 0V, and the voltage applied to the other shared bit line is the target voltage.

[0119] Voltages are applied respectively to the shared bit lines B1t, ..., Bnt and storage and computing word lines W1t, ..., Wmt in the first storage and computing integrated array 10a and the shared bit lines B1c, ..., Bnc and storage and computing word lines W1c, ..., Wmc in the second storage and computing integrated array 10b.

[0120] In each pair of complementary shared bit lines, one shared bit line is applied at 0V, while the other shared bit line is applied at the target voltage, VDD. For example, shared bit line B1t is at 0V, while shared bit line B1c is at VDD; shared bit line Bnt is at VDD, while shared bit line Bnc is at 0V. Each storage word line is applied at 0V, VDD, or VDD / 2.

[0121] Step 130 : Obtain two currents of a corresponding pair of complementary storage and calculation word lines through each processing module, and perform calculation processing on the two currents of the corresponding pair of complementary storage and calculation word lines to obtain a calculation result.

[0122] For example, a processing module 20 obtains the currents of a corresponding pair of complementary storage word lines W1t and W1c, performs calculation processing on the currents of the storage word lines W1t and W1c, and outputs the corresponding calculation results.

[0123] In some embodiments, the processing module 20 may include an analog-to-digital conversion module. The current of the storage word line is an analog signal, and the calculation result output by the processing module 20 is a digital signal. The processing module 20 may first perform calculation processing on the two currents of the corresponding pair of complementary storage word lines, then perform analog-to-digital conversion on the processing result, and output the calculation result. The processing module 20 may also first perform analog-to-digital conversion on the two currents of the corresponding pair of complementary storage word lines, then perform calculation processing on the conversion result, and output the calculation result.

[0124] It should be noted that the voltages of the storage and computing word lines and the functions of the processing modules 20 are different in different storage and computing integrated methods.

[0125] In this embodiment, the processing module 20 performs calculations on the currents of the corresponding pair of complementary storage word lines, which can reduce the common-mode noise in the array while completing the calculation of the positive and negative storage matrices in one step instead of twice, thereby reducing the calculation delay of the positive and negative storage matrices.

[0126] In some embodiments, the value stored in each memory 11t in the first integrated memory and computing array 10a is set to a real value, which is the value that the memory 11t needs to store. The value stored in each memory 11c in the second integrated memory and computing array 10b is set to a target value, which can be 0, 1, or any other value, to ensure that all the memories 11c in the second integrated memory and computing array 10b store the same value. The voltage applied to each memory and computing word line is 0V, or the voltage applied to each memory and computing word line is the target voltage, that is, the voltage applied to all memory and computing word lines is the same, which can be 0V or VDD. The voltage applied to one shared bit line in each pair of complementary shared bit lines is 0V, and the voltage applied to the other shared bit line is the target voltage VDD.

[0127] The computation process includes calculating the difference between the two currents of a corresponding pair of complementary storage wordlines. Each processing module 20 can subtract the two currents of the corresponding pair of complementary storage wordlines and then convert the result into a digital signal. This digital signal is the computation result output by the processing module 20. Alternatively, each processing module 20 can convert the two currents of the corresponding pair of complementary storage wordlines into digital signals and then subtract them to obtain a final digital signal. This final digital signal is the computation result output by the processing module 20. This processing method can reduce common-mode noise in the array.

[0128] The two integrated storage and computation arrays in this embodiment can realize the multiplication of two non-negative matrices, or the multiplication of two non-positive matrices, or the multiplication of a non-negative matrix and a non-positive matrix.

[0129] In some embodiments, the value stored in each memory 11t in the first integrated memory array 10a is set to a real value, which is the value that memory 11t needs to store. The value stored in each memory 11c in the second integrated memory array 10b is set to the value stored in its complementary memory, that is, the two memories in each pair of complementary memories store the same value. The voltage applied to each memory and computing word line is half the target voltage, that is, VDD / 2. In each pair of complementary shared bit lines, the voltage applied to one shared bit line is 0V, and the voltage applied to the other shared bit line is the target voltage VDD.

[0130] The computation process includes calculating the difference between the two currents of a corresponding pair of complementary storage wordlines. Each processing module 20 can subtract the two currents of the corresponding pair of complementary storage wordlines and then convert the result into a digital signal. This digital signal is the computation result output by the processing module 20. Alternatively, each processing module 20 can convert the two currents of the corresponding pair of complementary storage wordlines into digital signals and then subtract them to obtain a final digital signal. This final digital signal is the computation result output by the processing module 20. This processing method can reduce common-mode noise in the array.

[0131] The two integrated storage and computing arrays in this embodiment can realize the multiplication of a positive and negative matrix (bit line voltage matrix) and a non-negative matrix (memory matrix), or the multiplication of a positive and negative matrix (bit line voltage matrix) and a non-positive matrix (memory matrix).

[0132] In some embodiments, the voltage applied to each storage and computing word line in the first storage and computing integrated array 10a is 0V, and the voltage applied to each storage and computing word line in the second storage and computing integrated array 10b is the target voltage VDD.

[0133] The setting of the values ​​stored in each memory in step 110 includes:

[0134] Obtain the value to be stored in each pair of complementary memories;

[0135] If the required value stored in a pair of complementary memories is 0, the values ​​stored in the pair of complementary memories are both set to high impedance;

[0136] If the required value stored in the pair of complementary memories is a positive value, the value stored in the memory located in the first storage and computing integrated array of the pair of complementary memories is set to a positive value, and the value stored in the memory located in the second storage and computing integrated array is set to high impedance;

[0137] If the required value stored in a pair of complementary memories is a negative value, the value stored in the memory located in the first storage and computing array in the pair of complementary memories is set to high impedance, and the value stored in the memory located in the second storage and computing array is set to a negative value.

[0138] The values ​​required to be stored in each pair of complementary memories are obtained respectively. If the values ​​required to be stored in a pair of complementary memories are both 0, both memories in the pair of complementary memories are set to a high-impedance state (approximately an open circuit); if the values ​​required to be stored in a pair of complementary memories are both positive values, the value stored in one memory in the pair of complementary memories (the memory is located in the first storage and computing integrated array 10a) is set to the positive value, and the other memory in the pair of complementary memories (the memory is located in the second storage and computing integrated array 10b) is set to a high-impedance state (approximately an open circuit); if the values ​​required to be stored in a pair of complementary memories are both negative values, the value stored in one memory in the pair of complementary memories (the memory is located in the second storage and computing integrated array 10b) is set to the negative value, and the other memory in the pair of complementary memories (the memory is located in the first storage and computing integrated array 10a) is set to a high-impedance state (approximately an open circuit).

[0139] The computation process includes calculating the sum of the two currents in the corresponding pair of complementary storage wordlines. Each processing module 20 can add the two currents in the corresponding pair of complementary storage wordlines and convert them into a digital signal. This digital signal is the computation result output by the processing module 20. Alternatively, each processing module 20 can convert the two currents in the corresponding pair of complementary storage wordlines into digital signals and then add them to obtain a final digital signal. This final digital signal is the computation result output by the processing module 20. This processing method can reduce common-mode noise in the array.

[0140] The two integrated storage and computing arrays in this embodiment can realize the multiplication of a non-negative matrix (bit line voltage matrix) and a matrix with both positive and negative values ​​(memory matrix), or the multiplication of a non-positive matrix (bit line voltage matrix) and a matrix with both positive and negative values ​​(memory matrix).

[0141] According to the operating method of the storage and computing integrated chip provided in the embodiment of the present application, it is possible to complete the calculation of positive and negative storage matrices in one time instead of twice while reducing the common-mode noise in the array, thereby reducing the calculation delay of positive and negative storage matrices.

[0142] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0143] In the description of this application, “plurality” means two or more.

[0144] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0145] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A storage and computing integrated chip, characterized in that: The system comprises two complementary memory-computing integrated arrays and m processing modules, wherein the memory-computing integrated array comprises at least one memory, m memory-computing word lines and n shared bit lines, where m≥1 and n≥1; The at least one memory is distributed in m rows and n lines, the m rows of memory are connected to the m storage and calculation word lines in a one-to-one correspondence, and the n rows of memory are connected to the n shared bit lines in a one-to-one correspondence; The two integrated storage and computing arrays include a first integrated storage and computing array and a second integrated storage and computing array. The m storage and computing word lines in the first integrated storage and computing array correspond one-to-one with the m storage and computing word lines in the second integrated storage and computing array to form m pairs of complementary storage and computing word lines. The n shared bit lines in the first integrated storage and computing array correspond one-to-one with the n shared bit lines in the second integrated storage and computing array to form n pairs of complementary shared bit lines. The at least one memory in the first integrated storage and computing array corresponds one-to-one with the at least one memory in the second integrated storage and computing array to form at least one pair of complementary memories. The m pairs of complementary storage word lines are connected to the m processing modules in a one-to-one correspondence. The processing modules are used to perform calculations on the two currents of the corresponding pair of complementary storage word lines and output calculation results.

2. The integrated storage and computing chip according to claim 1, characterized in that: The storage and computing integrated chip further includes a dynamic random access memory DRAM array, wherein the DRAM array includes a plurality of bit lines, and every two bit lines in the plurality of bit lines form a pair of complementary bit lines; The n pairs of complementary bit lines are connected to the n pairs of complementary shared bit lines in a one-to-one correspondence.

3. The integrated storage and computing chip according to claim 2, characterized in that: The storage and computing integrated chip further includes n gating modules, wherein the plurality of pairs of complementary bit lines formed by the plurality of bit lines are divided into n groups of bit lines, each group of bit lines includes k pairs of complementary bit lines, and k ≥ 2; The n groups of bit lines are connected to the input ends of the n gating modules in a one-to-one correspondence, the n pairs of complementary shared bit lines are connected to the output ends of the n gating modules in a one-to-one correspondence, and the gating module is used to select a pair of complementary bit lines from the corresponding k pairs of complementary bit lines and connect them to the corresponding pair of complementary shared bit lines.

4. The integrated storage and computing chip according to claim 3, characterized in that: The gating module includes two gating units; The two bit lines in each pair of complementary bit lines are respectively connected to the input ends of the two gating units in the corresponding gating module, and the two shared bit lines in each pair of complementary shared bit lines are respectively connected to the output ends of the two gating units in the corresponding gating module.

5. The storage and computing integrated chip according to claim 3, characterized in that: The storage and computing integrated chip further includes a substrate; The DRAM array and the integrated storage and computing array are located on opposite sides of the substrate, the gating module and the integrated storage and computing array are located on the same side of the substrate, and the bit lines in the DRAM array pass through the substrate and are connected to the corresponding gating modules.

6. The integrated storage and computing chip according to claim 1, characterized in that: The integrated storage and computing chip further includes a substrate, and the integrated storage and computing array is located on one side of the substrate; The integrated storage and computing array includes at least one stack structure spaced apart along a first direction, the stack structure including a memory layer and a word line layer distributed along the first direction, wherein the first direction is parallel to the substrate; The word line layer includes a plurality of storage and calculation word lines spaced apart along a second direction, and the storage and calculation word lines extend along a third direction, the second direction is perpendicular to the substrate, the third direction is parallel to the substrate, and the third direction is perpendicular to the first direction; The memory layer includes a plurality of memories distributed in multiple rows and columns, the multiple rows of memories in the memory layer are distributed along the second direction and are connected one-to-one with the multiple storage and calculation word lines in the word line layer; the multiple columns of memories in the memory layer are distributed along the third direction, the multiple columns of memories in the at least one stack structure constitute multiple rows of memories distributed along the third direction, and the multiple shared bit lines are distributed at intervals along the third direction and are connected one-to-one with the multiple rows of memories.

7. The integrated storage and computing chip according to claim 6, characterized in that: The memory layer includes two memory sub-layers distributed along the first direction, and the word line layer is located between the two memory sub-layers.

8. The integrated storage and computing chip according to claim 6, characterized in that: The stack structure includes two memory layers and two word line layers distributed along the first direction, and the two word line layers are located between the two memory layers.

9. The integrated storage and computing chip according to claim 6, characterized in that: The shared bit line includes a first line segment and a second line segment; The at least one stack structure is provided with the first line segment extending along the first direction; each memory layer is provided with a second line segment on a side away from the word line layer, the second line segment extending along the second direction and connected to the first line segment.

10. The storage and computing integrated chip according to claim 6, characterized in that: The shared bit line includes a third line segment, a fourth line segment and a fifth line segment; Each stack structure is provided with the third line segment extending along the first direction, the substrate is provided with the fourth line segment extending along the first direction, and each memory layer is provided with the fifth line segment on the side away from the word line layer. The fifth line segment extends along the second direction and is respectively connected to the third line segment and the fourth line segment.

11. The storage-computing integrated chip according to any one of claims 1 to 10, characterized in that: The two integrated storage and computing arrays are arranged in a mirror-symmetrical manner.

12. A method for operating a storage and computing integrated chip, characterized in that: Applied to the storage-computing integrated chip according to any one of claims 1 to 11, the method comprising: Set the value stored in each memory; Applying voltages to each shared bit line and each storage word line, wherein the voltage applied to one shared bit line in each pair of complementary shared bit lines is 0V and the voltage applied to the other shared bit line is the target voltage; The two currents of a corresponding pair of complementary storage and calculation word lines are acquired through each processing module, and the two currents of the corresponding pair of complementary storage and calculation word lines are processed to obtain a calculation result.

13. The method for operating a memory-computing integrated chip according to claim 12, wherein: The numerical value stored in each memory in the first integrated memory and computing array is set to a real numerical value, the numerical value stored in each memory in the second integrated memory and computing array is set to a target value, the voltage applied to each memory and computing word line is 0V, or the voltage applied to each memory and computing word line is the target voltage, and the calculation processing includes calculating the difference between the two currents of a corresponding pair of complementary memory and computing word lines.

14. The method for operating a storage-computing integrated chip according to claim 12, wherein: The numerical value stored in each memory in the first integrated storage and computing array is set to a real numerical value, the numerical value stored in each memory in the second integrated storage and computing array is set to the numerical value stored in its complementary memory, the voltage applied to each storage and computing word line is half of the target voltage, and the calculation processing includes calculating the difference between the two currents of a corresponding pair of complementary storage and computing word lines.

15. The method for operating a memory-computing integrated chip according to claim 12, wherein: The voltage applied to each storage and computing word line in the first storage and computing integrated array is 0V, and the voltage applied to each storage and computing word line in the second storage and computing integrated array is the target voltage, and the calculation processing includes calculating the sum of two currents of a corresponding pair of complementary storage and computing word lines; The setting of the values ​​stored in each memory includes: Obtain the value to be stored in each pair of complementary memories; If the value to be stored in a pair of complementary memories is 0, the values ​​stored in the pair of complementary memories are both set to high impedance; If the value to be stored in a pair of complementary memories is a positive value, the value stored in the memory located in the first memory-computing integrated array in the pair of complementary memories is set to the positive value, and the value stored in the memory located in the second memory-computing integrated array is set to high impedance; If the value to be stored in a pair of complementary memories is a negative value, the value stored in the memory located in the first storage and computing integrated array in the pair of complementary memories is set to high impedance, and the value stored in the memory located in the second storage and computing integrated array is set to the negative value.

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