Process method for shallow trench isolation structure

Abstract

The present application relates to the technical field of semiconductor, and in particular to a shallow trench isolation structure and a process method thereof. The shallow trench isolation structure comprises a trench and a filling structure. The bottom of the trench has a vertical sidewall, and the top of the trench is a trapezoidal opening which gradually expands from outside to inside, and the inclined sidewall of the trapezoidal opening intersects with the vertical sidewall. The filling structure is filled in the trench. The process method of the shallow trench isolation structure comprises: introducing process gas into a process chamber to excite plasma, and vertically bombarding the substrate; gradually adjusting the bombardment angle of the plasma to perform inclined bombardment on the bottom of the sidewall of the trench; reducing the radio frequency power, and gradually adjusting the bombardment angle of the plasma to perform inclined bombardment on the top of the sidewall of the trench; and a filling step of filling insulating material into the trench. The shallow trench isolation structure and the process method thereof provided by the present application have a low filling defect rate, and significantly improve the reliability and yield of the shallow trench isolation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a shallow trench isolation structure and its manufacturing process. Background Technology

[0002] In integrated circuit manufacturing processes above 0.35 micrometers, LOCOS (Local Oxidation of Silicon) technology is widely used, with a long history of development and mature technology. However, the field oxidation process used in this technology limits its further application due to the depth of the oxide film and the bird's beak effect generated in the active region at the edge of the field area.

[0003] As the feature size of semiconductor devices continues to shrink, the isolation area between devices also needs to be reduced accordingly. Shallow trench isolate (STI) technology is often used to replace LOCOS technology to adapt to deep submicron processes below 0.35 micrometers. However, the shallow trench isolation structure in related technologies has problems such as high filling defect rate and low reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a shallow trench isolation structure and its manufacturing process to alleviate the technical problems of high filling defect rate and low reliability of existing shallow trench isolation structures.

[0005] The shallow trench isolation structure provided by the present invention includes a trench and a filling structure.

[0006] The bottom of the trench has a vertical sidewall, and the top of the trench has a trapezoidal opening that gradually expands from the outside to the inside, with the inclined sidewall of the trapezoidal opening intersecting the vertical sidewall; the filling structure fills the trench.

[0007] Preferably, as one possible implementation, the ratio of the width difference between the large and small ends of the trapezoidal opening to the width of the small end is 20-30%;

[0008] And / or, the inclination angle of the inclined sidewall is 10°~30°.

[0009] Preferably, as one possible implementation, the vertical sidewall and the bottom wall are smoothly transitioned through an arc-shaped corner.

[0010] Preferably, as one possible implementation, the radius of curvature of the arc-shaped corner is 5~20nm.

[0011] Preferably, as one possible implementation, the inner wall of the trench is coated with a SiON layer.

[0012] The process method for the shallow trench isolation structure provided by the present invention includes:

[0013] In the first etching step, process gas is introduced into the process chamber to generate plasma, which is then used to vertically bombard the substrate to form the initial morphology of the trench; wherein the initial morphology of the trench is U-shaped.

[0014] In the second etching step, the bombardment angle of the plasma is gradually adjusted to bombard the bottom of the sidewall of the trench at an angle, so as to widen the bottom of the trench and form the vertical sidewall.

[0015] In the third etching step, the radio frequency power is reduced and the bombardment angle of the plasma is gradually adjusted to bombard the top of the sidewall of the trench at an angle to form the trapezoidal opening.

[0016] The filling step involves filling the trench with insulating material.

[0017] Preferably, as one possible implementation, the substrate is a silicon substrate.

[0018] In the first etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2; and / or, in the second etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2; and / or, in the third etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2.

[0019] Preferably, as one possible implementation, in the first etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2):(1.8 to 2.2):(0.4 to 0.7).

[0020] And / or, in the second etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7).

[0021] And / or, in the third etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7).

[0022] Preferably, as one possible implementation, the second etching step includes: gradually increasing the bombardment angle of the plasma, and obliquely bombarding the bottom of the sidewall of the trench from bottom to top to widen the bottom of the trench and form the vertical sidewall;

[0023] And / or, the third etching step includes: gradually increasing the bombardment angle of the plasma to obliquely bombard the top of the sidewall of the trench from bottom to top to form the trapezoidal opening.

[0024] Preferably, as one possible implementation, the radio frequency power in the second etching step is 1200~1500W;

[0025] And / or, in the third etching step, the radio frequency power is 200~300W.

[0026] Preferably, as one possible implementation, the filling step includes:

[0027] In the first filling step, an insulating material is generated by high-density plasma chemical vapor deposition to fill the bottom of the trench;

[0028] The second filling step involves generating the insulating material via fluidized chemical vapor deposition to fill the remaining portion of the trench.

[0029] Preferably, as one possible implementation, in the first filling step, the deposition rate is 3~6 nm / min, the gas flow rate is 300 sccm or higher, and the process pressure is 5~10 mTorr;

[0030] And / or, in the second filling step, the deposition rate is 10~14 nm / min, the gas flow rate is 100~150 sccm, and the process pressure is 10~2000 mTorr.

[0031] Preferably, as one possible implementation, in the first filling step, the filling height of the insulating material is 40-60% of the trench depth.

[0032] Preferably, as one possible implementation, the insulating material is SiO2;

[0033] And / or, the substrate is a silicon substrate.

[0034] Preferably, as one possible implementation, in the first filling step, the process gas includes SiH4 and O2, wherein the volume percentage of SiH4 is 70-80% and the volume percentage of O2 is 20-30%.

[0035] And / or, in the second filling step, the process gas includes SiH4 and O2, wherein the volume percentage of SiH4 is 70-80% and the volume percentage of O2 is 20-30%.

[0036] Preferably, as one possible implementation, prior to the filling step, the process further includes:

[0037] In the deposition step, a SiON layer is deposited on the inner wall of the trench.

[0038] Preferably, as one possible implementation, after the filling step, the process further includes:

[0039] The annealing step involves plasma annealing in a nitrogen atmosphere.

[0040] Preferably, as one possible implementation, in the annealing step, the radio frequency power is 200~400W, the process temperature is 400~500℃, and the process duration is 20~40s.

[0041] Preferably, as one possible implementation, after the filling step, the process further includes:

[0042] In the planarization step, excess portion of the top of the insulating material is removed by chemical mechanical polishing so that the top of the insulating material is flush with the peripheral structure of the trench.

[0043] Preferably, as one possible implementation, before the first etching step, the process further includes:

[0044] The masking step involves depositing a hard mask layer on the substrate.

[0045] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0046] The shallow trench isolation structure provided by this invention has a bottom width greater than the top width, gradually transitioning through a trapezoidal opening. On one hand, this delays premature closure of the top material, allowing for wider compatibility with filling processes (such as subsequent annealing or CMP steps). This optimizes the uniformity and density of the subsequent insulation structure, reduces residual stress caused by insulation shrinkage, lowers the filling defect rate, and enhances breakdown voltage. On the other hand, it reduces microvoids or seams generated during filling, thereby improving the electrical reliability of the shallow trench isolation structure. Furthermore, it allows for better control of the trench shape and depth, helping to reduce edge effects and leakage current, enhancing isolation, suppressing parasitic capacitance and leakage current, and improving device reliability. In addition, the trapezoidal opening gradually narrows from the inside out, creating a mechanical interlocking structure between the trench sidewalls and the internal insulation material, which improves interfacial bonding strength and fracture toughness, further enhancing device reliability.

[0047] Therefore, the shallow trench isolation structure provided by the present invention has a low filling defect rate, and while maintaining process compatibility, it significantly improves the reliability and yield of shallow trench isolation, and has high industrialization value.

[0048] The process method for the shallow trench isolation structure provided by the present invention can produce the above-mentioned shallow trench isolation structure, and therefore has all the technical effects of the above-mentioned shallow trench isolation structure, which will not be repeated here. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0050] Figure 1 This is a cross-sectional schematic diagram of a shallow trench isolation structure in related technologies;

[0051] Figure 2 This is a schematic diagram of the principle structure of the trench in the shallow trench isolation structure provided in the embodiment of the present invention;

[0052] Figure 3 This is a cross-sectional view of the trench in the shallow trench isolation structure provided in an embodiment of the present invention;

[0053] Figure 4 This is a cross-sectional view of the shallow trench isolation structure provided in an embodiment of the present invention;

[0054] Figure 5 This is another cross-sectional view of the shallow trench isolation structure provided in an embodiment of the present invention;

[0055] Figure 6 A first schematic flowchart of the process method for the shallow trench isolation structure provided in the embodiment of the present invention;

[0056] Figure 7 This is a second schematic flowchart of the process method for the shallow trench isolation structure provided in an embodiment of the present invention;

[0057] Figure 8 This is a schematic diagram of the process equipment provided in an embodiment of the present invention. Detailed Implementation

[0058] In related technologies, the trench shape of shallow trench isolation structures is usually U-shaped (e.g., Figure 1 As shown in the figure, the trench is either V-shaped or has poor isolation effect and a high filling defect rate. Chemical vapor deposition (CVD) is usually used to fill the trench with oxides, which easily creates voids. This problem is more prominent in trenches with a high depth-to-width ratio.

[0059] Based on this, embodiments of the present invention provide a shallow trench isolation structure and its process method and equipment. By setting the top of the trench as a trapezoidal opening structure and filling the trench with insulating material in two steps, stress concentration can be reduced, filling uniformity can be optimized, filling defect rate can be reduced, and device reliability can be improved.

[0060] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0062] See Figures 2-5 An embodiment of the present invention provides a shallow trench isolation structure, which includes a trench 100 and a filling structure 200; the bottom of the trench 100 has a vertical sidewall 110, the top of the trench 100 is a trapezoidal opening 120, the trapezoidal opening gradually expands from the outside to the inside, and the inclined sidewall 121 of the trapezoidal opening 120 intersects with the vertical sidewall 110; the filling structure fills the trench.

[0063] The shallow trench isolation structure provided in this embodiment has a bottom width greater than the top width of the trench 100, which gradually transitions through a trapezoidal opening 120. On the one hand, this delays premature closure of the top material, allowing for compatibility with a wider range of filling processes (such as subsequent annealing or CMP steps). This facilitates optimization of the filling uniformity and density of the subsequent insulation structure, reduces residual stress caused by the shrinkage of the insulation structure 200, lowers the filling defect rate, and enhances the breakdown voltage. On the other hand, it reduces microvoids or seams generated during filling, thereby improving the electrical reliability of the shallow trench isolation structure. Furthermore, it allows for better control of the shape and depth of the trench 100, helping to reduce edge effects and leakage current, enhance isolation performance, suppress parasitic capacitance and leakage current, and improve device reliability. In addition, the trapezoidal opening 120 gradually narrows from the inside out, allowing the trench sidewalls and their internal filling structure 200 to form a mechanical interlocking structure, which helps improve the interface bonding strength and fracture toughness, further enhancing device reliability.

[0064] Therefore, the shallow trench isolation structure provided in this embodiment has a low filling defect rate, and while maintaining process compatibility, it significantly improves the reliability and yield of shallow trench isolation, and has high industrialization value.

[0065] Specifically, the ratio of the difference between the inner and outer widths of the trapezoidal opening 120 to the width of the outer end can be set to 20-30%, which is equivalent to increasing the bottom size of the trench 100 by 20-30%. This can significantly enhance the electrical isolation effect between adjacent devices, suppress parasitic capacitance and leakage current, and enhance reliability.

[0066] Specifically, see Figure 2The inclination angle α of the inclined sidewall 121 of the trapezoidal opening 120 can be set to 10°~30°, which can effectively delay the corner closure during the filling process, reduce the risk of keyhole or crack formation, and thus reduce the sudden change in local stress caused by voids.

[0067] Preferably, the vertical sidewall 110 and bottom wall 130 of the trench 100 are smoothly transitioned by an arc-shaped corner 140. Compared with the sharp corner of the trench bottom in related technologies, the arc-shaped corner 140 disperses the mechanical stress caused by thermal expansion or mechanical load at the trench edge, alleviates the stress concentration problem, and reduces the risk of substrate cracks or isolation layer delamination caused by stress concentration. It is particularly effective in applications with high aspect ratios (such as 20:1). In addition, the arc-shaped corner 140 can also prevent the collision ionization of charge carriers at the sharp corner, reduce the electric field concentration effect, and improve the breakdown voltage and leakage characteristics of the isolation structure.

[0068] Specifically, see Figure 2 The radius of curvature R of the 140° arc corner can be set to 5~20nm, which can reduce stress by 30~50%, with better stress dispersion effect and can effectively reduce electric field concentration effect.

[0069] Preferably, see Figure 4 A SiON layer 300 is attached to the inner wall of the trench 100. The SiON layer 300 forms a trap level through nitrogen doping, which can effectively capture charge carriers and suppress leakage current on the inner wall of the trench 100. It also has high density, which can suppress oxygen vacancy defects and impurity diffusion. In addition, since the stress characteristics of SiON are between those of Si3N4 and SiO2, it is more compatible with the thermal expansion coefficient of the silicon substrate. Therefore, it can reduce the risk of cracks or voids in the insulating structure 200 caused by thermal expansion mismatch, which is beneficial to reducing the filling defect rate.

[0070] Based on the above structure, the stress of the shallow trench isolation structure can be reduced by 30%-50%. The shallow trench isolation structure in this embodiment was subjected to a 1000-hour high-temperature reverse bias (HTRB) test, and no stress-induced failure was found, demonstrating high reliability.

[0071] Figure 6 A schematic flowchart of a process method for a shallow trench isolation structure is provided as an embodiment of the present invention. The process method includes:

[0072] S102, the first etching step, introduces process gas into the process chamber to generate plasma, which is then used to vertically bombard the substrate to form the initial morphology of the trench; wherein, the initial morphology of the trench is U-shaped.

[0073] S104, the second etching step, gradually adjusts the bombardment angle of the plasma to bombard the bottom of the trench sidewall at an angle, so as to widen the bottom of the trench and form a vertical sidewall.

[0074] By adjusting the bombardment angle of the plasma, it is possible to tilt and bombard the sidewalls at different heights at the bottom of the trench, so as to form a vertical sidewall 110 of a certain height after the bottom of the trench is widened.

[0075] S106, the third etching step, reduces the radio frequency power and gradually adjusts the bombardment angle of the plasma to bombard the top of the sidewall of the trench at an angle to form a trapezoidal opening.

[0076] S108, Filling step, filling the trench with insulating material.

[0077] By adjusting the bombardment angle of the plasma, it is possible to tilt and bombard the sidewalls at different heights on the top of the trench to form a trapezoidal opening 120 at the top of the trench.

[0078] The process method provided in this embodiment can produce the above-mentioned shallow trench isolation structure, and therefore has all the technical effects of the shallow trench isolation structure.

[0079] Select a silicon substrate as the substrate.

[0080] In the first etching step, a fluorine-based gas can be introduced as a process gas. The fluorine-based gas can chemically react with the silicon material to generate volatile silicon fluoride gas, which can regulate the silicon etching rate. Cl2 can also be introduced as a process gas, as Cl2 enhances anisotropic etching, which is beneficial for forming steep sidewalls. HBr can also be introduced as a process gas, as HBr helps suppress lateral etching to obtain an initial trench morphology with the target width. O2 can also be introduced as a process gas, as O2 can react with the fluorine-based gas to generate a fluoropolymer, which can regulate the deposition rate of the fluoropolymer. This fluoropolymer, deposited on the mask layer, can suppress etching of the mask layer. Specifically, SF6 can be selected as the fluorine-based gas, with the volume ratio of SF6 to O2 set to 2:1 to 4:1, and the volume ratio of Cl2, HBr, and O2 set to (0.8 to 1.2):(1.8 to 2.2):(0.4 to 0.7), preferably 1:2:0.5. Among them, the flow rate of O2 is positively correlated with the deposition rate of fluoropolymers.

[0081] In the second etching step, a fluorine-based gas can be introduced as a process gas. The chemical reaction between the fluorine-based gas and the silicon material has high selectivity and a high etching rate. When the plasma bombards the bottom of the sidewall of the trench 100, it can remove the silicon material at the bottom of the trench 100, thereby widening the bottom of the trench 100 and forming an arc-shaped corner 140 between the vertical sidewall 110 and the bottom wall 130. Cl2 can also be introduced as a process gas to smoothly form the vertical sidewall 110 at the bottom of the trench 100. HBr can also be introduced as a process gas to obtain the trench 100 with the target width. O2 can also be introduced as a process gas. The fluorinated polymer generated by the reaction of O2 with the fluorine-based gas can cover the surface of the sidewall of the trench 100 to smooth the micro-undulations and reduce the roughness of the sidewall. Specifically, SF6 can be used as the fluorine-based gas, and the volume ratio of SF6 to O2 can be set to 2:1 to 4:1, which can control the roughness of the vertical sidewall 110 at the bottom of the groove 100 to below 2 mm; the volume ratio of Cl2, HBr and O2 can be set to (0.8~1.2):(1.8~2.2):(0.4~0.7), preferably 1:2:0.5.

[0082] In the third etching step, a fluorine-based gas can be introduced as a process gas. The fluorine-based gas can chemically react with the silicon material to generate volatile silicon fluoride gas. Cl2 can also be introduced as a process gas to smoothly form the inclined sidewall 121 of the top trapezoidal opening 120. HBr can also be introduced as a process gas to obtain the inclined sidewall 121 with the target tilt angle. O2 can also be introduced as a process gas; the fluorinated polymer generated by the reaction of O2 with the fluorine-based gas can cover the inner wall surface of the trench to smooth microscopic undulations and reduce the roughness of the inner wall. Specifically, SF6 can be selected as the fluorine-based gas, and the volume ratio of SF6 to O2 can be set to 2:1 to 4:1 to control the roughness of the inclined sidewall 121 of the trapezoidal opening 120 to below 2 mm. The volume ratio of Cl2, HBr, and O2 can be set to (0.8~1.2):(1.8~2.2):(0.4~0.7), preferably 1:2:0.5.

[0083] As one possible implementation, in the second etching step, the plasma bombardment angle is gradually increased, and the bottom of the trench sidewall is bombarded obliquely from bottom to top to widen the bottom of the trench and form the aforementioned vertical sidewall 110. Correspondingly, in the third etching step, the plasma bombardment angle is gradually increased, and the top of the trench sidewall is bombarded obliquely from bottom to top to form a trapezoidal opening 120.

[0084] In the second etching step, the radio frequency (RF) power can be set to 1200~1500W. At this high RF power, the silicon material at the bottom of the trench can be removed preferentially. The high RF power combined with fluorine-based gas can quickly remove the silicon material at the bottom of the trench.

[0085] In the third etching step, the radio frequency power can be set to 200~300W. At this low radio frequency power, the bombardment intensity of the plasma is weakened, making the etching rate at the top of the trench lower than the etching rate at the bottom, thus forming a conical transition.

[0086] The filling step may include the following steps: a first filling step, in which an insulating material is generated by high-density plasma chemical vapor deposition to fill the bottom of the trench; and a second filling step, in which an insulating material is generated by fluidized chemical vapor deposition to fill the remaining portion of the trench.

[0087] In other words, during the initial filling stage, high-density plasma-enhanced chemical vapor deposition (HDPCVD) is used to produce insulating material, preferentially filling the bottom of trench 100 to achieve uniform coverage of the bottom of trench 100. After filling trench 100 to a certain height using HDPCVD, the deposition method is changed to fluidized chemical vapor deposition (FCVD) to utilize fluid properties to eliminate the bottleneck effect at the top, achieving uniform coverage of the top of trench 100. Figure 4 As shown, the area below the dashed line within the trench 100 is filled with insulating material using HDPCVD, while the area above the dashed line within the trench 100 is filled with insulating material using FCVD. By using different deposition methods to fill the bottom and top of the trench 100 in stages, void formation can be avoided, improving the uniformity of the insulating material coverage of the trench 100, which is beneficial for further reducing the filling defect rate and improving device reliability.

[0088] In the first filling step, setting the deposition rate to 3~6 nm / min, the gas flow rate to 300 sccm or higher, and the process pressure to 5~10 mTorr can achieve uniform coverage of the bottom of the trench 100.

[0089] In the second filling step, the deposition rate is increased to 10~14 nm / min, the gas flow rate is reduced to 100~150 sccm, and the process pressure is increased to 100~2000 mTorr, which can achieve uniform coverage of the top of the trench 100.

[0090] In the first filling step, the filling height of the insulating material is set to 40-60% of the depth of the trench 100. That is, after the HDPCVD-deposited insulating material fills the bottom of the trench 100 to 40-60% of the depth of the trench 100, the FCVD-deposited insulating material fills the remaining trench 100, which can achieve a good filling effect.

[0091] Specifically, the substrate can be a silicon substrate, and SiO2 can be used as an insulating material. The thermal expansion coefficients of SiO2 and silicon substrate are well matched, which can reduce the risk of cracks or voids caused by thermal expansion mismatch in the insulating material filled in the trench 100, and help reduce the filling defect rate.

[0092] In the first filling step, a mixture of SiH4 and O2 can be used as the process gas, with the volume percentage of SiH4 set to 70-80% and the volume percentage of O2 set to 20-30%. Its high fluidity is beneficial to improving the uniformity of the insulation material's coverage of the bottom of the trench 100.

[0093] Correspondingly, in the second filling step, a mixture of SiH4 and O2 can also be used as the process gas, with the volume percentage of SiH4 set to 70-80% and the volume percentage of O2 set to 20-30%. This also helps to improve the uniformity of the insulation material covering the top of the trench 100.

[0094] In semiconductor manufacturing, liner oxidation (STI) is a key step. It's used to grow a thin oxide layer (e.g., SiO2) on the surface of trench 100 before filling it with insulating material (e.g., HDPCVD SiO2). This repairs surface damage caused by trench 100 etching, reduces interface defects, and improves the adhesion and electrical properties of subsequent insulating materials. In related technologies, a high-temperature (typically above 900°C) thermal oxidation process is used to generate a SiO2 layer on the trench surface, buffering thermal stress between the mask and substrate and repairing surface damage caused by dry etching (RIE). Then, a low-temperature plasma-assisted oxidation technique is used, employing plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to generate a SiO2 layer at low temperatures (200~400°C) to reduce thermal stress. Finally, a two-step chemical mechanical polishing (CMP) process is used to control the uniformity of the oxide layer thickness (deviation <5%) to avoid the bird's beak effect. However, this technology requires high-temperature operation, which can easily lead to changes in substrate material properties, mismatch in thermal expansion coefficients, lattice defects and leakage problems, affecting device reliability, high thermal budget, and limiting compatibility with advanced processes.

[0095] Based on this, the process method has been improved in this embodiment. Before the filling step, the process method provided in this embodiment further includes a deposition step, in which a SiON layer 300 is deposited on the inner wall of the trench 100.

[0096] It should be noted that the material properties of SiON (such as adhesion and flowability) support uniform deposition on the inner walls of trenches with high aspect ratios 100, eliminating the need for additional photolithography steps to correct filling defects or adjust morphology, and eliminating the need for chemical mechanical polishing. This avoids mechanical stress damage to the SiON layer 300. The deposition temperature of SiON is lower than that of traditional high-temperature oxidation processes, avoiding the damage to sensitive structures such as ultra-thin gate oxide layers and strained silicon in advanced processes caused by high-temperature (>900℃) thermal oxidation (such as interface defects or uncontrolled doping diffusion). This helps maintain the matching of substrate material properties and coefficient of thermal expansion, reduces lattice defects and leakage current problems, has a smaller impact on device reliability, helps reduce thermal budget, is compatible with advanced processes (such as 40nm and below), and helps save costs.

[0097] Following the filling step, the process method provided in this embodiment may further include an annealing step, in which plasma annealing is performed in a nitrogen environment, which can improve the compactness of the completed shallow trench isolation structure.

[0098] In the annealing step, the RF power can be set to 200~400W, the process temperature to 400~500℃, and the process duration to 20~40s. Under these process conditions, the density of the isolation material can be increased to over 2.2g / cm³, while the density of the isolation material after traditional high-temperature annealing can only reach 2.0g / cm³. Therefore, using the annealing process provided in this embodiment to anneal the shallow trench isolation structure can achieve a higher density of the isolation material, and the lower process temperature is beneficial for maintaining the substrate material properties and thermal expansion coefficient matching, reducing lattice defects and leakage problems, having a smaller impact on device reliability, and helping to reduce the thermal budget.

[0099] Following the filling step, the process method provided in this embodiment may further include a planarization step, in which excess portion of the top of the insulating material is removed by chemical mechanical polishing, so that the top of the insulating material is flush with the peripheral structure 400 of the trench 100, thereby avoiding gate short circuits or parasitic capacitance problems in subsequent processes. Specifically, the standard for the top of the insulating material to be flush with the peripheral structure 400 of the trench 100 can be that the height difference between the two is less than or equal to 3 mm.

[0100] By using the above-described process to fill the trench 100 of the shallow trench isolation structure, a filling defect rate of <0.1% can be achieved. Compared with the 1-5% filling defect rate in traditional processes, the filling defect rate is significantly reduced, enhancing reliability. The leakage current of the shallow trench isolation structure can be reduced by more than 50%, the device leakage current by more than 20%, the isolation voltage between adjacent devices is greater than 20V, and the leakage current is reduced to 1nA / μm.

[0101] Prior to the first etching step, the process method provided in this embodiment further includes a masking step, in which a hard mask layer is deposited on the substrate. The hard mask layer has a patterned structure adapted to the top of the trapezoidal opening 120. Under the protection of the hard mask layer, the substrate is bombarded to form the trench 100 of the shallow trench isolation structure described above.

[0102] Figure 7 A process method provided in one embodiment of the present invention includes:

[0103] S201, Trench Etching and Morphology Optimization

[0104] A hard mask layer is deposited on a silicon substrate, and a trench 100 is formed by dry etching. By adjusting the ratio of etching gases (SF6, Cl2, HBr, O2) and radio frequency power, the arc-shaped corner 140 at the bottom of the trench 100 and the trapezoidal opening 120 at the top of the trench 100 are controlled.

[0105] S202, multi-step filling process

[0106] First filling stage: HDPCVD deposition of SiO2 to fill 40-60% of the bottom of trench 100 to the depth of trench 100; Second filling stage: FCVD deposition of SiO2 to fill the remaining trench 100.

[0107] S203, low-temperature densification treatment

[0108] Plasma annealing is performed in a nitrogen atmosphere.

[0109] S204, Flattening and Post-processing

[0110] Chemical mechanical polishing (CMP) removes excess oxides while preserving the isolation structure; selective wet etching adjusts the height of the isolation layer, making the top of the insulating material flush with the hard mask layer to avoid gate short circuits or parasitic capacitance problems in subsequent processes.

[0111] This invention can employ SAQP (Self-Aligned Quadruple Patterning) and STI etching methods from related technologies.

[0112] Figure 8 A process apparatus 200, provided as an embodiment of the present invention, includes a process chamber 20, an air inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller (not shown in FIG9). The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method of any of the above embodiments.

[0113] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air inlet assembly 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the flow rate of the process gas by controlling the opening and closing degree of the valve of the air inlet assembly 20A. The controller can also control the evacuation assembly 20D to evacuate the process chamber 20, thereby controlling the gas pressure inside the process chamber 20 and removing reaction byproducts.

[0114] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matching unit 25. The controller is also used to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 through the upper matching unit 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0115] The lower electrode assembly 20C includes a carrier device 22, a lower RF power supply 24, and a lower matching unit 26. The controller further controls the lower RF power supply 24 to provide lower electrode power to the lower electrode of the carrier device 22 through the lower matching unit 26, thereby providing an RF bias voltage to the lower electrode of the carrier device 22 to attract plasma above the object to be etched and bombard it. The wafer carrier device 22 can be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.

[0116] The process equipment 200 in this application embodiment can be either an inductively coupled plasma (ICP) process equipment or a capacitively coupled plasma (CCP) process equipment. This application embodiment does not limit the type of process equipment 200.

[0117] The process equipment provided in this embodiment of the invention has the same technical features as the process method for the shallow trench isolation structure provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0118] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions cause the processor to implement the above-described shallow trench isolation structure process.

[0119] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0120] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, and read-only memory (ROM). Various media that can store program code, such as random access memory (RAM), magnetic disks, or optical disks.

[0121] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing process for a shallow trench isolation structure, characterized in that, The process includes: In the first etching step, process gas is introduced into the process chamber to generate plasma, which is then used to vertically bombard the substrate to form the initial morphology of the trench; wherein the initial morphology of the trench is U-shaped. In the second etching step, the bombardment angle of the plasma is gradually adjusted to bombard the bottom of the sidewall of the trench at an angle, so as to widen the bottom of the trench and form a vertical sidewall. In the third etching step, the radio frequency power is reduced and the bombardment angle of the plasma is gradually adjusted to bombard the top of the sidewall of the trench at an angle to form a trapezoidal opening. The filling step involves filling the trench with insulating material.

2. The process method according to claim 1, characterized in that, The substrate is a silicon substrate; In the first etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2; and / or, in the second etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2; and / or, in the third etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr, and O2.

3. The process method according to claim 2, characterized in that, In the first etching step, the fluorine-based gas includes SF6, with a volume ratio of SF6 to O2 of 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7). And / or, in the second etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7). And / or, in the third etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7).

4. The process method according to claim 1, characterized in that, The second etching step includes: gradually increasing the bombardment angle of the plasma, and obliquely bombarding the bottom of the sidewall of the trench from bottom to top to widen the bottom of the trench and form the vertical sidewall; And / or, the third etching step includes: gradually increasing the bombardment angle of the plasma to obliquely bombard the top of the sidewall of the trench from bottom to top to form the trapezoidal opening.

5. The process method according to claim 1, characterized in that, In the second etching step, the radio frequency power is 1200~1500W; And / or, in the third etching step, the radio frequency power is 200~300W.

6. The process method according to any one of claims 1-5, characterized in that, The filling step includes: In the first filling step, an insulating material is generated by high-density plasma chemical vapor deposition to fill the bottom of the trench; The second filling step involves generating the insulating material via fluidized chemical vapor deposition to fill the remaining portion of the trench.

7. The process method according to claim 6, characterized in that, In the first filling step, the deposition rate is 3~6 nm / min, the gas flow rate is above 300 sccm, and the process pressure is 5~10 mTorr; And / or, in the second filling step, the deposition rate is 10~14 nm / min, the gas flow rate is 100~150 sccm, and the process pressure is 10~2000 mTorr.

8. The process method according to claim 6, characterized in that, In the first filling step, the filling height of the insulating material is 40-60% of the trench depth.

9. The process method according to claim 6, characterized in that, The insulating material is SiO2; And / or, the substrate is a silicon substrate.

10. The process method according to claim 9, characterized in that, In the first filling step, the process gas includes SiH4 and O2, wherein the volume percentage of SiH4 is 70-80% and the volume percentage of O2 is 20-30%. And / or, in the second filling step, the process gas includes SiH4 and O2, wherein the volume percentage of SiH4 is 70-80% and the volume percentage of O2 is 20-30%.

11. The process method according to any one of claims 1-5, characterized in that, Prior to the filling step, the process method further includes: In the deposition step, a SiON layer is deposited on the inner wall of the trench.

12. The process method according to any one of claims 1-5, characterized in that, Following the filling step, the process method further includes: The annealing step involves plasma annealing in a nitrogen atmosphere.

13. The process method according to claim 12, characterized in that, In the annealing step, the radio frequency power is 200~400W, the process temperature is 400~500℃, and the process time is 20~40s.

14. The process method according to any one of claims 1-5, characterized in that, Following the filling step, the process method further includes: In the planarization step, excess portion of the top of the insulating material is removed by chemical mechanical polishing so that the top of the insulating material is flush with the peripheral structure of the trench.

15. The process method according to any one of claims 1-5, characterized in that, Prior to the first etching step, the process method further includes: In the masking step, a hard mask layer is deposited on the substrate.

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