Board-level fan-out type packaging structure and manufacturing method thereof

Abstract

The invention provides a board-level fan-out type packaging structure and a manufacturing method thereof, the board-level fan-out type packaging structure comprises a protection structure, a chip and a first insulation passivation layer on a chip wafer segment are packaged in the protection structure, the protection structure is provided with a through hole penetrating through the protection structure, and the first insulation passivation layer is arranged on the chip wafer segment. Adding layers on the front and back surfaces of the protection structure and filling through holes to form a rewiring layer with the front and back surfaces interconnected, wherein the front and back surfaces of the rewiring layer are interconnected to realize the front and back surface interconnection of the chip; direct interconnection of the front and back double-sided rewiring layers is realized through the through holes penetrating through the protection structure, the problem of depth-to-width ratio interconnection defect limitation of traditional blind hole electroplating is avoided, the double-sided rewiring layers are symmetrically distributed, so that thermal stress is balanced, the warping degree is reduced, the stability of the structure is improved, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a board-level fan-out packaging structure and a manufacturing method thereof. Background Art

[0002] As an iterative technology derived from wafer-level fan-out (WLF) packaging, plate-level fan-out (BFL) packaging has largely addressed the high cost of WLF. Wafer-level fan-out packaging primarily utilizes semiconductor-grade packaging materials, equipment, and corresponding design rules, resulting in high packaging costs. Consequently, it has been primarily used for high-end integrated circuits such as CPUs, GPUs, and APEs. Due to cost constraints, mid-range and low-end integrated circuits have traditionally used packaging formats such as wire bond and QFN, making further performance improvements difficult. The emergence of board-level fan-out packaging technology offers a perfect balance between cost and performance for mid-range and low-end integrated circuits: improving product performance while further reducing costs. Currently, BFL packaging faces challenges such as chip warpage and long die bonding times, and it cannot implement double-sided interconnects. The industry has struggled to find effective solutions to these issues, and few process solutions have been implemented on a large scale.

[0003] Currently, two-sided interconnection is achieved in the following ways:

[0004] 1. Laser drilling of blind vias followed by electroplating to achieve metallization. This method cannot achieve structures with high aspect ratios because it uses blind vias. This is because the smaller and deeper the blind vias, the more difficult it is to drill. In addition, it is difficult for the electroplating solution to circulate fully in blind vias with high aspect ratios, making effective via filling impossible. The limited fluidity of the electroplating solution in blind vias with high aspect ratios leads to abnormal additive concentration gradient distribution, destroying the super-conformal via filling pattern, resulting in incomplete filling at the bottom of the vias and even forming voids. The uneven electric field distribution at the bottom of the blind vias leads to asynchronous electroplating copper deposition rates and insufficient current density at the bottom of deep vias, exacerbating the risk of incomplete filling. Blind vias with high aspect ratios require strict control of laser energy. Insufficient energy leads to residual resin at the bottom of the vias, while excessive energy causes carbonization of the substrate, affecting the reliability of subsequent metallization.

[0005] 2. The interconnected copper pillars are first made through photolithography and electroplating, and then the copper pillars are exposed by plastic sealing and grinding. This method introduces customized thickness photoresist and grinding process, which brings about the problem of a significant increase in production costs.

[0006] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of this application. Summary of the Invention

[0007] In order to solve the technical problems of high aspect ratio blind hole interconnection defects in the existing technology, high cost of double-sided interconnection process and insufficient structural stability, the present invention proposes a board-level fan-out packaging structure and a manufacturing method thereof. Direct interconnection of the front and back double-sided redistribution layers is achieved by through holes penetrating the protective structure, avoiding the aspect ratio interconnection defect limitation problem of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances the thermal stress and reduces the warpage, which not only improves the stability of the structure but also reduces the production cost.

[0008] In order to achieve the above object, the technical solution of the present invention is as follows:

[0009] On the one hand, the present invention provides a board-level fan-out packaging structure, comprising: a protective structure, wherein a chip and a first insulating passivation layer on the chip wafer segment are encapsulated in the protective structure, the protective structure is provided with a through hole penetrating the protective structure, the front and back sides of the protective structure are layered and the through hole is filled to form a redistribution layer interconnected on both sides, and the front and back sides of the redistribution layer are interconnected to achieve front and back interconnection of the chip.

[0010] The present invention proposes a board-level fan-out packaging structure and a manufacturing method thereof, which realizes direct interconnection of the front and back double-sided redistribution layers by through holes penetrating the protective structure, avoiding the depth-to-width ratio interconnection defect limitation problem of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances the thermal stress and reduces the warping, which not only improves the stability of the structure but also reduces the production cost.

[0011] As a preferred technical solution, passive components are also encapsulated in the protection structure.

[0012] As a preferred technical solution, a plurality of windows are provided on the first insulating passivation layer, and the positions of the windows correspond to the positions of the pads on the chip to achieve connection between the pads on the chip and the redistribution layer on the reverse side.

[0013] As a preferred technical solution, a front and back second insulating passivation layer is provided on the front and back redistribution layers, and the second insulating passivation layer is provided with an external connection window.

[0014] As an optimal technical solution, a first external interconnection metal layer is provided on the front and back second insulating passivation layers, a second external interconnection metal layer is provided on the first external interconnection metal layer, and the first external interconnection metal layer is connected to the redistribution layer through an external connection window.

[0015] On the other hand, the present invention provides a method for manufacturing a board-level fan-out packaging structure, which manufactures a board-level fan-out packaging structure as described in any one of the above items, comprising the following manufacturing steps:

[0016] S1 forms a first insulating passivation layer on the active surface of the chip wafer segment and opens windows corresponding to the chip pads, and then thins and cuts it into single chips;

[0017] S2: a temporary bonding layer is provided on the carrier board, and the first insulating passivation layer on the chip is attached to the temporary bonding layer;

[0018] S4 performs plastic encapsulation on the combined structure to form a protective structure and then removes the temporary bonding layer and the carrier board;

[0019] S5 forms a through hole on the protection structure, and simultaneously forms interconnected front and back redistribution layers through double-sided electroplating to achieve front and back interconnection of the chip.

[0020] As a preferred technical solution, in step S5, the interconnected redistribution layers on the front and back sides are simultaneously formed by double-sided electroplating to realize the interconnection between the front and back sides of the chip, which specifically includes the following steps:

[0021] forming a seed layer on the upper surface of the protection structure having the through-hole;

[0022] forming a photoresist layer on the seed layer, wherein the photoresist layer has a photoresist layer window;

[0023] The photoresist layer windows and through-holes are filled simultaneously through a double-sided electroplating process to form a redistribution layer with interconnections on the front and back sides.

[0024] As a preferred technical solution, the double-sided electroplating process utilizes through-holes to achieve double-sided circulation and exchange of electroplating solution, and simultaneously forms a redistribution layer interconnected on both sides.

[0025] As an optimal technical solution, the following steps are also included:

[0026] S6: forming a second insulating passivation layer on the front and back surfaces of the redistribution layer and opening an external connection window;

[0027] S7 repeatedly constructs a multi-layer metal interconnection structure on the second insulating passivation layer and connects it to the redistribution layer through the external connection window to achieve double-sided signal extraction.

[0028] As a preferred technical solution, step S2 further includes the following steps: synchronously mounting the passive components and the chip on the temporary bonding layer.

[0029] The present invention provides a board-level fan-out packaging structure and a manufacturing method thereof, which have the following beneficial effects:

[0030] 1) The present invention provides a board-level fan-out packaging structure and a manufacturing method thereof. Through holes penetrating the protective structure, direct interconnection of redistribution layers on both sides is achieved, avoiding the aspect ratio interconnection defect limitation of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances thermal stress and reduces warpage, thereby improving structural stability and reducing production costs.

[0031] 2) The present invention provides a board-level fan-out packaging structure and a manufacturing method thereof. Through holes penetrating the protective structure, direct interconnection of the front and back redistribution layers (RDL) is achieved. This circumvents the aspect ratio limitations of traditional blind via electroplating. The through-hole structure allows bidirectional flow of the plating solution, ensuring complete metal filling within the hole (void ratio <0.1%). This formation of the front and back redistribution layers reduces interconnection resistance by over 40%, achieving high-reliability double-sided interconnection.

[0032] Compared with wafer-level fan-out packaging, the use of board-level plastic encapsulation materials and electroplating processes eliminates the need to first produce interconnected copper pillars through photolithography and electroplating, and then plastic encapsulate and polish to expose the copper pillars. The introduction of customized thickness photoresist and polishing processes reduces production costs.

[0033] The symmetrical distribution of double-sided redistribution layers balances thermal stress, reduces warpage to <50μm / m, and improves structural stability.

[0034] 2) The present invention provides a board-level fan-out packaging structure and a manufacturing method thereof. This structure incorporates a through-hole structure into the board-level fan-out package, and builds up layers on both sides of the protective structure to form a redistribution layer for interconnection on both the front and back sides. This mitigates the warping problem caused by traditional single-sided packaging. This double-sided buildup of layers on the protective structure to form a redistribution layer for interconnection on both the front and back sides significantly reduces the chip packaging cycle time (CT) while also enabling front- and back-side interconnection of the chip.

[0035] The pre-passivation treatment on the chip wafer segment forms a first insulating passivation layer, which solves the problem of interconnect window accuracy in the subsequent redistribution layer (RDL) build-up stage caused by the drift problem of the embedded chip after plastic packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic structural diagram of a board-level fan-out packaging structure provided by the present invention;

[0037] Figure 2A structural diagram of step S1 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0038] Figure 3 A structural diagram of step S2 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0039] Figure 4 A structural diagram of step S3 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0040] Figure 5 A structural diagram of step S4 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0041] Figure 6 A structural diagram of step S5 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0042] Figure 7 A structural diagram of step S6 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0043] Figure 8 A structural diagram of step S7 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0044] Figure 9 A structural diagram of step S8 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0045] Figure 10 A structural diagram of step S9 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0046] Figure 11 A structural diagram of step S10 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0047] Figure 12 A structural diagram of step S11 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0048] Figure 13 A structural diagram of step S12 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0049] Figure 14 A structural diagram of step S13 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0050] Figure 15A structural diagram of step S14 of a method for manufacturing a board-level fan-out packaging structure provided in Example 1;

[0051] Among them, 100-carrier; 200-temporary bonding layer; 300-chip; 310-first insulating passivation layer; 320-window; 400-passive device; 500-protection structure; 600-through hole; 700-photoresist layer; 710-photoresist layer window; 800-rewiring layer; 900-second insulating passivation layer; 910-external connection window; 1000-first external interconnection metal layer; 1100-second external interconnection metal layer. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] like Figure 1 As shown, the present invention provides a board-level fan-out packaging structure, including: a protection structure 500, wherein the protection structure 500 encapsulates a chip 300 and a first insulating passivation layer 310 on the wafer segment of the chip 300, the protection structure 500 is provided with a through hole 600 penetrating the protection structure, the protection structure 500 is layered on the front and back sides and filled with the through hole 600 to form a redistribution layer 800 interconnected on both sides, and the front and back sides of the redistribution layer 800 are interconnected to achieve front and back interconnection of the chip 300.

[0054] The present invention proposes a board-level fan-out packaging structure, which realizes direct interconnection of the front and back double-sided redistribution layers through through holes penetrating the protective structure, avoiding the depth-to-width ratio interconnection defect limitation problem of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances the thermal stress and reduces warping, which not only improves the stability of the structure but also reduces production costs.

[0055] Preferably, if Figure 1 As shown, the protection structure 500 also encapsulates a passive device 400; the passive device 400 is directly embedded in the protection structure 500, which can eliminate the parasitic effects brought by traditional external discrete components and optimize the signal transmission quality; the passive device 400 and the chip 300 are plastic-encapsulated synchronously to avoid the risk of interface delamination caused by traditional welding processes.

[0056] Preferably, if Figure 1As shown, a plurality of windows 320 are provided on the first insulating passivation layer 310, and the positions of the windows 320 correspond to the positions of the pads on the chip 300 to realize the connection between the pads on the chip 300 and the redistribution layer 800 on the reverse side; the positions of the windows 320 are strictly aligned with the pads of the chip 300, so that the pads on the chip 300 form a vertical interconnection path with the reverse redistribution 800 (RDL) through the through-holes 600, and the chip 300 I / O contacts are extended to both sides of the package. Compared with the traditional single-sided solution, the interconnection resistance is greatly reduced; the pad metal layer is exposed by the windows 320 to avoid the passivation insulating material from interfering with the transmission of electrical signals.

[0057] Preferably, if Figure 1 As shown, a second insulating passivation layer 900 is provided on the front and back sides of the redistribution layer 800, and the second insulating passivation layer 900 is provided with an external connection window 910. The second insulating passivation layer 900 exposes the pad area of ​​the redistribution layer 800 (RDL) through the opened external connection window 910, forming an interface connected to the external pin, ensuring the reliability of the signal transmission path and reducing the contact resistance.

[0058] Preferably, if Figure 1 As shown, a first external interconnection metal layer 1000 is provided on the front and back second insulating passivation layers 900, a second external interconnection metal layer 1100 is provided on the first external interconnection metal layer 1000, and the first external interconnection metal layer 1000 is connected to the redistribution layer 800 through an external connection window 910;

[0059] The first external interconnection metal layer 1000 directly contacts the redistribution layer 800 (RDL) through the external connection window 910, forming a low-impedance interconnection interface (contact resistance ≤ 0.5 mΩ·cm≤), thereby reducing signal transmission loss;

[0060] The second external interconnection metal layer 1100 increases the conductive cross-sectional area (thickness increased to 5-10 μm) on the basis of the first external interconnection metal layer 1000, and can carry a larger current density (≥5A / mm≤) to meet the needs of power devices.

[0061] On the other hand, Figure 2-15 As shown, the present invention provides a method for manufacturing a board-level fan-out packaging structure, which manufactures a board-level fan-out packaging structure as described in any of the above items, including the following manufacturing steps:

[0062] S1 forms a first insulating passivation layer 310 on the active surface of the chip 300 wafer segment and opens windows corresponding to the chip 300 pads, and then thins and cuts to form a single chip 300;

[0063] S2: a temporary bonding layer 200 is provided on the carrier 100, and the first insulating passivation layer 310 on the chip 300 is mounted on the temporary bonding layer 200;

[0064] S4 performs plastic encapsulation on the combined structure to form a protective structure, and then removes the temporary bonding layer 200 and the carrier 100;

[0065] S5: forming a through hole 600 on the protection structure 500, and simultaneously forming interconnected front and back redistribution layers 800 by double-sided electroplating to achieve front and back interconnection of the chip 300.

[0066] The present invention proposes a method for manufacturing a board-level fan-out packaging structure, which realizes direct interconnection of the front and back double-sided redistribution layers by through holes penetrating the protective structure, avoiding the depth-to-width ratio interconnection defect limitation problem of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances the thermal stress and reduces warping, which not only improves the stability of the structure but also reduces production costs.

[0067] Preferably, in step S5, the redistribution layer 800 on the front and back sides of the chip 300 is formed simultaneously by double-sided electroplating to realize the front and back interconnection, which specifically includes the following steps:

[0068] forming a seed layer (not shown) on the upper surface of the protection structure 500 having the through-hole 600;

[0069] A photoresist layer 700 is formed on the seed layer (not shown), and a photoresist window 710 is formed in the photoresist layer;

[0070] The photoresist layer opening 710 and the through hole 600 are simultaneously filled by a double-sided electroplating process to form a redistribution layer 800 with interconnections on the front and back sides;

[0071] The double-sided electroplating process ensures the geometric symmetry of the front- and back-side redistribution layers (RDLs) 800 by simultaneously filling the photoresist layer openings 710 and the through-holes 600, optimizing the consistency of signal transmission paths and reducing losses caused by impedance mismatch. Through-hole electroplating fills the through-holes 600 and combines them with the window wiring to form an interconnect structure that supports direct interconnection between the front and back electrodes of the chip 300, increasing interconnection density and achieving a high-precision symmetrical interconnect architecture.

[0072] The filling of the through-hole 600 and the surface wiring are completed simultaneously by a single double-sided electroplating, which reduces the process steps compared with the traditional single-sided layer-by-layer processing and significantly shortens the manufacturing cycle. The uniform conductive substrate design of the seed layer (not shown) is used to achieve the thickness uniformity of the redistribution layer 800 for interconnection between the front and back sides formed by electroplating, avoiding the risk of interface delamination caused by step-by-step processing, simplifying the process flow and improving efficiency.

[0073] Preferably, the double-sided electroplating process utilizes the through-hole 600 to realize the double-sided circulation exchange of the plating solution, and simultaneously forms a redistribution layer 800 interconnected on the front and back sides; the plating solution is realized to flow on both sides through the through-hole 600, and the through-hole 600 and the surface window are simultaneously filled to form a conductive channel running through the front and back sides, thereby realizing the three-dimensional interconnection architecture of the chip 300 and improving the interconnection density; the one-piece molded redistribution layer 800 (RDL) significantly reduces the interface contact resistance and optimizes the high-frequency signal transmission performance; the double-sided electroplating solution exchange mechanism on the front and back eliminates the concentration polarization phenomenon of traditional single-sided electroplating, reduces the thickness unevenness (CV value) of the redistribution layer 800 (RDL), and ensures the conductivity consistency of the circuit; synchronous deposition in the through-hole 600 avoids local bubble residue and reduces the micropore filling defect rate.

[0074] Preferably, the method further comprises the following steps:

[0075] S6: forming a second insulating passivation layer 900 on the front and back surfaces of the redistribution layer 800 and opening an external connection window 910;

[0076] S7 repeatedly constructs a multi-layer metal interconnection structure on the second insulating passivation layer 900 and connects it to the redistribution layer 800 through the external connection window 910 to achieve double-sided signal lead-out; the multi-layer metal interconnection structure is superimposed to construct a three-dimensional conductive network, and the interconnection density is improved to meet the requirements of 3D stacking packaging; through the precise alignment of the external connection window 910 and the redistribution layer 800, the contact resistance is reduced to support large current transmission.

[0077] Preferably, step S2 also includes the following steps: synchronously mounting the passive device 400 and the chip 300 on the temporary bonding layer 200; directly embedding the passive device 400 into the protective structure 500 to eliminate the parasitic effects brought by traditional external discrete components and optimize the signal transmission quality; and synchronously plastic-encapsulating the passive device 400 and the chip 300 to avoid the risk of interface delamination caused by traditional welding processes.

[0078] Example 1

[0079] The present invention provides a method for manufacturing a board-level fan-out packaging structure, comprising the following steps:

[0080] S1 Figure 2As shown, the chip is first passivated and insulated, and a first insulating passivation layer 310 is first formed on the active surface of the chip 300 wafer, and one or more windows 320 are formed on the first insulating passivation layer 310. The three-dimensional position of the window 320 corresponds to the pad position (not shown) on the chip 300: the first insulating passivation layer 310 is formed by methods including but not limited to coating photoresist, spraying photoresist, vacuum lamination, wafer-level plastic packaging, etc., and the corresponding window formation methods include but are not limited to exposure and development, laser drilling, etc.; after the passivation insulation and windowing processes are completed, the chip 300 wafer is thinned and cut to a specified thickness to form a single chip 300; in addition to packaging a single chip 300, this structure can also integrate various passive devices 400;

[0081] S2 Figure 3 As shown, a carrier 100 is prepared, and a temporary bonding layer 200 is formed on the carrier 100. The types of the carrier 100 include, but are not limited to, stainless steel carriers 100, glass carriers 100, plastic encapsulation material carriers 100, polymer carriers 100, metal alloy carriers 100, ceramic carriers 100, and other materials that can be used to serve as a support. The temporary bonding layer 200 includes, but is not limited to, release films, detachable double-sided tapes, pyrolytic films, and releasable temporary bonding adhesives.

[0082] S3 Figure 4 As shown, the single chip 300 and the passive device 400 in step S1 are mounted on the temporary bonding layer 200, wherein the active surface (i.e., the window surface) of the single chip 300 is in direct contact with the temporary bonding layer 200, and the active surface of the passive device 400 is also in contact with the temporary bonding layer 200;

[0083] S4 Figure 5 As shown, in Figure 4 On the basis of the above, the combined structure is protected by plastic encapsulation to form a protective structure 500. The protective plastic encapsulation method can be board-level plastic encapsulation, and the plastic encapsulation materials used include but are not limited to various powder materials, liquid materials and other plastic encapsulation materials. The protective plastic encapsulation method can also be vacuum lamination, and the lamination is preferably made of a plastic dry film of a specified thickness or a resin material such as PP, BT, etc.

[0084] S5 Figure 6 As shown, the temporary bonding layer 200 is removed, and then the carrier 100 is taken away;

[0085] S6: As Figure 7 As shown, a through hole 600 is formed on the protective structure 500 by laser drilling or mechanical drilling. The advantage of the through hole 600 over the blind hole is that it does not need to stay at the bottom of the hole, and the technical difficulty is greatly reduced;

[0086] S7 Figure 8 As shown, in Figure 8A seed layer (not shown) is first formed on the basis of the structure. The seed layer may be formed by deposition methods including but not limited to PVD, CVD, ALD, etc., or may be formed by chemical copper deposition. A photoresist layer 700 is then coated on the seed layer, and corresponding photoresist window 710 is opened by exposure and development.

[0087] S8 Figure 9 As shown, 710 is filled with copper by wet electroplating to form a redistribution layer 800 (RDL). Due to the presence of the through-hole 600, the plating solution can flow and exchange through the through-hole 600 on both sides of the board surface at the same time, thereby realizing double-sided electroplating to simultaneously form the front and back redistribution layers 800 (RDL), and at the same time connect the front and back redistribution layers 800 to achieve interconnection of the front and back sides of the redistribution layer 800.

[0088] S9 Figure 10 As shown, the photoresist 700 and the seed layer in the non-redistribution layer (RDL) area are removed to completely expose the redistribution layer (RDL) 800;

[0089] S10 Figure 11 As shown, a second insulating passivation layer 900 is formed on both sides of the redistribution layer (RDL) 800. The forming method includes: vacuum lamination with an insulating dry film, and the insulating dry film includes but is not limited to insulating materials such as ABF (Ajinomoto deposited film), PP (polypropylene), and BT (bismaleimide triazine resin). It can also be formed by coating with a liquid insulating photoresist.

[0090] S11 Figure 12 As shown, a window 910 is formed on one end of the second insulating passivation layer 900. If the second insulating passivation layer 900 is made of a non-photosensitive material, the corresponding window 910 is formed by laser drilling, mechanical drilling, or dry etching. If the second insulating passivation layer 900 is made of a photosensitive material, the corresponding formation method is exposure and development.

[0091] S12 Figure 13 As shown, in Figure 12A seed layer (not shown) is first formed on the basis of the structure. The seed layer includes but is not limited to being formed by deposition methods such as PVD, CVD, and ALD, and can also be formed by chemical copper deposition. A photoresist layer (not shown) is then coated on the seed layer. Corresponding photoresist layer windows (not shown) are opened by exposure and development. The photoresist layer windows (not shown) are filled with wet copper electroplating to form a first external interconnection metal layer 1000. The photoresist (not shown) and the seed layer (not shown) in the area other than the first external interconnection metal layer 1000 are removed to completely expose the first external interconnection metal layer 1000 to form a first external interconnection metal layer 1000 for external signal connection. The above steps are repeated to form a second external interconnection metal layer 1100 for external signal connection, wherein the first external interconnection metal layer 1000 is a metal copper layer and the second external interconnection metal layer 1100 is a metal tin layer for upper board welding.

[0092] S13 Figure 14 As shown, steps S11 to S12 are repeated, except that the passivation window 910 is on the other end of the second insulating passivation layer 900;

[0093] S14 Figure 15 As shown, a first external interconnection metal layer 1000 and a second external interconnection metal layer 1100 are formed on both sides of the package structure to meet more diverse connection requirements and obtain a board-level fan-out package structure.

[0094] The present invention proposes a board-level fan-out packaging structure, which is manufactured according to the manufacturing method of the board-level fan-out packaging structure described above.

[0095] The present invention proposes a board-level fan-out packaging structure and a manufacturing method thereof, which realizes direct interconnection of the front and back double-sided redistribution layers by through holes penetrating the protective structure, avoiding the depth-to-width ratio interconnection defect limitation problem of traditional blind hole electroplating. The symmetrical distribution of the double-sided redistribution layers balances the thermal stress and reduces the warping, which not only improves the stability of the structure but also reduces the production cost.

[0096] It will be appreciated that the present invention is described through some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are subject to various changes or equivalent substitutions. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope protected by the present invention.

Claims

1. A board-level fan-out packaging structure, characterized in that: include: A protective structure encapsulates a chip and a first insulating passivation layer on the chip wafer segment. The protective structure is provided with a through hole that penetrates the protective structure. The front and back sides of the protective structure are layered and filled with through holes to form a redistribution layer with front and back double-sided interconnection. The front and back sides of the redistribution layer are interconnected to achieve front and back interconnection of the chip.

2. The board-level fan-out packaging structure according to claim 1, wherein: Passive components are also packaged in the protection structure.

3. The board-level fan-out packaging structure according to claim 1, wherein: The first insulating passivation layer is provided with a plurality of windows, and the positions of the windows correspond to the positions of the pads on the chip so as to realize the connection between the pads on the chip and the redistribution layer on the reverse side.

4. The board-level fan-out packaging structure according to claim 1, wherein: A front and back second insulating passivation layer is provided on the front and back redistribution layers, and the second insulating passivation layer is provided with an external connection window.

5. The board-level fan-out packaging structure according to claim 4, characterized in that: A first external interconnection metal layer is provided on the front and back second insulating passivation layers, a second external interconnection metal layer is provided on the first external interconnection metal layer, and the first external interconnection metal layer is connected to the redistribution layer through an external connection window.

6. A method for manufacturing a board-level fan-out packaging structure, characterized in that: Manufacturing the board-level fan-out packaging structure according to any one of claims 1 to 5 comprises the following manufacturing steps: S1 forms a first insulating passivation layer on the active surface of the chip wafer segment and opens windows corresponding to the chip pads, and then thins and cuts it into single chips; S2: a temporary bonding layer is provided on the carrier board, and the first insulating passivation layer on the chip is attached to the temporary bonding layer; S4 performs plastic encapsulation on the combined structure to form a protective structure and then removes the temporary bonding layer and the carrier board; S5 forms a through hole on the protection structure, and simultaneously forms interconnected front and back redistribution layers through double-sided electroplating to achieve front and back interconnection of the chip.

7. The method for manufacturing a board-level fan-out packaging structure according to claim 6, wherein: In step S5, interconnected front and back redistribution layers are simultaneously formed by double-sided electroplating to achieve front and back interconnection of the chip, which specifically includes the following steps: forming a seed layer on the upper surface of the protection structure having the through-hole; forming a photoresist layer on the seed layer, and providing a photoresist layer window on the photoresist layer; The photoresist layer windows and through-holes are filled simultaneously through a double-sided electroplating process to form a redistribution layer with interconnections on the front and back sides.

8. The method for manufacturing a board-level fan-out packaging structure according to claim 7, wherein: The double-sided electroplating process utilizes through-holes to achieve double-sided circulation and exchange of electroplating solution, and simultaneously forms a redistribution layer interconnected on both the front and back sides.

9. The method for manufacturing a board-level fan-out packaging structure according to claim 6, wherein: The following steps are also included: S6 forms a second insulating passivation layer on the front and back surfaces of the redistribution layer and opens an external connection window; S7 repeatedly constructs a multi-layer metal interconnection structure on the second insulating passivation layer and connects it to the redistribution layer through the external connection window to achieve double-sided signal extraction.

10. The method for manufacturing a board-level fan-out packaging structure according to claim 6, wherein: Step S2 also includes the following steps: synchronously mounting the passive components and the chip on the temporary bonding layer.

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