Semiconductor packaging structure and preparation method thereof

Abstract

The invention discloses a semiconductor packaging structure and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor packaging structure comprises a first chip, a second chip, a first plastic packaging body, a second plastic packaging body, a first rewiring layer and a second rewiring layer, the first plastic packaging body wraps the first chip, and the second plastic packaging body wraps the second chip. The first rewiring layer and the second rewiring layer are arranged on the two opposite sides of the first plastic package body respectively, the second chip is arranged on the side, away from the first chip, of the second rewiring layer, the second plastic package body wraps the second chip, the thermal expansion coefficient of the second rewiring layer is larger than that of the first rewiring layer, and the thermal expansion coefficient of the second rewiring layer is larger than that of the first rewiring layer. At least one bonding wire and an insulating glue layer wrapping the bonding wire are arranged in the first redistribution layer. According to the semiconductor packaging structure and the preparation method thereof, the problem of warping of a traditional packaging structure caused by differences of thermal expansion coefficients and shrinkage characteristics of materials of different levels can be solved, meanwhile, stray capacitance between wiring layers can be reduced, and therefore the device performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a method for preparing the same. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology, as an emerging design approach, integrates and packages small chips with different functions to achieve system-level functionality. However, differences in thermal expansion coefficients and Young's modulus among various materials within the package structure can easily lead to inconsistent warping and deformation between the upper and lower layers, which in turn can cause delamination (for example, between the dielectric layer and the plastic package, and between the wiring layer and the dielectric layer), directly impacting product reliability and performance.

[0003] Specifically, the stacked side of the package structure, consisting of materials such as the stacked chip, wiring layers, and plastic encapsulation, has a significantly greater overall thermal expansion coefficient than the underlying redistribution layer. This difference in thermal expansion and contraction can easily cause package warping. Furthermore, the inductive effect created by current flow between wiring layers creates parasitic inductance, which can cause leakage, leading to short circuits between wiring layers, overheating, and other problems. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor packaging structure and its preparation method, which can solve the warping problem of traditional packaging structures caused by differences in thermal expansion coefficients and shrinkage characteristics of materials at different levels, and at the same time reduce the parasitic capacitance between wiring layers, thereby improving device performance.

[0005] The embodiment of the present application is implemented as follows: According to a first aspect of an embodiment of the present application, a semiconductor packaging structure is provided, comprising a first chip, a second chip, a first plastic package, a second plastic package, a first redistribution layer, and a second redistribution layer, wherein the first plastic package is wrapped around the outside of the first chip, the first redistribution layer and the second redistribution layer are respectively arranged on opposite sides of the first plastic package, the second chip is arranged on a side of the second redistribution layer away from the first chip, the second plastic package is wrapped around the outside of the second chip, the thermal expansion coefficient of the second redistribution layer is greater than the thermal expansion coefficient of the first redistribution layer, and at least one bonding wire and an insulating glue layer covering the bonding wire are arranged in the first redistribution layer.

[0006] As an implementation method, the bonding wire has an arched structure, and the arched structure protrudes toward a side away from the second redistribution layer.

[0007] As an implementation, the second redistribution layer includes a plurality of second sub-redistribution layers arranged in a step shape in sequence, and the third chip is arranged on one of the second sub-redistribution layers.

[0008] As an implementation, the second sub-redistribution layer on the side away from the first chip extends outwardly along the connection direction of the second chip and the first chip and has a dielectric layer.

[0009] As an implementation, the dielectric layer has a through hole, the pin of the third chip is arranged in the through hole, and the pin of the third chip is electrically connected to the second sub-redistribution layer on the side close to the first chip.

[0010] As an implementation, the dielectric layer has a gap with the second sub-redistribution layer on the side close to the first chip, the third chip has a protective glue layer arranged at the bottom, and the protective glue layer fills the gap.

[0011] As an implementation, the second redistribution layer includes a plurality of second sub-redistribution layers arranged in a step shape in sequence, and the second sub-redistribution layer on the side away from the first chip extends outwardly along the connection direction of the second chip and the first chip and has a second metal layer, and the second metal layer has a second gap with the second sub-redistribution layer on the side close to the first chip.

[0012] As an implementation, the first redistribution layer includes a plurality of first sub-redistribution layers arranged in a step shape in sequence, and the first sub-redistribution layer on the side away from the first chip extends outwardly along the connection direction of the second chip and the first chip and has a first metal layer, and the first metal layer has a first gap with the first sub-redistribution layer on the side close to the first chip.

[0013] As an implementation, at least one wire is arranged in the range of the orthographic projection of the first metal layer on the first redistribution layer.

[0014] As an implementation, the orthographic projection of the second metal layer on the first plastic package and the orthographic projection of the second plastic package on the first plastic package have an overlapping area.

[0015] As an implementation, a conductive column is arranged in the first plastic package, and the first redistribution layer and the second redistribution layer are electrically connected through the conductive column.

[0016] As an implementable manner, solder balls are further included, which are arranged on the side of the first redistribution layer away from the second chip, the first chip is electrically connected with the solder balls through the first redistribution layer, and the second chip is electrically connected with the solder balls through the second redistribution layer, the conductive column and the first redistribution layer.

[0017] In a second aspect, the application provides a preparation method of the semiconductor packaging structure.

[0018] The application has the following beneficial effects: The semiconductor packaging structure includes a first chip, a second chip, a first plastic package, a second plastic package, a first redistribution layer and a second redistribution layer. The first plastic package covers the first chip. The first redistribution layer and the second redistribution layer are arranged on opposite sides of the first plastic package. The second chip is arranged on the side of the second redistribution layer away from the first chip. The second plastic package covers the second chip. The thermal expansion coefficient of the second redistribution layer is greater than that of the first redistribution layer. The first redistribution layer is provided with at least one wire and an insulating adhesive layer covering the wire. The wire introduced by the wire bonding process is a high-rigidity conductive material, which can increase the proportion (such as the volume ratio or the area ratio) of the metal material of the bottom structure (i.e. the side where the first redistribution layer is located). Since the Young's modulus of the metal material is much higher than that of the dielectric material, the mechanical support of the bottom structure can be effectively enhanced, thereby reducing the deformation space. At the same time, the thermal expansion coefficient of the metal material is between the thermal expansion coefficients of the dielectric material and the material used in the plastic package. With the increase of the proportion of the metal material of the bottom structure, the overall thermal expansion coefficient of the bottom structure can be increased, so that the overall thermal expansion coefficients of the bottom structure and the top structure (i.e. the side where the second redistribution layer is located) are closer, thereby reducing the difference in thermal contraction between the first redistribution layer and the second redistribution layer, and further improving the warping phenomenon of the traditional packaging structure. On this basis, the semiconductor packaging structure provided by the application further introduces an insulating adhesive layer outside the wire through the dispensing process, so as to form a composite structure of "metal wire and insulating adhesive layer" by wrapping the wire with the insulating adhesive layer, so as to buffer the thermal stress between the metal wire and the surrounding material through the insulating adhesive layer, and avoid the fracture of the metal wire due to the excessively high rigidity. At the same time, the overall rigidity of the composite structure is higher than that of the pure wire, which can effectively resist the shrinkage force of the top structure, and further balance the warping. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1 State schematic diagram of a semiconductor package structure provided by the first embodiment of the present application; Figure 2 State schematic diagram of a semiconductor package structure provided by the second embodiment of the present application; Figure 3 State schematic diagram of a semiconductor package structure provided by the third embodiment of the present application; Figure 4 Structure schematic diagram of a semiconductor package structure provided by the fourth embodiment of the present application.

[0021] Figure legend: 100-semiconductor package structure; 10-first chip; 20-second chip; 30-first plastic package body; 40-second plastic package body; 50-first redistribution layer; 51-wire; 52-insulating adhesive layer; 53-first sub-redistribution layer; 54-first metal layer; 55-first gap; 60-second redistribution layer; 61-second sub-redistribution layer; 62-dielectric layer; 621-through hole; 63-second metal layer; 631-second gap; A-overlapping area; 70-third chip; 71-pin; 72-protective adhesive layer; 80-conductive column; 90-solder ball. DETAILED DESCRIPTION

[0022] The embodiments set forth below represent information needed to practice the embodiments and demonstrate the best mode of practicing the embodiments. Those skilled in the art will appreciate the concepts upon reading the following description and will recognize appropriate applications of those concepts. It should be understood that these concepts and applications belong to the present disclosure and the following claims, and are not limited to any specific embodiments described here.

[0023] It should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element, or intervening elements can also be present. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as being "above" or extending "above" another element, it can be directly above or extend directly above the other element, or intervening elements can also be present.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] The overall coefficient of thermal expansion of the laminated side of the conventional packaging structure is significantly greater than that of the bottom redistribution layer due to the presence of materials such as laminated chips, wiring layers, and plastic encapsulation bodies. The difference in thermal expansion and contraction characteristics between these materials can easily cause the packaging structure to warp. In addition, the inductive effect of the current between the wiring layers can generate parasitic inductance, which can cause leakage and lead to problems such as short circuits between the wiring layers, overheating, and the like.

[0027] To solve the above problems, please refer to Figures 1 to 4 The present application provides a semiconductor packaging structure 100 and a preparation method thereof, which can solve the warping problem caused by the difference in the coefficients of thermal expansion and the contraction characteristics of different levels of materials in the conventional packaging structure, and also reduce the parasitic capacitance between the wiring layers, thereby improving the performance of the device.

[0028] Specifically, as Figures 1 to 4 shown, the first aspect of the embodiments of the present application provides a semiconductor packaging structure 100, which includes a first chip 10, a second chip 20, a first plastic encapsulation body 30, a second plastic encapsulation body 40, a first redistribution layer 50, and a second redistribution layer 60. The first plastic encapsulation body 30 covers the first chip 10, the first redistribution layer 50 and the second redistribution layer 60 are respectively arranged on opposite sides of the first plastic encapsulation body 30, the second chip 20 is arranged on the side of the second redistribution layer 60 away from the first chip 10, the second plastic encapsulation body 40 covers the second chip 20, the coefficient of thermal expansion of the second redistribution layer 60 is greater than that of the first redistribution layer 50, and at least one wire 51 and an insulating glue layer 52 covering the wire 51 are arranged in the first redistribution layer 50.

[0029] It should be noted that the semiconductor package structure 100 includes the first chip 10, the second chip 20, the first plastic package 30, the second plastic package 40, the first redistribution layer 50 and the second redistribution layer 60, wherein the first chip 10 is a core functional chip (such as a logic chip, a memory chip), the first chip 10 is completely covered by the first plastic package 30, the first plastic package 30 can be made of a low-stress epoxy resin material, and the first chip 10 is wrapped by an injection molding process to play a mechanical protection and insulation role through the first plastic package 30; the first redistribution layer 50 and the second redistribution layer 60 are located on opposite (such as upper and lower) sides of the first plastic package 30, the first redistribution layer 50 and the second redistribution layer 60 can be made of copper wires and dielectric materials (such as polyimide) stacked alternately, the first redistribution layer 50 is responsible for signal transmission between the first chip 10 and an external circuit, and the second redistribution layer 60 serves as a connecting bridge between the first chip 10 and the second chip 20; the second chip 20 (such as a radio frequency chip, a sensor chip) is arranged on a side of the second redistribution layer 60 away from the first chip 10, the second chip 20 can be electrically connected to the second redistribution layer 60 through a solder ball or a copper pillar, the second plastic package 40 can be made of a material compatible with the first plastic package 30, and the second plastic package 40 covers the second chip 20 to play a mechanical protection and insulation role through the second plastic package 40.

[0030] In the conventional package structure, since the second redistribution layer 60 has a high line complexity and a large thickness, and the first redistribution layer 50 has a low line complexity and a small thickness, the second redistribution layer 60 has a larger thermal expansion coefficient than the first redistribution layer 50, and after a heat process, a large shrinkage occurs on the side of the second redistribution layer 60 with a large thickness, which easily causes the conventional package structure to warp upward.

[0031] To address the aforementioned issues, the semiconductor package structure 100 provided in the present application includes at least one bonding wire 51 (e.g., gold or copper wire) within the first redistribution layer 50 and an insulating adhesive layer 52 (which may be a low-dielectric-constant polymer, such as benzocyclobutene) covering the bonding wire 51. The bonding wire 51, introduced through the bonding process, is a highly rigid conductive material and can increase the proportion (e.g., volume or area) of metal material in the bottom structure (i.e., the side where the first redistribution layer 50 is located). Because the Young's modulus of metal material is much higher than that of dielectric material, the mechanical support of the bottom structure can be effectively enhanced, thereby reducing deformation space. Furthermore, the thermal expansion coefficient of metal material lies between that of dielectric material and that of the plastic encapsulation material. As the proportion of metal material in the bottom structure increases, the overall thermal expansion coefficient of the bottom structure can be increased, bringing it closer to that of the top structure (i.e., the side where the second redistribution layer 60 is located). This reduces the difference in thermal contraction between the first redistribution layer 50 and the second redistribution layer 60, thereby improving the warping phenomenon of conventional package structures.

[0032] On this basis, the semiconductor packaging structure 100 provided in the present application also introduces an insulating adhesive layer 52 outside the bonding wire 51 through a dispensing process, so that the bonding wire 51 is wrapped by the insulating adhesive layer 52 to form a composite structure of "metal bonding wire 51 and insulating adhesive layer 52", so that the thermal stress between the metal bonding wire 51 and the surrounding materials is buffered by the insulating adhesive layer 52, thereby avoiding the metal bonding wire 51 from breaking due to excessive rigidity; at the same time, the overall rigidity of the formed composite structure is higher than the overall rigidity of the simple bonding wire 51, which can effectively resist the shrinkage tension of the top structure and further balance the warping.

[0033] In traditional packaging structures, the materials used for the redistribution layer are mostly single materials, and the distance between layers is limited by process precision, making it difficult to reduce parasitic capacitance. The semiconductor packaging structure 100 provided in the present application wraps the metal bonding wire 51 with an insulating adhesive layer 52, which is equivalent to adding an extra layer of physical isolation on the basis of the original medium. Therefore, the interlayer distance between the first redistribution layer 50 and the second redistribution layer 60 can be increased, thereby reducing the capacitance effect between the first redistribution layer 50 and the second redistribution layer 60. At the same time, since capacitance is positively correlated with dielectric constant and negatively correlated with insulation performance, the capacitance effect between the first redistribution layer 50 and the second redistribution layer 60 can be further reduced. In addition, short circuits between the bonding wire 51 and other surrounding conductive structures (such as adjacent bonding wires 51 and the edge of the first redistribution layer 50) can be avoided, thereby improving the performance of the device.

[0034] As an implementable method, Figures 1 to 4 As shown, the bonding wire 51 is in an arched structure, and the arched structure protrudes toward a side away from the second redistribution layer 60 .

[0035] It should be noted that the bonding wire 51 has an arched structure, which protrudes toward the side away from the second redistribution layer 60. This increases the physical distance between the metal bonding wire 51 and the second redistribution layer 60. Combined with the low dielectric properties of the insulating adhesive layer 52, this further enhances the effect of reducing interlayer capacitance. Furthermore, when the arched structure protrudes toward the side away from the second redistribution layer 60, more space is created between the bonding wire 51 and the second redistribution layer 60, facilitating the insulating adhesive layer 52 to completely encapsulate the arched bonding wire 51 during the subsequent dispensing process. This prevents the insulating adhesive layer 52 from being too thin or partially uncovered, ensuring that the insulating adhesive layer 52 can effectively play its supporting role and balance warping.

[0036] As an implementable method, Figure 2 As shown, the semiconductor package structure 100 further includes a third chip 70 , the second redistribution layer 60 includes a plurality of second sub-redistribution layers 61 , the plurality of second sub-redistribution layers 61 are arranged in a step-like manner, and the third chip 70 is disposed on one of the second sub-redistribution layers 61 .

[0037] It should be noted that, for example, the second redistribution layer 60 includes 3 to 5 second sub-redistribution layers 61, and the multiple second sub-redistribution layers 61 are arranged in a step-shaped manner along the connection direction of the second chip 20 and the first chip 10. Each second sub-redistribution layer 61 is made of copper wiring and dielectric materials (such as polyimide) stacked alternately; the semiconductor packaging structure 100 also includes a third chip 70 (such as a power management chip, an image processing chip), and the third chip 70 is arranged on the step plane of one of the second sub-redistribution layers 61. The third chip 70 can be electrically connected to the pad of the second sub-redistribution layer 61 through a solder ball or a copper pillar. There is a certain distance (such as 10 to 20 μm) between the edge of the third chip 70 and the step side of the adjacent second sub-redistribution layer 61 to avoid physical interference. The second plastic package 40 can simultaneously cover the second chip 20 and the third chip 70 to fill the step surface to form an overall sealed structure.

[0038] Multiple second sub-rewiring layers 61 are arranged in a step-like manner, so that the third chip 70 and the second chip 20 can be arranged in layers in the vertical direction. Compared with a planar layout of the two, the utilization rate of the packaging area can be further improved. For example, in a 5mm×5mm packaging area, a logic chip (i.e., the first chip 10), a radio frequency chip (i.e., the second chip 20) and a power chip (i.e., the third chip 70) can be integrated at the same time; the direct connection between the third chip 70 and the corresponding second sub-rewiring layer 61 can shorten the signal transmission path, reduce signal delay, and increase the data transmission rate; the stepped structure formed by the above-mentioned multiple second sub-rewiring layers 61 can be achieved through multiple photolithography and etching processes, and then combined with first setting a sacrificial layer and then releasing the sacrificial layer, and can be compatible with the existing rewiring layer preparation process.

[0039] As an implementable manner, as shown in Figure 2 The second sub-redistribution layer 61 on the side away from the first chip 10 extends outward to form a dielectric layer 62 along the connection direction of the second chip 20 and the first chip 10 (or the direction perpendicular to the first chip 10).

[0040] It should be noted that the second sub-redistribution layer 61 on the side away from the first chip 10 extends outward to form a dielectric layer 62 along the connection direction of the second chip 20 and the first chip 10 (or the direction perpendicular to the first chip 10). The extended dielectric layer 62 can be made of polyimide or benzocyclobutene material, which is consistent with the selection of the dielectric material of the second sub-redistribution layer 61, to ensure the compatibility between the materials. The dielectric layer 62 extends outward from the edge of the second sub-redistribution layer 61 by a certain length (such as 50-100 μm), and the thickness should be flush with the thickness of the dielectric material of the second sub-redistribution layer 61. One side of the third chip 70 is lapped on the dielectric layer 62, and the lapped area can account for 30%-50% of the bottom area of the third chip 70. The side of the third chip 70 away from the dielectric layer 62 can be fixed with the second sub-redistribution layer 61 on the side close to the first chip 10 to improve the stability of supporting the third chip 70.

[0041] The dielectric layer 62 extended by the second sub-redistribution layer 61 can provide additional edge support for the third chip 70. In combination with the support between the third chip 70 and the second sub-redistribution layer 61 on the side close to the first chip 10, a double-support-point support structure can be formed to improve the reliability of the connection between the third chip 70 and the second sub-redistribution layer 61. The dielectric layer 62 can be formed by synchronous lithography with the dielectric material of the second sub-redistribution layer 61.

[0042] As an implementable manner, as shown in Figure 2 The dielectric layer 62 is provided with a through hole 621, and the pin 71 of the third chip 70 is arranged in the through hole 621, and the pin 71 of the third chip 70 is electrically connected with the second sub-redistribution layer 61 on the side close to the first chip 10.

[0043] It should be noted that the number of through holes 621 can be at least one, when the number of through holes 621 is multiple, the multiple through holes 621 can be uniformly distributed in the lap region of the dielectric layer 62, only the number of through holes 621 needs to match the number of pins 71 of the third chip 70, and the hole wall of the through hole 621 can be formed by plasma etching to form a rough surface to enhance the metal adhesion; the pin 71 of the third chip 70 is arranged in the through hole 621, and the pin 71 of the third chip 70 is electrically connected to the second sub-redistribution layer 61 located on the side close to the first chip 10 below the third chip 70. The outer wall of the pin 71 and the hole wall of the through hole 621 can be filled with conductive adhesive, which can enhance the conductivity and buffer thermal stress.

[0044] As an implementable manner, as shown in Figure 2 The dielectric layer 62 has a gap between the second sub-redistribution layer 61 located on the side close to the first chip 10, and the bottom of the third chip 70 is provided with a protective adhesive layer 72, and the protective adhesive layer 72 fills the gap.

[0045] It should be noted that along the connection direction of the second chip 20 and the first chip 10 (or in the direction perpendicular to the first chip 10), there is a gap between the lower surface of the dielectric layer 62 and the upper surface of the second sub-redistribution layer 61 located on the side close to the first chip 10, which does not affect the electrical connection of the pin 71, and also reserves space for the protective adhesive layer 72; the gap between the lower surface of the dielectric layer 62 and the upper surface of the second sub-redistribution layer 61 located on the side close to the first chip 10 can be realized by multiple photoetching processes, and then the sacrificial layer is set first and the sacrificial layer is released later, which is compatible with the existing redistribution layer preparation process; the protective adhesive layer 72 is coated on the bottom of the third chip 70 by the dispensing process, and the gap is naturally filled by capillary action, so that the protective adhesive layer 72 can cover the entire bottom area of the third chip 70, forming a continuous protective film, and ensuring that the protective adhesive layer 72 is tightly bonded with the dielectric layer 62, the second sub-redistribution layer 61 and the third chip 70.

[0046] As an implementable manner, as shown in Figure 3 And Figure 4 The second redistribution layer 60 includes a plurality of second sub-redistribution layers 61, and the plurality of second sub-redistribution layers 61 are arranged in a stepped shape. Along the connection direction of the second chip 20 and the first chip 10, the second sub-redistribution layer 61 located on the side away from the first chip 10 extends outwardly with a second metal layer 63, and the second metal layer 63 has a second gap 631 between the second sub-redistribution layer 61 located on the side close to the first chip 10.

[0047] It should be noted that the second redistribution layer 60 includes a plurality of second sub-redistribution layers 61 arranged in steps, and the second sub-redistribution layer 61 located on the side away from the first chip 10 extends outwardly with a second metal layer 63 in the direction of the connection between the second chip 20 and the first chip 10 (or the direction perpendicular to the first chip 10). The second metal layer 63 can be made of high-conductivity copper or copper alloy, which is consistent with the wiring material of the second sub-redistribution layer 61, ensuring that the electrical properties match. The second metal layer 63 extends outwardly from the edge of the second sub-redistribution layer 61 by a certain length (such as 50-100 μm). The second metal layer 63 has a second gap 631 between the second sub-redistribution layer 61 located on the side close to the first chip 10 to avoid interference with other structures. Since the thermal conductivity of the second metal layer 63 is much higher than that of the dielectric material, the second metal layer 63 formed by extending outwardly from the second sub-redistribution layer 61 can directly conduct the heat of the second sub-redistribution layer 61 to the surface of the semiconductor package structure 100, and at the same time, it can also increase the heat dissipation area of the semiconductor package structure 100, which can further improve the heat dissipation efficiency and be suitable for high-power-density chips. The second gap 631 between the second metal layer 63 and the second sub-redistribution layer 61 located on the side close to the first chip 10 can be realized by multiple photoetching processes, and can be compatible with the existing redistribution layer preparation process by setting a sacrificial layer first and then releasing the sacrificial layer.

[0048] As an implementable manner, as shown in Figure 4 The first redistribution layer 50 includes a plurality of first sub-redistribution layers 53 arranged in steps, and the first sub-redistribution layer 53 located on the side away from the first chip 10 extends outwardly with a first metal layer 54 in the direction of the connection between the second chip 20 and the first chip 10. The first metal layer 54 has a first gap 55 between the first sub-redistribution layer 53 located on the side close to the first chip 10.

[0049] It should be noted that the first redistribution layer 50 includes a plurality of first sub-redistribution layers 53 arranged in steps in sequence, and the first sub-redistribution layer 53 located on the side away from the first chip 10 extends outwardly with a first metal layer 54 in the direction of the connection of the second chip 20 and the first chip 10 (or the direction perpendicular to the first chip 10). The first metal layer 54 can be made of high-conductivity copper or copper alloy, which is consistent with the wiring material of the first sub-redistribution layer 53, ensuring that the electrical properties match. The first metal layer 54 extends outwardly from the edge of the first sub-redistribution layer 53 by a certain length (such as 50-100 μm). The first metal layer 54 has a first gap 55 with the first sub-redistribution layer 53 located on the side close to the first chip 10 to avoid interference with other structures. Since the thermal conductivity of the first metal layer 54 is much higher than that of the dielectric material, the first metal layer 54 formed by extending outwardly from the first sub-redistribution layer 53 can directly conduct the heat of the first sub-redistribution layer 53 to the surface of the semiconductor package structure 100, and at the same time, it can also increase the heat dissipation area of the semiconductor package structure 100, which can further improve the heat dissipation efficiency and be suitable for high-power-density chips. The first gap 55 between the first metal layer 54 and the first sub-redistribution layer 53 located on the side close to the first chip 10 can be realized by multiple photoetching processes, in combination with the first setting of the sacrificial layer and the later release of the sacrificial layer, and can be compatible with the existing redistribution layer preparation process.

[0050] As an implementable manner, as shown in Figure 3 and Figure 4 At least one wire 51 is located in the orthographic projection range of the first metal layer 54 on the first redistribution layer 50. The wire 51, as a conductive structure, also has a certain heat conduction capacity. When at least one wire 51 is provided in the orthographic projection range of the first metal layer 54, it is equivalent to adding an additional heat dissipation channel through the wire 51, so that the heat of the first redistribution layer 50 can also be conducted to the surface of the semiconductor package structure 100 through the wire 51, and the first metal layer 54 further improves the heat dissipation effect of the semiconductor package structure 100.

[0051] As an implementable manner, as shown in Figure 3 and Figure 4 The orthographic projection of the second metal layer 63 on the first plastic package 30 and the orthographic projection of the second plastic package 40 on the first plastic package 30 have an overlapping area A.

[0052] It should be noted that, along the direction of the connection between the second chip 20 and the first chip 10 (or in the direction perpendicular to the first chip 10), the orthographic projection of the second metal layer 63 on the first plastic package 30 partially overlaps with the orthographic projection of the second plastic package 40 on the first plastic package 30, and the overlapping area A is located on the inner side of the second metal layer 63 (i.e., the side close to the second sub-redistribution layer 61). The overlapping area A corresponds to the portion of the second plastic package 40 covering the third chip 70. That is, while the second plastic package 40 covers the third chip 70, the edge of the second plastic package 40 extends to the orthographic projection range of the second metal layer 63, forming a physical cover, so that the cantilever end of the second metal layer 63 (i.e., the end away from the second sub-redistribution layer 61) obtains additional support to reduce the risk of fracture of the second metal layer 63. At the same time, the overlapping area A and the second gap 631 are staggered in the vertical direction, and the stress buffering function of the second gap 631 is not affected.

[0053] Similarly, if Figure 4 As shown, the orthographic projection of the first metal layer 54 on the first plastic packaging body 30 and the orthographic projection of the second plastic packaging body 40 on the first plastic packaging body 30 also have an overlapping area A to reduce the risk of fracture of the first metal layer 54. At the same time, the overlapping area A and the first gap 55 are staggered in the vertical direction, and the stress buffering function of the first gap 55 is not affected.

[0054] As an implementable method, Figures 1 to 4 As shown, the semiconductor package structure 100 further includes a conductive pillar 80 . The conductive pillar 80 is disposed in the first plastic package 30 . The first redistribution layer 50 and the second redistribution layer 60 are electrically connected via the conductive pillar 80 .

[0055] It should be noted that the semiconductor packaging structure 100 also includes a conductive column 80, which is inserted into the first plastic package body 30. The conductive column 80 can be made of high-conductivity oxygen-free copper or copper-tungsten alloy. The length of the conductive column 80 should match the thickness of the first plastic package body 30. When passing through the first plastic package body 30, a pre-formed channel can be formed by laser drilling, and then the conductive column 80 can be formed by electroplating and filling metal. The first redistribution layer 50 and the second redistribution layer 60 are electrically connected through the conductive column 80 to reduce the on-resistance of the first redistribution layer 50 and the second redistribution layer 60, shorten the transmission path, reduce parasitic capacitance, and effectively suppress signal reflection and crosstalk.

[0056] As an implementable method, Figures 1 to 4As shown, the semiconductor package structure 100 further comprises solder balls 90, which are arranged on the side of the first redistribution layer 50 away from the second chip 20 (i.e. the bottom surface of the package structure), the first chip 10 is electrically connected with the solder balls 90 through the first redistribution layer 50, and the second chip 20 is electrically connected with the solder balls 90 through the second redistribution layer 60, the conductive pillars 80 and the first redistribution layer 50, so as to form an external electrical connection interface through the solder balls 90.

[0057] As shown in the first aspect of the embodiments of the present application, a semiconductor package structure 100 is provided. Figures 1 to 4 As shown in the second aspect of the embodiments of the present application, a preparation method of the semiconductor package structure 100 is provided, which is used for preparing the semiconductor package structure 100 described above.

[0058] It should be noted that the preparation method of the semiconductor package structure 100 provided by the present embodiment is the same as the specific structure of the semiconductor package structure 100 described above, and those skilled in the art can infer the preparation method of the semiconductor package structure 100 according to the description of the specific structure of the semiconductor package structure 100. The present application will not be repeated here. Since the preparation method of the semiconductor package structure 100 provided by the present embodiment is used for preparing the semiconductor package structure 100 described above, the preparation method of the semiconductor package structure 100 has the same beneficial effects as the semiconductor package structure 100 described above, which will not be repeated here.

[0059] The above only describes optional embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0060] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present application will not further describe various possible combinations.

Claims

1. A semiconductor packaging structure, characterized in that: It includes a first chip, a second chip, a first plastic package, a second plastic package, a first redistribution layer and a second redistribution layer, the first plastic package is coated on the outside of the first chip, the first redistribution layer and the second redistribution layer are respectively arranged on opposite sides of the first plastic package, the second chip is arranged on the side of the second redistribution layer away from the first chip, the second plastic package is coated on the outside of the second chip, the thermal expansion coefficient of the second redistribution layer is greater than the thermal expansion coefficient of the first redistribution layer, and at least one bonding wire and an insulating glue layer covering the bonding wire are arranged in the first redistribution layer.

2. The semiconductor package structure according to claim 1, wherein: The bonding wire has an arched structure, and the arched structure protrudes toward a side away from the second redistribution layer.

3. The semiconductor package structure according to claim 1, wherein: A third chip is also included. The second redistribution layer includes a plurality of second sub-redistribution layers. The plurality of second sub-redistribution layers are arranged in sequence in a step-like shape. The third chip is disposed on one of the second sub-redistribution layers.

4. The semiconductor package structure according to claim 3, wherein: Along the connection direction between the second chip and the first chip, a dielectric layer extends outward from the second sub-redistribution layer located on a side away from the first chip, and the third chip is overlapped on the dielectric layer.

5. The semiconductor package structure according to claim 4, wherein: The dielectric layer is provided with a through hole, the pins of the third chip are passed through the through hole, and the pins of the third chip are electrically connected to the second sub-redistribution layer located on a side close to the first chip.

6. The semiconductor package structure according to claim 4, wherein: A gap is formed between the dielectric layer and the second sub-redistribution layer located on a side close to the first chip. A protective adhesive layer is provided at the bottom of the third chip, and the protective adhesive layer fills the gap.

7. The semiconductor package structure according to claim 1, wherein: The second redistribution layer includes multiple second sub-redistribution layers, which are arranged in a step-like manner. Along the connection direction of the second chip and the first chip, the second sub-redistribution layer located on the side away from the first chip has a second metal layer extending outward, and a second gap is provided between the second metal layer and the second sub-redistribution layer located on the side close to the first chip.

8. The semiconductor package structure according to claim 7, wherein: The first redistribution layer includes multiple first sub-redistribution layers, which are arranged in sequence in a step-like manner. Along the connection direction of the second chip and the first chip, the first sub-redistribution layer located on the side away from the first chip has a first metal layer extending outward, and a first gap is provided between the first metal layer and the first sub-redistribution layer located on the side close to the first chip.

9. The semiconductor package structure according to claim 8, wherein: At least one of the bonding wires is located within an orthographic projection of the first metal layer on the first redistribution layer.

10. The semiconductor package structure according to claim 7, wherein: An orthographic projection of the second metal layer on the first plastic packaging body and an orthographic projection of the second plastic packaging body on the first plastic packaging body have an overlapping area.

11. The semiconductor package structure according to claim 1, wherein: The system further includes a conductive column, which is disposed inside the first plastic package. The first redistribution layer and the second redistribution layer are electrically connected via the conductive column.

12. The semiconductor package structure according to claim 11, wherein: It also includes a solder ball, which is arranged on a side of the first redistribution layer away from the second chip. The first chip is electrically connected to the solder ball through the first redistribution layer, and the second chip is electrically connected to the solder ball through the second redistribution layer, the conductive column and the first redistribution layer.

13. A method for preparing a semiconductor packaging structure, characterized in that: Used to prepare the semiconductor packaging structure according to any one of claims 1 to 12.

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