Method and system for recovering clock at VOIP receiving end through FPGA

Abstract

The invention discloses a method and system for recovering a clock at a VOIP receiving end through an FPGA, and relates to the field of clock recovery. The method for recovering the clock at the VOIP receiving end through the FPGA comprises the steps that a sending end packages source data transmitted by a falling edge of a source clock into a message and then transmits the message to the receiving end; a receiving end extracts source data in the message and stores the source data in a receiving buffer area; outputting a recovery clock by adopting a clock control algorithm according to the change of the number of the data in the receiving buffer area, and outputting the data in the receiving buffer area through the rising edge of the recovery clock; the clock control algorithm introduces the data transmission rate and the maximum network jitter delay of a source clock. According to the method, the accuracy and the stability of clock recovery can be improved, the influence of the maximum network jitter time delay is solved, and meanwhile, the operation scale of an algorithm is reduced.

Description

Technical Field

[0001] The present invention relates to the field of clock recovery, and in particular to a method and system for clock recovery at a VOIP receiving end through FPGA. Background Art

[0002] VoIP, short for Voice over Internet Protocol, refers to the transmission of voice signals in the form of data packets over an IP network after compression and encapsulation of analog voice signals. This commonly refers to Internet telephony, or simply IP telephony. In VoIP communications, clock synchronization is crucial for ensuring accurate voice data transmission. Reference patent CN111600813A proposes a multimode interconnect interface controller for converged networks. This controller automatically performs link training and rate negotiation, provides message physical layer encoding to enhance the versatility and flexibility of interconnect chips, and reduces message penetration latency, making it suitable for interconnection between data center Ethernet and high-performance computing high-speed networks. However, this patent primarily focuses on physical layer optimization and does not provide a specific solution to the clock recovery problem in VoIP data transmission. Consequently, reference patent CN108551378A discloses a method for long-distance transmission of radio frequency signals. This method uses time-division multiplexing to serialize data through down-conversion, analog-to-digital conversion, and low-pass filtering, ultimately recovering the radio frequency signal at the receiving end. While the patent proposes an effective data transmission and recovery solution, it focuses on long-distance transmission of RF signals and lacks a specific description of clock recovery technology at the VOIP data transmission end. In particular, it fails to consider the impact of network delay jitter on clock recovery. Current market solutions to this problem include adaptive clock recovery algorithms that employ jitter prediction and discrete interpolation transforms. These algorithms are complex to implement, involve a large number of computations, and place high demands on FPGA hardware resources. A field-programmable gate array (FPGA) is an integrated circuit containing programmable logic blocks and programmable interconnect resources. Its internal structure can be modified through programming after manufacturing to achieve specific functions or application requirements. This programmability makes FPGAs highly flexible and customizable in digital circuit design. Based on the above, existing clock recovery mechanisms at the VOIP data transmission end have shortcomings, particularly when addressing the synchronization between the source data clock and the received data clock, failing to effectively consider the impact of maximum network jitter delay. To address this technical problem, it is necessary to propose a method and system for recovering the clock at the VOIP receiving end through FPGA, aiming to improve the accuracy and stability of clock recovery by optimizing the clock control algorithm, thereby ensuring high-quality transmission of VOIP data. Summary of the Invention

[0003] The technical problem to be solved by the present invention is that the clock recovery at the VOIP data transmission end fails to effectively consider the influence of the maximum network jitter delay when processing the synchronization problem between the source data clock and the received data clock. The purpose is to provide a method and system for clock recovery at the VOIP receiving end through FPGA, aiming to improve the accuracy and stability of clock recovery by optimizing the clock control algorithm, thereby ensuring high-quality transmission of VOIP data, solving the influence of the maximum network jitter delay, and reducing the calculation scale of the algorithm.

[0004] The present invention is achieved through the following technical solutions:

[0005] By using FPGA to recover the clock at the VOIP receiving end, the sending end packages the source data transmitted on the falling edge of the source clock into a message and transmits it to the receiving end;

[0006] The receiving end extracts the source data from the message and stores it in the receiving buffer;

[0007] According to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output through the rising edge of the recovered clock;

[0008] The clock control algorithm introduces the data transmission rate and maximum network jitter delay of the source clock.

[0009] The above clock control algorithm specifically includes:

[0010] Based on the weight of the data transmission rate of the above-mentioned source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the above-mentioned receiving buffer reaches the preset data quantity; when it reaches it, the data in the above-mentioned receiving buffer is output according to the initial rate value of the above-mentioned recovered clock; and it is recorded as the first data output cycle.

[0011] The above-mentioned method of outputting a recovered clock using a clock control algorithm according to the change in the number of data in the above-mentioned receiving buffer, and outputting the data in the above-mentioned receiving buffer through the rising edge of the recovered clock, specifically includes:

[0012] Determine in real time whether the number of remaining data in the above-mentioned receiving buffer is greater than a preset maximum number threshold. If so, determine whether the above-mentioned first data output period is greater than the preset acceleration adjustment time interval of the above-mentioned recovery clock; if and only if it is greater than the above-mentioned preset acceleration adjustment time interval, clear the timing of the above-mentioned first data output period and increase the rate value of the above-mentioned recovery clock.

[0013] The method of outputting a recovered clock using a clock control algorithm according to the change in the number of data in the receive buffer, and outputting the data in the receive buffer via the rising edge of the recovered clock, further includes:

[0014] If the number of remaining data in the above-mentioned receiving buffer is less than the above-mentioned preset maximum number threshold, determine whether the number of remaining data in the above-mentioned receiving buffer is less than the preset minimum number threshold; if so, record it as the second data output cycle; determine whether the above-mentioned second data output cycle is greater than the preset deceleration adjustment time interval of the recovery clock; if and only if it is yes, clear the timing of the above-mentioned second data output cycle and reduce the rate value of the above-mentioned recovery clock.

[0015] The first data output cycle is timed by a first timer; the second data output cycle is timed by a second timer.

[0016] A system for recovering clock at a VOIP receiving end through FPGA includes a transmitting end and a receiving end; the transmitting end is used to package source data transmitted at the falling edge of the source clock into a message and transmit it to the receiving end; the receiving end is used to extract the source data in the message;

[0017] The receiving end includes a receiving buffer and a clock recovery control module;

[0018] The receiving buffer is used to store the source data transmitted by the sending end;

[0019] The clock recovery control module is used to output a recovery clock using a clock control algorithm according to the change in the number of data in the receiving buffer, and output the data in the receiving buffer through the rising edge of the recovery clock;

[0020] The clock control algorithm introduces the data transmission rate and maximum network jitter delay of the source clock.

[0021] The above clock control algorithm specifically includes:

[0022] Based on the weight of the data transmission rate of the above-mentioned source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the above-mentioned receiving buffer reaches the preset data quantity; when it reaches it, the data in the above-mentioned receiving buffer is output according to the initial rate value of the above-mentioned recovered clock; and it is recorded as the first data output cycle.

[0023] The above-mentioned sending end includes a data-to-IP message module; the above-mentioned receiving end includes an IP message data parsing module; the source data is transmitted to the data-to-IP message module through the falling edge of the source clock; the above-mentioned data-to-IP message module packages the source data into an IP message and sends it to the above-mentioned receiving end through the network; the above-mentioned receiving end extracts the source data in the IP message through the above-mentioned IP message data parsing module.

[0024] An electronic device includes a memory, a processor, and a computer program running on the processor. When the processor executes the computer program, the steps of the method for recovering the clock at a VOIP receiving end through an FPGA are implemented.

[0025] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the method for recovering a clock at a VOIP receiving end through an FPGA are implemented.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] The present invention provides a method for clock recovery at a VoIP receiver using an FPGA. The transmitting end packages source data transmitted on the falling edge of the source clock into a message and transmits it to the receiving end. The receiving end extracts the source data from the message and stores it in a receiving buffer. Based on the changes in the amount of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output on the rising edge of the recovered clock. The clock control algorithm incorporates the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay. By optimizing the clock control algorithm, the present invention improves the accuracy and stability of clock recovery, thereby ensuring high-quality transmission of VoIP data, addressing the impact of the maximum network jitter delay, and making the recovered clock faster and more stable. It also reduces the algorithm's computational scale, thereby reducing the demand for hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings:

[0029] Figure 1 This is a circuit schematic diagram of a method for recovering clock at a VOIP receiving end using FPGA in an embodiment of the present application;

[0030] Figure 2 This is a schematic diagram of the clock control algorithm according to an embodiment of the present application;

[0031] Figure 3 This is a circuit schematic diagram of a method for recovering clock at a VOIP receiving end through FPGA according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0033] Example

[0034] like Figures 1-3 As shown, the embodiment of the present application provides a method for recovering the clock at the VOIP receiving end through FPGA, and the sending end packages the source data transmitted on the falling edge of the source clock into a message and transmits it to the receiving end;

[0035] The receiving end extracts the source data from the message and stores it in the receiving buffer;

[0036] According to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the receiving buffer is output through the rising edge of the recovered clock;

[0037] The clock control algorithm introduces the data transmission rate and maximum network jitter delay of the source clock.

[0038] The above clock control algorithm specifically includes:

[0039] Based on the weight of the data transmission rate of the above-mentioned source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the above-mentioned receiving buffer reaches the preset data quantity; when it reaches it, the data in the above-mentioned receiving buffer is output according to the initial rate value of the above-mentioned recovered clock; and it is recorded as the first data output cycle.

[0040] The above-mentioned method of outputting a recovered clock using a clock control algorithm according to the change in the number of data in the above-mentioned receiving buffer, and outputting the data in the above-mentioned receiving buffer through the rising edge of the recovered clock, specifically includes:

[0041] Determine in real time whether the number of remaining data in the above-mentioned receiving buffer is greater than a preset maximum number threshold. If so, determine whether the above-mentioned first data output period is greater than the preset acceleration adjustment time interval of the above-mentioned recovery clock; if and only if it is greater than the above-mentioned preset acceleration adjustment time interval, clear the timing of the above-mentioned first data output period and increase the rate value of the above-mentioned recovery clock.

[0042] The method of outputting a recovered clock using a clock control algorithm according to the change in the number of data in the receive buffer, and outputting the data in the receive buffer via the rising edge of the recovered clock, further includes:

[0043] If the number of remaining data in the above-mentioned receiving buffer is less than the above-mentioned preset maximum number threshold, determine whether the number of remaining data in the above-mentioned receiving buffer is less than the preset minimum number threshold; if so, record it as the second data output cycle; determine whether the above-mentioned second data output cycle is greater than the preset deceleration adjustment time interval of the recovery clock; if and only if it is yes, clear the timing of the above-mentioned second data output cycle and reduce the rate value of the above-mentioned recovery clock.

[0044] The first data output cycle is timed by a first timer; the second data output cycle is timed by a second timer.

[0045] A system for recovering clock at a VOIP receiving end through FPGA includes a transmitting end and a receiving end; the transmitting end is used to package source data transmitted at the falling edge of the source clock into a message and transmit it to the receiving end; the receiving end is used to extract the source data in the message;

[0046] The receiving end includes a receiving buffer and a clock recovery control module;

[0047] The receiving buffer is used to store the source data transmitted by the sending end;

[0048] The clock recovery control module is used to output a recovery clock using a clock control algorithm according to the change in the number of data in the receiving buffer, and output the data in the receiving buffer through the rising edge of the recovery clock;

[0049] The clock control algorithm introduces the data transmission rate and maximum network jitter delay of the source clock.

[0050] The above clock control algorithm specifically includes:

[0051] Based on the weight of the data transmission rate of the above-mentioned source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the above-mentioned receiving buffer reaches the preset data quantity; when it reaches it, the data in the above-mentioned receiving buffer is output according to the initial rate value of the above-mentioned recovered clock; and it is recorded as the first data output cycle.

[0052] The above-mentioned sending end includes a data-to-IP message module; the above-mentioned receiving end includes an IP message data parsing module; the source data is transmitted to the data-to-IP message module through the falling edge of the source clock; the above-mentioned data-to-IP message module packages the source data into an IP message and sends it to the above-mentioned receiving end through the network; the above-mentioned receiving end extracts the source data in the IP message through the above-mentioned IP message data parsing module.

[0053] This embodiment of the present application provides a method for clock recovery during VoIP data transmission using an FPGA. Specifically, the FPGA analyzes the size of the data in the data receiving FIFO at the VoIP data receiving end to dynamically correct the clock, thereby achieving synchronization between the receiving end clock and the transmitting end clock. This method can effectively avoid delay jitter in IP networks and ensure the stability of the recovered clock. By adopting this clock recovery control algorithm, it can effectively eliminate the interference of network jitter on clock recovery, quickly restore the clock to a stable state, reduce a large number of operations, and reduce the algorithm's hardware requirements.

[0054] When the embodiment of the present application is applied, Figure 1 As shown, the source data DATA is transmitted to the data-to-IP message module at the falling edge of the source clock CLK. The data-to-IP message module packages the source data DATA into an IP message and transmits it to the receiving end through the network. After receiving the IP message, the receiving end device extracts the source data from the IP message and then stores the source data in the receiving buffer RX FIFO. The clock recovery module uses a control algorithm to output a recovered clock based on the changes in the number of data in the receiving buffer. The data in the receiving buffer is output through the rising edge of this recovered clock. When the recovered clock is consistent with the source clock, although the jitter of the network delay will cause rapid fluctuations in the data in the receiving buffer, the data in the receiving buffer is generally stable. When the recovered clock is inconsistent with the source clock, the data in the receiving buffer will accumulate more or less over time. The clock recovery control algorithm first eliminates the influence of network delay jitter and then keeps the number of data in the receiving buffer stable for a relatively long time, thereby achieving the purpose of synchronizing the recovered clock with the source clock. As shown Figure 2 As shown, N represents the total capacity of the receive buffer; L represents the number of valid source data extracted from a network message; the preset value X represents the preset data quantity; the threshold value A represents the preset maximum quantity threshold value, which is used to determine the threshold value of increasing data in the receive buffer; the threshold value B represents the preset minimum quantity threshold value, which is used to determine the threshold value of decreasing data in the receive buffer. Figure 3 In FIG, the first timer is represented as cntA, the second timer is represented as cntB, and the clock rate represents the rate value of the recovered clock.

[0055] In the clock control algorithm of the present application, the preset data quantity X is calculated based on the maximum supported network jitter delay, X = data transmission rate of the source clock * maximum network jitter delay + message length L, the preset acceleration adjustment time interval Ta, the preset deceleration adjustment time interval Tb must be set greater than the maximum network jitter delay, the preset maximum number threshold A setting must be greater than X, and the preset minimum number threshold B setting must be less than X. The clock recovery algorithm mainly utilizes that when the recovered clock is equal to the source clock, when there is no jitter in the network, the number of data in the receiving buffer changes from the preset value X to XL, and when there is network jitter, the number of data in the receiving buffer changes from the preset value X to 0. In these two processes, the number of data in the receiving buffer is initially greater than the threshold B, less than the threshold A, and then less than the threshold B, and at the same time less than the threshold A, so the second timer cntB will be continuously cleared. Therefore, cntB will not exceed the preset deceleration adjustment time interval Tb, and the clock rate will remain unchanged. When the recovered clock rate value is greater than the source clock, the data received by the receive buffer will be less than the data read out of the receive buffer in each message cycle, resulting in less and less data in the receive buffer, and thus causing the variation interval of the number of data in the receive buffer to be always less than the set threshold B. To eliminate the misjudgment that the number of data in the receive buffer is less than the set threshold B due to network delay jitter, if the number of data in the receive buffer is less than the set threshold B within the time Tb, it is determined that the recovered clock rate is too high and the recovered clock rate needs to be reduced. When the recovered clock rate is less than the source clock, the data received by the receive buffer will be greater than the data read out of the receive buffer in each message cycle, resulting in more and more data in the FIFO, and thus causing the variation interval of the number of data in the receive buffer to be greater than the set threshold A. Since network jitter will only reduce the number of data in the receive buffer, as long as the data in the receive buffer is greater than threshold A, the recovered clock is determined to be too low and the recovered clock rate needs to be accelerated. However, to prevent the recovered clock from being unstable due to excessive frequency adjustment, a first timer, cntA, is added. Each time the recovered clock rate is accelerated, cntA is cleared and the timer is kept ticking. When cntA is greater than Ta, a second acceleration of the recovered clock rate is allowed. The specific implementation steps of the clock control algorithm are as follows:

[0056] 1. Initialize parameters, including the preset data quantity X in the receive buffer, the preset maximum quantity threshold A, the preset minimum quantity threshold B, the preset acceleration adjustment time interval Ta of the recovery clock, and the preset deceleration adjustment time interval Tb of the recovery clock.

[0057] 2. Read the number of remaining data in the receiving buffer of the current data reception.

[0058] 3. Determine whether the number of data in the receive buffer is greater than the preset data quantity X. If not, jump back to step 2; if yes, start data output from the receive buffer and output the data in the receive buffer according to the initial recovered clock rate.

[0059] 4. Read the number of remaining data in the receiving buffer of the current data reception.

[0060] 5. Determine whether the data in the receive buffer is empty. If so, consider that the network is disconnected, turn off the data output of the receive buffer, reset the rate value of the receive buffer output recovery clock to the initial value, and then jump to step 2; if not, execute the next step.

[0061] 6. The first timer cntA accumulates one cycle time.

[0062] 7. Determine whether the number of remaining data in the receive buffer is greater than the preset maximum number threshold A. If yes, proceed to the next step; if no, jump directly to step 9.

[0063] 8. Determine whether cntA is greater than the preset acceleration adjustment time interval Ta. If so, clear the first timer cntA, restore the clock rate value plus one, and jump to step 11; if not, jump directly to step 11.

[0064] 9. Determine whether the number of remaining data in the receive buffer is less than the preset minimum number threshold B. If so, the second timer cntB accumulates a cycle time and then executes the next step; if not, the second timer cntB is cleared and jumps to step 11.

[0065] 10. Determine whether cntB is greater than the preset deceleration adjustment time interval Tb. If so, reset the second timer cntB and reduce the rate value of the recovery clock by one; if not, do nothing.

[0066] 11. Adjust the output recovery clock according to the rate value. After successful adjustment, jump to step 4 to adjust the output recovery clock in a loop.

[0067] In summary, the embodiments of the present application provide a method and system for recovering the clock at a VOIP receiving end through FPGA: The present invention provides a method for recovering the clock at a VOIP receiving end through FPGA, wherein the sending end packages the source data transmitted by the falling edge of the source clock into a message and transmits it to the receiving end; the receiving end extracts the source data in the message and stores it in a receiving buffer; according to the change in the number of data in the receiving buffer, a clock control algorithm is used to output a recovered clock, and the data in the above-mentioned receiving buffer is output through the rising edge of the recovered clock, and the clock control algorithm introduces the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay. The present invention improves the accuracy and stability of clock recovery by optimizing the clock control algorithm, thereby ensuring high-quality transmission of VOIP data, solving the influence of the maximum network jitter delay, and making the recovered clock faster and more stable, while reducing the computational scale of the algorithm, thereby reducing the demand for hardware resources.

[0068] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for recovering clock at a VOIP receiving end by using FPGA, characterized in that: The sending end packages the source data transmitted on the falling edge of the source clock into a message and transmits it to the receiving end; The receiving end extracts the source data from the message and stores it in the receiving buffer; According to the change of the number of data in the receiving buffer, a clock control algorithm is used to output a recovery clock, and the data in the receiving buffer is output through the rising edge of the recovery clock; The clock control algorithm introduces the data transmission rate and maximum network jitter delay of the source clock.

2. The method for recovering clock at a VOIP receiving end through FPGA according to claim 1, characterized in that: The clock control algorithm specifically includes: Based on the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the receiving buffer reaches the preset data quantity; when it reaches it, the data in the receiving buffer is output according to the initial rate value of the recovered clock; and it is recorded as the first data output cycle.

3. The method for recovering clock at a VOIP receiving end through FPGA according to claim 2, characterized in that: The method of outputting a recovered clock according to a change in the number of data in the receiving buffer using a clock control algorithm, and outputting the data in the receiving buffer through a rising edge of the recovered clock, specifically includes: Determine in real time whether the number of remaining data in the receive buffer is greater than a preset maximum number threshold; if so, determine whether the first data output period is greater than a preset acceleration adjustment time interval of the recovery clock; if and only if it is greater than the preset acceleration adjustment time interval, clear the timing of the first data output period and increase the rate value of the recovery clock.

4. The method for recovering clock at a VOIP receiving end through FPGA according to claim 3, characterized in that: The method further comprises: outputting a recovered clock using a clock control algorithm according to a change in the number of data in the receive buffer, and outputting the data in the receive buffer through a rising edge of the recovered clock; If the number of remaining data in the receiving buffer is less than the preset maximum number threshold, determine whether the number of remaining data in the receiving buffer is less than the preset minimum number threshold; if so, record it as the second data output cycle; determine whether the second data output cycle is greater than the preset deceleration adjustment time interval of the recovery clock; if and only if it is yes, clear the timing of the second data output cycle and reduce the rate value of the recovery clock.

5. The method for recovering clock at a VOIP receiving end through FPGA according to claim 4, characterized in that: The first data output cycle is timed by a first timer; the second data output cycle is timed by a second timer.

6. A system for recovering the clock at the VOIP receiving end through FPGA, characterized in that: It includes a transmitting end and a receiving end; the transmitting end is used to package the source data transmitted by the falling edge of the source clock into a message and transmit it to the receiving end; the receiving end is used to extract the source data in the message; The receiving end includes a receiving buffer and a clock recovery control module; The receiving buffer is used to store the source data transmitted by the sending end; The clock recovery control module is used to output a recovery clock using a clock control algorithm according to the change in the number of data in the receiving buffer, and output the data in the receiving buffer through the rising edge of the recovery clock.

7. The system for recovering clock at a VOIP receiving end through FPGA according to claim 6, characterized in that: The clock control algorithm specifically includes: Based on the weight of the data transmission rate of the source clock and the weight of the maximum network jitter delay, the preset data quantity is calculated according to the message length; it is determined whether the number of data in the receiving buffer reaches the preset data quantity; when it reaches it, the data in the receiving buffer is output according to the initial rate value of the recovered clock; and it is recorded as the first data output cycle.

8. The system for recovering clock at a VOIP receiving end through FPGA according to claim 6, characterized in that: The sending end includes a data-to-IP message module; the receiving end includes an IP message data parsing module; the source data is transmitted to the data-to-IP message module through the falling edge of the source clock; the data-to-IP message module packages the source data into an IP message and sends it to the receiving end through the network; the receiving end extracts the source data in the IP message through the IP message data parsing module.

9. An electronic device comprising a memory, a processor, and a computer program running on the processor, characterized in that: When the processor executes the computer program, the steps of the method for recovering the clock at the VOIP receiving end through FPGA are implemented as described in any one of claims 1 to 5.

10. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the steps of the method for recovering a clock at a VOIP receiving end through an FPGA are implemented as claimed in any one of claims 1 to 5.

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