Parameter configuration method and system of interface link, storage medium and program product

Abstract

The application discloses a parameter configuration method and system of an interface link, a storage medium and a program product, relates to the technical field of communication, and comprises the following steps: identifying a device model, loading a corresponding storage component, configuring a time delay parameter and a driving capability parameter of the storage component, traversing and adjusting interface link parameters according to priority, and realizing parameter optimization in combination with loopback testing and stress testing to form an automatic parameter configuration and adjustment mechanism, so that accurate parameter adaptation and efficient optimization are realized, the labor cost is reduced, the communication link stability and the debugging efficiency are improved, the communication between devices is ensured to be reliable, and the problems, such as low efficiency, errors and high cost, in manual debugging mainly relied on in the related art when the link is unstable or communication is interrupted are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a parameter configuration method and system of an interface link, a storage medium and a program product. BACKGROUND

[0002] With the rapid development of information technology, high-speed digital interfaces are increasingly widely used in communication, computing and embedded systems. Among them, RGMII (Reduced Gigabit Media Independent Interface) as an efficient and low-cost Ethernet physical layer connection scheme is widely used in various network devices to realize data transmission between a media access controller (MAC) and a physical layer transceiver (PHY). The RGMII specification requires that the transmission (TX) and reception (RX) data signals and the clock signal maintain strict timing alignment, and the allowed deviation range is usually ±1.5 ns. However, factors such as PCB wiring length difference, signal integrity problems, chip batch difference and the like easily lead to timing violations, causing unstable links and even communication interruption.

[0003] In the related art, when the link is unstable or the communication is interrupted, manual intervention is mainly relied on, usually expensive test equipment such as an oscilloscope is used for signal measurement, and related delay parameters of the MAC or the PHY chip are manually adjusted, a large amount of manpower is needed to match, and finally the circuit is modified by hardware or the delay parameters of the mac or the phy are configured by firmware. However, since a large number of adjustable parameters are involved, omission is easy to occur; secondly, there is a coupling effect between some parameters, and if artificial traversal testing is performed, a large amount of manpower and material resources will be consumed. SUMMARY

[0004] The present application provides a parameter configuration method and system of an interface link, a storage medium and a program product to at least solve the problem in the related art that manual parameter debugging is mainly relied on when the link is unstable or the communication is interrupted, and there are problems of low efficiency, easy errors and high cost.

[0005] The application provides a parameter configuration system of an interface link, two ends of the interface link are connected with a first device and a second device, a physical layer of the first device communicates with the second device through the interface link, and the system comprises the following steps: identifying a model of the first device and a model of the second device, loading a first storage component of the physical layer according to the model of the first device, and loading a second storage component of the second device according to the model of the second device; configuring a first delay parameter and a first driving capability parameter of the first storage component and a second delay parameter and a second driving capability parameter of the second storage component; traversing interface link parameters configured by the first storage component and the second register, controlling a configuration engine to adjust the interface link parameters, and the interface link parameters comprise at least one of the first delay parameter, the first driving capability parameter, the second delay parameter and the second driving capability parameter; starting loopback detection test of the first device and the second device, and the loopback detection test comprises the following steps: in a test process, a detection engine calls a control engine to traverse the interface link parameters, the interface link parameters are adjusted in the traversing process, and first stress test is conducted on the interface link after the traversing is completed.

[0006] The application also provides a parameter configuration system of an interface link, two ends of the interface link are connected with a first device and a second device, a physical layer of the first device communicates with the second device through the interface link, and the system comprises the following steps: identifying a model of the first device and a model of the second device, loading a first storage component of the physical layer according to the model of the first device, and loading a second storage component of the second device according to the model of the second device; configuring a first delay parameter and a first driving capability parameter of the first storage component and a second delay parameter and a second driving capability parameter of the second storage component; traversing interface link parameters configured by the first storage component and the second register, controlling a configuration engine to adjust the interface link parameters, and the interface link parameters comprise at least one of the first delay parameter, the first driving capability parameter, the second delay parameter and the second driving capability parameter; starting loopback detection test of the first device and the second device, and the loopback detection test comprises the following steps: in a test process, a detection engine calls a control engine to traverse the interface link parameters, the interface link parameters are adjusted in the traversing process, and first stress test is conducted on the interface link after the traversing is completed.

[0007] Embodiments of the application also provide an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the parameter configuration method of the interface link.

[0008] The application also provides a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of any one of the parameter configuration methods of the interface link.

[0009] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the parameter configuration method of any one of the interface links.

[0010] Through the application, the device model is identified and the corresponding storage component is loaded, the time delay and driving capability parameters of the storage component are configured, the interface link parameters are adjusted according to the priority, and the parameter optimization is realized in combination with the loopback test and the stress test, thereby forming an automatic parameter configuration and adjustment mechanism, realizing accurate adaptation and efficient optimization of the parameters, reducing the labor cost, improving the link stability and the debugging efficiency, ensuring the reliable communication between devices, and solving the problems of low efficiency, easy error and high cost in the related art when the link is unstable or the communication is interrupted, which mainly relies on manual debugging. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1 The flowchart of the parameter configuration method of the interface link provided by the embodiments of the application is shown in the figure.

[0013] Figure 2 The connection block diagram of the two-end devices of the interface link provided by one of the embodiments of the application is shown in the figure.

[0014] Figure 3 The parameter iteration flowchart provided by one of the embodiments of the application is shown in the figure.

[0015] Figure 4 The stress test flowchart provided by one of the embodiments of the application is shown in the figure.

[0016] Figure 5 The block diagram of the parameter configuration system of the interface link provided by the embodiments of the application is shown in the figure.

[0017] Figure 6 The specific framework diagram of the parameter configuration system of the interface link provided by one of the embodiments of the application is shown in the figure. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the application will be described clearly and completely in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0019] It should be noted that in the description of the present application, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0020] Embodiments of the present application provide a parameter configuration system of an interface link, the interface link connects a first device and a second device at both ends, and a physical layer of the first device communicates with the second device through the interface link. Wherein, the first device can be a MAC controller, and the second device can be a PHY chip, and the two communicate through an RGMII bus.

[0021] Specifically, as shown in the figure, Figure 1 The parameter configuration method of the interface link includes the following steps:

[0022] In step S101, the model of the first device and the model of the second device are identified, the first storage component of the physical layer is loaded according to the model of the first device, and the second storage component of the second device is loaded according to the model of the second device.

[0023] For the convenience of understanding, the embodiments of the present application can be described in detail with the first device as a MAC chip and the second device as a PHY chip. As shown in the figure, Figure 2 The MAC chip is connected with the PHY chip through an RGMII bus (txc\tx_ctl\txd\rxc\rx_ctl\rxd) for communication, and an mdc / mdio bus is used for management of the PHY.

[0024] Now in the specification, the signal naming of the PHY chip should be consistent with that of the MAC chip, so for the PHY chip, the signals starting with tx are the reception of the PHY chip, and the signals starting with rx are the transmission of the PHY chip. Pay attention to distinguish and understand later. The delay parameter is the phase of txc\rxc, which generally delays the transmission end of the chip, so that it can be reflected on the actual physical signal, which can be measured by an oscilloscope. If the reception of the chip is delayed, the physical signal cannot be measured, so the training priority is to use the transmission end of the chip for training first. When the training result is not ideal, the reception end of the chip is used for delay test. In some scenarios, the driving capability of the chip will also affect the signal quality, so the driving capability is also included in the tuning algorithm, with the lowest priority. The driving capability adjustment is generally the data line of the chip, but different chips may not be the same, which is only used to explain that all transmission signals are adjusted together.

[0025] It can be understood that the embodiment of the present application can identify the model of the two-end device and load the corresponding parameter configuration information. In the embedded system, the MAC chip is usually integrated with the master chip, and the model can be obtained by reading the chip ID or from the configuration file, and the first storage component corresponding to the MAC chip is loaded. For the PHY chip, the manufacturer and model of the PHY chip can be identified by reading reg02 and reg03 of the standard PHY through the mdio bus, and the second storage component of the PHY chip is loaded according to the identified content. The storage component refers to the parameter configuration options and parameter adjustment range of the device of the model.

[0026] In the embodiment of the present application, the model of the first device and the model of the second device are identified, including: determining the first model of the first device through the configuration file, and loading the first register operation method of the first storage component according to the first model; determining the second model of the second device through the bus, and loading at least one of the second register operation method, the parameter configuration option and the parameter adjustment range of the second storage component according to the second model.

[0027] Since the MAC is usually integrated with the chip in the embedded field, the first model of the first device can be determined by directly reading the configuration file in the embodiment of the present application, and then the corresponding first register operation method in the first storage component is loaded according to the first model, which provides a basis for the subsequent configuration of MAC related parameters (such as delay, driving ability, etc.). For the second device (PHY), the second model of the second device can be determined by reading the reg02 and reg03 registers of the standard PHY through the MDIO bus in the embodiment of the present application; according to the second model, the corresponding second register operation method in the second storage component is loaded, and the parameter configuration option (which parameters can be adjusted) and the parameter adjustment range are also loaded to support the accurate configuration of the PHY parameters. Therefore, the embodiment of the present application can efficiently and accurately obtain the model and related operation information of the MAC and the PHY according to the different characteristics of the MAC and the PHY, which lays a foundation for the subsequent parameter configuration and link optimization.

[0028] In step S102, the first delay parameter and the first driving capability parameter of the first storage component, and the second delay parameter and the second driving capability parameter of the second storage component are configured.

[0029] The first delay parameter refers to the sending / receiving delay of the MAC chip (such as MAC_TX_DLY), the first driving capability parameter refers to the driving strength of the output signal of the MAC chip, the second delay parameter refers to the sending / receiving delay of the PHY chip (such as PHY_RX_DLY), and the second driving capability parameter refers to the driving strength of the output signal of the PHY chip. The embodiment of the application can write these parameters through the MDIO or other interfaces according to the register addresses and values in the respective storage components.

[0030] In step S103, the interface link parameters configured by the first storage component and the second storage component are traversed, and the interface link parameters are adjusted. The interface link parameters include at least one of the first delay parameter, the first driving capability parameter, the second delay parameter, and the second driving capability parameter.

[0031] The embodiment of the application automatically attempts all possible delay and driving capability parameter combinations to find a configuration that enables the RGMII link to work normally through parameter traversal, various parameter priority controls, and the like.

[0032] The first storage component includes a first register and a second register. The first register stores the first delay parameter, and the second register stores the first driving capability parameter. The second storage component includes a third register and a fourth register. The third register stores the second delay parameter of the second storage component, and the fourth register stores the second driving capability parameter.

[0033] In an embodiment of the application, before traversing the interface link parameters configured by the first storage component and the second storage component, at least one of the read / write method and the register address of the first register is configured; at least one of the read / write method and the register address of the second register is configured; at least one of the read / write method and the register address of the third register is configured; and at least one of the read / write method and the register address of the fourth register is configured.

[0034] It can be understood that the first register and the second register of the first storage component correspond to the storage carriers of the delay parameters (such as MAC TX_DLY and MAC RX_DLY) and the driving capability parameters (MAC TX_DRV) of the MAC respectively; and the third register and the fourth register of the second storage component correspond to the storage carriers of the delay parameters (such as PHY RX_DLY and PHY TX_DLY) and the driving capability parameters (PHY RX_DRV) of the PHY. Before the interface link parameters configured by the first storage component and the second storage component are traversed, at least one of the respective read-write methods and the register addresses of the above four registers is configured, the read-write logic and the address management of different chip registers are realized, and it is ensured that the delay parameters, the driving capability parameters and the like can be correctly set and called. Therefore, the division of the parameters and the configurations in the embodiments of the present application provides a basis for subsequent parameter traversal and optimization, and ensures the accuracy and efficiency of parameter operation in the communication link timing optimization process.

[0035] Specifically, the first delay parameter includes a first sending delay and a second sending delay, the second delay parameter includes a second sending delay and a second receiving delay, and the traversal process of the interface link parameters includes: performing a first test stage, adjusting at least one of the first receiving delay, the second sending delay, the first sending delay and the second receiving delay, performing a second stress test on the interface link, adjusting at least one of the first receiving delay, the second sending delay, the first sending delay and the second receiving delay if the test fails, and performing a second test stage if the test passes; starting the second test stage, recording the number of valid samples, determining whether the number of valid samples is less than a sample number threshold, performing the first test stage if the number of valid samples is less than the sample number threshold, and adjusting the first driving capability parameter and the second driving capability parameter if the at least one of the first receiving delay, the second sending delay, the first sending delay and the second receiving delay is traversed and the number of valid samples is less than the sample number threshold, until the interface link parameter traversal is completed.

[0036] Specifically, as shown in Figure 3 The embodiments of the present application realize the overall optimization of the parameters by adjusting the delay parameters and the driving capability parameters in stages, in combination with the stress test and the sample number determination, and the specific implementation is as follows:

[0037] The first test stage is a core parameter adjustment link, and the first receiving delay, the second sending delay, the first sending delay and the second receiving delay are preferentially adjusted. After adjustment, a second stress test is performed to verify the validity of the link. If the test fails, the set of delay parameters will be repeatedly adjusted; if the test passes, the second test stage is entered, which reflects the priority of the delay parameters in the link optimization.

[0038] The second test stage judges the sufficiency of the current parameter adjustment by recording the number of valid samples (i.e. the parameter combinations passed the test) and comparing the number of valid samples with a sample number threshold: if the number of valid samples is insufficient, the first test stage is returned to reiterate the delay parameters to ensure that no potential valid combination is missed; if the number of valid samples is still insufficient after all the delay parameters are iterated, the first driving capability parameter and the second driving capability parameter (the lower priority parameters) are adjusted, and the first test stage is re-executed until all the parameters are iterated, thereby ensuring the orderliness and completeness of the parameter iteration.

[0039] In step S104, a loopback detection test of the first device and the second device is started, and the loopback detection test comprises: iterating the interface link parameters in a test process, adjusting the interface link parameters in the iteration process, and performing a first stress test on the interface link after the iteration is completed.

[0040] The embodiment of the application can verify the link quality under each group of parameters, and only needs to configure the interface link parameters to complete the link self-checking by starting the loopback test between the MAC chip and the PHY chip, without the need of external network connection or additional test equipment; after all the parameter combinations are tested, the preliminary qualified parameters are screened out; the parameters are subjected to a long-time and large-data stress test (such as a million packets, large packet transmission), and the truly stable parameter configuration is further screened out.

[0041] In an embodiment of the application, the iteration of the interface link parameters in the test process comprises: obtaining the parameter priority of the interface link parameters; and iterating the interface link parameters according to the parameter priority.

[0042] The interface link parameters are stored in the first parameter space, the second parameter space and the third parameter space, the priority of the first parameter space is higher than that of the second parameter space, the priority of the second parameter space is higher than that of the third parameter space, the first parameter space, the second parameter space and the third parameter space are iterated according to the priority, the first parameter space comprises a first receiving delay and a second sending delay, the second parameter space comprises a first sending delay and a second receiving delay, and the third parameter space comprises a first driving capability parameter and a second driving capability parameter.

[0043] It can be understood that the first, second and third parameter spaces are iterated according to the priority in the embodiment of the application, wherein,

[0044] The first parameter space (the highest priority): contains the MAC TX_DLY (the first receiving delay) of the first storage component and the PHY RXDLY (the second sending delay) of the second storage component, and is mainly for adjusting the delay of the sending end of the device.

[0045] Second parameter space (medium priority): contains MAC RXDLY (first transmission delay) of the first storage component and PHY TXDLY (second receiving delay) of the second storage component, and adjusts the delay of the receiving end of the device.

[0046] Third parameter space (lowest priority): contains MAC TX_DRV (first driving capability parameter) of the first storage component and PHY RX_DRV (second driving capability parameter) of the second storage component, and adjusts the driving capability of the device.

[0047] In actual execution, the embodiment of the present application preferentially traverses the first parameter space, calculates the failure rate of the parameter in real time (for example, if the packet loss rate exceeds a threshold, it is marked as failure), records the valid parameter and the bit error rate; if the number of qualified samples is less than a threshold (for example, 10), the second parameter space is traversed, and the traversal of the first parameter space needs to be re-executed every time it is adjusted; if it still does not meet the requirements, the third parameter space is entered, and the driving capability is adjusted, and the traversal of the first two parameter spaces is re-executed.

[0048] In addition, the embodiment of the present application can also record the parameters and states before the test is interrupted, support breakpoint continuous measurement, and avoid repeated traversal of the tested parameters.

[0049] It should be noted that the configuration of the delay parameter in the embodiment of the present application may be different in the step adjustment of each manufacturer. Here, the step of yt8531s is used for illustration. The delay increases by 150ps every time the register increases by 1. The register occupies 4 bits, and the adjustment range is 0-2.4ns. The driving capability: the default driving capability is used at the beginning, the driving capability parameter is based on the chip configuration, and is classified. Taking yt8531s as an example, 3 bits are used for control. From 000-111, 000 is off, the default is 011, and when the link is not connected, it should be adjusted from 001 to 111.

[0050] In an embodiment of the present application, the test process of the first pressure test includes: starting the first pressure test, identifying whether the first pressure test of the interface link passes; if the first pressure test of the interface link passes, recording the interface link parameters and the error rate of the test passing, and generating a test report according to the interface link parameters and the error rate of the test passing.

[0051] It can be understood that, for example, Figure 4As shown, the embodiments of the present application can verify the validity of the interface link parameters through the first pressure test and form a quantitative result. Specifically, after starting the first pressure test, it is determined whether the interface link passes the test. If it passes, the interface link parameters (such as delay, driving capacity, etc.) and the corresponding error rate at the time of passing the test are recorded, and finally a test report is generated based on these data, which provides a reference basis for subsequent parameter optimization, and the stability performance of the link can also be intuitively presented through the test report, ensuring the reliability of the interface link parameter configuration.

[0052] In addition, in the actual test process, the embodiments of the present application can perform secondary pressure testing on other devices according to the parameters screened by one device, and screen specific general configuration, so as to prevent the process of parameter mismatching or re-matching caused by hardware slight differences, and effectively reduce the time cost and labor cost.

[0053] In an embodiment of the present application, the parameter configuration method of the interface link further includes: in the loopback detection test process, collecting loopback data, wherein the loopback data includes at least one of sending loopback data packets, receiving loopback data packets, verifying loopback data packets, and data packet index accumulation. In the loopback detection test process, the loopback data is error counted.

[0054] It can be understood that the loopback detection test of the first device (MAC) and the second device (PHY) is started by the starting module of the embodiments of the present application, for example, the loopback environment is constructed by configuring the loopback register of the PHY, and the test can be carried out without external hardware support. The detection module is used to collect loopback data, including at least one of sending loopback data packets, receiving loopback data packets, verifying loopback data packets, and data packet index accumulation. In the actual execution process, the detection is carried out by the method of constructing a loopback packet, sending and then reading, detecting whether there is data return, and adding the concept of id in the data, so that whether there is a packet loss scenario can be conveniently detected. Due to the size problem of network packets, hierarchical detection is also used for loopback test packets, which only needs to be classified into two categories of small packet and large packet detection. Small packets are mainly used to quickly verify whether the rgmii parameters are consistent, and large packets are used to test stability. Small packets use data amount below 32 bytes, and large packets use 1000 bytes or more for detection, which facilitates the detection of link reliability. Detection rounds: small packet fast detection, at least 1000 packets are used; pressure detection is at least to million packets. Packet loss rate: only when the packet loss rate is less than 1 / 1000, the corresponding parameters can enter the next round; large packet pressure detection, only when the packet loss rate is less than 1 / 10000, the link is considered to be basically reliable. The counting module counts the errors of the loopback data, such as the small packet fast detection in the above embodiment, the packet loss rate is less than 1 / 1000, and the large packet pressure test needs to be less than 1 / 10000, and the interface link is considered to be basically reliable.

[0055] In an embodiment of the present application, the parameter configuration method of the interface link further comprises: recording the parameter traversal state at the time of interruption when the test is interrupted abnormally, and restoring the parameter traversal state at the current time of the interface link to the parameter traversal state at the time of interruption when the test is resumed.

[0056] It can be understood that the embodiments of the present application can cope with abnormal interruption in the test process, can record the parameter traversal state at the time of interruption when the test is interrupted abnormally, and can restore the current parameter traversal state of the interface link to the state at the time of interruption when the test is resumed, and perform breakpoint testing. Thus, it can avoid the waste of previous parameter traversal work due to interruption of the test, and does not need to start from the beginning to re-traverse, thereby saving a lot of time and labor cost, improving the efficiency of parameter optimization, and ensuring that the entire test process can be carried out continuously and efficiently.

[0057] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0058] According to the parameter configuration system of the interface link provided by the embodiments of the present application, the identification engine identifies the device model and loads the corresponding storage component, the configuration engine configures the delay and driving capability parameters, the control engine traverses and adjusts the interface link parameters according to the priority, and the detection engine realizes parameter optimization in combination with loopback test and stress test, forms an automatic parameter configuration and adjustment mechanism, realizes accurate adaptation and efficient optimization of parameters, reduces labor cost, improves link stability and debugging efficiency, ensures reliable communication between devices, and solves the problems of low efficiency, easy error and high cost in manual debugging in the related art when the link is unstable or communication is interrupted.

[0059] Specifically, as shown in Figure 5 The parameter configuration system of the interface link 10 comprises an identification engine 100, a configuration engine 200, a control engine 300 and a detection engine 400.

[0060] The identification engine 100 is configured to identify the model of the first device and the model of the second device, load the first storage component of the physical layer according to the model of the first device, and load the second storage component of the second device according to the model of the second device. The configuration engine is configured to configure the first latency parameter and the first driving capability parameter of the first storage component, and the second latency parameter and the second driving capability parameter of the second storage component. The control engine 300 is configured to traverse the interface link parameter of the first storage component and the second register, control the configuration engine to adjust the interface link parameter, and the interface link parameter includes at least one of the first latency parameter, the first driving capability parameter, the second latency parameter and the second driving capability parameter. The detection engine 400 is configured to start a loopback detection test of the first device and the second device, and the loopback detection test includes that the detection engine 400 calls the control engine 300 to traverse the interface link parameter during the test process, adjusts the interface link parameter during the traversal process, and performs the first stress test on the interface link after the traversal ends.

[0061] The parameter configuration system of the interface link of the embodiment of the application realizes the automatic identification of hardware, intelligent traversal of parameters, closed-loop loopback test and hierarchical stress verification, and realizes the automatic configuration of the timing and driving parameters of the interface link without manual intervention, with high efficiency and high reliability, and significantly shortens the product development cycle.

[0062] In an embodiment of the application, the first storage component includes a first register and a second register, and the second storage component includes a third register and a fourth register, wherein the first register stores the first latency parameter, the second register stores the first driving capability parameter, the third register stores the second latency parameter of the second storage component, and the fourth register stores the second driving capability parameter.

[0063] In an embodiment of the application, the control engine 300 is provided with a parameter priority, and the interface link parameter is traversed in order according to the parameter priority.

[0064] In an embodiment of the application, the control engine 300 is provided with a first parameter space, a second parameter space and a third parameter space, the priority of the first parameter space is higher than that of the second parameter space, the priority of the second parameter space is higher than that of the third parameter space, and the first parameter space, the second parameter space and the third parameter space are traversed in order according to the priority.

[0065] In an embodiment of the application, the first latency parameter includes a first sending latency and a second sending latency, the second latency parameter includes a second sending latency and a second receiving latency, the first parameter space includes a first receiving latency and a second sending latency, the second parameter space includes a first sending latency and a second receiving latency, and the third parameter space includes a first driving capability parameter and a second driving capability parameter.

[0066] In an embodiment of the present application, the configuration engine 200 comprises a first configuration module, a second configuration module, a third configuration module and a fourth configuration module, wherein the first configuration module configures at least one of the read-write method and the register address of the first register, the second configuration module configures at least one of the read-write method and the register address of the second register, the third configuration module configures at least one of the read-write method and the register address of the third register, and the fourth configuration module configures at least one of the read-write method and the register address of the fourth register.

[0067] In an embodiment of the present application, the identification engine 100 comprises a first identification module and a second identification module, wherein the first identification module determines the first model of the first device through the configuration file and loads the first register operation method of the first storage component according to the first model, and the second identification module determines the second model of the second device through the bus and loads at least one of the second register operation method, the parameter configuration option and the parameter adjustment range of the second storage component according to the second model.

[0068] In an embodiment of the present application, the control engine 300 comprises a scheduling module and a management module, wherein the scheduling module is used to traverse the interface link parameter and adjust the interface link parameter in the traversal process, and the management module is used to manage the driving capability of the first device and the second device.

[0069] In an embodiment of the present application, the detection engine 400 comprises a starting module and a detection module, wherein the starting module is used to start the loopback detection test of the first device and the second device, and the detection module is used to collect the loopback data, wherein the loopback data comprises at least one of the sending loopback data packet, the receiving loopback data packet, the checking loopback data packet and the data packet index accumulation.

[0070] In an embodiment of the present application, the detection engine 400 further comprises a counting module, which is used to count the errors of the loopback data.

[0071] The following will be described in combination with Figure 6 The parameter configuration system of the interface link in the embodiment of the present application will be described in detail, as shown in Figure 6 the main program, the chip identification engine, the optimization control engine, the register configuration layer and the detection module.

[0072] The main program is responsible for parsing the configuration file and obtaining the parameters in the configuration file. In the embodiment of the present application, the configuration of the register parameters is carried by the configuration file, which is convenient for subsequent expansion. In the configuration file, the main configuration is the training level (fast training, pressure training, etc.). The parameter configuration configures the register address and parameter range of different MAC chips and different PHY chips.

[0073] The identification engine comprises a MAC identification module (a first identification module) and a PHY identification module (a second identification module). The MAC identification module obtains a MAC chip model, a register base address and a parameter adjustable range by reading a device configuration file. The PHY identification module can identify a chip manufacturer and model by reading reg02 and reg03 of a standard PHY through an mdio bus. According to the identified content, a register operation method, a parameter configuration option (which parameters are adjustable) and a parameter adjustment range of the corresponding chip are loaded.

[0074] The control engine comprises a parameter traversal scheduler, a driver capability manager and an interrupt recovery module. The parameter traversal scheduler traverses high-priority parameters (such as a MAC TX_DLY) according to parameter priority levels. If the number of valid samples of the high-priority parameters is not enough after testing, the next level of parameter traversal is entered. The driver capability manager re-traverses a core delay parameter after the driver capability is adjusted when there is no valid result of the delay parameter traversal. When a test interruption (such as device abnormal power-off or manual termination) is detected, the interrupt recovery module automatically records the current parameter level, the measured value and the packet loss statistics state (breakpoint snapshot). The next time the device is started, the breakpoint is continued to be executed, and it is not necessary to start from the beginning to traverse, thereby saving repeated test time.

[0075] The configuration engine comprises a first configuration module (a MAC delay configuration module), a second configuration module (a MAC driver capability configuration module), a third configuration module (a PHY delay configuration module) and a fourth configuration module (a PHY driver capability configuration module). Different configuration modules encapsulate register read and write operations and register addresses of different chips.

[0076] The detection engine comprises a starting module, a detection module and a calculation module. The starting module starts the internal loopback detection function by writing a register, thereby saving the cost of external hardware construction. The detection module first detects small packets (to filter out obviously problematic parameters), and then runs a large packet stress test (to confirm stability), thereby ensuring parameter reliability through hierarchical verification. The calculation module records the number of sent loopback data packets, the number of received loopback data packets and the number of error loopback data packets in the test process.

[0077] Embodiments of the present application also provide an electronic device comprising a processing circuit, wherein the processing circuit is provided with the interface link parameter configuration system of the above-described embodiments.

[0078] Embodiments of the present application also provide a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is configured to execute the steps in any of the above-described interface link parameter configuration method embodiments when running.

[0079] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0080] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the parameter configuration method embodiments of any of the above-described interface links.

[0081] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] The parameter configuration system for an interface link provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A parameter configuration method for an interface link, characterized in that, The interface link connects a first device and a second device at both ends, and the physical layer of the first device communicates with the second device through the interface link. The method includes: Identify the model of the first device and the model of the second device, load the first storage component of the physical layer according to the model of the first device, and load the second storage component of the second device according to the model of the second device; Configure the first latency parameter and the first drive capability parameter of the first storage component, and the second latency parameter and the second drive capability parameter of the second storage component; The interface link parameters configured for the first storage component and the second storage component are traversed, and the interface link parameters are adjusted. The interface link parameters include at least one of the first latency parameter, the first drive capability parameter, the second latency parameter, and the second drive capability parameter. Initiate a loopback detection test for the first device and the second device. The loopback detection test includes: traversing the interface link parameters during the test process, adjusting the interface link parameters during the traversal, and performing a first stress test on the interface link after the traversal is completed.

2. The parameter configuration method for the interface link according to claim 1, characterized in that, The first delay parameter includes a first transmission delay and a first reception delay, the second delay parameter includes a second transmission delay and a second reception delay, and the traversal process of the interface link parameters includes: The first test phase is executed, adjusting at least one of the first receive delay, the second send delay, the first send delay, and the second receive delay, and performing a second stress test on the interface link. If the test fails, at least one of the first receive delay, the second send delay, the first send delay, and the second receive delay is adjusted. If the test passes, the second test phase is executed, and the parameter combination that passes the test is recorded as a valid sample. The second test phase is initiated, the number of valid samples is recorded, and it is determined whether the number of valid samples is less than the sample number threshold. If the number of valid samples is less than the sample number threshold, the first test phase is executed. After traversing at least one of the first receive delay, the second transmit delay, the first transmit delay, and the second receive delay, if the number of valid samples is less than the sample number threshold, then adjust at least one of the first driving capability parameter and the second driving capability parameter, and execute the first test phase until the interface link parameters have been traversed.

3. The parameter configuration method for the interface link according to claim 2, characterized in that, The test procedure for the first stress test includes: Initiate the first stress test to determine whether the first stress test of the interface link passes. If the first stress test of the interface link passes, record the interface link parameters and error rate that passed the test, and generate a test report based on the interface link parameters that passed the test and the error rate.

4. The parameter configuration method for the interface link according to claim 2, characterized in that, The step of traversing the interface link parameters during the testing process includes: Obtain the parameter priority of the interface link parameters; The interface link parameters are traversed according to the parameter priority.

5. The parameter configuration method for the interface link according to claim 4, characterized in that, The interface link parameters are stored in a first parameter space, a second parameter space, and a third parameter space. The first parameter space has a higher priority than the second parameter space, and the second parameter space has a higher priority than the third parameter space. The first parameter space, the second parameter space, and the third parameter space are traversed according to their priorities. The first parameter space includes a first receive delay and a second transmit delay. The second parameter space includes a first transmit delay and a second receive delay. The third parameter space includes a first drive capability parameter and a second drive capability parameter.

6. The parameter configuration method for the interface link according to claim 1, characterized in that, The first storage component includes a first register and a second register, wherein the first register stores the first latency parameter and the second register stores the first drive capability parameter.

7. The parameter configuration method for the interface link according to claim 6, characterized in that, Before iterating through the interface link parameters configured for the first and second storage components, the process also includes: Configure at least one of the read / write method and register address of the first register; Configure at least one of the read / write method and register address of the second register.

8. The parameter configuration method for the interface link according to claim 1, characterized in that, The second storage component includes a third register and a fourth register, wherein the third register stores a second latency parameter of the second storage component and the fourth register stores a second drive capability parameter.

9. The parameter configuration method for the interface link according to claim 8, characterized in that, Before iterating through the interface link parameters configured for the first and second storage components, the process also includes: Configure at least one of the read / write method and register address of the third register; Configure at least one of the read / write methods and register addresses of the fourth register.

10. The parameter configuration method for the interface link according to claim 1, characterized in that, The identification of the model of the first device and the model of the second device includes: The first model of the first device is determined by the configuration file, and the first register operation method of the first storage component is loaded according to the first model. The second model of the second device is determined by the bus, and at least one of the second register operation method, parameter configuration options, and parameter adjustment range of the second storage component is loaded according to the second model.

11. The parameter configuration method for the interface link according to claim 1, characterized in that, Also includes: During the loopback detection test, loopback data is collected, which includes at least one of sending loopback data packets, receiving loopback data packets, verifying loopback data packets, and accumulating data packet indexes.

12. The parameter configuration method for the interface link according to claim 11, characterized in that, Also includes: During the loopback detection test, error counts are performed on the loopback data.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the parameter configuration method for the interface link as described in any one of claims 1 to 12 when executing the computer program.

14. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the parameter configuration method for the interface link according to any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the parameter configuration method for the interface link according to any one of claims 1 to 12.

Images