Clock-buffer bi-directional linkage adjustment method and device for voice gateway

Abstract

The application relates to the technical field of voice communication, and discloses a clock-buffer bidirectional linkage adjustment method and device for a voice gateway. The method comprises the following steps: acquiring a clock frequency error, and compensating for an initial depth of a jitter buffer according to the clock frequency error to obtain a target depth of the jitter buffer; the initial depth of the jitter buffer is a dynamic initial depth at a current moment determined based on a prediction model; a depth change rate corresponding to the jitter buffer is determined based on an original depth of the jitter buffer and the target depth of the jitter buffer; a dynamic gain of a clock phase-locked loop is determined based on the depth change rate, and a clock signal is updated according to the dynamic gain, so that the clock-buffer bidirectional linkage adjustment can effectively improve the accuracy and reliability of voice playing of the voice gateway.

Description

Technical Field

[0001] This disclosure generally relates to the field of voice communication technology, and specifically to a clock-buffer bidirectional linkage adjustment method and apparatus for a voice gateway. Background Technology

[0002] A voice gateway is a VoIP (Voice over IP) / FoIP (Fax over IP) media access gateway used in NGN (Next Generation Network) or IMS (IP Multimedia Subsystem) networks. In NGN and IMS network architectures, both voice and data services are transmitted over IP networks. The role of the voice gateway is to convert analog voice data to IP data, allowing traditional analog telephone equipment to access modern IP networks, thus realizing the IP-based transformation of voice communication.

[0003] In IP networks, real-time voice data is transmitted via RTP (Real-Time Transport Protocol), encapsulated in UDP (User Datagram Protocol) packets. Using UDP for data transmission can lead to out-of-order delivery and duplicate packets. To ensure efficient voice transmission and call quality over data networks, the adverse effects of network latency, jitter, packet loss, out-of-order delivery, and duplicate packets must be considered.

[0004] Network jitter, or latency variation, occurs in VoIP applications. The sending gateway's DSP (Digital Signal Processing) transmits encoded and compressed voice packets at consistent time intervals. As these packets travel through the IP network, jitter occurs, causing the time intervals between adjacent packets to change by the time they reach the receiving gateway. If the receiving gateway then directly plays these jittered voice packets, the receiver will hear a different message than the sender, thus affecting the quality of voice communication.

[0005] Currently, the solution to this network jitter problem involves adding a jitter buffer (JB) mechanism to the receiving gateway. This buffers received voice packets for a certain period, allowing the receiving gateway to play them at the same intervals as when they were sent. By adding a delay at the receiving end, the jitter problem caused by the IP network is eliminated.

[0006] JB depth is the difference between the time the first packet arrives at the JB queue and the time the packet is played (i.e., removed from the JB queue). Once the playback time of the first packet is determined, the playback time of subsequent packets is also determined. Therefore, JB depth is used to describe the initial delay caused by the JB queue.

[0007] Traditional solutions to jitter problems primarily rely on static JB (Job Bound) mechanisms. A static JB mechanism means that the JB depth remains constant throughout the entire voice playback process. However, because the latency experienced by voice packets in an IP network constantly changes with the current network conditions, a static JB solution with a fixed JB depth cannot effectively combat jitter.

[0008] Based on this, related technologies propose to accurately reflect the current network status by statistically analyzing the average latency and average jitter of the network in real time, and to adjust the JB depth in real time according to the constantly changing average latency and average jitter conditions in the network. However, dynamic adjustment of the JB depth can cause changes in the clock frequency, resulting in abnormal speech playback. Summary of the Invention

[0009] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a clock-buffer bidirectional linkage adjustment method and apparatus for a voice gateway, which can effectively improve the accuracy and reliability of voice playback by the voice gateway through clock-buffer bidirectional linkage adjustment.

[0010] In a first aspect, embodiments of this application provide a clock-buffer bidirectional linkage adjustment method for a voice gateway, comprising:

[0011] The clock frequency error is obtained, and the initial depth of the jitter buffer is compensated according to the clock frequency error to obtain the target depth of the jitter buffer; the initial depth of the jitter buffer is the dynamic initial depth at the current time determined based on the prediction model.

[0012] Based on the original depth of the jitter cache and the target depth of the jitter cache, determine the depth change rate corresponding to the jitter cache;

[0013] The dynamic gain of the clock phase-locked loop is determined based on the depth change rate, and the clock signal is updated according to the dynamic gain.

[0014] In some embodiments, obtaining the clock frequency error and compensating for the initial depth of the jitter buffer based on the clock frequency error includes:

[0015] Obtain the clock frequency error and nominal sampling rate, and determine the frequency compensation coefficient;

[0016] The initial depth of the jitter buffer is compensated based on the frequency compensation coefficient to obtain the target depth of the jitter buffer.

[0017] In some embodiments, when the voice gateway employs satellite communication, the method further includes:

[0018] Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching;

[0019] The Doppler dynamic compensation coefficient is obtained based on the Doppler frequency shift and the Doppler dynamic compensation factor.

[0020] The initial depth of the jitter buffer is compensated based on the Doppler dynamic compensation coefficient to obtain the target depth of the jitter buffer.

[0021] In some embodiments, prior to the dynamic initial depth determined based on the prediction model at the current moment, the method further includes:

[0022] The handover warning time and the current time are predicted based on the satellite ephemeris, and the handover growth factor is determined based on the handover warning time and the current time.

[0023] The initial depth of the jitter cache is determined based on the switching growth factor and the original depth of the jitter cache.

[0024] In some embodiments, before determining the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache, the method further includes:

[0025] Obtain the compensated jitter buffer target depth requirement value and the resource data corresponding to the voice gateway terminal. The resource data includes at least available memory, utilization factor, encoding bitrate and frame duration.

[0026] Based on the resource data, the target depth constraint value of the jitter cache is determined;

[0027] The jitter cache target depth is determined based on the jitter cache target depth requirement value and the jitter cache target depth constraint value, and is used to calculate the depth change rate.

[0028] In some embodiments, determining the dynamic gain of the clock phase-locked loop based on the depth change rate includes:

[0029] The dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop are determined based on the depth change rate, respectively.

[0030] Secondly, embodiments of this application provide a clock-buffer bidirectional linkage adjustment device for a voice gateway, comprising:

[0031] The depth compensation module is used to obtain the clock frequency error and compensate the initial depth of the jitter buffer according to the clock frequency error to obtain the target depth of the jitter buffer; the initial depth of the jitter buffer is a dynamic initial depth determined based on the prediction model at the current time.

[0032] The determination module is used to determine the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache;

[0033] The clock update module is used to determine the dynamic gain of the clock phase-locked loop based on the depth change rate, and update the clock signal according to the dynamic gain.

[0034] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in embodiments of this application.

[0035] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in embodiments of this application.

[0036] Fifthly, embodiments of this application provide a computer program product, including a computer program, characterized in that, when the computer program is executed by a processor, it implements the method described in embodiments of this application.

[0037] The clock-buffer bidirectional linkage adjustment method and apparatus for voice gateways proposed in this application, through the mutual coordination of clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation, enables accurate and reliable adjustment of the jitter buffer depth of the voice gateway, adapting to changes in dynamic latency and improving the accuracy of voice playback. Simultaneously, by dynamically adjusting the dynamic gain of the clock phase-locked loop based on the depth change rate, the reliability of clock operation is ensured. This allows the clock signal to converge quickly when jitter buffer depth is frequent or drastic, further ensuring the accuracy and reliability of voice playback.

[0038] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0039] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0040] Figure 1 The implementation environment architecture diagram of the clock-buffer bidirectional linkage adjustment method for a voice gateway provided in the embodiments of this application is shown;

[0041] Figure 2 A schematic diagram of the structure of a receiving gateway provided in an embodiment of this application is shown;

[0042] Figure 3 A schematic flowchart of a clock-buffer bidirectional linkage adjustment method for a voice gateway according to an embodiment of this application is shown;

[0043] Figure 4 A schematic diagram of the structure of a clock-buffer bidirectional linkage adjustment device for a voice gateway provided in an embodiment of this application is shown;

[0044] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing an electronic device or server according to embodiments of this application is shown. Detailed Implementation

[0045] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] With the rapid development of communication technology, Integrated Access Devices (IADs), as key equipment for realizing the convergence of voice communication and network, are widely used in enterprise communication, IP telephony, call centers, and other fields. In the current environment where information security is highly valued, various industries have an increasingly urgent need for the localization of communication equipment, requiring core components, operating systems, and software to be independently controllable to ensure communication security.

[0048] Existing voice gateway solutions have shortcomings in terms of functional integration, compatibility, and scalability. Regarding functional integration, some devices' voice processing and network adaptation modules are relatively independent, lacking efficient collaboration, resulting in low signal transmission efficiency and high processing latency. In terms of compatibility, when interfacing with communication terminals and network devices from different brands, issues such as protocol incompatibility and abnormal data interaction can easily arise. Regarding scalability, when a company's business expands and needs to add new functions or connect more devices, existing solutions struggle to quickly achieve functional expansion, often requiring large-scale equipment modifications or even replacements, increasing the company's operating costs and technical risks.

[0049] Some voice gateways suffer from numerous issues with voice playback quality. Voice quality is unstable, and in complex network environments or high-concurrency call scenarios, issues such as voice loss, distortion, and dropouts are common. Voice storage management is weak, lacking efficient storage strategies and retrieval mechanisms. When the volume of voice data is large, searching for and retrieving specific voice files is time-consuming and labor-intensive, failing to meet actual business needs.

[0050] For the specific implementation environment of the clock-buffer bidirectional linkage adjustment method for voice gateways proposed in this application, please refer to [link / reference needed]. Figure 1 . Figure 1 The implementation environment architecture diagram of the clock-buffer bidirectional linkage adjustment method for a voice gateway provided in the embodiments of this application is shown.

[0051] like Figure 1 As shown, the implementation environment architecture includes: voice transmitter device 101, transmission gateway 102, satellite network 103, receiving gateway 104, and voice receiver device 105.

[0052] Voice transmitter device 101 receives voice signals from the user and converts them into analog voice signals. Transmitting gateway 102 encodes and compresses the analog voice signals and transmits the encoded and compressed voice packets to receiving gateway 104 via satellite network 103. Receiving gateway 104 stores and plays the received voice packets, and reduces voice perception anomalies for the listener when playing the received voice packets.

[0053] In the embodiments of this application, such as Figure 2 As shown, the receiving gateway 104 includes a chip module, an FPGA module, an external interface module, a serial port module, a storage module, an analog signal processing module, and a network interface module.

[0054] The chip module uses a domestically produced multi-core processor chip (such as the GigaDevice GD32F470 series or HiSilicon Hi3516DV300), integrating an ARM Cortex-M7 core with a main frequency of ≥400MHz, and built-in 2MB Flash and 512KB SRAM. The chip is soldered to the center of the motherboard via a 40-pin LGA package, and is surrounded by eight 10μF tantalum capacitors for power filtering to ensure stable power supply. The interface uses two sets of PCIe 2.0 interfaces (500MB / s bandwidth per channel) to connect the FPGA and network control module respectively; a 4-channel SPI interface (up to 50MHz) is used to control the ADC conversion of the domestically produced analog module; an integrated SDIO 3.0 controller supports high-speed read and write of TF cards (up to 50MB / s), and this interface is also equipped with a dedicated voice data transmission channel, which can operate independently of other data transmissions to avoid mutual interference.

[0055] The FPGA module uses the domestically produced Ziguang Tongchuang PGT280H FPGA chip, manufactured using a 28nm process, with ≥280K logic units and 16 built-in hard-core DSP modules. The chip is BGA packaged and soldered to the upper left corner of the motherboard, ≤2cm from the main control chip, and connected via a 200-pin high-speed differential trace (impedance controlled at 50Ω) to reduce signal delay. A 125MHz differential crystal oscillator (accuracy ±50ppm) provides the reference clock for timing control, and the crystal is shielded from electromagnetic interference by a metal shield.

[0056] The analog signal processing module adopts a three-stage signal processing architecture, including a front-end amplification stage, a filtering stage, and an ADC conversion stage. The front-end amplification stage uses a domestically produced SGM8552 operational amplifier from Sanbang Microelectronics, with a gain of 20dB, an input impedance ≥1MΩ, and is matched to a telephone line (600Ω characteristic impedance). The filtering stage uses a 4th-order Butterworth low-pass filter (cutoff frequency 3.4kHz) and domestically produced Fenghua Advanced Technology 0603 packaged inductors and capacitors, with ripple suppression ≥40dB. The ADC conversion stage is equipped with a domestically produced Chipsea Technologies CS5368 16-bit ADC, with a sampling rate of 8kHz, a signal-to-noise ratio (SNR) ≥90dB, and transmits digital signals to the FPGA via an SPI interface (2MHz clock).

[0057] The voice conversion process involves an analog telephone signal (-10dBm to +2.0dBm) input via an RJ11 interface. It is first clamped by an ESD protection diode (SMBJ6.0CA), then DC-blocked by an RC coupling circuit (R=470Ω, C=10μF). The amplified and filtered signal is then fed into an ADC, where sampling and quantization are completed under the FPGA's voice timing control. The output is a PCM code (A-law format) transmitted to the FPGA via an 8-bit parallel bus (data rate 128kbps). In voice mode, the ADC's sampling frequency and quantization accuracy can be dynamically adjusted according to the main control chip's instructions to meet different voice quality requirements.

[0058] The storage module uses a recessed TF card slot, soldered to the lower right corner of the motherboard. It is connected to the SDIO interface of the main control chip via 5 wires (CLK, CMD, D0~D2), with a trace length ≤3cm. A 10Ω matching resistor is connected in series to eliminate signal reflection. A 100nF ceramic capacitor (0603 package) is placed next to the card slot for power supply decoupling, with an operating voltage of 3.3V±5%.

[0059] The network interface module uses the domestically produced YT8521 Gigabit Ethernet controller from Yutai Microelectronics, supporting 10 / 100 / 1000Mbps auto-sensing, integrating MAC and PHY layers, and connecting to the main control chip via the RMII interface (clock 25MHz). The network interface uses an RJ45 connector (with transformer H1102NL), with built-in LED indicators (LINK / ACT). The isolation voltage between the primary and secondary windings of the transformer is ≥1500Vrms, meeting telecommunications-grade protection requirements.

[0060] The clock-buffer bidirectional linkage adjustment method for voice gateways proposed in this application can be implemented by the receiving gateway.

[0061] To further illustrate the technical solutions provided in the embodiments of this application, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation instruction steps as shown in the following embodiments or drawings, the method may include more or fewer operation instruction steps based on conventional or non-creative effort. In steps where there is no logically necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. In actual processing or when the device executes the method, it may be executed sequentially or in parallel according to the method shown in the embodiments or drawings.

[0062] It should be noted that the acquisition or use of data in the embodiments of this application requires the user's consent. The relevant data can only be obtained after the user's authorization, and the acquisition or use of the data complies with the provisions of relevant laws and regulations.

[0063] Please refer to Figure 3 , Figure 3 A schematic flowchart of a clock-buffer bidirectional linkage adjustment method for a voice gateway according to an embodiment of this application is shown. Figure 3 As shown, the method includes:

[0064] Step 301: Obtain the clock frequency error and compensate the initial depth of the jitter buffer according to the clock frequency error to obtain the target depth of the jitter buffer; the initial depth of the jitter buffer is the dynamic initial depth determined based on the prediction model at the current time.

[0065] Step 302: Determine the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache.

[0066] Step 303: Determine the dynamic gain of the clock phase-locked loop based on the depth change rate, and update the clock signal according to the dynamic gain.

[0067] It's important to note that clock frequency error refers to the frequency deviation between the receiving gateway's clock frequency and the sending gateway's clock frequency. A faster receiving clock causes the playback rate to exceed the arrival rate, resulting in an underloaded jitter buffer. Conversely, a slower receiving clock causes the playback rate to be less than the arrival rate, leading to a jitter buffer overflow. For example, a 100ppm drift in an 8kHz clock frequency will result in a cumulative error of 0.8 frames per second, or 480 frames per second over 10 minutes. Therefore, clock frequency error significantly impacts the accuracy and reliability of voice playback from the receiving gateway.

[0068] On the other hand, during the buffer compensation process, drastic changes in buffer depth can cause traditional fixed-gain phase-locked loops (PLLs) to lose lock. Moreover, when the buffer depth changes frequently or drastically, the clock re-convergence speed is slow, which in turn affects the accuracy and reliability of the final receiving gateway's voice playback.

[0069] Based on this, the clock-buffer bidirectional linkage adjustment method for voice gateways proposed in this application, through the mutual coordination of clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation, enables accurate and reliable adjustment of the jitter buffer depth of the voice gateway, adapting to changes in dynamic latency and improving the accuracy of voice playback. Simultaneously, by dynamically adjusting the dynamic gain of the clock phase-locked loop based on the depth change rate, the reliability of clock operation is ensured. This allows the clock signal to converge quickly when jitter buffer depth is frequent or drastic, further ensuring the accuracy and reliability of voice playback.

[0070] It should be noted that, in the embodiments of this application, the initial depth of the jitter buffer is a dynamic initial depth determined based on a prediction model at the current moment. Specifically, the initial depth of the jitter buffer can be determined by predicting the time of satellite handover in the communication satellite constellation.

[0071] In one specific embodiment, the handover warning time and the current time of satellite handover are predicted based on the satellite ephemeris, and the handover growth factor is determined based on the handover warning time and the current time. The initial depth of the jitter buffer is determined based on the handover growth factor and the original depth of the jitter buffer.

[0072] It should be understood that, compared to IP network jitter, inter-satellite handover jitter time is relatively long, for example, greater than 500ms. Therefore, this application uses a prediction model to predict the handover time based on the satellite ephemeris and the location of the receiving gateway, obtaining the handover warning time, i.e., the handover start time. Then, based on the handover warning time and the current time, a handover growth factor is determined, i.e., the factor influencing the increase in jitter buffer depth during this satellite handover. Finally, based on the handover growth factor and the original jitter buffer depth, the initial jitter buffer depth is determined.

[0073] For example, the initial depth of the jitter buffer can be determined using the following formula:

[0074]

[0075] in, The initial depth of the jitter buffer. The original depth of the jitter cache. This refers to the satellite coefficient, which represents the scene sensitivity corresponding to that satellite constellation. As a growth factor, To switch the warning time, This is the current time, i.e., the current system time of the receiving gateway.

[0076] It should also be noted that, in the embodiments of this application, the compensation requirements caused by clock frequency changes include two aspects. On the one hand, there is the compensation requirement caused by the natural frequency drift of the clock under normal conditions, that is, the compensation requirement caused by the frequency error generated by multiple clock alignments. On the other hand, when the voice gateway uses satellite communication, there is the compensation requirement caused by the Doppler frequency shift generated by satellite switching.

[0077] In one feasible embodiment, the clock frequency error is obtained, and the initial depth of the jitter buffer is compensated based on the clock frequency error, including: obtaining the clock frequency error and the nominal sampling rate, determining the frequency compensation coefficient, compensating the initial depth of the jitter buffer based on the time compensation coefficient, and obtaining the target depth of the jitter buffer.

[0078] For example, the compensation based on the natural frequency drift of the clock under normal conditions can be calculated using the following formula:

[0079]

[0080] in, The jitter buffer target depth requirement value is obtained based on clock frequency compensation. The initial depth of the jitter buffer. For frequency sensitivity coefficient, This refers to the clock frequency error, specifically the frequency error between the local time of the receiving gateway and the transmission time of the sending gateway. The nominal sampling frequency, This is the frequency compensation coefficient.

[0081] Therefore, this application can add a depth deviation caused by time and frequency errors to the jitter buffer based on the initial depth of the jitter buffer by using a frequency compensation coefficient, thereby improving the reliability of the dynamic setting of the jitter buffer depth.

[0082] In another embodiment, the Doppler frequency shift and Doppler dynamic compensation factor generated by satellite handover are predicted. Based on the Doppler frequency shift and Doppler dynamic compensation factor, Doppler dynamic compensation is obtained. Based on the Doppler dynamic compensation coefficient, the initial depth of the jitter buffer is compensated to obtain the target depth of the jitter buffer.

[0083] For example, the compensation caused by the Doppler frequency shift resulting from satellite handover can be calculated using the following formula:

[0084]

[0085] in, The jitter buffer target depth requirement value is obtained by compensating for jitter generated during satellite handover. The initial depth of the jitter buffer. This is the Doppler frequency shift, i.e., the frequency deviation caused by relative motion. The Doppler dynamic compensation factor. This is the Doppler dynamic compensation coefficient.

[0086] It should be understood that the two jitter buffer initial depth compensation methods can be performed independently or in combination. For example, when there is no satellite handover requirement, only the compensation algorithm based on the natural frequency drift of the clock under normal conditions can be used. When there is a satellite handover requirement, the two compensation algorithms can be used in combination. Optionally, when the two compensation algorithms are used in combination, the frequency compensation coefficient and the Doppler compensation coefficient can be used simultaneously to compensate for the jitter buffer initial depth to obtain the jitter buffer target depth.

[0087] For example, it can be represented as:

[0088]

[0089] in, The target depth requirement value for jitter caching.

[0090] Therefore, this application provides a solution for depth compensation for receiving gateways under different operating conditions, realizing dynamic depth adjustment of jitter buffer, and providing a reliable time interval basis for subsequent voice playback.

[0091] In some embodiments, in order to make the dynamic adjustment of the jitter buffer depth more reliable, for example, to meet the hardware resource or capability constraints of the receiving gateway, this application further proposes: obtaining the compensated jitter buffer target depth requirement value and the resource data corresponding to the voice gateway terminal, determining the jitter buffer target depth constraint value based on the resource data, and determining the jitter buffer target depth for calculating the depth change rate based on the jitter buffer target depth requirement value and the jitter buffer target depth constraint value.

[0092] The resource data includes at least available memory, utilization factor, coding rate, and frame duration.

[0093] Specifically, the jitter buffer target depth constraint value is the maximum jitter buffer depth that the receiving gateway can currently provide. Therefore, this application takes the smaller of the jitter buffer target depth requirement value and the jitter buffer target depth constraint value to ensure that the receiving gateway's buffer can provide the jitter buffer target depth. That is, if the jitter buffer target depth requirement value is less than the jitter buffer target depth constraint value, it means that the receiving gateway can provide sufficient jitter buffer target depth, and the jitter buffer target depth requirement value can be used as the jitter buffer target depth to adjust the jitter buffer depth. If the jitter buffer target depth constraint value is less than the jitter buffer target depth requirement value, it means that the receiving gateway cannot provide sufficient jitter buffer target depth. In order to avoid operational failure of the receiving gateway, the jitter buffer target depth constraint value is used as the jitter buffer target depth to adjust the jitter buffer depth, so as to provide the largest possible depth while ensuring the stable operation of the receiving gateway and meeting more buffering needs.

[0094] For example, the target depth of the jitter buffer can be determined using the following formula:

[0095]

[0096] in, To determine the target depth of the jitter cache, To determine the target depth requirement value for jitter caching, For memory utilization factor, Available memory, The encoding bitrate for voice data. The duration is the frame length.

[0097] In another feasible embodiment of this application, determining the dynamic gain of the clock phase-locked loop based on the depth change rate includes: determining the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop based on the depth change rate, respectively.

[0098] For example, the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop can be determined using the following formulas:

[0099]

[0100]

[0101] in, For dynamic proportional gain, For dynamic integral gain, For depth change rate, The sensitivity coefficient is the value corresponding to the phase-locked loop. Based on the proportional gain, Based on the integral gain.

[0102] It should be understood that the receiving gateway provided in this application embodiment uses a digital phase-locked loop (DPLL) to provide a stable clock signal. After determining the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop in this application, the digital phase-locked loop can update the clock signal in real time according to the dynamic proportional gain and dynamic integral gain.

[0103] In summary, the clock-buffer bidirectional linkage adjustment method for voice gateways proposed in this application, through the coordination of clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation, enables accurate and reliable adjustment of the jitter buffer depth of the voice gateway, adapting to changes in dynamic latency and improving the accuracy of voice playback. Simultaneously, by dynamically adjusting the dynamic gain of the clock phase-locked loop based on the depth change rate, the reliability of clock operation is ensured. This allows the clock signal to converge quickly when jitter buffer depth is frequent or drastic, further ensuring the accuracy and reliability of voice playback.

[0104] It should be noted that although the operation of the method of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed in order to achieve the desired result.

[0105] Figure 4 A schematic diagram of a clock-buffer bidirectional linkage adjustment device for a voice gateway provided in an embodiment of this application is shown.

[0106] like Figure 4 As shown, the clock-buffer bidirectional linkage adjustment device 10 for a voice gateway includes:

[0107] The depth compensation module 11 is used to obtain the clock frequency error and compensate the initial depth of the jitter buffer according to the clock frequency error to obtain the target depth of the jitter buffer; the initial depth of the jitter buffer is the dynamic initial depth at the current time determined based on the prediction model.

[0108] The determination module 12 is used to determine the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache;

[0109] The clock update module 13 is used to determine the dynamic gain of the clock phase-locked loop based on the depth change rate, and update the clock signal according to the dynamic gain.

[0110] In some embodiments, the depth compensation module 11 is specifically used for:

[0111] Obtain the clock frequency error and nominal sampling rate, and determine the frequency compensation coefficient;

[0112] The initial depth of the jitter buffer is compensated based on the frequency compensation coefficient to obtain the target depth of the jitter buffer.

[0113] In some embodiments, the depth compensation module 11 is specifically used for:

[0114] Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching;

[0115] The Doppler dynamic compensation coefficient is obtained based on the Doppler frequency shift and the Doppler dynamic compensation factor.

[0116] The initial depth of the jitter buffer is compensated based on the Doppler dynamic compensation coefficient to obtain the target depth of the jitter buffer.

[0117] In some embodiments, the depth compensation module 11 is specifically used for:

[0118] The handover warning time and the current time are predicted based on the satellite ephemeris, and the handover growth factor is determined based on the handover warning time and the current time.

[0119] The initial depth of the jitter cache is determined based on the switching growth factor and the original depth of the jitter cache.

[0120] In some embodiments, the determining module 12 is specifically used for:

[0121] Obtain the compensated jitter buffer target depth requirement value and the resource data corresponding to the voice gateway terminal. The resource data includes at least available memory, utilization factor, encoding bitrate and frame duration.

[0122] Based on the resource data, the target depth constraint value of the jitter cache is determined;

[0123] The jitter cache target depth is determined based on the jitter cache target depth requirement value and the jitter cache target depth constraint value, and is used to calculate the depth change rate.

[0124] In some embodiments, the clock update module 13 is specifically used for:

[0125] The dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop are determined based on the depth change rate, respectively.

[0126] It should be understood that the modules or modules described in the clock-buffer bidirectional linkage adjustment device 10 for the voice gateway are similar to those in the reference. Figure 3The steps in the described method correspond accordingly. Therefore, the operations and features described above for the method are also applicable to the clock-buffer bidirectional linkage adjustment device 10 for a voice gateway and the modules contained therein, and will not be repeated here. The clock-buffer bidirectional linkage adjustment device 10 for a voice gateway can be pre-implemented in the browser or other security applications of an electronic device, or it can be loaded into the browser or other security applications of an electronic device through download or other means. The corresponding modules in the clock-buffer bidirectional linkage adjustment device 10 for a voice gateway can cooperate with the modules in the electronic device to implement the solutions of the embodiments of this application.

[0127] The division of modules or units mentioned in the detailed description above is not mandatory. In fact, according to the embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0128] The following is for reference. Figure 5 , Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the embodiments of this application is shown.

[0129] like Figure 5 As shown, the computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 502 or programs loaded from storage section 508 into random access memory (RAM) 503. RAM 503 also stores various programs and data required for the system's operating instructions. CPU 501, ROM 502, and RAM 503 are interconnected via bus 504. Input / output (I / O) interface 505 is also connected to bus 504.

[0130] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 510 as needed so that computer programs read from it can be installed into storage section 508 as needed.

[0131] Specifically, according to embodiments of this application, the flowchart above refers to... Figure 2 The described process can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program contains program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by central processing unit (CPU) 501, it performs the functions defined in the system of this application.

[0132] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0133] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operational instructions of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two connected blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified functions or operational instructions, or using a combination of dedicated hardware and computer instructions.

[0134] The units or modules described in the embodiments of this application can be implemented in software or hardware. The described units or modules can also be located in a processor; for example, a processor can be described as including a depth compensation module, a determination module, and a clock update module. The names of these units or modules do not necessarily limit the specific unit or module itself. For example, a depth compensation module can also be described as "acquiring a clock frequency error and compensating for the initial depth of the jitter buffer based on the clock frequency error to obtain a target depth of the jitter buffer; the initial depth of the jitter buffer is a dynamic initial depth determined based on a prediction model at the current moment."

[0135] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not assembled into the electronic device. The aforementioned computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the clock-buffer bidirectional linkage adjustment method for a voice gateway described in this application.

[0136] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A clock-buffer bidirectional linkage adjustment method for a voice gateway, characterized in that, include: Obtain the clock frequency error, and compensate the initial depth of the jitter buffer based on the clock frequency error to obtain the target depth of the jitter buffer; The initial depth of the jitter buffer is a dynamic initial depth determined based on the prediction model at the current moment; Based on the original depth of the jitter cache and the target depth of the jitter cache, determine the depth change rate corresponding to the jitter cache; The dynamic gain of the clock phase-locked loop is determined based on the depth change rate, and the clock signal is updated according to the dynamic gain. Before obtaining the dynamic initial depth, the method further includes: The handover warning time and the current time are predicted based on the satellite ephemeris, and the handover growth factor is determined based on the handover warning time and the current time. The initial depth of the jitter cache is determined based on the switching growth factor and the original depth of the jitter cache.

2. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that, The step of obtaining the clock frequency error and compensating for the initial depth of the jitter buffer based on the clock frequency error includes: Obtain the clock frequency error and nominal sampling rate, and determine the frequency compensation coefficient; The initial depth of the jitter buffer is compensated based on the frequency compensation coefficient to obtain the target depth of the jitter buffer.

3. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that, When the voice gateway uses satellite communication, the method further includes: Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching; The Doppler dynamic compensation coefficient is obtained based on the Doppler frequency shift and the Doppler dynamic compensation factor. The initial depth of the jitter buffer is compensated based on the Doppler dynamic compensation coefficient to obtain the target depth of the jitter buffer.

4. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that, Before determining the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache, the method further includes: Obtain the compensated jitter cache target depth requirement value and the resource data corresponding to the voice gateway. The resource data includes at least available memory, utilization factor, encoding bitrate and frame duration. Based on the resource data, the target depth constraint value of the jitter cache is determined; The jitter cache target depth is determined based on the jitter cache target depth requirement value and the jitter cache target depth constraint value, and is used to calculate the depth change rate.

5. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that, The determination of the dynamic gain of the clock phase-locked loop based on the depth change rate includes: The dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop are determined based on the depth change rate, respectively.

6. A clock-buffer bidirectional linkage adjustment device for a voice gateway, characterized in that, include: The depth compensation module is used to obtain the clock frequency error and compensate the initial depth of the jitter buffer according to the clock frequency error to obtain the target depth of the jitter buffer. The initial depth of the jitter buffer is a dynamic initial depth determined based on the prediction model at the current moment; The determination module is used to determine the depth change rate corresponding to the jitter cache based on the original depth of the jitter cache and the target depth of the jitter cache; The clock update module is used to determine the dynamic gain of the clock phase-locked loop based on the depth change rate, and update the clock signal according to the dynamic gain; Before obtaining the dynamic initial depth, the method further includes: The handover warning time and the current time are predicted based on the satellite ephemeris, and the handover growth factor is determined based on the handover warning time and the current time. The initial depth of the jitter cache is determined based on the switching growth factor and the original depth of the jitter cache.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the clock-buffer bidirectional linkage adjustment method for a voice gateway as described in any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the clock-buffer bidirectional linkage adjustment method for a voice gateway as described in any one of claims 1-5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the clock-buffer bidirectional linkage adjustment method for a voice gateway as described in any one of claims 1-5.

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