Method and device for converting UDP protocol to multi-channel UART protocol based on FPGA

Abstract

The invention provides a method and a device for converting a UDP (User Datagram Protocol) to a multi-channel UART (Universal Asynchronous Receiver / Transmitter) protocol based on an FPGA (Field Programmable Gate Array), and the method comprises the following steps: receiving and analyzing a UDP datagram to obtain pseudo header information and header information; performing data verification on the UDP datagram according to the pseudo header information and the header information, and caching the UDP datagram according to a verification result to obtain UDP cached data; performing application layer protocol analysis on the UDP cache data to obtain application layer data; caching the application layer data to obtain application layer cache data; performing UART frame formatting on the application layer cache data according to a preset UART frame packaging format to obtain a UART data frame; and searching a channel mapping table according to the head information, determining a UART channel ID set, and sending the UART data frame through a UART interface based on a dynamic priority arbitration mechanism according to the UART channel ID set and preset configuration parameters. According to the method and the device provided by the invention, multi-channel expansion can be carried out, so that the real-time performance and the reliability of data in a transmission process are ensured.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for converting a UDP protocol to a multi-channel UART protocol based on FPGA, as well as electronic equipment and a computer-readable storage medium. Background Art

[0002] As a mature and reliable serial communication interface, the Universal Asynchronous Receiver / Transmitter (UART) is widely used in embedded systems, industrial control, and other fields. As application complexity increases, a single UART channel often cannot meet the concurrent communication needs of multiple devices or diverse data streams.

[0003] In the existing technology, multi-channel UART communication mainly relies on two methods: one is to use a hardware multiplexer to time-share multiplex a single UART physical channel. However, when the number of channels increases or the data rate is high, this method is prone to significant communication delays and reduced efficiency due to frequent switching; the other is to directly integrate multiple independent UART controllers. Although this can provide true parallel communication, it significantly increases hardware cost, power consumption and PCB area, and its application is limited in resource-constrained embedded scenarios.

[0004] Another key issue is the lack of an effective priority arbitration mechanism when multiple channels simultaneously require data transmission. Existing solutions often employ simple round-robin or fixed-priority strategies. Polling mechanisms cannot guarantee the real-time delivery of high-priority data, potentially causing delays in the delivery of critical information. Fixed-priority strategies lack flexibility, and low-priority channels may be unable to receive service for extended periods under sustained high loads, leading to a "starvation" phenomenon. Existing mechanisms struggle to dynamically and adaptively adjust priorities based on data characteristics and system status.

[0005] Therefore, the existing technology lacks a UDP protocol to multi-channel UART protocol conversion method and device based on FPGA (field programmable gate array), which can perform multi-channel expansion and control multi-channel output data based on a dynamic priority arbitration mechanism to ensure the real-time and reliability of data during transmission. Summary of the Invention

[0006] The purpose of the present invention is to provide a method and device for converting UDP protocol to multi-channel UART protocol based on FPGA, as well as an electronic device and a computer-readable storage medium, so as to solve the above-mentioned problems existing in the related art.

[0007] According to a first aspect of the present invention, a method for converting a UDP protocol to a multi-channel UART protocol based on an FPGA is provided, the method comprising: Receive and parse UDP datagrams to obtain pseudo-header information and header information; Perform data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result, and cache the UDP datagram according to the verification result to obtain UDP cache data; Perform application layer protocol analysis on UDP cache data to obtain corresponding application layer data; Cache the application layer data to obtain application layer cache data; According to the preset UART frame encapsulation format, the application layer buffer data is formatted as a UART frame to obtain a UART data frame; According to the header information, the channel mapping table is searched to determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters, the UART data frame is sent through the corresponding UART interface.

[0008] Optionally, the pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, UDP total length, data information and checksum.

[0009] Optionally, performing data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result, and caching the UDP datagram according to the verification result to obtain UDP cache data, including: Perform data transmission verification on UDP datagrams based on pseudo-header information and header information; If the data transmission verification result is that it fails the verification, the UDP datagram is discarded; If the data transmission check result is passed, a cyclic redundancy check is performed on the UDP datagram based on the pseudo header information and the header information; If the cyclic redundancy check result is a failure, the UDP datagram is discarded; If the check result of the cyclic redundancy check is passed, the UDP datagram is cached in the first first-in-first-out queue to obtain UDP cache data.

[0010] Optionally, after caching the UDP datagram into the first first-in-first-out queue and obtaining the UDP cache data, the method further includes: Check whether the first FIFO queue is full; If the first FIFO queue is full, new UDP buffered data is discarded.

[0011] Optionally, according to a preset UART frame encapsulation format, the application layer buffer data is formatted as a UART frame to obtain a UART data frame, including: Extracting a command word field and a length field from the application layer buffer data; Add a 1-byte channel identification prefix before the command word field; Generate a CRC16 checksum based on the encapsulated data, where the encapsulated data includes the source port number, the destination port number, the total UDP length, the data information, and the checksum; The channel identification prefix, command word field, length field, data information and CRC16 check code are encapsulated into a serial frame format to obtain a UART data frame, wherein the UART data frame includes a start bit, a channel identification prefix, a command word field, a length field, data information, a CRC16 check code and a stop bit in sequence.

[0012] Optionally, according to the header information, searching the channel mapping table, determining the UART channel ID set, and based on the dynamic priority arbitration mechanism, sending the UART data frame through the corresponding UART interface according to the UART channel ID set and preset configuration parameters, including: According to the destination port number in the header information, search the channel mapping table to determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include the basic priority, the basic wait count, and the basic baud rate; Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority of each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Select the minimum value of the valid priority corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current wait count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

[0013] According to a second aspect of the present invention, a UDP protocol to multi-channel UART protocol conversion device based on FPGA is provided, the device comprising: a UDP protocol parsing module, a UDP verification module, a first buffer module, an application layer protocol parsing module, a second buffer module, a UART encapsulation module and a channel management module; wherein, UDP protocol parsing module, used to receive and parse UDP datagrams to obtain pseudo header information and header information; The UDP verification module is connected to the UDP protocol parsing module and is used to perform data verification on the UDP datagram based on the pseudo header information and the header information to obtain the verification result; The first buffer module and the UDP verification module are used to buffer the UDP datagram according to the verification result to obtain UDP buffer data; The application layer protocol parsing module is connected to the first cache module and is used to perform application layer protocol parsing on the UDP cache data to obtain corresponding application layer data; The second cache module is connected to the application layer protocol parsing module and is used to cache the application layer data to obtain application layer cache data; The UART encapsulation module is connected to the second buffer module and is used to perform UART frame formatting on the application layer buffer data according to a preset UART frame encapsulation format to obtain a UART data frame; The channel management module is connected to the UDP protocol parsing module and the UART encapsulation module respectively. It is used to search the channel mapping table according to the header information, determine the UART channel ID set, and send the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters.

[0014] Optionally, the channel management module is further configured to: According to the destination port number in the header information, search the channel mapping table to determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include the basic priority, the basic wait count, and the basic baud rate; Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority of each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Select the minimum value of the valid priority corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current wait count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

[0015] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory storing a computer program; and a processor configured to execute the computer program in the memory to implement the steps of any one of the above methods.

[0016] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, which implements the steps of any of the above methods when executed by a processor.

[0017] The FPGA-based UDP protocol to multi-channel UART protocol conversion method and device provided by the present invention receive and parse UDP datagrams to obtain pseudo-header information and header information; perform data verification on the UDP datagram based on the pseudo-header information and header information, and cache the UDP datagram based on the verification result to obtain UDP cache data; perform application layer protocol parsing on the UDP cache data to obtain application layer data; cache the application layer data to obtain application layer cache data; perform UART frame formatting on the application layer cache data according to a preset UART frame encapsulation format to obtain a UART data frame; search a channel mapping table based on the header information to determine a UART channel ID set, and based on a dynamic priority arbitration mechanism, transmit the UART data frame through a UART interface according to the UART channel ID set and preset configuration parameters. The FPGA-based UDP protocol to multi-channel UART protocol conversion method and device provided by the present invention can perform multi-channel expansion to ensure the real-time and reliability of data transmission.

[0018] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 A flow chart of the FPGA-based UDP protocol to multi-channel UART protocol conversion method provided by the present invention; Figure 2 A structural block diagram of the FPGA-based UDP protocol to multi-channel UART protocol conversion device provided by the present invention; Figure 3 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0021] It should be noted that, in the present invention, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order; terms such as "S11", "S12", "S13", "S14", etc. are used to distinguish steps, and do not necessarily mean that the method steps are performed in a specific order or sequential order; multiple includes two or more; when the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0022] Exemplary Methods Figure 1 A flow chart of the FPGA-based UDP protocol to multi-channel UART protocol conversion method provided by the present invention. Figure 1 As shown, the method includes: Step S11: Receive and parse the UDP datagram to obtain pseudo header information and header information; The pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, UDP total length, data information and checksum.

[0023] Optionally, before step S11 of the present invention, the method further includes: receiving target data, and stripping the frame header of the target data to obtain network layer data; Perform network layer protocol analysis on the network layer data, strip off the IP header in the network layer data, and obtain the UDP datagram.

[0024] Step S12: performing data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result, and caching the UDP datagram according to the verification result to obtain UDP cache data; Wherein, step S12 may specifically include: Step S121: Perform data transmission verification on the UDP datagram based on the pseudo-header information and the header information; wherein, the checksum method in the prior art can be used to perform data transmission verification, and those skilled in the art can make a choice based on actual needs, which is not limited here.

[0025] Step S122: If the data transmission verification result is failure, the UDP datagram is discarded; Step S123: If the data transmission verification result is passed, a cyclic redundancy check is performed on the UDP datagram based on the pseudo header information and the header information; wherein the cyclic redundancy check adopts the method in the prior art, and those skilled in the art can select it according to actual needs, which is not limited here.

[0026] Step S124: If the cyclic redundancy check result is failure, discard the UDP datagram; Step S125: If the cyclic redundancy check result is passed, the UDP datagram is cached in the first first-in-first-out queue to obtain UDP cache data.

[0027] Optionally, after caching the UDP datagram into the first first-in-first-out queue in step S125 to obtain the UDP cache data, the method further includes: Check whether the first FIFO queue is full; If the first FIFO queue is full, new UDP buffered data is discarded.

[0028] Step S13: performing application layer protocol analysis on the UDP buffer data to obtain corresponding application layer data; Step S14: caching the application layer data to obtain application layer cache data; Step S15: Formatting the application layer buffer data into a UART frame according to a preset UART frame encapsulation format to obtain a UART data frame; Optionally, step S15 specifically includes: Extracting a command word field and a length field from the application layer buffer data; Add a 1-byte channel identification prefix before the command word field; Generate a CRC16 checksum based on the encapsulated data, where the encapsulated data includes the source port number, the destination port number, the total UDP length, the data information, and the checksum; The channel identification prefix, command word field, length field, data information and CRC16 check code are encapsulated into a serial frame format to obtain a UART data frame, wherein the UART data frame includes a start bit, a channel identification prefix, a command word field, a length field, data information, a CRC16 check code and a stop bit in sequence.

[0029] Step S16: According to the header information, the channel mapping table is searched to determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, according to the UART channel ID set and preset configuration parameters, the UART data frame is sent through the corresponding UART interface.

[0030] In an optional embodiment of the present invention, step S16 specifically includes: Step S161: searching a channel mapping table based on the destination port number in the header information to determine a UART channel ID set, and obtaining a channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include a basic priority, a basic wait count, and a basic baud rate; Regarding the number of UART channels, those skilled in the art can flexibly set it according to actual needs, and it is not limited here. In the present invention, the number of UART channels is preferably greater than or equal to 20.

[0031] In the present invention, the channel ID and preset configuration parameters corresponding to the UART channel are pre-set, and those skilled in the art can flexibly set them according to actual needs, which is not limited here.

[0032] Step S162: detecting the current request parameters of each UART channel in the UART channel ID set, wherein the current request parameters include a current wait count, a current channel baud rate, and a current pointer; Step S163: Calculate the effective priority corresponding to each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Step S164: selecting the minimum value of the valid priorities corresponding to the UART channels in the UART channel ID set, and determining the target UART channel based on the current pointer; Step S165: After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current waiting count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

[0033] In order to enable those skilled in the art to clearly understand this optional implementation, the present invention is described in detail by taking 4 UART channels, a basic wait count=100 clock cycles, and a basic baud rate=115200 as an example.

[0034] UART channel 0: Basic priority = 1, current channel baud rate = 115200, therefore, baud rate boost value = current channel baud rate / basic baud rate = 115200 / 115200 = 1; UART channel 1: Basic priority = 2, current channel baud rate = 230400, therefore, baud rate boost value = current channel baud rate / basic baud rate = 230400 / 115200 = 2; UART channel 2: Basic priority = 0, current channel baud rate = 57600, baud rate boost value = current channel baud rate / basic baud rate = 57600 / 115200 = 0 (rounded to the integer); UART channel 3: Basic priority = 3, current channel baud rate = 115200, baud rate boost value = current channel baud rate / basic baud rate = 115200 / 115200 = 1.

[0035] Initialization: current wait count = 0, current pointer = 0.

[0036] First round: Calculate effective priority: UART channel 0: effective priority = 1-0-1 = 0; UART channel 1: effective priority = 2-0-2 = 0; UART channel 2: effective priority = 0-0-0 = 0; UART channel 3: effective priority = 3-0-1 = 2; The lowest valid priority among the four UART channels is 0. Starting from the current pointer 0, UART channel 0 is found first, so it is selected and the current pointer moves to 1. Assume that sending data through UART channel 0 takes 80 clock cycles. During this time, the current wait counts of the other channels increase by 80.

[0037] Second round: UART channel 0 finishes sending data and re-priority arbitration.

[0038] UART channel 0: Since UART channel 0 is selected in the first round, its current wait count = 0, so the effective priority of UART channel 0 = 1-0-1 = 0; UART channel 1: Current wait count = 80, wait boost value = current wait count / basic wait count = 80 / / 100 = 0 (rounded up), so the effective priority of UART channel 1 = 2-0-2 = 0; UART channel 2: Current wait count = 80, wait boost value = current wait count / basic wait count = 80 / / 100 = 0 (rounded), so the effective priority of UART channel 2 = 0-0-0 = 0; UART channel 3: Current wait count = 80, wait boost value = current wait count / basic wait count = 80 / / 100 = 0 (rounded up), so the effective priority of UART channel 3 = 3-0-1 = 2; The lowest effective priority among the four UART channels is 0. There are UART channels 0, 1, and 2, and the current pointer is 1. Starting from 1, the first channel with an effective priority of 0 is UART channel 1. Therefore, UART channel 1 is selected, and the current pointer moves to 2. Assume that sending data through UART channel 1 takes 40 clock cycles, and the current wait counts of the other UART channels increase by 40.

[0039] Round 3: UART channel 1 finishes sending data and re-priority arbitration begins.

[0040] UART channel 0: Current wait count = 0 + 40 = 40, wait boost value = current wait count / basic wait count = 40 / 100 = 0 (rounded to the integer), so the effective priority of UART channel 0 = 1-0-1 = 0; UART channel 1: Since UART channel 1 is selected in the second round, its current wait count = 0, so the effective priority of UART channel 1 = 2-0-2 = 0; UART channel 2: Current wait count = 80 + 40 = 120, wait boost value = current wait count / basic wait count = 120 / 100 = 1 (rounded to the integer), so the effective priority of UART channel 2 = 0 - 1 - 0 = -1; UART channel 3: Current wait count = 80 + 40 = 120, wait boost value = current wait count / basic wait count = 120 / 100 = 1 (rounded to the integer), so the effective priority of UART channel 3 = 3 - 1 - 1 = 1; The lowest effective priority among the four UART channels is -1 (i.e., channel 2). The current pointer is 2. Starting from 2, the first channel with an effective priority of -1 is UART channel 2. Therefore, UART channel 2 is selected, and the current pointer moves to 3. Assume that sending data through UART channel 2 takes 100 cycles. The current wait counts of the other UART channels increase by 100.

[0041] Round 4: UART channel 2 finishes sending data and re-priority arbitration.

[0042] UART channel 0: Current wait count = 40 + 100 = 140, wait boost value = current wait count / basic wait count = 140 / 100 = 1 (rounded to the integer), so the effective priority of UART channel 0 = 1-1-1 = -1; UART channel 1: Current wait count = 100, wait boost value = current wait count / basic wait count = 100 / 100 = 1, so the effective priority of UART channel 1 = 2-1-2 = -1; UART channel 2: Since UART channel 2 is selected in the third round, its current wait count = 0, so the effective priority of UART channel 2 = 0-0-0 = 0; UART channel 3: Current wait count = 80 + 40 + 100 = 220, wait boost value = current wait count / basic wait count = 220 / 100 = 2, so the effective priority of UART channel 3 = 3-2-1 = 0; The minimum effective priority among the 4 UART channels is -1 (UART channels 0 and 1). The current pointer is 3. Starting from 3, the first one with an effective priority of -1 is UART channel 0. Therefore, UART channel 0 is selected and the current pointer moves to 0.

[0043] To prevent a UART channel from waiting too long, even if its base priority is low, its priority is gradually increased by increasing the current wait count. High-baud-rate UART channels also receive a fixed increase in priority, giving them more service opportunities. This priority arbitration mechanism dynamically adjusts priorities and ensures fairness in data transmission across all UART channels, ensuring real-time and reliable data transmission.

[0044] The FPGA-based UDP protocol to multi-channel UART protocol conversion method of an embodiment of the present invention receives and parses a UDP datagram to obtain pseudo-header information and header information; performs data verification on the UDP datagram based on the pseudo-header information and header information, and caches the UDP datagram based on the verification result to obtain UDP cache data; performs application layer protocol parsing on the UDP cache data to obtain application layer data; caches the application layer data to obtain application layer cache data; performs UART frame formatting on the application layer cache data according to a preset UART frame encapsulation format to obtain a UART data frame; searches a channel mapping table based on the header information to determine a UART channel ID set, and based on a dynamic priority arbitration mechanism, transmits the UART data frame through a UART interface according to the UART channel ID set and preset configuration parameters. The FPGA-based UDP protocol to multi-channel UART protocol conversion method provided by the present invention can perform multi-channel expansion and adopts a dynamic priority arbitration mechanism to ensure the real-time and reliability of data during transmission.

[0045] Exemplary devices Figure 2 This is a structural block diagram of the UDP protocol to multi-channel UART protocol conversion device based on FPGA provided by the present invention. Figure 2As shown, the present invention also provides an FPGA-based UDP protocol to multi-channel UART protocol conversion device, which includes: a UDP protocol parsing module 21, a UDP verification module 22, a first buffer module 23, an application layer protocol parsing module 24, a second buffer module 25, a UART encapsulation module 26 and a channel management module 27; wherein, UDP protocol parsing module 21, used to receive and parse UDP datagrams to obtain pseudo header information and header information; The UDP verification module 22 is connected to the UDP protocol analysis module 21 and is used to perform data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result; The first buffer module 23 and the UDP check module 22 are used to buffer the UDP datagram according to the check result to obtain UDP buffer data; The application layer protocol parsing module 24 is connected to the first buffer module 23 and is used to perform application layer protocol parsing on the UDP buffer data to obtain corresponding application layer data; The second cache module 25 is connected to the application layer protocol analysis module 24 and is used to cache the application layer data to obtain application layer cache data; The UART encapsulation module 26 is connected to the second buffer module 25 and is used to perform UART frame formatting on the application layer buffer data according to a preset UART frame encapsulation format to obtain a UART data frame; The channel management module 27 is connected to the UDP protocol parsing module 21 and the UART encapsulation module 26 respectively, and is used to search the channel mapping table according to the header information, determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, send the UART data frame through the corresponding UART interface according to the UART channel ID set and preset configuration parameters.

[0046] Optionally, the UDP check module 22 is specifically used to: perform data transmission check on the UDP datagram based on the pseudo-header information and the header information; if the check result of the data transmission check is failure, discard the UDP datagram; if the check result of the data transmission check is passing, perform a cyclic redundancy check on the UDP datagram based on the pseudo-header information and the header information; if the check result of the cyclic redundancy check is failure, discard the UDP datagram; if the check result of the cyclic redundancy check is passing, cache the UDP datagram in the first first-in-first-out queue (i.e., the first cache module 23).

[0047] At this time, the first buffer module 23 is specifically used to: buffer the UDP datagram according to the verification result to obtain UDP buffer data; Optionally, the device of the present invention also includes: a cache status determination module (not shown in the figure), which is connected to the first first-in-first-out queue and is used to detect whether the first first-in-first-out queue is full; if the first first-in-first-out queue is full, new UDP cache data is discarded.

[0048] Optionally, the UART encapsulation module 26 is specifically configured to: Extracting a command word field and a length field from the application layer buffer data; Add a 1-byte channel identification prefix before the command word field; Generate a CRC16 checksum based on the encapsulated data, where the encapsulated data includes the source port number, the destination port number, the total UDP length, the data information, and the checksum; The channel identification prefix, command word field, length field, data information and CRC16 check code are encapsulated into a serial frame format to obtain a UART data frame, wherein the UART data frame includes a start bit, a channel identification prefix, a command word field, a length field, data information, a CRC16 check code and a stop bit in sequence.

[0049] Optionally, the channel management module 27 is further configured to: According to the destination port number in the header information, search the channel mapping table to determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include the basic priority, the basic wait count, and the basic baud rate; Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority of each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Select the minimum value of the valid priority corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current wait count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

[0050] It should be noted that Figure 2 The device and Figure 1 The corresponding methods described can be interpreted with reference to each other. Figure 2 The device can be implemented by a field programmable logic gate array.

[0051] In an embodiment of the present invention, an FPGA-based UDP protocol to multi-channel UART protocol conversion device comprises a UDP protocol parsing module that receives and parses a UDP datagram to obtain pseudo header information and header information; a UDP check module that performs data check on the UDP datagram based on the pseudo header information and header information to obtain a check result; a first buffer module that caches the UDP datagram based on the check result to obtain UDP buffer data; an application layer protocol parsing module that performs application layer protocol parsing on the UDP buffer data to obtain corresponding application layer data; a second buffer module that caches the application layer data to obtain application layer buffer data; a UART encapsulation module that performs UART frame formatting on the application layer buffer data according to a preset UART frame encapsulation format to obtain a UART data frame; a channel management module that searches a channel mapping table based on the header information to determine a UART channel ID set and, based on a dynamic priority arbitration mechanism, sends the UART data frame through a corresponding UART interface according to the UART channel ID set and preset configuration parameters. The FPGA-based UDP protocol to multi-channel UART protocol conversion device provided by the present invention is capable of multi-channel expansion and adopts a dynamic priority arbitration mechanism to ensure the real-time and reliability of data during transmission.

[0052] Exemplary electronic devices Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent of them. The stand-alone device may communicate with the first device and the second device to receive the collected input signals from them. Figure 3 As shown, the electronic device 30 includes one or more processors 31 and a memory 32 .

[0053] The processor 31 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0054] The memory 32 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 31 may execute the program instructions to implement the method for determining the actual controller and / or other desired functions of the software program of the various embodiments of the present disclosure described above. In one example, the electronic device may further include: an input device 33 and an output device 34, these components being interconnected via a bus system and / or other form of connection mechanism (not shown).

[0055] In addition, the storage input device 33 may also include, for example, a keyboard, a mouse, and the like.

[0056] The output device 34 can output various information to the outside. The output device 34 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto.

[0057] Of course, to simplify, Figure 3 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, the electronic device may further include any other appropriate components according to specific application scenarios.

[0058] Exemplary computer program products and storage media In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps in the method for determining the actual controller according to various embodiments of the present disclosure described in the above "Exemplary Method" section of this specification.

[0059] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0060] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enable the processor to execute the steps of the method for determining the actual controller according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0061] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0062] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be construed as necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0063] Each embodiment in this specification is described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. For system embodiments, since they largely correspond to method embodiments, their description is relatively simple. For relevant parts, references to the description of the method embodiments are sufficient.

[0064] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0065] The methods and apparatus of the present disclosure may be implemented in many ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specified. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers recording media that store programs for executing the methods according to the present disclosure.

[0066] It should also be noted that, in the apparatus, equipment and method of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent schemes of the present disclosure. The above description of the disclosed aspects is provided to enable any technician in this field to make or use the present disclosure. Various modifications to these aspects will be very obvious to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown here, but to the widest range consistent with the principles and novel features disclosed herein.

[0067] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A UDP protocol to multi-channel UART protocol conversion method based on FPGA, characterized in that: The method comprises: Receive and parse UDP datagrams to obtain pseudo-header information and header information; Perform data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result, and cache the UDP datagram according to the verification result to obtain UDP cache data; Perform application layer protocol analysis on UDP cache data to obtain corresponding application layer data; Cache the application layer data to obtain application layer cache data; According to the preset UART frame encapsulation format, the application layer buffer data is formatted as a UART frame to obtain a UART data frame; According to the header information, the channel mapping table is searched to determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters, the UART data frame is sent through the corresponding UART interface.

2. The method according to claim 1, characterized in that The pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, UDP total length, data information and checksum.

3. The method according to claim 1, characterized in that The method of performing data verification on the UDP datagram according to the pseudo header information and the header information to obtain a verification result, and caching the UDP datagram according to the verification result to obtain UDP cache data includes: Perform data transmission verification on UDP datagrams based on pseudo-header information and header information; If the data transmission verification result is that it fails the verification, the UDP datagram is discarded; If the data transmission check result is passed, a cyclic redundancy check is performed on the UDP datagram based on the pseudo header information and the header information; If the cyclic redundancy check result is a failure, the UDP datagram is discarded; If the check result of the cyclic redundancy check is passed, the UDP datagram is cached in the first first-in-first-out queue to obtain UDP cache data.

4. The method according to claim 3, characterized in that After caching the UDP datagram into the first first-in-first-out queue and obtaining the UDP cache data, the method further includes: Check whether the first FIFO queue is full; If the first FIFO queue is full, new UDP buffered data is discarded.

5. The method according to claim 1, wherein The method of performing UART frame formatting on the application layer buffer data according to a preset UART frame encapsulation format to obtain a UART data frame includes: Extracting a command word field and a length field from the application layer buffer data; Add a 1-byte channel identification prefix before the command word field; Generate a CRC16 checksum based on the encapsulated data, where the encapsulated data includes the source port number, the destination port number, the total UDP length, the data information, and the checksum; The channel identification prefix, command word field, length field, data information and CRC16 check code are encapsulated into a serial frame format to obtain a UART data frame, wherein the UART data frame includes a start bit, a channel identification prefix, a command word field, a length field, data information, a CRC16 check code and a stop bit in sequence.

6. The method according to claim 1 or 2, characterized in that The method includes searching the channel mapping table according to the header information, determining the UART channel ID set, and sending the UART data frame through the corresponding UART interface based on the UART channel ID set and preset configuration parameters based on the dynamic priority arbitration mechanism, including: According to the destination port number in the header information, search the channel mapping table to determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include the basic priority, the basic wait count, and the basic baud rate; Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority of each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Select the minimum value of the valid priority corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current wait count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

7. A UDP protocol to multi-channel UART protocol conversion device based on FPGA, characterized in that: The device includes: a UDP protocol parsing module, a UDP verification module, a first buffer module, an application layer protocol parsing module, a second buffer module, a UART encapsulation module and a channel management module; wherein, UDP protocol parsing module, used to receive and parse UDP datagrams to obtain pseudo header information and header information; The UDP verification module is connected to the UDP protocol parsing module and is used to perform data verification on the UDP datagram based on the pseudo header information and the header information to obtain the verification result; The first buffer module and the UDP verification module are used to buffer the UDP datagram according to the verification result to obtain UDP buffer data; The application layer protocol parsing module is connected to the first cache module and is used to perform application layer protocol parsing on the UDP cache data to obtain corresponding application layer data; The second cache module is connected to the application layer protocol parsing module and is used to cache the application layer data to obtain application layer cache data; The UART encapsulation module is connected to the second buffer module and is used to perform UART frame formatting on the application layer buffer data according to a preset UART frame encapsulation format to obtain a UART data frame; The channel management module is connected to the UDP protocol parsing module and the UART encapsulation module respectively. It is used to search the channel mapping table according to the header information, determine the UART channel ID set, and send the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters.

8. The device according to claim 7, characterized in that The channel management module is further configured to: According to the destination port number in the header information, search the channel mapping table to determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set, where the preset configuration parameters include the basic priority, the basic wait count, and the basic baud rate; Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority of each UART channel in the UART channel ID set respectively, where effective priority = basic priority - wait boost value - baud rate boost value, wait boost value = current wait count / basic wait count, baud rate boost value = current channel baud rate / basic baud rate; Select the minimum value of the valid priority corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After the target UART channel is determined, the current pointer is reset to the channel ID of the target UART channel plus 1, and the current wait count of the target UART channel is reset to zero, waiting for the next round of priority arbitration.

9. An electronic device, characterized in that: include: a memory having a computer program stored thereon; A processor, configured to execute the computer program in the memory to implement the steps of the method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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