Data storage device with file system manager

Abstract

The memory subsystem is configured to run a file system manager and provide a file service via a memory service. For example, a connection from a memory subsystem to a host system may support both a cache coherent memory access protocol for a memory device attached by the memory subsystem to the host system and a storage access protocol for a storage device attached by the memory subsystem to the host system. Message channels through the memory device are available for an operating system running in the host system to communicate with a file system manager running in the memory subsystem to access a file system. For example, a hypertext transfer protocol (HTTP) concrete state transfer (REST) application programming interface (API) may be implemented to cause the host system to access the file system in the memory subsystem.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application serial number 18 / 439,684, filed on February 12, 2024, which claims priority to provisional U.S. patent application serial number 63 / 487,137, filed on February 27, 2023, the entire disclosure of which is hereby incorporated by reference into this document. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, to memory systems configured to be accessible to memory services and storage services. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments are illustrated by way of example and not limitation in the accompanying figures in which like reference numerals indicate similar elements.

[0006] Figure 1 An example computing system having a memory subsystem according to some embodiments of the present disclosure is described.

[0007] Figure 2 Shown is a memory subsystem configured to provide both memory services and storage services to a host system through a physical connection, according to one embodiment.

[0008] Figure 3 A memory subsystem configured to provide memory services using a portion of the non-volatile storage capacity of the memory subsystem is shown according to one embodiment.

[0009] Figure 4 Operations configured in a memory subsystem to respond to a memory access request according to one embodiment are described.

[0010] Figure 5 A configuration for allowing a portion of a memory subsystem's non-volatile storage capacity to be addressable via both memory services and storage services is described according to one embodiment.

[0011] Figure 6 A computing system having a file system manager configured in a memory subsystem is shown according to one embodiment.

[0012] Figure 7 A technique is presented for storing files in a file system operated by a file system manager configured in a memory subsystem according to one embodiment.

[0013] Figure 8 A technique for retrieving files from a file system operated by a file system manager configured in a memory subsystem is presented according to one embodiment.

[0014] Figure 9 and Figure 10 A technique for accessing the contents of a file in a file system operated by a file system manager configured in a memory subsystem is presented according to one embodiment.

[0015] Figure 11 A method of managing a file system via a memory subsystem according to one embodiment is presented. DETAILED DESCRIPTION

[0016] At least some aspects of the present disclosure relate to techniques for a memory subsystem to provide memory and storage services to a host system via a physical connection. The memory subsystem can be configured to allocate a portion of its fast volatile random access memory and, optionally, a portion of its non-volatile memory to implement a memory device that is attached to the host system by the memory subsystem via a connection. The memory subsystem can manipulate a file system and file contents stored in the memory subsystem. The host system and the memory subsystem can communicate via the memory device to allow the host system to store files in and retrieve files from the file system implemented in the memory subsystem.

[0017] For example, a host system and a memory subsystem (e.g., a solid-state drive (SSD)) can be connected via a physical connection based on the Compute Express Link (CXL) computer component interconnect standard. Compute Express Link (CXL) includes protocols for storage access (e.g., cxl.io) and protocols for cache-coherent memory access (e.g., cxl.mem and cxl.cache). Thus, the memory subsystem can be configured to provide both storage services and memory services to the host system via the physical connection using Compute Express Link (CXL).

[0018] A typical solid-state drive (SSD) is configured or designed as a non-volatile storage device that preserves an entire set of data received from a host system during an unexpected power outage. An SSD utilizes volatile memory (e.g., SRAM or DRAM) as a buffer when processing storage access messages (e.g., read commands, write commands) received from the host system. To prevent data loss during a power outage, an SSD is typically configured with an internal backup power supply. This allows the SSD to continue operating for a limited period of time during a power outage to save data buffered in the volatile memory (e.g., SRAM or DRAM) to non-volatile memory (e.g., NAND). When the limited period is sufficient to ensure data preservation in the volatile memory (e.g., SRAM or DRAM) during a power outage, the volatile memory backed by the backup power supply can be considered non-volatile from the host system's perspective. Typical implementations of the backup power supply (e.g., capacitors, batteries) limit the amount of volatile memory (e.g., SRAM or DRAM) configured in the SSD to maintain the SSD's non-volatile nature as a data storage device. When the functionality of this volatile memory is implemented via fast non-volatile memory, the backup power supply can be eliminated from the solid state drive.

[0019] When an SSD is configured with a host interface that supports the Compute Express Link protocol, a portion of the SSD's fast volatile memory can optionally be configured to provide cache-coherent memory services to the host system. Such memory services can be accessed via load / store instructions executed in the host system at the byte level (e.g., 64B or 128B) over the Compute Express Link connection. Another portion of the SSD's volatile memory can be reserved for internal use by the SSD as a buffer memory to facilitate storage services to the host system. Such storage services can be accessed via read / write commands provided by the host system at the logical block level (e.g., 4KB) over the Compute Express Link connection.

[0020] When such a solid-state drive (SSD) is connected to a host system via a computing express link, the SSD can be attached and used as both a memory device and a storage device for the host system. The storage device provides storage capacity addressable by the host system at the block level via read and write commands for data logging in a database; and the memory device provides physical memory addressable by the host system at the byte level via load and store instructions.

[0021] A solid-state drive may have a small amount of volatile memory (such as DRAM or SRAM) and a large amount of non-volatile memory (such as NAND). Volatile memory is faster than non-volatile memory. A portion of the volatile memory and a portion of the non-volatile memory can be used to implement a memory device that a host system can access via a Compute Express Link (CXL) connection. The memory device provided by the solid-state drive may have an addressable memory space that is larger than the addressable memory space that can be implemented via the volatile memory of the solid-state drive.

[0022] The memory device provided by the solid-state drive can be configured so that some pages of the memory space reside in volatile memory and are therefore addressable via physical memory addresses in the portion of the volatile memory allocated to the memory device. The remaining pages of the memory space can be swapped out to non-volatile memory.

[0023] When a memory access request (e.g., generated by executing a load instruction or a store instruction) addresses a page that is not currently in volatile memory, the SSD's paging system can pull the contents of the page from non-volatile memory into volatile memory. For example, the SSD can allocate a page from volatile memory, retrieve the contents of the accessed page from non-volatile memory, and store the contents in the allocated page.

[0024] When a memory access request is configured to load data from a page of memory space provided by the memory device, the solid state drive may service the request using data from corresponding physical addresses of memory cells in the allocated page.

[0025] When a memory access request is configured to store data in a page of memory space provided by a memory device, the solid-state drive can serve the request by storing the data at the corresponding physical address of a memory cell in a page allocated from volatile memory. If the memory access request causes a page allocated from volatile memory to represent a page of memory space to be accessed, the storage of the data can be performed in parallel with retrieving the contents of the page from non-volatile memory. After retrieving the contents of the page from non-volatile memory, the portion of the content outside the physical address updated by the memory access request can be stored in the memory cells in the allocated page, and the corresponding portion that has been updated by the memory access request is not stored. Alternatively, the data of the memory access request can be buffered to be combined with the page contents pulled in from the non-volatile memory before the modified page contents are stored in the allocated page of the volatile memory.

[0026] The solid state drive may be configured to write the contents of a page in volatile memory to a corresponding page in memory space in nonvolatile memory periodically, upon power outage, or during an active memory operation where a page in volatile memory would be reallocated to another page in memory space.

[0027] For example, when the portion of the volatile memory allocated to the memory device is full (e.g., some pages that have been assigned to represent memory space hosted in non-volatile memory), when the host system requests access to another page of memory space that has not yet been pulled into the volatile memory, the solid-state drive can select a page for swapping back to the non-volatile memory. For example, the solid-state drive can select a least recently used (LRU) page and write the selected page from the volatile memory to the non-volatile memory. Alternatively, another page replacement technique can be used, such as first-in-first-out (FIFO), best-effort page replacement, etc.

[0028] Optionally, the paging system of the solid-state drive can be configured to actively save pages that can be selected for swapping out in the background based on page replacement technology. For example, when the host system is accessing some of the pages that have been pulled into the volatile memory, if the selected page has a change that makes the corresponding page in the non-volatile memory obsolete, the paging system can select the page as a candidate for swapping out and write the page to the non-volatile memory. Once the page in the volatile memory and the corresponding page in the non-volatile memory have the same content, the page in the volatile memory is clean and ready for reuse. When the host system requests access to another page that has not yet been pulled into the volatile memory, a clean page can be immediately allocated to represent the accessed page because the content in the clean page can be erased immediately when there is no need to save the content. Therefore, the delay in responding to memory requests can be reduced or minimized.

[0029] Optionally, a portion of the non-volatile memory allocated to implement the memory device is also configured to be accessible as part of the storage device. Thus, the host system can choose to access data in the portion of the non-volatile memory via a memory access protocol or to access data via a storage access protocol. For example, the memory space of the memory device can be accessed using a storage access protocol via logical block addresses in the namespace of the storage space in the solid-state drive, and can be accessed using a cache coherent memory access protocol via memory addresses in the memory space implemented by the memory device.

[0030] Optionally, the host system may send a configuration request to the SSD via the compute fast link connection to customize the memory services provided by the SSD. For example, the configuration request may identify resource allocation for implementing the memory device, such as the size of the memory space provided by the memory device, the amount of volatile memory allocated to represent pages of the memory space, the amount of non-volatile memory allocated to host pages of the memory space, a memory address range for accessing the memory space, a namespace of the memory space for accessing data in the memory space via a storage access protocol, etc.

[0031] It is advantageous to configure a solid-state drive with a file system manager that uses the storage capacity of the solid-state drive to operate a file system. The solid-state drive can store the contents of files as well as metadata that organizes the files in the file system. The file system manager in the solid-state drive can be configured to manage the metadata and operate files without the assistance of the host system. Thus, the task of operating the file system configured in the storage capacity of the solid-state drive can be offloaded from the host system to the solid-state drive.

[0032] When a file system is deployed on an SSD, a file system manager running on the SSD can control various aspects of the file system, such as file names, directory organization, access attributes, security, etc. The file system's structure and access control features can be used to facilitate cross-process and system collaboration.

[0033] The solid-state drive can be configured to manage the storage location of files of a file system configured in the solid-state drive. For example, a file can be stored in a storage device that is attached to a host system by the solid-state drive through a computing fast link connection for access using a storage access protocol. For example, a file can be stored in a memory device that is attached to a host system by the solid-state drive through a computing fast link connection for access using a cache coherent memory access protocol. Optionally, the memory space of the memory device is implemented in the storage space of the storage device, so that the same file data can be accessed by the host system using the cache coherent memory access protocol through the computing fast link connection, and can be accessed by the host system using the storage access protocol through the computing fast link connection.

[0034] The host system and the solid-state drive can communicate with each other via a memory device that is attached to the host system by the solid-state drive through a computing fast link connection. Through the memory device, the solid-state drive can receive requests for files in the file system from the host system and provide responses to the host system. The solid-state drive can be configured to use the memory device to establish a connection between files organized in the file system hosted on the solid-state drive and access capabilities connected through the computing fast link using a cache coherent memory access protocol and a storage access protocol, such as in Figure 6 middle.

[0035] For example, one or more message queues may be configured in the memory device to facilitate communication between the host system and the SSD. The host system may send file access requests to the file system via the message queues; and the SSD may use the message queues to provide responses after a file system manager, configured as part of the SSD's firmware, processes the requests.

[0036] For example, the host system may request to create a file in the file system, write content to the file, and request to retrieve the content of the file. The solid-state drive may be configured to use a message queue to receive the request, receive the content to be written to the file, and provide the content of the file retrieved from the file system, as in Figure 7 and Figure 8 middle.

[0037] Optionally, the solid-state drive may identify to the host system the logical block addresses of the storage resources allocated to the file; and the host system may use the storage access protocol to write data to the logical block addresses, and therefore to the corresponding portion of the file, and read data from the logical block addresses, and therefore from the corresponding portion of the file, over a computing fast link connection, as in Figure 9 middle.

[0038] Optionally, the solid-state drive may identify to the host system a memory address of a memory region in the memory device that is allocated to the file; and the host system may use a cache coherent memory access protocol to store data to and load data from the memory address, and therefore, the corresponding portion of the file, over a computationally fast link connection, as in Figure 10 middle.

[0039] Optionally, the SSD and the host system can be configured to communicate with each other through the memory device using a Representational State Transfer (REST) ​​application programming interface (API) to allow the host system to access a file system configured in the SSD. For example, the API for allowing the host system to access the file system in the SSD can be configured according to the Simple Storage Service (S3) (e.g., the Hypertext Transfer Protocol (HTTP) REST API used in Amazon Cloud Storage).

[0040] It is advantageous for the host system to use a communication protocol to query the solid-state drive about the memory attachment capabilities of the solid-state drive, such as whether the solid-state drive can provide cache-coherent memory services, how much memory the solid-state drive can attach to the host system when providing memory services, how much of the memory that can be attached to provide memory services can be considered non-volatile (e.g., implemented via non-volatile memory or supported by a backup power supply), how much access time the memory that can be allocated by the solid-state drive to the memory service, etc.

[0041] The query results can be used to configure memory allocation in the solid-state drive to provide cache-coherent memory services. For example, a portion of the solid-state drive's fast memory can be provided to the host system for cache-coherent memory access; and the remaining portion of the fast memory can be retained internally by the solid-state drive. The partitioning of the solid-state drive's fast memory for different services can be configured to balance the benefits of the memory services provided by the solid-state drive to the host system with the performance of the storage services implemented by the solid-state drive for the host system. Optionally, the host system can explicitly request the solid-state drive to allocate a requested portion of its fast volatile memory as memory that can be accessed by the host system through a connection based on a computing fast link using a cache-coherent memory access protocol.

[0042] For example, when a solid-state drive is connected to a host system via a computing express link to provide storage services, the host system may send a command to the solid-state drive to query the storage attachment capability of the solid-state drive.

[0043] For example, a command to query memory attachment capabilities may be configured with a different command identifier than a read command; and in response, the solid-state drive is configured to provide a response indicating whether the solid-state drive is capable of operating as a memory device to provide memory services accessible via load instructions and store instructions. In addition, the response may be configured to identify the amount of available memory that can be allocated and attached as a memory device accessible via a compute express link connection. Optionally, the response may be further configured to include an identification of the amount of available memory that can be viewed as non-volatile by the host system and that can be used as a memory device by the host system. The non-volatile portion of the memory device attached by the solid-state drive may be implemented via non-volatile memory or volatile memory supported by a backup power source and the non-volatile storage capacity of the solid-state drive.

[0044] Optionally, the solid-state drive may be configured with more volatile memory than its backup power supply supports. After a power outage to the solid-state drive, the backup power supply is sufficient to store data from a portion of the solid-state drive's volatile memory to its storage capacity, but is insufficient to save all of the data in the volatile memory to its storage capacity. Therefore, the response to the memory attachment capability query may include an indication of the ratio of the volatile to non-volatile portions of the memory that can be allocated by the solid-state drive to the memory service. Optionally, the response may further include an identification of the access time of the memory that can be allocated by the solid-state drive to the cache coherent memory service. For example, when a host system requests data from the solid-state drive via a cache coherent protocol over a compute fast link, the solid-state drive may provide the data within a period of time no longer than the access time.

[0045] Optionally, a preconfigured response to this query can be stored at a predetermined location in a storage device attached to the host system by the SSD. For example, the predetermined location can be at a predetermined logical block address in a predetermined namespace. For example, the preconfigured response can be configured as part of the SSD's firmware. The host system can use a read command to retrieve the response from the predetermined location.

[0046] Optionally, when the solid-state drive has the capability to function as a memory device, the solid-state drive may automatically allocate a predetermined amount of its fast volatile memory as a memory device attached to the host system via a computing fast link connection. The predetermined amount may be a minimum or default amount configured in the solid-state drive's manufacturing facility or an amount specified by configuration data stored in the solid-state drive. Subsequently, a memory attachment capability query may optionally be implemented in a command set of a cache coherent memory access protocol (rather than a command set of a storage access protocol); and the host system may use the query to retrieve parameters specifying the memory attachment capability of the solid-state drive. For example, the solid-state drive may place the parameters in a memory device at a predetermined memory address; and the host may retrieve the parameters by executing a load command with the corresponding memory address.

[0047] It would be advantageous for a host system to customize aspects of the memory services of a memory subsystem (eg, a solid state drive) to the host system's memory and storage usage patterns.

[0048] For example, the host system may specify the size of a memory device provided by the SSD for attachment to the host system so that a set of physical memory addresses configured according to the size can be addressed via execution of load / store instructions in a processing device of the host system.

[0049] Optionally, the host system can specify time requirements for accessing a memory device over a Compute Express Link (CXL) connection. For example, when a cache request accesses a memory location over the connection, the SSD is required to provide a response within the access time specified by the host system when configuring the SSD's memory services.

[0050] Optionally, the host system can specify how much of the memory device attached to the solid-state drive is required to be non-volatile, so that when the external power supply to the solid-state drive fails, data in the non-volatile portion of the memory device attached to the host system by the solid-state drive is not lost. The non-volatile portion can be implemented by the solid-state drive via non-volatile memory or volatile memory with a backup power supply to continue copying data from the volatile memory to the non-volatile memory during the interruption of the external power supply to the solid-state drive.

[0051] Optionally, the host system can specify whether the solid state drive will attach the memory device to the host system via a Compute Express Link (CXL) connection.

[0052] For example, a solid-state drive may have an area configured to store configuration parameters for a memory device attached to a host system via a Compute Express Link (CXL) connection. When the solid-state drive is restarted, started, or powered on, the solid-state drive may allocate a portion of its memory resources as a memory device for attachment to the host system according to the configuration parameters stored in the area. After the solid-state drive configures the memory service according to the configuration parameters stored in the area, the host system can access it through the cache by executing load instructions and store instructions that identify the corresponding physical memory addresses. The solid-state drive can configure its remaining memory resources to provide storage services through a Compute Express Link (CXL) connection. For example, a portion of its volatile random access memory may be allocated as a buffer memory reserved for the processing device of the solid-state drive; and the host system cannot access and address the buffer memory via load / store instructions.

[0053] When the solid-state drive is connected to the host system via a compute express link, the host system may send a command to adjust configuration parameters stored in an area of ​​an attachable memory device. The host system may then request the solid-state drive to reattach the memory device with the memory service configured according to the configuration parameters to the host system via the compute express link.

[0054] For example, the host system may be configured to issue a write command (or store command) to save configuration parameters at a predetermined logical block address (or predetermined memory address) in a region to customize the settings of a memory device configured to provide memory services over a compute fast link connection.

[0055] Alternatively, a command having a command identifier different from the write command (or store instruction) may be configured in the read-write protocol (or load-store protocol) to instruct the solid-state drive to adjust the configuration parameters stored in the area.

[0056] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include computer-readable storage media, such as one or more volatile memory devices (e.g., memory device 107), one or more non-volatile memory devices (e.g., memory device 109), or a combination thereof.

[0057] exist Figure 1 In FIG. 1 , the memory subsystem 110 is configured as an article of manufacture (eg, a solid-state drive) that can be used as a component installed in a computing device.

[0058] The memory subsystem 110 further includes a host interface 113 for physical connection 103 with a host system 120 .

[0059] The host system 120 may have an interconnect 121 connecting a cache 123 , a memory 129 , a memory controller 125 , a processing device 127 , and a memory manager 101 that is configured to set up memory services for the memory subsystem 110 .

[0060] The memory manager 101 in the host system 120 may be implemented at least in part via instructions executed by the processing device 127 or via logic circuitry, or both. The memory manager 101 in the host system 120 may send configuration parameters to the memory subsystem to customize or control memory devices attached to the host system 120 by the memory subsystem 110. Optionally, the memory manager 101 in the host system 120 is implemented as part of an operating system 135 of the host system 120 or as a device driver configured to operate the memory subsystem 110, or a combination of such software components.

[0061] Connections 103 may be in accordance with the Compute Express Link (CXL) standard or other communication protocols that support cache coherent memory access and storage access. Optionally, multiple physical connections 103 are configured to support cache coherent memory access communications and to support storage access communications.

[0062] The processing device 127 may be a microprocessor configured as a central processing unit (CPU) of a computing device. Instructions executed in the processing device 127 (e.g., load instructions, store instructions) may access the memory 129 via the memory controller 125 and the cache 123. In addition, when the memory subsystem 110 attaches the memory device to the host system via the connection 103, the instructions executed in the processing device 127 (e.g., load instructions, store instructions) may access the memory device via the memory controller 125 and the cache 123 in a manner similar to accessing the memory 129.

[0063] For example, in response to executing a load instruction in processing device 127, memory controller 125 may convert the logical memory address specified by the instruction into a physical memory address to request cache 123 to perform a memory access to retrieve data. For example, the physical memory address may be in memory 129 of host system 120 or in a memory device attached to host system 120 by memory subsystem 110 via connection 103. If the data at the physical memory address is not already in cache 123, cache 123 may load the data from the corresponding physical address as cache contents 131. Cache 123 may provide cache contents 131 to service the memory access request at the physical memory address.

[0064] For example, in response to executing a store instruction in the processing device 127, the memory controller 125 may convert the logical memory address specified by the instruction into a physical memory address to request the cache 123 to perform a memory access to store the data. The cache 123 may retain the data of the store instruction as cache content 131 and indicate that the corresponding data at the physical memory address has expired. When the cache 123 needs to free up a cache block (e.g., to load new data from a different memory address or to retain data for a store instruction at a different memory address), the cache 123 may flush the cache content 131 from the cache block to the corresponding physical memory address (e.g., in the host system's memory 129 or in a memory device attached to the host system 120 by the memory subsystem 110 via the connection 103).

[0065] The connection 103 between the host system 120 and the memory subsystem 110 can support a cache coherent memory access protocol. Cache coherence ensures that changes to a copy of data corresponding to a memory address are propagated to other copies of the data corresponding to the memory address, and that a processing device (e.g., 127) sees load / store accesses to the same memory address in the same order.

[0066] Operating system 135 may include routines programmed to process instructions for storage access requests from applications.

[0067] In some embodiments, the host system 120 configures a portion of its memory (e.g., 129) to serve as a queue 133 for storage access messages. Such storage access messages may include read commands, write commands, erase commands, and the like. A storage access command (e.g., read or write) may specify a logical block address of a data block in a storage device (e.g., attached to the host system 120 by the memory subsystem 110 via connection 103). The storage device may retrieve the message from the queue 133, execute the command, and provide the result in the queue 133 for further processing by the host system 120 (e.g., using routines in the operating system 135).

[0068] Typically, the data blocks addressed by storage access commands (e.g., read or write) are much larger than the data units accessible via memory access instructions (e.g., load or store). Therefore, storage access commands can facilitate batch processing of large amounts of data (e.g., data in files managed by a file system) simultaneously and in the same manner with the help of routines in operating system 135. Memory access instructions can be used efficiently for random access to small pieces of data without the overhead of routines in operating system 135.

[0069] The memory subsystem 110 has an interconnect 111 that connects a host interface 113 , a controller 115 , and memory resources (eg, memory devices 107 , . . . , 109 ).

[0070] The controller 115 of the memory subsystem 110 may control the operation of the memory subsystem 110. For example, the operation of the memory subsystem 110 may be responsive to storage access messages in the queue 133 or responsive to a memory access request from the cache 123.

[0071] In some implementations, each of the memory devices (e.g., 107, ..., 109) includes one or more integrated circuit devices, each enclosed in a separate integrated circuit package. In other implementations, each of the memory devices (e.g., 107, ..., 109) is configured on an integrated circuit die; and the memory devices (e.g., 107, ..., 109) may be configured in the same integrated circuit device enclosed within the same integrated circuit package. In yet another implementation, the memory subsystem 110 is implemented as an integrated circuit device having an integrated circuit package that encloses the memory devices 107, ..., 109, the controller 115, and the host interface 113.

[0072] For example, the memory device 107 of the memory subsystem 110 may have a volatile random access memory 138 that is faster than the non-volatile memory 139 of the memory device 109 of the memory subsystem 110. Thus, the non-volatile memory 139 may be used to provide storage capacity of the memory subsystem 110 for retaining data. At least a portion of the storage capacity may be used to provide storage services to the host system 120. Optionally, a portion of the volatile random access memory 138 may be used to provide cache coherent memory services to the host system 120. The remaining portion of the volatile random access memory 138 may be used to provide buffering services to the controller 115 when processing storage access messages in the queue 133 and when performing other operations (e.g., wear leveling, garbage collection, error detection and correction, encryption).

[0073] When the volatile random access memory 138 is used to buffer data received from the host system 120 before being stored in the non-volatile memory 139, the data in the volatile random access memory 138 may be lost when power to the memory device 107 is interrupted. To prevent data loss, the memory subsystem 110 may have a backup power supply 105 that may be sufficient to operate the memory subsystem 110 for a period of time to allow the controller 115 to commit the buffered data from the volatile random access memory 138 to the non-volatile memory 139 in the event that external power to the memory subsystem 110 is interrupted.

[0074] Optionally, fast memory 138 may be implemented via non-volatile memory (e.g., cross-point memory); and backup power supply 105 may be eliminated. Alternatively, a combination of fast non-volatile memory and fast volatile memory may be configured in memory subsystem 110 for both memory and buffer services.

[0075] The host system 120 may send a memory attachment capability query to the memory subsystem 110 via the connection 103. In response, the memory subsystem 110 may provide a response identifying whether the memory subsystem 110 can provide cache coherent memory services via the connection 103, how much memory can be attached to provide memory services via the connection 103, how much of the memory available for the host system's 120 memory services is considered non-volatile (e.g., implemented via non-volatile memory or backed by the backup power supply 105), how much access time can be allocated to the memory services of the host system 120, etc.

[0076] The host system 120 may send a request to the memory subsystem 110 over the connection 103 to configure the memory services provided by the memory subsystem 110 to the host system 120. In the request, the host system 120 may specify whether the memory subsystem 110 will provide cache coherent memory services over the connection 103, how much memory is to be provided as memory services over the connection 103, how much of the memory provided over the connection 103 is to be considered non-volatile (e.g., implemented via non-volatile memory or backed up by the backup power supply 105), how long the memory is to be accessed as a memory service to the host system 120, etc. In response, the memory subsystem 110 may partition its resources (e.g., memory devices 107, . . . , 109) and provide the requested memory services over the connection 103.

[0077] When a portion of memory 138 is configured to provide memory services over connection 103, host system 120 can access cache portion 132 of memory 138 via load and store instructions and cache 123. Non-volatile memory 139 can be accessed via read and write commands, which are transmitted via queue 133 configured in memory 129 of host system 120.

[0078] The memory manager 101 in the memory subsystem 110 can use the resources of the memory subsystem 110 to implement memory services provided through the connection 103 to the memory devices attached to the host system 120. For example, the memory manager 101 can allocate a portion of the fast volatile memory 138 as cache memory to access the memory space hosted in the slow non-volatile memory 139. Optionally, the memory space can overlap with a portion of the memory space provided by the memory subsystem 110 to the host system 120. Thus, a portion of the non-volatile memory 139 can be accessed both via the memory services and via the storage services.

[0079] In general, the memory manager 101 may be implemented in the host system 120 or the memory subsystem 110, or partially implemented in the host system 120 and partially implemented in the memory subsystem 110. The memory manager 101 in the memory subsystem 110 may be implemented at least partially via instructions (e.g., firmware) executed by the processing device 117 of the controller 115 of the memory subsystem 110, or via logic circuitry, or both.

[0080] Figure 2 A memory subsystem is shown that is configured to provide both memory services and storage services to a host system through a physical connection according to one embodiment. Figure 2 The memory subsystem 110 and the host system 120 can be implemented in a manner as Figure 1 computing system 100.

[0081] exist Figure 2 , the memory resources of the memory subsystem 110 (e.g., memory devices 107, ..., 109) are partitioned into a loadable portion 141 and a readable portion 143 (and in some cases, an optional portion of a buffer memory 149, as in Figure 5 The physical connection 103 between the host system 120 and the memory subsystem 110 may support a protocol 145 for load and store instructions to access memory services provided in the loadable portion 141. For example, the load and store instructions may be executed via the cache 123. The connection 103 may further support a protocol 147 for read and write commands to access storage services provided in the readable portion 143. For example, the read and write commands may be provided via a queue 133 configured in the memory 129 of the host system 120. For example, a physical connection 103 supporting Compute Express Link may be used to connect the host system 120 and the memory subsystem 110.

[0082] Figure 2An example is illustrated of the same physical connection 103 (e.g., a Compute Express Link connection) configured to facilitate both memory access communications according to a protocol 145 and memory access communications according to another protocol 147. In general, a single physical connection can be used to provide memory access according to the memory access protocol 145 and memory access according to another memory access protocol 147 to the host system 120.

[0083] Figure 3 A memory subsystem is shown configured to provide memory services using a portion of the non-volatile storage capacity of the memory subsystem according to one embodiment. For example, Figure 3 The storage service can be implemented in Figure 1 and Figure 2 In the computing system 100.

[0084] exist Figure 3 In FIG. 1 , the memory subsystem 110 has a non-volatile storage capacity 151. The non-volatile storage capacity 151 may be implemented using non-volatile memory (eg, 139) of a memory device (eg, 109) of the memory subsystem 110.

[0085] The loadable portion 141 of the non-volatile storage capacity 151 may be allocated to provide memory space for a memory device attached by the memory subsystem 110 to the host system 120 via the connection 103. The host system 120 may access the loadable portion 141 via the connection 103 using a cache coherent memory access protocol (e.g., 145), as described in Figure 2 middle.

[0086] The readable portion 143 of the non-volatile storage capacity 151 can be allocated to provide storage space for a storage device attached by the memory subsystem 110 to the host system 120 via the connection 103. The host system 120 can access the readable portion 143 via the connection 103 using a storage access protocol (e.g., 147), as described in Figure 2 middle.

[0087] A portion of the volatile random access memory 138 of the memory subsystem 110 may be allocated as cache memory 157 to implement memory services provided by the memory subsystem 110 to the host system 120 via the connection 103 .

[0088] Memory manager 101 of memory subsystem 110 may be configured to use cache memory 157 to support and accelerate memory operations addressing active pages of loadable portion 141. Memory manager 101 may be implemented via instructions or logic circuitry executed in processing device 117 of memory subsystem 110, or both.

[0089] The remainder of the volatile random access memory 138 of the memory subsystem 110 may be used as a buffer memory 149 by the memory subsystem 110 when running the firmware 153 and the memory manager 101 .

[0090] When pages of loadable portion 141 are used by host system 120, memory manager 101 may allocate pages in cache memory 157 as a proxy or cache for the pages of loadable portion 141. Memory manager 101 may operate address map 155 to identify dynamic associations between pages in cache memory 157 and pages in loadable portion 141.

[0091] When the address map 155 indicates that a page of the loadable portion 141 has a corresponding page of the cache memory 157, a memory access request addressed to the page of the loadable portion 141 can be performed on the corresponding page of the cache memory 157. For example, when the host system 120 uses the cache coherent memory access protocol 145 to store data in a memory address identifying the page of the loadable portion 141, the memory manager 101 can identify the corresponding address of a memory cell in the corresponding page of the cache memory 157 of the memory subsystem 110 to initially store the data in the corresponding page of the cache memory 157. The memory subsystem 110 can (e.g., using the address map 155) indicate that the corresponding page of the cache memory 157 is dirty because it has data to be saved to the corresponding page of the loadable portion 141. After the data in the page of the cache memory 157 is saved to the page of the loadable portion 141, the page of the cache memory 157 becomes clean because it has the same content as the corresponding page of the loadable portion 141.

[0092] Cache memory 157 has fewer pages than loadable portion 141. Cache memory 157 becomes full when all of its pages are used to represent some active pages in loadable portion 141. Memory manager 101 may identify one or more pages in cache memory 157 as candidates for replacement pages representing loadable portion 141 to be actively used by host system 120. For example, memory manager 101 may be configured to identify candidate pages using techniques such as least recently used (LRU), first in first out (FIFO), optimal page replacement, etc.

[0093] If the address map 155 indicates that the candidate page is dirty, the memory manager 101 may proactively clean the page by writing its contents to the corresponding page in the loadable portion 141 .

[0094] Subsequently, when the host system 120 uses the cache coherence protocol 145 to access a page of the loadable portion 141 that is not yet represented by a corresponding page in the cache memory 157, the memory manager 101 may update the address map 155 to use the clean candidate page of the cache memory 157 to represent the accessed page of the loadable portion 141. The memory manager 101 may read the accessed page of the loadable portion 141 to retrieve the page data and store the page data in the clean candidate page of the cache memory 157, thereby discarding the existing contents of the clean candidate page. No data is lost because the existing contents are the same as in the page previously represented by the candidate page. The address map 155 may be updated to identify the accessed page as represented by the candidate page.

[0095] A memory access that allocates a candidate page as an access page representing the loadable portion 141 may request retrieval of data from the access page. In response to this memory access, the memory manager 101 may be configured to store the page data retrieved from the loadable portion 141 in the candidate page. Subsequently, the candidate page may be addressed to service the memory access as if it were the access page.

[0096] Because it takes longer to retrieve data from the loadable portion 141 than to serve data from the cache memory 157, significant delays can occur in servicing a memory access that causes a candidate page to be allocated and set to represent a page in the loadable portion 141. Optionally, the memory manager 101 can indicate an error in response to the memory access when retrieving the page data from the loadable portion 141. Subsequently, when the host system 120 makes the same memory access, the candidate page can be ready to represent the access page; and the memory manager 101 can use the candidate page to service the memory access as if it were the access page. Using the cache memory 157 to service the memory access is faster than using the loadable portion 141 in the non-volatile storage capacity 151 to service the memory access.

[0097] A memory access that allocates a candidate page as an access page representing loadable portion 141 may request that data be stored in the access page. In response to this memory access, memory manager 101 may be configured to store combined data representing the page data updated by the memory access in the candidate page. The candidate page is then dirty (e.g., as indicated in address map 155) until the changes are saved to the corresponding page in loadable portion 141.

[0098] For example, after the memory manager 101 allocates a candidate page of the cache memory 157 to represent the access page of the loadable portion 141 in response to a memory access that stores data at a memory address, the memory manager 101 may store the data at the corresponding memory address in the cache memory 157 while reading the access page of the loadable portion 141. After the data for the access page is available, the memory manager 101 may write the data to the remaining addresses in the candidate page, thereby skipping the memory addresses that already store the data provided by the memory access from the host system 120.

[0099] Alternatively, the memory manager 101 may temporarily save data received from the host system 120 in a memory access in the buffer memory 149 while retrieving the page data from the accessed page in the loadable portion 141. When the page data is available, the memory manager 101 may update the page data (e.g., in the buffer memory 149) and move the updated page data to the candidate page of the cache memory 157. Optionally, the update may be performed in situ in the candidate page of the cache memory 157.

[0100] In some embodiments, the nonvolatile memory 139 of the memory subsystem 110 has a structure of memory cell pages and memory cell page blocks. A memory cell page is the smallest unit for programming memory cells to store data. Memory cells in a page are configured to be programmed together in an atomic programming operation. A memory cell page block is the smallest unit for erasing memory cells, allowing individual memory cell pages in a block to be programmed to store data. Memory cell pages in a block are configured to be erased together in an atomic erase operation.

[0101] The pages of memory space in the loadable portion 141 that are to be represented by pages in the cache memory 157 can be configured to align with the memory cell pages of the non-volatile memory 139. Therefore, when dirty pages in the cache memory 157 are stored in the loadable portion 141, the number of programming operations required to save the data from the pages of the cache memory 157 is minimized. For example, the pages in the cache memory 157 can be configured to represent the memory cell pages in the loadable portion 141. When a page of the cache memory 157 is dirty, the corresponding memory cell page can be marked as no longer in use and can therefore be erased. When the page of the cache memory 157 is to be stored back in the loadable portion, the memory subsystem 110 can allocate a free memory cell page that has been erased and program the allocated memory cell page to store the data of the page of the cache memory 157.

[0102] For example, firmware 153 may include a flash translation layer (FTL) configured to translate logical storage addresses into physical memory cell addresses in non-volatile storage capacity 151. Rather than mapping pages of cache memory 157 to fixed memory cell pages, memory manager 101 may configure address mapping 155 to map pages of cache memory 157 to logical storage pages, which may be mapped by the flash translation layer (FTL) to dynamically allocated memory cell pages to store the page's data in cache memory 157.

[0103] Optionally, the loadable portion 141 can also be configured to be accessible via the connection 103 via a storage access protocol 147. For example, the memory subsystem 110 can create a namespace of the non-volatile storage capacity 151 and assign the namespace to the loadable portion 141. Storage locations in the namespace, and therefore the loadable portion 141, can be addressed via logical block addresses in the namespace; and the host system 120 can use write commands and read commands in the storage access protocol 147 to write data to and retrieve data from the loadable portion 141. Furthermore, locations in the loadable portion 141 can be addressed via memory addresses mapped to the namespace via the address map 155 (and the address map of the flash translation layer (FTL)); and the host system 120 can use load instructions and store instructions to access via the cache coherent memory access protocol 145 to store data in and load data from the loadable portion 141.

[0104] Figure 4 The following describes operations configured in a memory subsystem to respond to a memory access request according to one embodiment. For example, Figure 4 The operation can be performed on Figure 1 and Figure 2 In the computing system 100 Figure 3 In the memory subsystem 110.

[0105] exist Figure 4 In FIG. 1 , a memory access request 161 is transmitted from the host system 120 to the host interface 113 of the memory subsystem 110 via the connection 103 . For example, the memory access request 161 may be in accordance with the cache coherent memory access protocol 145 .

[0106] Memory access request 161 identifies a memory address 163 representing a memory location in a memory device attached by memory subsystem 110 to host system 120 via connection 103 .

[0107] The memory subsystem 110 manages an address map 155 that identifies the association between pages of cache memory 157 (eg, 177 ) and pages of storage memory in the loadable portion 141 (eg, 167 ).

[0108] Cache memory 157 is faster than loadable portion 141 but has fewer pages than loadable portion 141. A page (e.g., 177) of cache memory 157 may be used to represent a portion of a memory page (e.g., 167) that is actively used by host system 120.

[0109] The memory space in the loadable portion 141 is pre-divided into pages 167. Thus, the memory subsystem 110 can calculate, from the memory address 163, the page identification 165 of the storage memory page 167 containing the memory location identified by the memory address 163.

[0110] The memory subsystem 110 may determine whether the storage memory page identification 165 is in the address map 155 and is associated with the page identification 175 of the cache memory page 177 .

[0111] If a cache memory page 177 has been allocated to represent the storage memory page 167, the address map 155 contains data associating the storage memory page identification 165 with the cache memory page identification 175. The memory subsystem 110 can then translate the memory address 163 in the storage memory page 167 into the corresponding memory address 173 in the corresponding cache memory page 177.

[0112] For example, when memory address 163 identifies a memory location at memory cell 168 in memory page 167, memory subsystem 110 may determine that memory address 173 represents a corresponding memory cell 178 of memory cell 168. Thus, memory access request 161 applies to a corresponding memory operation at memory address 173 of memory cell 178.

[0113] For example, when memory access request 161 is for loading data from memory address 163 , memory subsystem 110 may retrieve data from memory unit 178 to provide a response to request 161 .

[0114] For example, when a memory access request 161 is used to store data to memory address 163, the memory subsystem 110 may store the data to memory cell 178 and update the page status 171 to indicate that cache memory page 177 is dirty, thereby indicating that page 177 contains data to be stored back to the storage memory page 167 identified by the storage memory page identifier 165.

[0115] When a cache memory page 177 is dirty but not actively used by the host system 120 via a memory access request (e.g., 161), the memory subsystem 110 may retrieve data from the cache memory page 177 and store the data in the storage memory page 167. The memory subsystem 110 may then update the page status 171 to indicate that the cache memory page 177 is clean, thereby indicating that the page 177 contains the same data as the corresponding storage memory page 167.

[0116] When a memory access request 161 has a memory address 163 in a storage memory page 167 but the address mapping 155 indicates that the storage memory page 167 is not yet represented by a cache memory page (e.g., 177), the memory subsystem 110 may allocate a clean cache memory page (e.g., 177) (or a free cache memory page that has not yet been allocated to represent a storage memory page) to represent the storage memory page 167.

[0117] To set the cache memory page 177 to represent the storage memory page 167, the memory subsystem 110 may retrieve data from the storage memory page 167 and store the data in the cache memory page 177. In addition, the memory subsystem 110 may update the address map 155 to associate the page identification 175 of the cache memory page 177 with the page identification 165 of the storage memory page 167.

[0118] In some implementations, cache memory page 177 is configured to represent a memory cell page 167 having memory cells 168, ..., 169 that are structured in the integrated circuit memory device 109 to be programmed together to store data in an atomic programming operation. Thus, storing data of cache memory page 177 to loadable portion 141 can be performed via a single programming operation.

[0119] In a typical implementation, cache memory 157 is less restrictive and faster than non-volatile memory 139. For example, memory cells 178, ..., 179 in cache memory page 177 are individually programmable to store data via separate programming operations.

[0120] In some embodiments, blocks of memory cell pages (e.g., 167) are configured to be erased together in the integrated circuit memory device 109 to allow the pages (e.g., 167) to be programmed to store data. To avoid unnecessary copying and erasing of data, the memory subsystem 110 can use storage memory page identification 165 to represent logical pages in the loadable portion 141. Logical pages can further be mapped to memory cell pages (e.g., 167).

[0121] Optionally, a flash translation layer (FTL) function of firmware 153 of memory subsystem 110 may be used to facilitate mapping of logical pages to pages of memory cells (eg, 167).

[0122] Optionally, memory address 163 can be configured based on the logical storage space of loadable portion 141. For example, a namespace of non-volatile storage capacity 151 can be allocated to host loadable portion 141. The flash translation layer (FTL) of firmware 153 can translate logical block addresses in the namespace into identifiers of one or more memory cell pages (e.g., 167). The memory address space of loadable portion 141 and the logical block addresses in the namespace can have a predetermined relationship. Thus, storage memory page identifier 165 can be configured to map to a memory cell page (e.g., 167) based on the logical block addresses in the namespace.

[0123] Because the relationship between the memory address (e.g., 163) of the memory access request (e.g., 161) and the logical block address in the namespace assigned to the loadable portion 141 is predetermined, the host system 120 can choose to address the memory cell page (e.g., 167) via the memory access request (e.g., 161) using the cache coherent memory access protocol 145 or via the memory access request using the storage access protocol 147, as shown in FIG. Figure 5 middle.

[0124] Figure 5 A configuration that allows a portion of a memory subsystem's non-volatile storage capacity to be addressable via both memory services and storage services is described according to one embodiment. Figure 5 The technology can be implemented in Figure 1 and Figure 2 In the computing system 100 Figure 3 In the memory subsystem 110.

[0125] exist Figure 5 In the embodiment, the non-volatile storage capacity 151 may have a readable portion 143 configured to be accessible via a storage access request (e.g., 181), which uses a logical block address (e.g., 183) to address a storage location according to a storage access protocol 147 through a connection 103 between the memory subsystem 110 and the host system 120.

[0126] A portion 141 of the readable portion 143 may be attached as a memory device by the memory subsystem 110 to the host system 120 via the connection 103. Thus, the host system may use a memory access request 161 to access a memory address (e.g., 163) in the loadable portion 141 via the connection 103 using the cache coherent memory access protocol 147. For example, Figure 5 Memory access in Figure 4 Generally implemented.

[0127] Optionally, a logical block address (e.g., 183) can be configured to address a page of memory cells (e.g., 167) in a non-volatile memory (e.g., 139) of the memory subsystem 110. Alternatively, a logical block address (e.g., 183) can be used to address a logical block having multiple pages of memory cells (e.g., 167).

[0128] In contrast, a memory address (eg, 163) is configured to identify a memory cell of a subset of the memory cells (eg, 168) in a page of memory cells (eg, 167).

[0129] Optionally, the memory subsystem 110 may allocate multiple namespaces of the non-volatile storage capacity 151 to the loadable portion 141. Thus, different portions of a memory device attached by the memory subsystem 110 may be accessed via different namespaces using the storage access protocol 147.

[0130] Optionally, the memory subsystem 110 may allocate multiple namespaces of non-volatile storage capacity 151 for each of the multiple loadable portions (e.g., 141). The loadable portions (e.g., 141) may be attached via connection 103 as separate memory spaces addressable by the host system 120 via a cache coherent memory access protocol 145.

[0131] In response to the memory access request 161 or the storage access request 181, the memory subsystem 110 may determine whether the storage memory page 167 is cached in the cache memory 157 according to the address map 155. If so, the memory subsystem 110 may identify the cache memory page 177 and use the cache memory page 177 to service the memory access request 161; otherwise, the memory subsystem 110 may cache the storage memory page 167 in the cache memory 157.

[0132] For example, a method for providing storage services using the storage capacity of a memory subsystem according to one embodiment may use Figure 4 and Figure 5 technology to implement Figure 1 and Figure 2 In the computing system Figure 3 In the memory subsystem 110.

[0133] For example, the memory subsystem 110 may have a host interface 113 that may operate according to a storage access protocol such as 147 and a cache coherent memory access protocol such as 145 over a connection 103 to the host system 120. The memory subsystem 110 may have a first non-volatile memory such as 139 configured to provide the non-volatile storage capacity 151 of the memory subsystem 110 and a second volatile memory such as 138 that is faster than the first memory such as 139. The controller 115 of the memory subsystem 110 may be configured to: allocate a first page (e.g., 177) of a second memory (e.g., 138) to represent a second page (e.g., 167) in a memory space provided by a memory device attached to the host system by the memory subsystem via a connection; and operate the first page (e.g., 177) of the second memory (e.g., 138) in response to the memory access request 161 when a memory access request 161 transmitted to the host interface 113 via the connection 103 according to the cache coherence memory access protocol 145 identifies a memory address 163 in the memory space.

[0134] For example, the controller 115 may be configured via the firmware 153 to implement operations of the memory manager 101 to swap pages between the volatile memory 138 and the non-volatile memory 139 and to cache the pages in the cache memory 157. Optionally, each page (e.g., 167) cached in the volatile memory (e.g., 138) of the memory subsystem 110 may be configured to have a size of a page of memory cells allocated to host a portion of the memory space addressable by the host system 120 using a memory address (e.g., 163). The memory cells in each page of memory cells are configured in the integrated circuit memory device (e.g., 109) to be programmed together in an atomic programming operation to store data.

[0135] Optionally, the memory manager 101 may allocate a portion 141 of the non-volatile storage capacity 151 of the memory subsystem 110 to the namespace, attach the namespace to the host system 120 as a memory device via a Compute Express Link (CXL) connection 103 between the host interface 113 of the memory subsystem 110 and the host system 120, and provide the host system 120 with: storage access to the namespace and to logical block addresses (e.g., 183) defined in the namespace using a storage access protocol 147 via the connection 103; and memory access to a memory space corresponding to the namespace and to memory addresses (e.g., 163) using a cache coherent memory access protocol 145 via the connection 103. For example, the memory manager 101 may map the memory space to the namespace according to a predetermined relationship so that the same data can be stored or retrieved via the memory address and the logical block address.

[0136] In the method, memory subsystem 110 attaches a memory device having memory space (eg, loadable portion 141 ) configured in a first memory (eg, 139 ) of memory subsystem 110 through connection 103 from host interface 113 of memory subsystem 110 to host system 120 .

[0137] For example, the memory subsystem 110 may be a solid-state drive having a volatile random access memory 138 and a non-volatile memory 139 .

[0138] In the method, memory subsystem 110 attaches a storage device having storage space (eg, readable portion 143 ) configured in a first memory (eg, 139 ) of memory subsystem 110 through connection 103 from host interface 113 of memory subsystem 110 to host system 120 .

[0139] Optionally, the storage space (eg, readable portion 143) coincides with (or contains) the memory space (eg, loadable portion 141).

[0140] In the method, when servicing a memory access request (e.g., 161) in a memory space, the memory subsystem 110 allocates an amount of a second memory (e.g., 138) that is faster than a first memory (e.g., 139) to represent pages of the memory space (e.g., loadable portion 141).

[0141] In the method, the memory subsystem 110 manages an address map 155 configured to identify an association between a page (e.g., 177) of a second memory (e.g., 138) and a corresponding page (e.g., 167) of a memory space represented by the page (e.g., 177) of the second memory (e.g., 138).

[0142] For example, the address map 155 may include data associating a first identification 175 of a first page (eg, 177 ) with a second identification 165 of a second page (eg, 167 ) of the memory space.

[0143] Optionally, the identification 165 of the second page (eg, 167) may be based on a logical block address 183 in the memory space.

[0144] For example, a flash translation layer (FTL) of the memory subsystem 110 may be used to map the logical block address 183 to one or more pages (e.g., 167) of memory cells (e.g., 168, . . . , 169) in the memory subsystem 110. Thus, the physical location of the memory address 163 may be changed in the non-volatile memory 139 based on the mapping of the flash translation layer (FTL).

[0145] In the method, the memory subsystem 110 operates on a first page 177 of a second memory (eg, 138 ) in response to a memory access request 161 transmitted over the connection 103 according to the cache coherent memory access protocol 145 identifying a memory address 163 in the memory space.

[0146] Optionally, the first page 177 of the second memory (e.g., 138) is configured to represent a page of memory cells having memory cells 168, ..., 169 configured to be programmed together to store data in one atomic programming operation. Thus, the memory size of the cache memory page 177 is equal to the memory size of the memory cell page 167.

[0147] The memory manager 101 may be configured to swap contents of the second page 167 from the first memory (eg, 139) into the first page 177 in response to the host system 120 accessing a memory address (eg, 163) in the second page 167 according to a cache coherent memory access protocol.

[0148] The memory manager 101 may be configured to save the contents of the first page 177 to the first memory (e.g., 139) in response to determining that the host system 120 is not actively accessing the second page 167. The saving of the contents of the first page 177 may be proactively performed before the host system 120 accesses the third page in the memory space, which will cause the memory manager 101 to use the first page 177 to represent the third page (e.g., based on a page replacement technique such as least recently used (LRU), first in first out (FIFO), optimal page replacement, etc.).

[0149] For example, in response to the memory access request 161 identifying the memory address 163, the memory manager 101 may determine that the second page 167 of the memory space is not already represented by any page in the second memory 138. In response, the memory manager 101 may allocate the first page 177 of the second memory 138, retrieve the page data from the page of memory cells (e.g., 167), store the page data in the first page 177 of the second memory 138, and update the address map 155 to indicate that the first page 177 represents the second page 167.

[0150] If the memory access request 161 is configured to store the first data in the memory address 163 , the memory manager 101 may store the first data in the first page 177 of the second memory 138 and update the page status 171 in the address map 155 to indicate that the first page 171 has content to be stored in the second memory 139 .

[0151] Optionally, in response to memory access request 161 being configured to store first data in memory address 163, memory manager 101 may store data identifying that memory cell page 167, previously used to host a second page containing memory address 163, is no longer in use. Thus, firmware 153 may reclaim storage space of memory cell page 167 during background operations of garbage collection.

[0152] For example, in response to the host system actively using other pages of the memory space and therefore not actively using the second page 167 of the memory space, the memory manager 101 can store the contents of the first page 177 in the second memory 139 and update the page status 171 in the address map 155 to indicate that the contents in the first page 177 are the same as in the corresponding page in the second memory. Thus, the first page 177 is clean and can be reallocated to represent another page of the memory space for use by the host system 120.

[0153] For example, to save the contents of first page 177, the flash translation layer may allocate memory cell page 167, and the memory subsystem 110 may perform an atomic program operation to store the contents in memory cell page 167. The memory manager 101 may then update the address map 155 to indicate that cache memory page 177 is clean and represents the page hosted in memory cell page 167.

[0154] In the method, the memory subsystem 110 operates a first memory (eg, 139 ) in response to a storage access request identifying a logical block address in a storage space transmitted over the connection 103 according to the storage access protocol 147 .

[0155] For example, when a logical block address identifies a storage location outside of loadable portion 141, a flash translation layer (FTL) of memory subsystem 110 may determine a memory cell in nonvolatile memory 139 for the logical block address and service the storage access request by reading or programming the memory cell.

[0156] When a logical block address identifies a memory location within the loadable portion 141, the memory manager 101 may determine whether a portion of the memory cells in the non-volatile memory 139 addressed by the logical block address is represented by a page (e.g., 177) in the cache memory 157. If so, the memory subsystem 110 may service the memory request via the cache memory page (e.g., 177) and first memory for the remaining portion of the logical block address that is not represented by the page in the cache memory 157.

[0157] Figure 6 A computing system having a file system manager configured in a memory subsystem is shown according to one embodiment.

[0158] For example, Figure 6 The technology can be implemented in Figure 1 and Figure 2 In the computing system Figure 3 The memory subsystem 110 and optionally combined Figure 4 and Figure 5 technology to use.

[0159] exist Figure 6 In , the memory subsystem 110 is configured (eg, via firmware 153 ) with a file system manager 207 to operate a file system 201 in the memory subsystem 110 without assistance from an operating system 135 of the host system 120 .

[0160] As in Figures 2 to 5 middle, Figure 6 The memory subsystem 110 in allocates a portion of its memory resources for attachment to the host system 120 via connection 103 as a memory device that the host system 120 can access using a cache coherent memory access protocol 145 .

[0161] The host system 120 can access the file system 201 in the memory subsystem 110 by communicating with the file system manager 207 using the loadable portion 141 .

[0162] For example, host system 120 may use loadable portion 141 to provide a request to file system manager 207 ; and file system manager 207 may use loadable portion 141 to provide a response to host system 120 .

[0163] For example, the host system 120 can communicate with the file system manager 207 in the memory subsystem 110 using a Representational State Transfer (REST) ​​application programming interface (API), such as a Hypertext Transfer Protocol (HTTP) REST API (such as a Simple Storage Service (S3)), through a message channel configured in the loadable portion 141.

[0164] The file system manager 207 in the memory subsystem 110 is configured to manage the file system 201 to store file content 205. Files can be organized using metadata 203 (e.g., file name 211, file directory 213, file access attributes 217, file security settings 219, etc.). The structure and access control features of the file system 201 can be used to simplify collaboration across processes and systems.

[0165] The file system 201 may be installed at least partially in the non-volatile storage capacity 151 (eg, the readable portion 143 ) of the memory subsystem 110 that is accessible to the host system 120 over the connection 103 using the storage access protocol 147 .

[0166] Optionally, file system manager 207 may identify the storage location of file content 205 to host system 120 to allow host system 120 to access file content 205 over connection 103 using storage access protocol 147 .

[0167] Alternatively, or in combination, file system 201 may be installed at least partially in a memory space (eg, loadable portion 141 ) provided by memory subsystem 110 that is accessible to host system 120 over connection 103 using cache coherent memory access protocol 145 .

[0168] Optionally, file system manager 207 may identify the memory address of file content 205 to host system 120 to allow host system 120 to access file content 205 over connection 103 using cache coherent memory access protocol 147 .

[0169] Optionally, the memory subsystem 110 may configure a cache memory 157 in fast memory (e.g., volatile random access memory 138) for implementing the loadable portion 141. The file system manager 207 may cache a portion of the file content 205 actively used by the host system 120 in the cache memory 157 to allow the host system 120 to access the cached portion over the connection 103 using the cache coherent memory access protocol 147.

[0170] The file system manager 207 running in the memory subsystem 110 is configured to manage the creation and modification of various aspects of the metadata 203, such as file names 211, directories 213, access attributes 217, security settings 219, etc. In addition, the file system manager 207 in the memory subsystem 110 is configured to manage the storage locations 215 of files stored in the memory subsystem 110.

[0171] For example, a file with identification 202 in file system 201 may be stored in memory subsystem 110 (e.g., in loadable portion 141 or in readable portion 143). To store file content 205, file system manager 207 in memory subsystem 110 is configured to allocate storage resources (e.g., logical storage blocks) identified by one or more logical block addresses 195 for storing the file (e.g., file content). File system manager 207 may identify the logical block addresses 195 assigned to the file with identification 202 and update the file storage location 215 in metadata 203.

[0172] An application running in the host system 120 may request the operating system 135 to access a file in the file system 201. In response, the operating system 135 in the host system 120 may communicate with the file system manager 207 through a message channel configured in the loadable portion 141. For example, the operating system 135 may write a request message to the loadable portion 141 using the cache coherent memory access protocol 145 over the connection 103. In response, the file system manager 207 may generate a response from the file system 201 and write the response message to the loadable portion 141 using the local connection. Subsequently, the operating system 135 may retrieve the response message from the loadable portion 141 using the cache coherent memory access protocol 145 over the connection 103.

[0173] Optionally, the file system manager 207 is configured with a REST API that allows the operating system 135 to access the file system 201 through a message channel configured in the loadable portion 141, as shown in Figure 7 and Figure 8 middle.

[0174] Optionally, the file system manager 207 is configured to identify to the operating system 135 a mapping between a logically defined contiguous file space for a file having identification 202 referenced in an application and a memory area in the loadable portion 141 allocated to the file. Thus, the operating system 135 can use the memory address determined from the mapping and the cache coherent memory access protocol 145 to store data in the file space or load data from the file space over the connection 103, as in Figure 10 middle.

[0175] For example, the memory area allocated to the file from the loadable portion 141 may be a cache area allocated to the file; and the file system manager 207 may cache the file from its non-volatile storage capacity 151 and save changes to the file from the cache area to the non-volatile storage capacity 151.

[0176] For example, the memory area allocated to the file from the loadable portion 141 may be part of the non-volatile storage capacity 151. In order to optimize the performance of the host system 120 accessing the memory area, the memory subsystem 110 may be combined with Figures 3 to 5 Discuss the way to cache pages of memory area.

[0177] Optionally, the file system manager 207 is configured to identify to the operating system 135 a mapping between a contiguous file space logically defined for a file having identification 202 referenced in an application and a logical storage area in the readable portion 143 allocated to the file. Thus, the operating system 135 can write data to or read data from the file space over the connection 103 using the logical block addresses determined from the mapping and the storage access protocol 147, as in Figure 9 middle.

[0178] Optionally, the file content 205 may be stored in a loadable portion 141 implemented in a readable portion 143 of the memory subsystem 110, as in Figure 5 Therefore, based on the address mapping identified by the file system manager 207, the operating system 135 can choose to access the file space through the connection 103 using either memory addresses and the cache coherent memory access protocol 145 or logical block addresses and the storage access protocol 147.

[0179] File system manager 207 may manage file storage locations 215 of file content 205 in file system 201 as part of metadata 203. For example, locations in the logical file space may be implemented in storage locations with addresses that are independent of the file.

[0180] For example, a storage location in the memory subsystem 110 may be represented by a logical block address 195 (e.g., a logical block address located in the namespace of the storage capacity 151) that is configured to reference a predetermined-size block of storage space in the memory subsystem 110. The definition of the logical block address 195 is independent of the file and file system 201. The host system 120 may use the storage access queue 133 and the logical block address 195 to request the memory subsystem 110 to read content 205 from and write content 205 to a file over the connection 103 using the storage access protocol 147.

[0181] For example, a storage location in the memory subsystem 110 may be represented by a memory address 196 that is configured to reference a predetermined-sized region of memory space in the loadable portion 141 of the memory subsystem 110. The memory address 196 is defined independently of the file and file system 201. The host system 120 may use the memory address 196 to request the memory subsystem 110 to load content 205 from a file and store content 205 to a file over the connection 103 using the cache coherent memory access protocol 145.

[0182] When the storage resources allocated to the file represented by the identifier 202 change, the file system manager 207 in the memory subsystem 110 may be used to update the file storage location 215 of the file.

[0183] Optionally, the operating system 135 in the host system 120 and the file system manager 207 in the memory subsystem 110 may share the file storage location 215 via the loadable portion 141 to reduce communications performed via the application programming interface (API) of the file system manager 207 .

[0184] For example, at least a portion of metadata 203, including file storage location 215, may be configured in loadable portion 141 for access by both operating system 135 in host system 120 and file system manager 207 in memory subsystem 110. Operating system 135 may access file storage location 215 over connection 103 using cache coherent memory access protocol 145; and file system manager 207 may access file storage location 215 via a local connection within memory subsystem 110 without using connection 103.

[0185] For example, metadata 203 of file content 205 stored in memory subsystem 110 may be configured in loadable portion 141. Operating system 135 of host system 120 may read metadata 203 to use file system 201 without changing metadata 203; and file system manager 207 in memory subsystem 110 may be configured to make changes to metadata 203.

[0186] Figure 7 Techniques for storing files in a file system operated by a file system manager configured in a memory subsystem according to one embodiment are presented. For example, Figure 7 The technology can be implemented in Figure 6 computing system.

[0187] exist Figure 7 In the embodiment, one or more message queues 191 are configured in the loadable portion 141 of the memory subsystem 110 as a message channel between the host system 120 and the file system manager 207 running in the memory subsystem 110 .

[0188] To store a file in file system 201 (e.g., configured in readable portion 143 of memory subsystem 110), host system 120 may use cache coherent memory access protocol 145 to store a message in message queue 191 over connection 103. The message identifies a file publish request 192 containing content 197 of a file to be stored in file system 201.

[0189] The file system manager 207 may retrieve a message with a file publish request 192 from the message queue 191. In response, the file system manager 207 may update the metadata 203 of the file and store the content 197 of the file in the file system 201. The file system manager 207 may generate a message in the queue 191 to provide a file publish response 193. For example, the response 193 may be configured to provide an execution status 204 of the file publish request 192. The host system 120 may retrieve the file publish response 193 from the queue 191 over the connection 103 using the cache coherent memory access protocol 145.

[0190] Using the message queue 191, the host system 120 can retrieve files from the file system 201, such as Figure 8 middle.

[0191] Figure 8 A technique for retrieving files from a file system operated by a file system manager configured in a memory subsystem is presented according to one embodiment. For example, Figure 8 The technology can be implemented in Figure 6 computing system.

[0192] As in Figure 7 middle, Figure 8 One or more message queues 191 are configured in the loadable portion 141 in the memory subsystem 110 to provide a message channel between the host system 120 and the file system manager 207 running in the memory subsystem 110 .

[0193] To retrieve a file from file system 201 (e.g., configured in readable portion 143 of memory subsystem 110), host system 120 may store a message in message queue 191 over connection 103 using cache coherent memory access protocol 145. The message identifies a file get request 194 containing an identifier 198 of a file to be retrieved from file system 201.

[0194] For example, a file identifier 198 used to store a file in or retrieve a file from the file system 201 may include a uniform resource locator (URL) identifying a path to a directory 213 of the file in the file system 201 and a file name 211 of the file. The file system manager 207 may be configured to update the metadata 203 of the file system 201 to identify the file attributes (e.g., the file name 211, the path to the directory 213, the file storage location 215) and use the file identifier 198 and the metadata 203 to retrieve the content 205 of the file.

[0195] For example, the file system manager 207 may retrieve a message with a file get request 194 from the message queue 191. In response, the file system manager 207 may use the file identifier 198 and the metadata 203 to determine the file storage location 215 of the file and retrieve the content 197 of the file from the file system 201. The file system manager 207 may generate a message in the queue 191 to provide a file get response 199. For example, the response 199 may be configured to provide the file content 197 generated by executing the file get request 194. The host system 120 may retrieve the file get response 199 from the queue 191 over the connection 103 using the cache coherent memory access protocol 145.

[0196] Optionally, requests (eg, 192 , 194 ) and responses (eg, 193 , 199 ) may be configured according to a REST API implemented in the file system manager 207 .

[0197] Optionally, instead of Figure 7 and Figure 8 In addition to or in addition to receiving file content 197 via message queue 191 and providing an API for file content 197, file system manager 207 may implement an API that allows host system 120 to obtain a logical block address (e.g., 195) and / or a memory address (e.g., 196) of a file storage location 215, as in Figure 9 and Figure 10 The host system 120 may then use the logical block address (e.g., 195) and the storage access protocol 147 to write data to or read data from the storage space allocated to the file over the connection 103. Similarly, the host system 120 may then use the memory address (e.g., 196) and the cache coherent memory access protocol 145 to store or load data to or from the memory space allocated to the file over the connection 103.

[0198] Figure 9 and Figure 10 A technique for accessing the contents of a file in a file system operated by a file system manager configured in a memory subsystem is shown according to one embodiment. For example, Figure 9 and Figure 10 The technology can be implemented in Figure 6 computing system.

[0199] As in Figure 7 middle, Figure 9 and Figure 10 One or more message queues 191 are configured in the loadable portion 141 in the memory subsystem 110 to provide a message channel between the host system 120 and the file system manager 207 running in the memory subsystem 110 .

[0200] exist Figure 9 In , file system 201 is in readable portion 143 that host system 120 can access through connection 103 using storage access protocol 147 .

[0201] To access storage space allocated to a file having identifier 198 from readable portion 143 using read and write commands, host system 120 may store a message in message queue 191 over connection 103 using cache coherent memory access protocol 145. The message identifies a file storage request 221 containing identifier 198 of a file to be operated on by host system 120 via storage access protocol 147.

[0202] The file system manager 207 may retrieve a message with a file storage request 221 from the message queue 191. In response, the file system manager 207 may use the file identifier 198 and the metadata 203 to determine the file storage location 215 of the file and generate a message in the queue 191 to provide a file storage response 223. For example, the response 223 may be configured to identify a list of logical block addresses 195 of logical blocks assigned to form the readable portion 143 of the file space of the file. The host system 120 may retrieve the file storage response 223 from the queue 191 over the connection 103 using the cache coherent memory access protocol 145.

[0203] To access a portion of file content 197 of a file having file identifier 198, host system 120 may determine a logical block address 183 of the portion based on file storage response 223 and send a storage access request 181 for logical block address 183 to access over connection 103 using storage access protocol 147. For example, host system 120 may use a read command to read data from logical block address 183 or a write command to write data to logical block address 183.

[0204] Optionally, file storage request 221 may be configured to indicate an adjustment in the size of a file identified in file system 201 using file identifier 198. File system manager 207 may be configured to adjust metadata 203 in accordance with the adjustment to the storage space allocation for the file.

[0205] exist Figure 10 In the example, the file system 201 is in both the readable portion 143 and the loadable portion 141. Thus, the host system 120 may use a file storage request 221 to request the logical block address 195 of a file identified in the file system 201 using a file identifier 198, as in Figure 9Furthermore, because readable portion 143 is accessible by host system 120 over connection 103 using cache coherent memory access protocol 145 , host system 120 may use file memory request 225 to obtain a list of memory addresses 196 in loadable portion 141 occupied by files having identifier 198 in file system 201 .

[0206] To access memory space allocated to a file having identifier 198 from loadable portion 141 using load and store commands, host system 120 may store a message in message queue 191 over connection 103 using cache coherent memory access protocol 145. The message identifies a file memory request 225 containing identifier 198 of a file to be operated on by host system 120 via cache coherent memory access protocol 145.

[0207] The file system manager 207 may retrieve a message with a file storage request 225 from the message queue 191. In response, the file system manager 207 may use the file identifier 198 and the metadata 203 to determine the file storage location 215 of the file and generate a message in the queue 191 to provide a file storage response 227. For example, the response 223 may be configured to identify a list of memory addresses 196 in the loadable portion 141 of the file space that are assigned to form the file. The host system 120 may retrieve the file storage response 227 from the queue 191 over the connection 103 using the cache coherent memory access protocol 145.

[0208] To access a portion of file content 197 of a file having file identifier 198, host system 120 may determine a memory address 163 of the portion based on file memory response 227 and send a memory access request 161 for memory address 163 to access over connection 103 using cache coherent memory access protocol 145. For example, host system 120 may execute a load instruction to load data from memory address 163 or execute a store instruction to store data to memory address 163.

[0209] Optionally, file storage request 225 may be configured to indicate an adjustment in the size of a file identified in file system 201 using file identifier 198. File system manager 207 may be configured to adjust metadata 203 in accordance with the adjustment to the memory space allocation for the file.

[0210] Optionally, metadata 203 is configured in loadable portion 141 for sharing between operating system 135 in host system 120 and file system manager 207 in memory subsystem 110. Operating system 135 of the host system may optionally use metadata 203 to determine file storage locations 215; and file system manager 207 may control the assignment of file storage locations 215 to files.

[0211] Figure 11 A method for managing a file system via a memory subsystem according to one embodiment is shown. For example, Figure 11 The method can be used Figures 7 to 10 technology to implement Figure 1 、 Figure 2 and Figure 6 In the computing system Figure 3 Optionally, when the loadable portion 141 is implemented in non-volatile memory 139 which is slower than the volatile memory 138 of the memory subsystem 110, Figure 4 、 Figure 5 and Figure 6 The technology can be used with Figure 11 method together with .

[0212] At block 241, the method includes providing, by the memory subsystem 110, memory services in a memory space (e.g., the loadable portion 141) to the host system 120. The memory space is addressable by the host system 120 through a connection 103 from the host interface 113 of the memory subsystem 110 to the host system 120 using a memory address (e.g., 163) in a first protocol 145 for cache coherent memory access.

[0213] For example, connection 103 may be configured according to the Compute Express Link (CXL) standard.

[0214] For example, the memory subsystem 110 may be configured to allocate a portion of its volatile random access memory 138 as cache memory 157, a second portion of its volatile random access memory 138 as buffer memory 149, and optionally a third portion of its volatile random access memory 138 as part of a memory device that provides memory space, such as the loadable portion 141. The majority of the memory device, such as the loadable portion 141, may be configured in the nonvolatile storage capacity 151 provided by the nonvolatile memory 139 of the memory subsystem 110. The nonvolatile memory 139 is typically slower than the volatile random access memory 138.

[0215] At block 243, the method includes providing storage services in the storage space (e.g., readable portion 143) by memory subsystem 110 to host system 120. The storage space is addressable by host system 120 over connection 103 using logical block addresses (e.g., 183) in a second storage access protocol 147.

[0216] For example, the memory subsystem 110 may be configured to allocate a portion of its non-volatile memory 139 as part of a storage device that provides a storage space, such as the readable portion 143. Optionally, a portion of the non-volatile memory 139 is used to implement both the memory space and the storage space; and thus, the portion of the non-volatile memory 139 may be accessed in both the memory space and the storage space, such as in Figure 5 middle.

[0217] At block 245 , the method includes managing, by the memory subsystem 110 , the file system 201 configured within the memory subsystem 110 .

[0218] For example, firmware 153 of memory subsystem 110 may include a file system manager 207 configured to operate file system 201 without assistance from host system 120 .

[0219] For example, the file system manager 207 may be configured to create and modify metadata 203 for files in the file system 201 independently of the operating system 135 running in the host system 120 .

[0220] Optionally, metadata 203 may be stored in memory allocated to implement a memory space (eg, loadable portion 141 ) so that operating system 135 may also read and use metadata 203 by loading data from the memory space.

[0221] At block 247 , the method includes providing, by the memory subsystem 110 , an application programming interface for the host system 120 to access the file system 201 via the memory space (eg, the loadable portion).

[0222] For example, the memory subsystem 110 and the host system 120 may be configured to communicate via a message channel configured in a memory device attached by the memory subsystem 110 via connection 103 to provide a memory space (e.g., the loadable portion 141). Communication via the message channel may be in accordance with an application programming interface of the file system manager 207.

[0223] For example, the message channel may include one or more message queues 191 configured in the loadable portion 141. The host system 120 and the file system manager 207 may input request messages and response messages according to the application programming interface of the file system manager 207.

[0224] For example, the application programming interface can be configured according to the Representational State Transfer (REST) ​​architecture. Optionally, the application programming interface can be further configured based on the Hypertext Transfer Protocol (HTTP) standard. For example, the application programming interface can include the Simple Storage Service (S3) protocol.

[0225] At block 249, the method includes receiving a request according to an application programming interface (e.g., 192, 194, 221, or 225) in the memory subsystem 110 using the first protocol 145 for cache coherent memory access over the connection 103. The request may include an identifier 198 of a file in the file system 201 (e.g., including file content 197).

[0226] For example, a request (eg, 192, 194, 221, or 225) may be stored by the host system via connection 103 using the first cache coherent memory access protocol 145 to a message queue 191 configured in a memory space (eg, loadable portion 141).

[0227] At block 251 , the method includes generating, by the memory subsystem, a response (e.g., 193 , 199 , 223 , or 227 ) according to the application programming interface in response to the request (e.g., 192 , 194 , 221 , or 225 ). The response may contain data for a file with identifier 198 in file system 201 .

[0228] For example, a response (e.g., 193, 199, 223, or 227) may be entered into the message queue 191 by the file system manager 207 using a local connection within the memory subsystem 110 rather than using the connection 103 to the host system 120. The host system 120 may load the response (e.g., 193, 199, 223, or 227) by executing a load instruction to access the message queue 191 through the connection 103 using the first protocol 145 for cache coherent memory access.

[0229] For example, when a request (eg, 194 ) is configured to obtain a file having a file identifier 198 , the data provided in a response (eg, 199 ) may include the contents 197 of the file in the file system 201 .

[0230] For example, the data provided in the response (e.g., 193) may include the execution status 204 of the request (e.g., 192). For example, when the request 192 is configured to publish a file to the file system 201, the request 192 may include the content 197 of the file having the file identifier 198.

[0231] For example, the data provided in the response (e.g., 227) may include one or more memory addresses (e.g., 196) configured to identify one or more memory regions assigned to the file from the memory space (e.g., loadable portion 141) to host the file's content 197. Using the memory addresses (e.g., 196) of the file in the loadable portion 141, the host system 120 can retrieve any portion of the file's content 197 by executing one or more load instructions. In response, the memory subsystem 110 may receive a memory access request 161 with the memory address 163 identified by the response (e.g., 227) from the host system 120 over the connection 103 using the first protocol 145 for cache-coherent memory access. The memory access request 161 may be executed in the memory subsystem 110 without the assistance of the file system manager 207. Processing of the memory access request 161 may cause the memory subsystem 110 to load a portion of the file's content 197 from the memory space (e.g., loadable portion 141). Similarly, host system 120 may execute one or more storage instructions to modify file content 197 at a memory address (e.g., 163) identified via response (e.g., 227). Using a memory address (e.g., 163) to retrieve and / or modify a small portion of file content 197 may be more efficient than operating on the file content over connection 103 via storage access protocol 147.

[0232] Optionally, or in combination, the data provided in the response (e.g., 223) may include one or more logical block addresses (e.g., 195) configured to identify one or more logical blocks assigned to the file from the storage space (e.g., readable portion 143) to host the file's content 197. Using the logical block addresses (e.g., 195) of the file in the readable portion 143, the host system 120 can retrieve any block of the file's content 197 by inputting one or more read commands into the storage access queue 133 (e.g., configured in the memory 129 of the host system 120). The memory subsystem 110 can retrieve the storage access request 181 from the storage access queue 133 from the host system 120 via the connection 103 using the second storage access protocol 147. The storage access request 181 can be configured with the logical block address 183 identified by the response (e.g., 223). The read command in the storage access request 181 can be executed in the memory subsystem 110 without the assistance of the file system manager 207. Processing of the storage access request 161 may cause the memory subsystem 110 to read a portion of the file's content 197 from the storage space (e.g., the readable portion 143). Similarly, the host system 120 may input one or more write commands into the storage access queue 133 to modify the file content 197 at the logical block address (e.g., 183) identified by the response (e.g., 223). In some scenarios, accessing the file via the storage access protocol 147 is more efficient and / or convenient.

[0233] Optionally, the data provided from the response (e.g., 223 or 227) can be configured to identify an address in a memory space (e.g., loadable portion 141) where metadata 203 for a file in file system 201 is stored. Metadata 203 can include a file storage location 215 for the file; and host system 120 can retrieve file storage location 215 using the address provided in the response (e.g., 223 or 227).

[0234] Optionally, the memory subsystem 110 and the host system 120 can be configured to share access to the metadata 203 of the file system 201 in the memory subsystem 110 via the loadable portion 141. Thus, the operating system 135 can be configured to load the metadata 203 from the loadable portion 141 to identify the file storage location 215 of the file without the assistance of the file system manager 207.

[0235] In general, the memory subsystem 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0236] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a portion of a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0237] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0238] For example, host system 120 may include a processor chipset (e.g., processing device 127) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches (e.g., 123), a memory controller (e.g., controller 125) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0239] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface 113. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, a Compute Express Link (CXL) interface, or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 109). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0240] The processing device 127 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller 125 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 125 controls communications via a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 125 may send commands or requests to the memory subsystem 110 to access the memory devices 109, 107. The controller 125 may further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry may convert responses received from the memory subsystem 110 into information for the host system 120.

[0241] The controller 125 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading, writing, or erasing data at the memory devices 109, 107, and other such operations. In some examples, the controller 125 is integrated into the same package as the processing device 127. In other examples, the controller 125 is separate from the package of the processing device 127. The controller 125 and / or the processing device 127 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 125 and / or the processing device 127 may be a microcontroller, dedicated logic circuitry (such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0242] Memory devices 109, 107 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices, such as memory device 107, may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0243] Some examples of nonvolatile memory devices include NAND (or NOT AND) flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. Cross-point nonvolatile memory arrays can perform bit storage based on bulk resistance changes in conjunction with a stacked cross-grid data access array. In addition, compared to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0244] Each of the memory devices 109 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and quintuple-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 109 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory devices 109 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. With some types of memory, such as NAND, pages may be grouped to form blocks.

[0245] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 109 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0246] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 109 to perform operations such as reading data, writing data, or erasing data at the memory device 109 and other such operations (e.g., in response to commands dispatched by the controller 125 on a command bus). The controller 115 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0247] The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0248] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG has been described as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0249] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 109. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 109. The controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 109, and also convert responses associated with the memory device 109 into information for the host system 120.

[0250] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 109.

[0251] In some embodiments, memory device 109 includes a local media controller 137 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 109. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 109 (e.g., perform media management operations on memory device 109). In some embodiments, memory device 109 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 137) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0252] In one embodiment, a computer system is an example machine in which a set of instructions for causing a machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 Memory subsystem 110) or may be used to perform the operations discussed above (e.g., execute instructions to perform operations corresponding to reference Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0253] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, a network attached storage facility, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0254] An example computer system includes a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM)), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0255] The term "processing device" refers to one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a combination of instruction sets. The processing device may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating over a network.

[0256] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The instructions may also reside completely or at least partially within the main memory and the processing device during their execution by the computer system, the main memory and the processing device also constituting machine-readable storage media. The machine-readable medium, data storage system, and / or main memory may correspond to Figure 1 Memory subsystem 110.

[0257] In one embodiment, the instructions include instructions for implementing the functionality discussed above (e.g., referring to Figure 1 Although the machine-readable medium is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that is capable of storing or encoding a set of instructions that is executed by a machine and causes the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should accordingly be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0258] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0259] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0260] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0261] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structures of various such systems will appear as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0262] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0263] In this description, various functions and operations are described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such expressions mean that the functions are generated by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively, or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using hard-wired circuitry without or in combination with software instructions. Thus, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0264] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are accordingly to be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: providing, by a memory subsystem to a host system, memory services in a memory space addressable using memory addresses in a first protocol for cache coherent memory accesses over a connection from a host interface of the memory subsystem to the host system; providing, by the memory subsystem, to the host system, storage services in a storage space addressable via the connection using a logical block address in a second storage access protocol; The memory subsystem manages a file system configured in the memory subsystem; The memory subsystem provides an application programming interface for the host system to access the file system via the memory space; receiving, in the memory subsystem, over the connection, a request according to the application programming interface using the first protocol for cache coherent memory access, the request having an identifier of a file in the file system; and The memory subsystem generates a response according to the application programming interface in response to the request, the response containing data of the file in the file system.

2. The method of claim 1, wherein the connection is in accordance with the Compute Express Link (CXL) standard.

3. The method of claim 2 , wherein the request is stored by the host system into the memory space over the connection using the first protocol for cache coherent memory access; and the response is provided in the memory space for loading by the host system over the connection using the first protocol for cache coherent memory access.

4. The method according to claim 3, further comprising: One or more message queues are configured in the memory space, wherein the request is input into the one or more message queues by the host system, and the response is input into the one or more message queues by the memory subsystem. The method of claim 4 , wherein the data comprises contents of the file in the file system.

6. The method of claim 4, wherein the data comprises one or more memory addresses configured to identify one or more memory areas assigned from the memory space to the file to host content of the file.

7. The method according to claim 6, further comprising: receiving, in the memory subsystem, a memory access request having a memory address identified via the response from the host system over the connection using the first protocol for cache coherent memory access; and The memory access request is processed by the memory subsystem to store a portion of the content of the file into the memory space or to load a portion of the content of the file from the memory space.

8. The method of claim 4, wherein the data comprises one or more logical block addresses configured to identify one or more logical blocks assigned from the storage space to the file to host content of the file.

9. The method according to claim 8, further comprising: Retrieving, by the memory subsystem, a storage access command from a storage access queue configured in a memory of the host system over the connection using the second storage access protocol, the storage access command having a logical block address identified by the response; and The storage access command is processed by the memory subsystem to read a portion of the content of the file from the storage space or write a portion of the content of the file to the storage space.

10. The method of claim 4, wherein the data is configured to identify an address in the memory space where metadata for the file in the file system is stored.

11. A memory subsystem comprising: a host interface capable of operating in connection with a host system according to a storage access protocol and a cache coherent memory access protocol; a first memory configured to provide non-volatile storage capacity of the memory subsystem, wherein at least a portion of the first memory is configured to implement a memory device attached to the host system via the connection; a second memory that is faster than said first memory; and A controller is configured to run a file system manager to operate a file system in the memory device.

12. The memory subsystem of claim 11 , wherein the controller is further configured to: An application programming interface according to the file system manager communicates with the host system via a message channel configured in the memory device.

13. The memory subsystem of claim 12, wherein the application programming interface is a Representational State Transfer (REST) ​​architecture.

14. The memory subsystem of claim 13, wherein the application programming interface is a standard further based on the Hypertext Transfer Protocol.

15. The memory subsystem of claim 12, wherein the controller is configured to share metadata of the file system with the host system through the memory device.

16. The memory subsystem of claim 15 , wherein data stored in the memory device is accessible by the host system over the connection both using the storage access protocol and the cache coherent memory access protocol; and the connection is a Compute Express link connection.

17. A non-transitory computer storage medium storing instructions that, when executed in a computing system, cause the computing system to perform a method comprising: establishing a connection between the host system and the memory subsystem, the connection being operable according to a storage access protocol and a cache coherent memory access protocol; attaching a portion of memory resources of the memory subsystem to the host system through the connection as a memory device accessible by the host system through the connection via the cache coherent memory access protocol; Running a file system manager in the memory subsystem to operate a file system hosted in the memory subsystem; and Communication is performed between the memory subsystem and the host system via the memory device to provide the host system with access to files in the file system.

18. The non-transitory computer storage medium of claim 17, wherein the method further comprises: attaching the portion of the memory resources of the memory subsystem to the host system through the connection as a storage device accessible by the host system through the connection via the storage access protocol; wherein the file is accessible in both the memory device and the storage device.

19. The non-transitory computer storage medium of claim 18, wherein the method further comprises: operating a message channel between an operating system running in the host system and the file system manager running in the memory subsystem via the memory device; The communication is via the message channel.

20. The non-transitory computer storage medium of claim 19, wherein the message channel is in accordance with a Hypertext Transfer Protocol (HTTP) Representational State Transfer (REST) ​​Application Programming Interface (API).

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