IC support plate test method and system

Abstract

The invention discloses an IC support plate test method and system, mainly relates to the technical field of IC support plates, and is used for solving the problems of single detection dimension, insufficient positioning precision and low test efficiency in the existing scheme. Comprising the following steps: screening out a test point whose contact resistance value exceeds a threshold value or is not conducted as a detection object; a TDR time domain reflectometer is adopted to carry out impedance testing under the frequency band of 1GHz, and an impedance abnormal area is identified; monitoring the temperature distribution of the IC carrier plate, and obtaining a monitoring temperature point exceeding a preset temperature; determining a monitoring temperature point overlapped with the detection object or the impedance abnormal area as a heat conduction abnormal point between the multiple layers of lines, and recording temperature gradient data of the heat conduction abnormal point; carrying out preset micro stress loading on the IC carrier plate by adopting a preset torque; comparing the resistance value change rate of the IC carrier plate before and after the stress is applied, and determining the defect type of the carrier plate according to the specific preset defect interval in which the resistance value change rate falls.

Description

Technical Field

[0001] The present application relates to the field of IC substrate technology, and in particular to an IC substrate testing method and system. Background Art

[0002] Existing IC substrate electrical performance testing techniques primarily involve manual or semi-automatic probe stations performing point-by-point contact testing on substrate pads, and measuring line resistance with a multimeter to identify open or short circuit defects. Impedance testing relies on a vector network analyzer (VNA) to collect S-parameters (such as S11 and S21), and frequency-domain analysis to assess transmission line characteristic impedance matching and signal attenuation.

[0003] However, existing technologies have the following defects: First, the detection dimension is single and can only reflect static electrical performance, but cannot identify thermal-mechanical coupling defects under dynamic working conditions (such as abnormal temperature rise caused by microcracks); second, the positioning accuracy is insufficient, and traditional VNA testing cannot associate impedance anomalies with specific physical defects (such as interlayer micro-shorts); third, the test efficiency is low, with manual intervention accounting for more than 60%, and there is a lack of intelligent determination mechanism for defect types. Summary of the Invention

[0004] The present application provides an IC substrate testing method and system to solve the problems of the existing solutions such as single detection dimension, insufficient positioning accuracy and low testing efficiency.

[0005] In a first aspect, the present application provides an IC substrate testing method, the method comprising: Conduct continuity testing on all pads on the IC substrate, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding the threshold or not conducting as test objects; Based on the node coordinates of the test object, a TDR time domain reflectometer is used to perform impedance testing at a frequency of 1 GHz to identify areas with abnormal impedance. These areas are line sections with pre-set micro-shorts or pre-set open circuits. Apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC substrate, and obtain the monitoring temperature point that exceeds the preset temperature; Determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; determine that the monitoring temperature point that coincides with the detection object or the impedance abnormal area is a heat conduction abnormal point between the multi-layer lines, and record the temperature gradient data of the heat conduction abnormal point; When the temperature gradient data falls into a preset abnormal range, a preset microstress is applied to the IC substrate using a preset torque. The resistance change rate of the IC substrate before and after the stress is applied is compared, and the type of defect in the substrate is determined based on the specific preset defect range in which the resistance change rate falls.

[0006] In one implementation of the present application, a continuity test is performed on all pads of the IC substrate, the contact resistance value of each test point is recorded, and test points with contact resistance values ​​exceeding a threshold or not conducting are selected as test objects, specifically including: Use a four-wire resistance tester to connect to the test points on the IC substrate; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

[0007] In one implementation of the present application, based on the node coordinates of the detection object, a TDR time domain reflectometer is used to perform impedance testing in the 1 GHz frequency band to identify the impedance abnormality area, specifically including: Use TDR time domain reflectometer to connect to IC carrier board; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

[0008] In one implementation of the present application, a preset constant current load is applied to the impedance abnormality area, the temperature distribution of the IC substrate is monitored, and a monitoring temperature point exceeding the preset temperature is obtained, specifically including: Build the constant current source circuit corresponding to the IC carrier board; Determine the specific test current corresponding to the preset constant current load based on the IC substrate specifications; Use infrared thermal imager to monitor IC substrate; Set the temperature threshold to a preset temperature and obtain the monitoring temperature point on the IC substrate that exceeds the preset temperature.

[0009] In one implementation of the present application, when the temperature gradient data falls within a preset abnormal range, a preset microstress is applied to the IC substrate using a preset torque; before comparing the resistance change rate of the IC substrate before and after the stress application, and determining the defect type of the substrate based on the specific preset defect range within which the resistance change rate falls, the method further includes: Through the preset interface, obtain the corresponding relationship between the preset abnormal interval, specific preset defect interval and defect type.

[0010] In one implementation of the present application, a preset microstress is applied to an IC carrier using a preset torque. The resistance change rate of the IC carrier before and after the stress is applied is compared, and the type of defect present in the carrier is determined based on the specific preset defect interval within which the resistance change rate falls. Specifically, the following types of defects are determined: The torque range of the six-axis micro-force loading platform is 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

[0011] In a second aspect, the present application provides an IC substrate testing system, the system comprising: The continuity detection module is used to perform continuity detection on all pads of the IC substrate, record the contact resistance value of each test point, and select the test points with contact resistance values ​​exceeding the threshold or not conducting as the detection objects; An identification module is used to perform impedance testing using a TDR time domain reflectometer at a frequency of 1 GHz based on the node coordinates of the detection object to identify areas with abnormal impedance. These areas are line sections with pre-set micro-short circuits or pre-set open circuit defects. An acquisition module is used to apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC carrier board, and obtain a monitoring temperature point that exceeds the preset temperature; The heat transfer module is used to determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; determine the monitoring temperature point that coincides with the detection object or the impedance abnormal area as the heat conduction abnormal point between the multi-layer circuits, and record the temperature gradient data of the heat conduction abnormal point; The determination module is used to apply a preset microstress to the IC substrate using a preset torque when the temperature gradient data falls into a preset abnormal range; compare the resistance value change rate of the IC substrate before and after the stress is applied, and determine the defect type of the substrate based on the specific preset defect range in which the resistance value change rate falls.

[0012] In one implementation of the present application, the conduction detection module includes a conduction detection unit, Used to connect IC carrier board test points using a four-wire resistance tester; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

[0013] In one implementation of the present application, the heat transfer module includes an abnormality detection unit. Used to connect IC carrier board using TDR time domain reflectometer; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

[0014] In one implementation of the present application, the determination module includes a determination unit, Used for six-axis micro-force loading platform with a torque range of 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

[0015] It can be seen from the above technical solutions that this application has the following advantages: By introducing temperature distribution monitoring and microstress loading testing under a constant current load, dynamic capture of thermal-mechanical coupling defects is achieved. This method can simultaneously detect abnormal temperature rises and resistance changes caused by defects such as microcracks and interlayer delamination, breaking through the limitations of traditional static electrical testing and improving the detection rate of hidden defects.

[0016] Combining TDR (Time Domain Reflectometry) impedance testing with temperature gradient data, a three-dimensional correlation model was established between the impedance anomaly area, the test object, and the thermal conductivity anomaly point. Through a coordinate coincidence determination mechanism, the specific circuit layer and physical location of the defect can be pinpointed, improving defect location accuracy.

[0017] The automated serial inspection process eliminates manual intervention. Through a pre-set defect interval determination mechanism, the system can autonomously complete the entire analysis process, from anomaly detection to type determination. This shortens single-board testing time and avoids the risk of human misjudgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for the description. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is a flow chart of an IC substrate testing method provided in an embodiment of the present application.

[0020] Figure 2 This is a schematic diagram of the internal structure of an IC substrate testing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] It should be understood by those skilled in the art that the embodiments described below are merely preferred embodiments of the present disclosure and do not imply that the present disclosure can only be implemented through these preferred embodiments. These preferred embodiments are merely intended to explain the technical principles of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Based on the preferred embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present disclosure.

[0023] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0024] The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] The embodiment provides an IC substrate testing method, such as Figure 1 As shown, the method provided in the embodiment of the present application mainly includes the following steps: Step 110 , performing a continuity test on all pads of the IC substrate, recording the contact resistance value of each test point, and selecting test points with contact resistance values ​​exceeding a threshold or not conducting as test objects.

[0026] In some embodiments, this step may specifically include: Use a four-wire resistance tester to connect to the test points on the IC substrate; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

[0027] As you can see, this step evaluates the quality of IC substrate pads through a systematic continuity testing process. First, by quantifying contact resistance (rather than simply determining continuity), potential defects such as oxidation and cold solder joints can be detected early. Second, a threshold screening mechanism automatically locates pads requiring repair, improving repair efficiency. Finally, standardized test parameter settings (such as current intensity and sampling rate) ensure repeatable test results.

[0028] Step 120: Based on the node coordinates of the detection object, an impedance test is performed using a TDR time domain reflectometer in a 1 GHz frequency band to identify an impedance abnormality area.

[0029] The impedance abnormality area is a line section where a preset micro-short circuit or preset open circuit defect exists.

[0030] In some embodiments, this step may specifically include: Use TDR time domain reflectometer to connect to IC carrier board; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

[0031] It can be understood that this step first uses a TDR time domain reflectometer to perform impedance testing at a frequency band of 1 GHz, which can effectively identify micro short circuits or open circuit defects in the line. The 1 GHz test frequency band and the rise time configuration of ≤35ps ensure the ability to sensitively capture tiny impedance changes in the high-frequency signal transmission path, thereby improving the accuracy of defect detection. Secondly, the introduction of the automatic calibration program eliminates the influence of the test cable on the measurement results, reduces human operation errors, and makes the test data more reliable and consistent. In addition, the automatic identification of impedance abnormality areas through preset waveform analysis software simplifies the data analysis process and improves detection efficiency. Overall, this method combines hardware configuration and software analysis to achieve efficient and accurate detection of IC substrate circuit defects, providing a reliable basis for subsequent fault location and repair.

[0032] Step 130: Apply a preset constant current load to the impedance abnormality area, monitor the temperature distribution of the IC carrier, and obtain a monitoring temperature point that exceeds the preset temperature.

[0033] In some embodiments, this step may specifically include: Build the constant current source circuit corresponding to the IC carrier board; Determine the specific test current corresponding to the preset constant current load based on the IC substrate specifications; Use infrared thermal imager to monitor IC substrate; Set the temperature threshold to a preset temperature and obtain the monitoring temperature point on the IC substrate that exceeds the preset temperature.

[0034] It can be understood that this step can simulate the current load of the IC carrier under actual working conditions by applying a preset constant current load, thereby truly reflecting the thermal effect characteristics of the impedance abnormality area. The introduction of a preset constant current load ensures the controllability and repeatability of the test conditions, making the monitoring results more reliable. Secondly, the use of an infrared thermal imager to monitor the temperature distribution of the IC carrier can capture the temperature changes of the entire carrier in a non-contact and high-resolution manner, avoiding the interference that may be introduced by traditional temperature measurement methods. The setting of the temperature threshold makes it possible to quickly identify the monitoring temperature points that exceed the preset temperature, providing a clear positioning basis for subsequent fault analysis and repair. In addition, the solution combines a constant current source circuit and infrared thermal imaging technology to achieve a comprehensive evaluation of the thermal performance of the IC carrier, which helps to detect potential thermal failure risks early, thereby improving the reliability and service life of the product.

[0035] Step 140: Determine whether the monitoring temperature point coincides with the detection object or the impedance abnormality area; determine that the monitoring temperature point coincides with the detection object or the impedance abnormality area is a heat conduction abnormality point between the multi-layer circuits, and record the temperature gradient data of the heat conduction abnormality point.

[0036] It can be understood that this step can locate the thermal conduction anomaly points between multi-layer circuits by determining whether the monitored temperature point coincides with the detection object and the impedance anomaly area, thereby effectively correlating the temperature monitoring results with the impedance test data, thereby improving the accuracy of fault diagnosis. Secondly, recording the temperature gradient data of the thermal conduction anomaly point can quantify the thermal distribution characteristics of the area, providing an objective basis for analyzing the severity and diffusion range of the thermal conduction anomaly. In addition, by combining impedance anomaly identification with temperature monitoring, this method realizes cross-dimensional analysis from electrical performance to thermal performance, which helps to deeply understand the impact mechanism of defects on the overall performance of IC substrates. Overall, through multi-parameter correlation analysis, comprehensive data support is provided for failure analysis and reliability assessment of IC substrates, which helps to optimize design and improve product quality.

[0037] Step 150: When the temperature gradient data falls within a preset abnormal range, a preset microstress is applied to the IC substrate using a preset torque; the resistance change rate of the IC substrate before and after the stress application is compared, and the defect type of the substrate is determined based on the specific preset defect range within which the resistance change rate falls.

[0038] When the temperature gradient data falls within a preset abnormal range, a preset microstress is applied to the IC substrate using a preset torque; before comparing the resistance change rate of the IC substrate before and after the stress application, and determining the defect type of the substrate based on the specific preset defect range within which the resistance change rate falls, the method further includes: Through the preset interface, obtain the corresponding relationship between the preset abnormal interval, specific preset defect interval and defect type.

[0039] In some embodiments, this step may specifically include: The torque range of the six-axis micro-force loading platform is 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

[0040] It can be understood that this step obtains the correspondence between the abnormal interval, defect interval and defect type through the preset interface, which unifies the test standards, reduces the subjectivity of human judgment, and improves the accuracy of defect classification. Secondly, a six-axis micro-force loading platform is used to apply a torque of 0.8N·m at the thermal conduction abnormal point and maintain it for 30 seconds, which can simulate the micro-stress environment in actual use, thereby effectively stimulating potential defects and making them appear in the change of resistance value. The resistance value is measured three times before and after stress loading by a multimeter to ensure the reliability and repeatability of the data. In addition, according to the specific preset defect interval (such as cold solder joint, microcracks, and delamination defects) that the resistance value change rate falls into, the defect type of the IC substrate can be accurately identified, providing a clear basis for subsequent maintenance and quality control. Overall, by combining temperature gradient monitoring, micro-stress loading and resistance change analysis, multi-dimensional diagnosis of IC substrate defects is achieved, which helps to improve the reliability and service life of the product.

[0041] As described above, this embodiment uses a four-wire resistance tester combined with a grid scanning method to systematically test the continuity of IC substrate pads. This method quantifies contact resistance rather than simply determining continuity. Standardized test parameters (such as test current and sampling rate) ensure repeatable test results. A threshold screening mechanism automatically flags pads that exceed the threshold or are not conductive, helping to quickly locate potential defects such as oxidation and cold solder joints, improving repair efficiency. This provides an accurate initial data foundation for subsequent defect analysis.

[0042] Impedance testing using a TDR time-domain reflectometer at 1 GHz, combined with an automated calibration routine and pre-set waveform analysis software, effectively detects micro-shorts and opens in circuits. High-frequency signal testing (rise time ≤ 35 ps) enhances sensitivity to minute impedance variations, while automated calibration reduces errors introduced by test cables. This improves defect location accuracy and provides reliable impedance anomaly data for subsequent thermal performance analysis.

[0043] By simulating actual operating conditions with a constant current source and monitoring temperature distribution with an infrared thermal imager, the thermal effects of areas with abnormal impedance can be accurately identified. Setting temperature thresholds allows for rapid location of hotspots, and overlaying temperature data with abnormal impedance areas further identifies thermal conductivity anomalies between multi-layer circuits. Recording temperature gradient data helps quantify thermal distribution characteristics, providing a basis for defect severity assessment. This enables correlation analysis between electrical and thermal performance, enhancing the comprehensiveness of fault diagnosis.

[0044] Microstress (e.g., 0.8 N·m torque) is applied to areas with abnormal temperature gradients. By comparing the rate of change in resistance before and after stress loading and combining this with pre-defined defect categories (solder joints, microcracks, and delamination), the carrier board defect type can be accurately identified. The six-axis micro-force loading platform simulates actual stress environments to stimulate potential defects, while multiple resistance measurements (three times) ensure data reliability. Standardized defect classification logic reduces subjective judgment errors and provides a clear basis for repair decisions.

[0045] Through a multi-step collaborative analysis process (continuity testing, impedance testing, temperature monitoring, and microstress testing), cross-dimensional defect diagnosis is achieved, encompassing electrical, thermal, and mechanical properties. Standardized test parameters, an automated analysis process, and multi-parameter correlation verification enhance the accuracy and reliability of test results. This method not only locates existing defects but also predicts potential failure risks through thermal conductivity analysis and microstress testing, helping to optimize IC substrate design and manufacturing processes, thereby improving long-term product reliability.

[0046] In addition, this application Figure 2 An IC substrate testing system is provided in an embodiment of the present application. Figure 2 As shown, the system provided in the embodiment of the present application mainly includes: The continuity detection module 210 is used to perform continuity detection on all pads of the IC carrier, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding a threshold or not conducting as detection objects.

[0047] The conduction detection module 210 includes a conduction detection unit, Used to connect IC carrier board test points using a four-wire resistance tester; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

[0048] The identification module 220 is used to perform impedance testing in the 1 GHz frequency band using a TDR time domain reflectometer based on the node coordinates of the detection object to identify an impedance abnormality area; wherein the impedance abnormality area is a line segment with a preset micro short circuit or preset open circuit defect.

[0049] The acquisition module 230 is used to apply a preset constant current load to the impedance abnormality area, monitor the temperature distribution of the IC carrier, and obtain a monitoring temperature point that exceeds a preset temperature.

[0050] The heat transfer module 240 is used to determine whether the monitoring temperature point coincides with the detection object or the impedance abnormality area; determine the monitoring temperature point that coincides with the detection object or the impedance abnormality area as a heat conduction abnormality point between multi-layer circuits, and record the temperature gradient data of the heat conduction abnormality point.

[0051] The heat transfer module 240 includes an abnormality detection unit, Used to connect IC carrier board using TDR time domain reflectometer; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

[0052] Determination module 250 is configured to apply a preset microstress to the IC substrate using a preset torque when the temperature gradient data falls within a preset abnormal range; compare the resistance change rate of the IC substrate before and after the stress is applied, and determine the type of defect in the substrate based on the specific preset defect range within which the resistance change rate falls.

[0053] The determination module 250 includes a determination unit, Used for six-axis micro-force loading platform with a torque range of 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

[0054] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing an IC substrate, characterized in that: The method comprises: Conduct continuity testing on all pads on the IC substrate, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding the threshold or not conducting as test objects; Based on the node coordinates of the test object, a TDR time domain reflectometer is used to perform impedance testing at a frequency of 1 GHz to identify areas with abnormal impedance. These areas are line sections with pre-set micro-shorts or pre-set open circuits. Apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC substrate, and obtain the monitoring temperature point that exceeds the preset temperature; Determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; determine that the monitoring temperature point that coincides with the detection object or the impedance abnormal area is a heat conduction abnormal point between the multi-layer lines, and record the temperature gradient data of the heat conduction abnormal point; When the temperature gradient data falls into a preset abnormal range, a preset microstress is applied to the IC substrate using a preset torque. The resistance change rate of the IC substrate before and after the stress is applied is compared, and the type of defect in the substrate is determined based on the specific preset defect range in which the resistance change rate falls.

2. The IC substrate testing method according to claim 1, wherein: Conduct continuity testing on all pads on the IC substrate, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding the threshold or not conducting as test objects. Specifically, the following are included: Use a four-wire resistance tester to connect to the test points on the IC substrate; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

3. The IC substrate testing method according to claim 1, wherein: Based on the node coordinates of the test object, a TDR time domain reflectometer is used to perform impedance testing at a frequency of 1 GHz to identify areas with abnormal impedance. Specifically, the following are performed: Use TDR time domain reflectometer to connect to IC carrier board; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

4. The IC substrate testing method according to claim 1, wherein: Apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC substrate, and obtain the monitoring temperature point that exceeds the preset temperature. Specifically, the following are included: Build the constant current source circuit corresponding to the IC carrier board; Determine the specific test current corresponding to the preset constant current load based on the IC substrate specifications; Use infrared thermal imager to monitor IC substrate; Set the temperature threshold to a preset temperature and obtain the monitoring temperature point on the IC substrate that exceeds the preset temperature.

5. The IC substrate testing method according to claim 1, wherein: When the temperature gradient data falls into a preset abnormal range, a preset micro-stress loading is applied to the IC carrier board using a preset torque; Before comparing the resistance change rates of the IC substrate before and after stress application and determining the defect type of the substrate based on the specific preset defect interval within which the resistance change rate falls, the method further includes: Through the preset interface, obtain the corresponding relationship between the preset abnormal interval, specific preset defect interval and defect type.

6. The IC substrate testing method according to claim 1, wherein: Apply preset micro-stress loading to the IC carrier board using a preset torque; Compare the resistance change rate of the IC substrate before and after stress application. Determine the type of defect in the substrate based on the specific preset defect range within which the resistance change rate falls. Specifically, the defect type includes: The torque range of the six-axis micro-force loading platform is 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

7. An IC substrate testing system, characterized in that: The system comprises: The continuity detection module is used to perform continuity detection on all pads of the IC substrate, record the contact resistance value of each test point, and select the test points with contact resistance values ​​exceeding the threshold or not conducting as the detection objects; An identification module is used to perform impedance testing using a TDR time domain reflectometer at a frequency of 1 GHz based on the node coordinates of the detection object to identify areas with abnormal impedance. These areas are line sections with pre-set micro-short circuits or pre-set open circuit defects. An acquisition module is used to apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC carrier board, and obtain a monitoring temperature point that exceeds the preset temperature; The heat transfer module is used to determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; determine the monitoring temperature point that coincides with the detection object or the impedance abnormal area as the heat conduction abnormal point between the multi-layer circuits, and record the temperature gradient data of the heat conduction abnormal point; The determination module is used to apply a preset microstress to the IC substrate using a preset torque when the temperature gradient data falls into a preset abnormal range; compare the resistance value change rate of the IC substrate before and after the stress is applied, and determine the defect type of the substrate based on the specific preset defect range in which the resistance value change rate falls.

8. The IC substrate testing system according to claim 7, wherein: The conduction detection module includes a conduction detection unit, Used to connect IC carrier board test points using a four-wire resistance tester; Setting test parameters; wherein the test parameters include at least: test current and sampling rate; Use the grid scanning method to traverse all pads and record the contact resistance value of each test point; Mark the test points that exceed the threshold or are not conducting as detection objects.

9. The IC substrate testing system according to claim 7, wherein: The heat transfer module includes an anomaly detection unit, Used to connect IC carrier board using TDR time domain reflectometer; Configure the test frequency band to 1 GHz, with a rise time of ≤ 35 ps; Use automatic calibration procedure to eliminate the influence of test cables; Identify abnormal impedance areas using preset waveform analysis software.

10. The IC substrate testing system according to claim 7, wherein: The determination module includes a determination unit, Used for six-axis micro-force loading platform with a torque range of 0-5N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and maintain it for 30 seconds; Use a multimeter to measure the resistance of the IC substrate three times before and after stress loading. When the change rate is less than the first preset percentage, it is determined to be a cold weld; When the first preset percentage ≤ the change rate ≤ the second preset percentage, it is determined to be a microcrack; When the change rate is greater than the second preset percentage, it is determined to be a delamination defect.

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