Single instruction stream multi-thread microarchitecture

Abstract

The invention provides a single instruction stream multi-fiber micro-architecture. The micro-architecture comprises a fiber front end and an execution rear end, the fiber thread front end comprises a first instruction cache component, an instruction fetching component, a decoding component, a second instruction cache component, a scoreboard component, an instruction transmitting component and a fiber thread stack; the execution back end includes an operand collection component and an instruction processing unit. According to the single-instruction-stream multi-fiber-thread micro-architecture, concurrent execution of asynchronous data streams is achieved, the resource utilization rate is effectively increased, and redundant calculation is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of data flow architecture, and in particular to a single instruction multiple fiber (SIMF) microarchitecture. Background Art

[0002] Computer technology is constantly developing and making breakthroughs in areas such as natural language and visual processing, information retrieval, and personalized recommendations, placing higher demands on the performance, power consumption, and usability of computer systems. Currently, general-purpose central processing units (CPUs) primarily adopt the von Neumann control flow architecture, and their performance has gradually reached saturation. In classic out-of-order execution CPU processors, the power consumption used for computing accounts for only 6%, while the overhead for instruction scheduling is close to 50% of the overall power consumption. To this end, NVIDIA's general-purpose graphics processing unit (GPU) uses a multi-threaded concurrent scheduling method, which greatly reduces the instruction overhead in the von Neumann architecture and can increase the power consumption of the computing part to more than 20%.

[0003] Furthermore, with the rapid development of artificial intelligence (AI) technology, processors are shifting from general-purpose architectures to domain-specific architectures, such as Google's Tensor Processing Unit (TPU), a dedicated processor for deep learning, and NVIDIA's Tensor Core, a tensor unit integrated into its GPU. Tensor Core specializes in general-matrix multiplication (GEMM) operations, delivering processing speeds 8 to 16 times faster than traditional Compute Unified Device Architecture (CUDA) cores. Depending on the configured shape and data type (e.g., 16×16×16, 8×32×16, 32×8×16), Tensor Cores load input data at the warp level and simultaneously perform computations using a large number of arithmetic logic units (ALUs). This approach of executing tasks in parallel across multiple warps is widely used for deep neural network workloads that are much larger than the scale supported by Tensor Cores.

[0004] Taking GEMM applications as an example, NVIDIA libraries such as CUTLASS and CUBLAS use a two-level blocking algorithm, partitioning the entire GEMM into multiple sub-GEMMs in two stages. First, the original GEMM is decomposed into sub-GEMMs (TB-GEMMs) assigned to thread blocks (TBs). Subsequently, the warps within the TB are further decomposed into TB-GEMMs, with each warp computing a smaller sub-GEMM (warp-GEMM). After each TB completes its assigned TB-GEMM, the entire GEMM is completed by accumulating and concatenating the results.

[0005] The Streaming Multiprocessor (SM) is the fundamental processing unit of NVIDIA GPUs. Starting with the Volta architecture, each SM consists of four processing blocks (PBs), each with its own independent scheduler unit, function unit, and register file (RF). Thread groups within the same PB share these modules, while thread groups between different PBs cannot. Research indicates that the Turing architecture's scheduler follows the mapping rule scheduler_id = warp_id % 4, indicating that the thread group's index can statically determine its assigned PB.

[0006] Figure 1 The following figure shows the SM structure and its data mapping for executing an example GEMM (256×64×K) on a Tensor Core. Each numbered box for matrices A and B corresponds to a row (16×K) of matrix A and a column (K×16) of matrix B. Assuming the basic compute unit of a Tensor Core is (16×16×16), the amount of data each thread group imports into the RF within its allocated PB and the duplication of this data within the RF indicates that the data for matrix A is loaded four times within the same RF.

[0007] In the GPU single-instruction multiple-thread execution mode, since each thread group processes data through its unique logical register number, PB cannot identify data duplication, which will cause inefficiency problems. Currently, CUDA libraries and applications often use shared memory as a solution to allow thread groups within TB to quickly access on-chip resources. This method gradually accumulates partial results by loading small blocks of matrices A and B into shared memory. However, since the amount of data stored in shared memory is much smaller than the size of large-scale GEMM matrices, the time interval from data loading to calculation is short, and the number of thread groups scheduled simultaneously is limited, the effect of hiding latency is poor. Therefore, how to make use of limited shared memory space becomes a key design issue. This burden can be alleviated when a register renaming scheme is applied. For example, in Figure 1In this example, the blocks of matrix A can be fully reused, effectively replacing the role of shared memory. However, the segments of matrix B (e.g., 0, 1, 2, and 3 in the orange box) are distributed across the register files of all PBs. Register renaming is only effective within a single PB and cannot address data duplication across PBs. Therefore, shared memory is only used for the segments that register renaming cannot address, making more efficient use of limited shared memory capacity while eliminating duplicate data generated in other PBs.

[0008] The L1 data cache is the innermost cache in the CPU cache hierarchy and is part of the Level 1 cache. While the L1 data cache may also help by reducing memory access latency, studies have shown that its efficiency is relatively low. In multiple tests where the GEMM matrix size was expanded from 512 to 4096, the L1 data cache hit rate averaged only 26.5%, far below expectations. The main reasons for the low L1 data cache hit rate include: the segments of matrices A and B may share the same cache line, thereby interfering with each other's cache hits; and as the matrix size increases, the address spacing between adjacent rows or columns increases, which can lead to conflict misses between rows or columns.

[0009] In the GPU architecture, the Single Instruction Multiple Thread (SIMT) model provides a higher dimension of concurrency. This allows programmers to launch large numbers of concurrent threads using simple syntax extensions, building on their sequential thinking, thereby fully realizing the hardware's computational potential. The GPU's abstract machine model not only simplifies programming but also enhances the architecture's applicability and versatility, enabling it to be used far more effectively than CPUs in emerging computer applications. However, in the traditional SIMT model, each thread has its own independent register file and execution path. Even if multiple threads execute the same instruction and access the same or regularly distributed memory addresses, they still need to perform address calculations and resource allocation independently. This design results in a double waste of both computational and register resources. On the one hand, multiple threads repeatedly perform the same or similar address calculations, resulting in redundant computational overhead. On the other hand, each thread has exclusive access to the register file, resulting in inefficient use of register resources. Summary of the Invention

[0010] In view of the above problems, the purpose of the present invention is to provide a single instruction stream multi-fiber micro-architecture that can realize the concurrent execution of asynchronous data streams, effectively improve resource utilization, and eliminate redundant calculations.

[0011] The present invention provides a single instruction stream multi-fiber microarchitecture, which includes a fiber front end and an execution back end; the fiber front end includes a first instruction cache component, an instruction fetch component, a decoding component, a second instruction cache component, a scoreboard component, an instruction emission component and a fiber stack; the first instruction cache component is used to store instructions; the instruction fetch component is used to obtain the instructions from the first instruction cache component when it is determined that there is an idle fiber group; the decoding component is used to decode the instructions; the second instruction cache component is used to store the decoded instructions; the scoreboard component is used to handle write-after-write and write-after-read hazards of the decoded instructions; the instruction emission component is used to emit the decoded instructions from the second instruction cache component; the fiber stack is used to resolve branch divergence for each fiber group; the execution back end includes an operand collection component and an instruction processing unit; the operand collection component is used to store corresponding instruction operands based on the decoded instructions; and the instruction processing unit is used to execute the decoded instructions based on the instruction operands.

[0012] In one implementation of the present invention, one thread corresponds to one fiber group, and each fiber group is provided with an independent program counter.

[0013] In one implementation of the present invention, when a fiber group does not have any valid instructions in the second instruction cache component, it is determined that the fiber group is idle.

[0014] In one implementation of the present invention, each entry of the second instruction cache component is divided into a preset number of parts of equal length, each part is used to store instructions corresponding to a fiber group; the preset number is the ratio of the maximum number of fibers to the number of fibers in the fiber group.

[0015] In one implementation of the present invention, the instruction issuing component determines the issuing order of the decoded instructions through a scheduler.

[0016] In one implementation of the present invention, one fiber stack corresponds to one fiber group, and when the next program counter of the top entry of the fiber stack is not equal to the program counter of the current instruction, it is determined that a branch divergence occurs.

[0017] In one implementation of the present invention, entries of the scoreboard component are of fixed length, and each entry is used to record all registers corresponding to an operand required by an instruction and whether the registers are ready.

[0018] In one implementation of the present invention, the storage content of the operand collection component includes the instruction name, fiber group ID, starting register, and operand; each fiber group corresponds to a continuous preset number of registers, and the register corresponding to each instruction is obtained according to the starting register and the fiber group ID to read the operand from the register.

[0019] In one implementation of the present invention, the operand collection component and the instruction processing unit communicate in a one-to-one correspondence.

[0020] In one implementation of the present invention, the instruction processing unit includes a stream processor pipeline, a special function unit pipeline and a memory pipeline; the stream processor pipeline is used to execute arithmetic and logic instructions; the special function unit pipeline is used to execute special instructions; and the memory pipeline is used to execute memory access instructions.

[0021] As described above, the single instruction stream multi-fiber microarchitecture of the present invention has the following beneficial effects:

[0022] (1) Through the single instruction stream multi-fiber microarchitecture, the concurrent execution of asynchronous data streams is achieved;

[0023] (2) It improves resource utilization efficiency, eliminates redundant calculations, improves overall performance, and brings new solutions to the field of parallel computing;

[0024] (3) It solves the problems of redundant address calculation, register resource waste, static parallelism and inability to reuse resources between kernels in the SIMT architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram showing the mapping of the general matrix multiplication in a streaming multiprocessor in the prior art in one embodiment;

[0026] Figure 2 Shown is a schematic diagram of the structure of a single instruction stream multi-fiber microarchitecture in one embodiment of the present invention;

[0027] Figure 3 FIG. 1 is a schematic diagram illustrating an architecture of a single instruction stream multi-filament microarchitecture according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] Following make use of specific working examples to explain the embodiments of the present application. Other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of this specification. The present application can also be implemented or applied by means of other different embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0029] It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be a random change in type, number and proportion, and the layout pattern of the components may also be more complex.

[0030] The single instruction stream multi-fiber micro-architecture of the present application introduces a fiber (Fiber) which is a more lightweight concurrent execution unit than a thread, further refines the minimum unit of concurrency, and has smaller context information and lower resource overhead. The single instruction stream multi-fiber micro-architecture of the present application solves the problems of redundant address calculation, waste of register resources, static parallelism and inability to reuse resources between Kernels existing in the SIMT architecture, not only reduces hardware overhead, but also avoids data redundancy, and improves overall efficiency.

[0031] The technical solutions in the embodiments of the present application will be described in detail below with reference to the accompanying drawings of the embodiments of the present application.

[0032] Fiber (Fiber) is a user-mode lightweight thread, which is an implementation of coroutine (Coroutine). Fiber has the following core features: (1) user-mode scheduling: not dependent on the operating system kernel, managed and scheduled by the application program itself; (2) cooperative execution: actively yielding execution right, rather than kernel preemption; (3) sharing thread resources: multiple fibers can reuse the same operating system thread; (4) very small overhead: the cost of creation / destruction is about 1 / 100 of that of a traditional thread, and the memory occupancy is only a few KB. Therefore, the context of the fiber only includes the unique identifier of the physical fiber (Fiber ID), the current instruction address and the execution state flag, and does not independently own the register file and stack space.

[0033] In the present invention, the concurrency modules from high to low include three levels: task, thread, and fiber. The task is set on the host; the thread and fiber are set on the device. The present invention uses fiber configuration instructions to set the number of concurrent fibers and create a corresponding number of fibers; and uses thread configuration instructions to set the number of concurrent threads and create a corresponding number of threads. After a task is completed, the number of concurrent threads and the number of concurrent fibers are set, and the number of concurrent threads and the number of concurrent fibers vary with different tasks.

[0034] In one embodiment, for a certain register, a stride field is set in the corresponding register access instruction. When the stride field is a first preset value (such as Stride=1), it indicates that a preset number of fibers read a preset number of consecutive registers starting from the register. When the stride field is a second preset value (such as Stride=0), it indicates that a preset number of fibers read the same register. In one embodiment, the Stride field is as follows:

[0035]

[0036] Among them, the above-mentioned Stride field adds a Stride field to the source operand registers (RS1, RS2). Stride = 1 means that multiple fibers read multiple consecutive registers. For example, assuming that the current number of fibers is 4, Stride of RS1 = 1, which means that 4 fibers read 4 consecutive registers starting from RS1 respectively. Stride = 0 means that multiple fibers read the same register. For write operations, Stride must be 1, because multiple fibers cannot write to the same register at the same time, so there is no need to explicitly mark the Stride field of the write register Rd. Therefore, through the Stride field, the fiber can directly obtain the required load or store address during execution, avoiding repeated address calculations, thereby saving computing resources.

[0037] like Figure 2 As shown, in one embodiment, the single instruction stream multi-fiber micro-architecture of the present invention includes a fiber front end (Fiber Front End) 1 and an execution back end (Execution Back End) 2. Figure 3 As shown, the green part represents the fiber front end 1, and the yellow part represents the execution back end 2. The division of the fiber front end 1 and the execution back end 2 is essentially the decoupling of control flow and data flow. The fiber front end 1 focuses on instruction flow / control flow, while the execution back end 2 focuses on single instruction execution / data flow.

[0038] The fiber front end 1 includes a first instruction cache component (I-Cache) 11, an instruction fetch component (Fetch) 12, a decoding component 13 (Decode), a second instruction cache component (I-Buffer) 14, a scoreboard component (Score-Board) 15, an instruction issue component (Issue) 16 and a fiber stack (Fiber-Stack) 17.

[0039] The first instruction cache component 11 is used to store instructions.

[0040] The instruction fetch component 12 is connected to the first instruction cache component 11 and is used to obtain the instruction from the first instruction cache component 11 when it is determined that there is an idle fiber group. One thread corresponds to one fiber group (FiberGroup), and each fiber group is set with an independent program counter (PC) and independently processes a portion of each instruction. Specifically, after reading the fiber number setting instruction Set_fiber_count(N), a synchronization is performed to ensure that all instructions before switching the number of fibers (Fibers) are completed. Then, ceil(N / Fiber GroupSize) fiber groups are allocated to process all subsequent instructions. N represents the total number of fibers, and Fiber GroupSize represents the number of fibers in each fiber group. Each fiber group processes the corresponding portion of the instruction sequentially. For example, when the number of fibers is set to 64 (assuming the Fiber Group Size is 16), 4 fiber groups are allocated to process all subsequent instructions. For each instruction, the first fiber group contains 0 to 15 fibers, the second fiber group contains 16 to 31 fibers, and so on.

[0041] The decoding component 13 is connected to the instruction fetching component 12 and is used to decode the instruction.

[0042] The second instruction cache component 14 is connected to the decoding component 13 and is used to store decoded instructions. The format of the entries in the second instruction cache component 14 includes the instruction body, fiber offset Offset, fiber Len, stride Stride, valid bit Valid and ready bit Ready. When there is no valid instruction for a fiber group in the second instruction cache component 14, the fiber group is judged to be idle. In one embodiment, each entry of the second instruction cache component 14 is divided into a preset number of parts of equal length, each part is used to store instructions corresponding to a fiber group; the preset number is the ratio of the maximum number of fibers to the number of fibers in the fiber group. In one embodiment, the content of each entry of the second instruction cache component 14 is shown in Table 1.

[0043] Table 1. Entry storage content of the second instruction cache component

[0044]

[0045] In one embodiment, if a fiber group does not have any valid instructions in the second instruction cache component 14, then this fiber group is eligible for instruction fetching. All eligible fiber groups will access the first instruction cache component (I-Cache) 11 in a polling manner, and fetch one or more consecutive instructions corresponding to the program counter (depending on the number of entries occupied by this fiber group), and store the decoded instructions in the second instruction cache component 14, while activating the valid bit of the corresponding entry.

[0046] The scoreboard component 15 is connected to the decode component 13 and is used to handle write-after-write (WAW) and write-after-read (WAR) hazards for decoded instructions. A write-after-write hazard occurs when two instructions write to the same memory cell or register, and their execution order is inconsistent with the order specified by the program. A read-after-write hazard occurs when an instruction needs to read the value of a memory cell or register before another instruction has completed its write operation to that memory cell or register. Both hazards can affect the correctness and performance of the computer system. The present invention addresses these issues through the scoreboard component 15, ensuring that instructions access data in the correct order and guaranteeing correct program execution. In one embodiment, the entries of the scoreboard component 15 are fixed-length, and each entry records all registers corresponding to an operand required by an instruction and whether the registers are ready. The entries of the scoreboard component 15 include the starting register, the fiber offset Offset, the fiber length Len, the stride Stride, and the ready bit Ready. The scoreboard component 15 tracks all issued instructions that have not been written back, retaining the registers written by these instructions (in the form of starting registers, Len, and Stride). The retained registers are released during the write-back phase. When all the bits of the Ready bit of a valid entry for an instruction are 1, the Ready bit of this instruction in the second instruction cache component 14 is set to 1.

[0047] The instruction issuing component 16 is connected to the second instruction cache component 14 and the scoreboard component 15, and is configured to issue the decoded instructions from the second instruction cache component 14. The instruction issuing component 16 determines the order in which the decoded instructions are issued via a scheduler. The scheduler may employ a scheduling strategy such as round-robin.

[0048] The fiber stack 17 is connected to the instruction emission component 16 and is used to resolve branch divergence for each fiber group. Fiber group branch divergence generally refers to the problem of decreased execution efficiency in GPU computing caused by fibers within a fiber group executing different control flow paths. When the valid value of an entry in the second instruction cache component 14 is set, the prepared value is also set by the scoreboard component 15, there is no branch divergence, and it is not waiting for synchronization, the instruction corresponding to the entry can be emitted. A fiber stack corresponds to a fiber group. When the next program counter of the top entry of the fiber stack 17 is not equal to the program counter of the current instruction, a branch divergence is determined to have occurred, and the emission of the decoded instruction is prevented. In one embodiment, when a branch divergence is detected, a new entry is pushed to the top of the fiber stack. The entry includes: the target program counter (Target PC), the program counter value corresponding to the immediate postdominator (Immediate postdominator reconvergence PC), and the active mask (ActiveMask). The length of ActiveMask is the FiberGroup Size. When the fiber group reaches the convergence point again, the top entry is popped.

[0049] The execution backend 2 includes an operand collection component 21 and an instruction processing unit 22 .

[0050] The operand collection component 21 is connected to the instruction emission component 16 and is used to store the corresponding instruction operands based on the decoded instruction. Since the stride can only be 0 or 1, this means that the registers required by all fibers to execute an instruction must be the same or multiple consecutive registers. In the present invention, the fiber group's strategy for allocating fibers is linear. Therefore, for a fiber group, the registers it processes can be stored in the form of (offset relative to the starting fiber, length Len, stride). The advantage of this is that all registers that need to be processed can be expressed while storing fewer fields. It should be noted that when the stride is 0, regardless of the offset relative to the starting fiber, the same register is always read. In one embodiment, the storage content of the operand collection component 21 includes the instruction name, fiber group ID, starting register, and operand. Each fiber group corresponds to a preset number of consecutive registers. The register corresponding to each instruction is obtained based on the starting register and the fiber group ID to read the instruction operand from the register. The number of fibers is obtained based on the fiber ID, and the product of the fiber number and the preset number is calculated. The registers after the starting register by the product number are the registers where the instruction operands are located. Therefore, the operand collection component 21 no longer needs to store the offset. Each instruction operand records the valid bit, the ready bit, and the register value. The storage content of the operand collection component 21 is shown in Table 2.

[0051] Table 2. Storage contents of the operand collection component

[0052]

[0053] The instruction processing unit 22 is connected to the operand collection component 21 and is configured to execute the decoded instruction based on the instruction operand. The operand collection component 21 and the instruction processing unit 22 communicate in a one-to-one correspondence.

[0054] In one embodiment, the instruction processing unit 22 includes a streaming processor pipeline (SP Pipeline), a special function unit pipeline (SFUPipeline), and a memory pipeline (MEM). The streaming processor pipeline is the core computing unit of the GPU, used to execute arithmetic and logic instructions (such as addition, subtraction, multiplication, division, vector operations, etc.). The special function unit pipeline is used to execute special instructions (such as trigonometric functions, exponentials, logarithms, square roots, etc.), thereby reducing the burden of the SP Pipeline and improving the overall computing throughput. The memory pipeline is used to execute memory access instructions.

[0055] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices or methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0056] Modules / units described as separate components may or may not be physically separate, and components displayed as modules / units may or may not be physical modules, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules / units may be selected based on actual needs to achieve the objectives of the embodiments of the present invention. For example, the functional modules / units in various embodiments of the present invention may be integrated into a single processing module, each module / unit may exist physically separately, or two or more modules / units may be integrated into a single module / unit.

[0057] Those skilled in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A single instruction stream multi-fiber microarchitecture, characterized by: The micro-architecture includes a fiber front-end and an execution back-end; The fiber front end includes a first instruction cache component, an instruction fetch component, a decoding component, a second instruction cache component, a scoreboard component, an instruction issue component and a fiber stack; The first instruction cache component is used to store instructions; The instruction fetch component is configured to fetch the instruction from the first instruction cache component when determining that there is an idle fiber group; The decoding component is used to decode the instruction; The second instruction cache component is used to store decoded instructions; The scoreboard component is used to process write-after-write and read-after-write hazards of the decoded instructions; The instruction issuing component is used to issue the decoded instruction from the second instruction cache component; The fiber stack is used to resolve branch divergence for each fiber group; The execution backend includes an operand collection component and an instruction processing unit; The operand collection component is used to store corresponding instruction operands based on the decoded instruction; The instruction processing unit is configured to execute the decoded instruction based on the instruction operand.

2. The single instruction stream multi-fiber microarchitecture according to claim 1, wherein: One thread corresponds to one fiber group, and each fiber group has an independent program counter.

3. The single instruction stream multi-fiber microarchitecture according to claim 1, wherein: When no valid instruction exists for a fiber group in the second instruction cache component, it is determined that the fiber group is idle.

4. The SIMS microarchitecture according to claim 1, wherein: Each entry of the second instruction cache component is divided into a preset number of parts of equal length, each part is used to store instructions corresponding to a fiber group; the preset number is the ratio of the maximum number of fibers to the number of fibers in the fiber group.

5. The SIMS microarchitecture according to claim 1, wherein: The instruction issuing component determines the issuing order of the decoded instructions through a scheduler.

6. The SIMS microarchitecture according to claim 1, wherein: One fiber stack corresponds to one fiber group. When the next program counter of the top entry of the fiber stack is not equal to the program counter of the current instruction, it is determined that a branch divergence occurs.

7. The SIMS micro-architecture according to claim 1, wherein: The entries of the scoreboard component are of fixed length, and each entry is used to record all registers corresponding to an operand required by an instruction and whether the registers are ready.

8. The SIMS micro-architecture according to claim 1, wherein: The storage content of the operand collection component includes the instruction name, fiber group ID, starting register, and operand; each fiber group corresponds to a preset number of consecutive registers, and the register corresponding to each instruction is obtained according to the starting register and the fiber group ID to read the operand from the register.

9. The SIMS micro-architecture according to claim 1, wherein: The operand collection component communicates with the instruction processing unit in a one-to-one correspondence.

10. The single instruction stream multi-fiber microarchitecture according to claim 1, wherein: The instruction processing unit includes a stream processor pipeline, a special function unit pipeline and a memory pipeline; the stream processor pipeline is used to execute arithmetic logic instructions; the special function unit pipeline is used to execute special instructions; and the memory pipeline is used to execute memory access instructions.

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