Processor, graphics card, computer device, and dependency release method

Abstract

A processor, a graphics card, a computer device, and a dependency release method, relating to the field of chips. The processor is provided with a first-type pathway and a second-type pathway between an instruction processing unit and a dependency processing unit. The instruction processing unit is used for sending a first dependency release signal by means of the first-type pathway (222), and the dependency processing unit is used for releasing, on the basis of the first dependency release signal, an instruction dependency relationship corresponding to a first-type register (224); and the instruction processing unit is further used for sending a second dependency release signal by means of the second-type pathway (242), and the dependency processing unit is used for releasing, on the basis of the second dependency release signal, an instruction dependency relationship corresponding to a second-type register (244), wherein both the first-type register and the second-type register are registers used by a same instruction.

Description

Processor, graphics card, computer equipment, and dependency removal methods

[0001] This application claims priority to Chinese patent application No. 202410977461.8, filed on July 19, 2024, entitled "Processor, Graphics Card, Computer Device and Dependency Removal Method". Technical Field

[0002] This application relates to the field of chips, and in particular to a processor, graphics card, computer device, and dependency removal method. Background Technology

[0003] Processors often employ multi-stage pipeline mechanisms when executing instructions. Taking a relatively simple five-stage pipeline as an example, the five stages include: fetch stage, decode stage, execution stage, memory access stage, and write-back stage. A five-stage pipeline can increase efficiency when multiple instructions are executed in parallel.

[0004] A dependency between two instructions means that both instructions are allocated to use the same register, and the later instruction must wait for the earlier instruction to finish using that register before it can begin using it. Dependencies are categorized into three types: read-before-write, write-before-read, and write-before-write. Taking a read-before-write dependency between the first and second instructions as an example, the processor must wait for the write-back phase of the first instruction to complete before it can remove the dependency of the second instruction on the first instruction and execute its write operation to the register.

[0005] Because the second instruction can only be released from its dependency on the first instruction after the write-back phase corresponding to the first instruction has been completed, the first instruction occupies the register for a relatively long time, resulting in reduced register utilization efficiency. Summary of the Invention

[0006] This application provides a processor, a graphics card, a computer device, and a dependency removal method. The technical solution is as follows:

[0007] On one hand, embodiments of this application provide a processor, the processor including: an instruction processing unit and a dependency processing unit, wherein at least two paths are provided between the instruction processing unit and the dependency processing unit, the at least two paths including a first type path and a second type path;

[0008] The instruction processing unit is configured to send a first dependency removal signal to the dependency processing unit through the first type of path; the dependency processing unit is configured to remove the first dependency relationship corresponding to the first type of register based on the first dependency removal signal.

[0009] The instruction processing unit is configured to send a second dependency release signal to the dependency processing unit through the second type of path; the dependency processing unit is configured to release the second dependency relationship corresponding to the second type of register based on the second dependency release signal.

[0010] Both the first type of register and the second type of register are registers used by the same instruction.

[0011] On the other hand, embodiments of this application provide a graphics card that includes the processor described above. Optionally, the processor is a graphics processing unit (GPU).

[0012] On the other hand, embodiments of this application provide a computer device including a processor as described above. Optionally, the processor is a graphics processor.

[0013] On the other hand, embodiments of this application provide a dependency resolution method, which is executed by a processor. The processor includes an instruction processing unit and a dependency processing unit, wherein at least two paths are provided between the instruction processing unit and the dependency processing unit, and the at least two paths include a first type path and a second type path; the method includes:

[0014] The instruction processing unit sends a first dependency removal signal to the dependency processing unit through the first type of path; the dependency processing unit removes the first dependency relationship corresponding to the first type of register based on the first dependency removal signal.

[0015] The instruction processing unit sends a second dependency release signal to the dependency processing unit through the second type of path; the dependency processing unit releases the second dependency relationship corresponding to the second type of register based on the second dependency release signal.

[0016] Both the first type of register and the second type of register are registers used by the same instruction.

[0017] In this embodiment, a first type of path and a second type of path are established between the instruction processing unit and the dependency processing unit. For two types of registers used by the same instruction, the first type of path is used to remove the first dependency, and the second type of path is used to remove the second dependency. Since the timing and duration of the same instruction's use of different types of registers vary, the dependency of the register that is used first can be removed earlier, thereby reducing the time the instruction occupies the register that is used first and improving the utilization efficiency of this register. Simultaneously, because this part of the register can be removed earlier, the possibility of parallel instructions between different instructions is increased. Attached Figure Description

[0018] Figure 1 is a schematic diagram of the structure of a processor provided in an exemplary embodiment of this application;

[0019] Figure 2 is a schematic diagram of a five-stage pipeline provided in an exemplary embodiment of this application;

[0020] Figure 3 is a flowchart of a multi-stage pipeline provided in an exemplary embodiment of this application;

[0021] Figure 4 is a schematic diagram of a device related to a loading instruction provided in an exemplary embodiment of this application;

[0022] Figure 5 is a schematic diagram of a device related to storage instructions provided in an exemplary embodiment of this application;

[0023] Figure 6 is a schematic diagram of the structure of a processor provided in an exemplary embodiment of this application;

[0024] Figure 7 is a schematic diagram of the structure of three candidate pathways provided in an exemplary embodiment of this application;

[0025] Figure 8 is a schematic diagram illustrating the usage of three candidate paths in a multi-stage pipeline according to an exemplary embodiment of this application.

[0026] Figure 9 is a schematic diagram of dependency removal of a loading instruction provided in an exemplary embodiment of this application;

[0027] Figure 10 is a schematic diagram of dependency removal of storage instructions provided in an exemplary embodiment of this application;

[0028] Figure 11 is a schematic diagram of dependency removal of a loading instruction provided in an exemplary embodiment of this application;

[0029] Figure 12 is a flowchart of a dependency removal method provided in an exemplary embodiment of this application. Detailed Implementation

[0030] First, the terms used in the embodiments of this application will be introduced.

[0031] An instruction is a command that directs a computer to perform a specific operation; it is the smallest functional unit of computer operation. An instruction is a statement in machine language, or a set of meaningful binary code. The collection of all the instructions of a computer constitutes its instruction set, also known as its instruction system.

[0032] Instruction Format: A readable representation of an instruction. An instruction typically includes an opcode and operands. The opcode describes the type of operation the instruction will perform, while the operands provide the data or addresses of data required to execute the instruction. The opcode is indispensable in an instruction, but operands are optional, and there can be one or two operands.

[0033] Operation type: at least one of the following: data transfer type, arithmetic logic type, shift type, transfer type, and input / output type. For example, the data transfer type is used to transfer data between memory and registers; another example is the arithmetic logic operation type, which is used to perform arithmetic or logical operations, such as addition, subtraction, multiplication, and division, and logical operations such as NAND, NOT, and OR.

[0034] Instruction types are categorized by the number of operands. Instruction types include zero-operand instructions, one-operand instructions, and two-operand instructions. Zero-operand instructions have no operands or the operand is implicitly defined. One-operand instructions have one operand or an implicit operand (actually two operands). Two-operand instructions have two operands: a destination operand and a source operand. The source operand is a read-only operand, while the destination operand can be both read from and written to (store the operation result).

[0035] Data operands: These are the data that needs to be loaded, stored, or calculated.

[0036] Control operands are distinct from data operands. They are used to indicate memory addresses or execution conditions. For example, control operands include at least one of the following: a memory address, an offset from that memory address, a predicate value in a predicate register, or bypass information.

[0037] Predicate register: A register used to implement conditional execution. For example, 1 is true, indicating that the current instruction or a branch of the current instruction needs to be executed; 0 is false, indicating that the current instruction or a branch of the current instruction does not need to be executed.

[0038] Bypassing information is a technique used to improve performance in pipelined designs of Central Processing Units (CPUs) and Graphics Processing Units (GPUs). In pipelined processing, the operation of each stage depends on the output of the previous stage. However, if the result of an operation in one stage needs to be used immediately in the next clock cycle without waiting for the entire pipeline to complete, bypassing techniques are used to directly pass data from one stage to the next stage that needs it.

[0039] Load instruction: Used to read data from memory into a register. When the processor is a GPU, this memory is called video memory.

[0040] Store instruction: Used to write data from a register into memory.

[0041] Pipeline hazards: In some cases, the next instruction in the next clock cycle cannot be executed in a pipeline. This situation is called a hazard, and there are three types of hazards: data hazards, structural hazards, and control hazards. This application's embodiments relate to data hazards.

[0042] Data hazard: A conflict that occurs when at least two instructions are executed in parallel in a pipeline, and the second instruction needs the result of the first instruction's execution, but the first instruction has not yet been written back. Data hazards are also known as data dependencies.

[0043] Data hazards are classified into three categories: Read After Write (RAW), Write After Write (WAW), and Write After Read (WAR).

[0044] RAW means that the second instruction reads the register, which must be later than the first instruction writes to the register; WAW means that the second instruction writes to the register, which must be later than the first instruction writes to the register; WAR means that the second instruction writes to the register, which must be later than the first instruction reads the register.

[0045] Sleep-Wake Mechanism: A dependency resolution mechanism for data hazard. If a second instruction depends on the result of the first instruction, the second instruction is put to sleep while the first instruction is still executing; once the first instruction has finished executing, the second instruction is woken up to continue execution.

[0046] Scoreboard mechanism: Another dependency resolution mechanism for data hazard. A scoreboard records the dependencies between instructions. When the dependency between a second instruction and the first instruction is detected to be resolved, the second instruction is executed immediately.

[0047] An instruction is a command that directs a computer to perform a specific operation; also known as a machine instruction, it is the smallest functional unit of computer operation. An instruction is a statement in machine language, a set of meaningful binary code. The collection of all the instructions of a computer constitutes its instruction set, also called the instruction system. Instructions are executed by a processor, such as the CPU or GPU.

[0048] Figure 1 shows a schematic diagram of the structure of a processor 100 provided in an exemplary embodiment of this application. The processor 100 includes: an instruction fetch unit 10, a decoding unit 20, a dependency processing unit 30, a load memory unit 40, a calculation unit 50, a register file 60, a memory 70, and a write-back unit 80.

[0049] The instruction fetch unit 10 is connected to the decoding unit 20, the decoding unit 20 is connected to the dependency processing unit 30, and the dependency processing unit 30 is connected to the load storage unit 40 and the calculation unit 50, respectively.

[0050] Instruction fetch unit 10 is connected to memory 70.

[0051] The computation unit 50 is connected to one or more registers in the register file 60. The register file 60 includes registers of different functions and types, such as general-purpose registers and instruction registers.

[0052] Load memory unit 40 is connected to register file 60 and memory 70 respectively, and load memory unit 40 is also connected to write-back unit 80. When processor 100 is a GPU, memory 70 is also called video memory. When processor 100 is a CPU, memory 70 can also be considered a device outside of processor 100.

[0053] Write-back unit 80 is connected to register file 60 and memory 70 respectively, and write-back unit 80 is also connected to dependency processing unit 30.

[0054] The processor 100 described above employs a multi-stage pipeline mechanism when executing instructions. Taking a simple five-stage pipeline as an example, the instruction execution process is divided into five basic stages to achieve parallel processing of instructions and improve processor efficiency.

[0055] As shown in Figure 2, this five-stage pipeline consists of five stages: Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM), and Write-Back (WB). The five-stage pipeline design allows multiple instructions to be processed simultaneously in different stages, thereby reducing the total execution time of each instruction. This parallelism can significantly improve processor performance, especially in high-throughput scenarios. For example, in Figure 2, the five stages of instruction 1's execution occupy cycles 1 to 5 sequentially; the five stages of instruction 2's execution occupy cycles 2 to 6 sequentially; and the five stages of instruction 3's execution occupy cycles 3 to 7 sequentially. Specifically:

[0056] During the instruction fetch phase, the instruction fetch unit 10 fetches an instruction from the memory address pointed to by the program counter (PC) and loads it into the instruction cache. The program counter is then updated to the address of the next instruction. Optionally, the program counter is a counter between the instruction fetch unit 10 and the decode unit 20, used to store the address of the next instruction that the processor 100 needs to process. The instruction cache and program counter are not shown in Figure 1.

[0057] During the decoding phase, decoding unit 20 parses the opcode and operands of the instruction in the instruction cache to determine the operation type and required operation of the instruction. This phase may also involve converting memory addresses or immediate values ​​in the instruction into a form that the processor can understand. After completing the decoding, decoding unit 20 issues the instruction to dependent processing unit 30.

[0058] Common instruction operation types include at least one of the following: data transfer type, arithmetic logic type, shift type, jump type, and input / output type. For example, the data transfer type is used to transfer data between memory and registers; and the arithmetic logic operation type is used to perform arithmetic or logical operations, such as addition, subtraction, multiplication, and division, and logical operations such as NAND, NOT, and OR.

[0059] During the execution phase, the dependency processing unit 30 is responsible for handling the dependencies between different instructions. Based on the dependencies between instructions and the operation type of each instruction, it schedules each instruction to the load storage unit 40 or the computation unit 50 for execution. For example, if the operation type of the instruction is data transfer, the dependency processing unit 30 will schedule the instruction to the load storage unit 40 for execution; if the operation type of the instruction is computation, the dependency processing unit 30 will schedule the instruction to the computation unit 50 for execution. For the current instruction that depends on other instructions, the dependency processing unit 30 needs to remove the dependency of the current instruction on other instructions before scheduling the current instruction to the load storage unit 40 or the computation unit 50.

[0060] During the memory access phase, the loading storage unit 40 or the computing unit 50 sends a memory access request to the memory according to the needs of different instructions. This memory access request can be a memory read request or a memory write request. A memory read request is used to request that data in memory be read into a register, while a memory write request is used to request that data in a register be written into memory.

[0061] During the write-back phase, write-back unit 80 writes the data or instruction execution result in memory into the register corresponding to the target operand.

[0062] In the embodiments of this application, the loading storage unit 40, the computing unit 50, and the write-back unit 80 can all be understood as instruction processing units, that is, units used to process different instructions.

[0063] This application's embodiments relate to improvements in the execution of load and store instructions within a loading memory unit. For more details regarding the multi-stage pipeline for load and store instructions, please refer to Figure 3. Figure 3 shows that both the execution phase and the memory access phase include at least one sub-phase. The execution phase includes at least one sub-phase selected from: dependency resolution, reading control operands, memory address calculation, and reading data operands. The memory access phase includes at least one sub-phase selected from: issuing a memory request and receiving return information. In different embodiments, the memory request sent to memory can be a memory read request or a memory write request; the return information can be data in memory, or a write success response or write failure response after writing data to memory.

[0064] Loading instructions:

[0065] Load instructions are used to read data from memory address 70 into a specific register. In different embodiments, load instructions have different forms. For example, load instruction 1 is `load src dst`, meaning to load the data at memory address `src` into register `dst`. Another example is load instruction 2 is `load R0, [R1, #4]`, meaning to load the data at the offset memory address pointed to by the base memory address stored in register `R1` (4 bytes offset) into register `R0`. Yet another example is load instruction 3 is `if p, load src dst`, meaning: if the predicate register `p` is true, load data from memory address `src` into the general-purpose register `dst`.

[0066] A load instruction includes at least one source operand and at least one destination operand. The source operand indicates the execution condition and / or memory address, and the destination operand indicates the register to be written to. In the example above, src, R1, #4, and p are source operands, and R0 and dst are destination operands. Furthermore, all of these source operands are control-type source operands.

[0067] Taking the load instruction `if p, load src dst` as an example, referring to Figures 3 and 4, in the read control operand sub-stage, the load storage unit 40 first reads the control operand `p`, where `p` is the value in the predicate register (1 for true, 0 for false), and determines whether loading is needed based on `p`. If loading is needed, in the memory address sub-stage, the memory address `src` is obtained or calculated. Since the load instruction does not need to read data operands from registers, there is no read data operand sub-stage. In the memory access stage, the load storage unit 40 sends a memory read request to the memory based on the memory address `src`, and the write-back unit 80 receives the return information, which is the data returned by the memory. In the write-back stage, the write-back unit 80 writes the data to the general-purpose register `dst`. After the write-back stage ends, the write-back unit 80 sends a dependency release signal to the dependency processing unit 30 to update the dependency information configured for this load instruction. For example, if other instructions depend on the loading instruction's use of the predicate register p and the general-purpose register dst, the write-back unit 80 notifies the dependency processing unit 30 to release the other instructions from their dependency on the current instruction.

[0068] Storage instructions:

[0069] The store instruction is used to write data from a register into memory address 70. In different embodiments, the store instruction has different forms. For example, store instruction 1 is `store src dst`, which means loading the data in register `src` into memory address `dst`. Another example is store instruction 2 is `store R0,[R1,#8]`, which means storing the data in register `R0` into a memory address offset 8 bytes from the base memory address stored in register `R1`. Yet another example is store instruction 3 is `if p, load src dst`, which means: if the predicate register `p` is true, write the data from register `src` into register `dst`.

[0070] A store instruction includes at least one source operand and at least one destination operand. The source operand indicates the execution condition and / or the register to be read, and the destination operand indicates the memory address. In the example above, src and p are the source operands, and R1, #8, and dst are the destination operands. Operand src is a data operand, and p, R1, #8, and dst are control operands.

[0071] Taking the store instruction `if p, store src dst` as an example, referring to Figures 3 and 5, in the read control operand stage, the load storage unit 40 reads the value in the predicate register `p` to determine whether storage is needed. If storage is needed, in the memory address calculation stage, the memory address `dst` is obtained or calculated. In the read data operand stage, the load storage unit 40 reads the data in the general-purpose register `src`. In the memory access stage, the load storage unit 40 issues a memory write request to the memory based on the data in the general-purpose register `src` and the memory address `dst` to write the data into memory. Then, the load storage unit 40 sends a dependency release signal to the dependency processing unit 30 to update the dependency information configured for this store instruction. For example, if other instructions depend on the store instruction's use of the predicate register `p` and the general-purpose register `src`, the load storage unit 40 notifies the dependency processing unit 30 to release the dependencies of other instructions on the current instruction.

[0072] Since a single instruction may involve multiple operands, and these operands may correspond to different registers, related technologies typically support only one dependency relationship per instruction. If multiple other instructions simultaneously depend on the current instruction, this single dependency relationship is used for maintenance and release. However, the timing and duration of a single instruction's use of different registers vary. Using the same dependency relationship for different registers can lead to some registers being occupied for a longer period until the last register is used up, at which point the dependencies of other instructions on the current instruction can be released uniformly.

[0073] This application provides an instruction dependency resolution scheme, which aims to divide multiple registers involved in the same instruction into at least two categories. The dependency relationship of the register that is used first is resolved first, and the dependency relationship of the register that is used later is resolved later, so that the register that is used first can be used by other instructions earlier.

[0074] Figure 6 shows a schematic diagram of the structure of a processor 200 provided in an exemplary embodiment of this application. The processor 200 includes at least an instruction processing unit 90 and a dependency processing unit 30.

[0075] The instruction processing unit 90 is a unit for executing different instructions. Optionally, the instruction processing unit 90 is a unit that processes instructions after decoding. The instruction processing unit 90 includes at least one of a load-to-memory unit and a write-back unit. It is not excluded that in other embodiments, the instruction processing unit 90 may include a computation unit.

[0076] The dependency processing unit 30 is a unit used to handle the dependencies between different instructions. Optionally, the dependency processing unit 30 is used to configure the dependencies between different instructions and to remove the dependencies between different instructions.

[0077] In this embodiment, at least two paths are provided between the instruction processing unit 90 and the dependency processing unit 30, including: a first type path 32 and a second type path 34.

[0078] Instruction processing unit 90 is used to send a first dependency release signal to dependency processing unit 30 through first type path 32; dependency processing unit 30 is used to release the dependency relationship corresponding to the first type register based on the first dependency release signal.

[0079] The instruction processing unit 90 is also used to send a second dependency release signal to the dependency processing unit 30 through the second type path 34; the dependency processing unit 30 is used to release the dependency relationship corresponding to the second type register based on the second dependency release signal.

[0080] In this case, both the first-type register and the second-type register are used by the same instruction. The end time of the use of the first-type register and the second-type register by the same instruction is different.

[0081] Optionally, the dependency release signal is a signal sent by the instruction processing unit 90 to the dependency processing unit 30, used to release the dependency relationship associated with a certain instruction. When an instruction supports at least two dependencies, the dependency release signal is used to release at least one dependency relationship associated with that instruction. Optionally, the dependency release signal carries at least one of the following information: instruction identifier, dependency identifier, register identifier, release reason, status information, timestamp, and resource release information.

[0082] Optionally, the first type register is the register corresponding to the first type of operand, and the second type register is the register corresponding to the second type of operand. Both the first type of operand and the second type of operand are operands of the same instruction. Optionally, the first dependency cancellation signal and the second dependency cancellation signal are sent at different times. For example, the first dependency cancellation signal is sent earlier than the second dependency cancellation signal; or, for example, the second dependency cancellation signal is sent earlier than the first dependency cancellation signal.

[0083] A path is a hardware-based signal transmission path, which includes at least one of the following: circuitry, cache, and other possible electronic devices within the chip. That is, a path is a signal transmission path composed of at least one of the following: metal lines, cache, and other possible electronic devices on the chip. In this embodiment, the path is a logical concept used to represent the signal transmission path through which the instruction processing unit 90 sends a dependency release signal to the dependency processing unit 30.

[0084] In some embodiments, the dependency processing unit 30 is integrated into the decoding unit 20; in some embodiments, the dependency processing unit 30 is independent of the decoding unit 20; in some embodiments, the dependency processing unit 30 includes the decoding unit 20 or a portion of the functionality of the decoding unit 20; in some embodiments, the dependency processing unit 30 and the decoding unit 20 cooperate to complete dependency processing. The implementation form of the dependency processing unit 30 is not limited in the embodiments of this application.

[0085] In some embodiments, the processor 200 further includes at least one of an instruction fetch unit, a decoding unit, a cache, a memory, and a register. The embodiments of this application do not limit the other units that the processor 200 may include, or the connection forms between the other units.

[0086] In some embodiments, the signal path between the instruction processing unit 90 and the dependent processing unit 30 can be three or more, and the first type path and the second type path are any two of the three or more signal paths. In this case, the registers used by the same instruction can be three or more, and they are released separately according to three or more release times. This application embodiment does not limit this.

[0087] In summary, the processor provided in this embodiment establishes a first type of path and a second type of path between the instruction processing unit and the dependency processing unit. For two types of registers used by the same instruction, the first type of path is used to remove the first dependency, and the second type of path is used to remove the second dependency. Since the timing and duration of the same instruction's use of different types of registers vary, the dependency of the register that is used first can be removed earlier, thereby reducing the time the instruction occupies the register that is used first and improving the utilization efficiency of this register. Simultaneously, because this part of the register can be removed earlier, the possibility of parallel instructions between different instructions is increased.

[0088] In different embodiments, the first type of path 32 and the second type of path 34 can be designed in various ways. For example, the first type of path 32 and the second type of path 34 are any two of the three candidate paths. As shown in Figure 7, the three candidate paths include: the first path, the second path, and the third path.

[0089] The first path is the signal transmission path between the loading storage unit 40 and the dependency processing unit 30.

[0090] The second path is the signal transmission path between the loading storage unit 40 and the dependency processing unit 30.

[0091] The third path is the signal transmission path between the write-back unit 80 and the dependency processing unit 30.

[0092] The three candidate paths send the dependency removal signal at different times. Figure 8 shows the timing of the dependency removal signal transmission for the three candidate paths in the multi-stage pipeline.

[0093] The storage unit 40 is loaded to send a first dependency release signal to the dependency processing unit 30 through the first path based on the first time T1, where the first time T1 is the end time of the read control class source operand.

[0094] The loading storage unit 40 is configured to send a first dependency release signal or a second dependency release signal to the dependency processing unit 30 via a second path based on a second time T2, where the second time T2 is the end time of issuing a memory read request or a memory write request. For example, for a load instruction, where the second time T2 is the end time of issuing a memory read request, the loading storage unit 40 sends the first dependency release signal to the dependency processing unit 30 via the second path at the second time T2; for a store instruction, where the second time T2 is the end time of issuing a memory write request, the loading storage unit 40 sends the second dependency release signal to the dependency processing unit 30 via the second path at the second time T2.

[0095] The write-back unit 80 is used to send a second dependency cancellation signal to the dependency processing unit 30 through the third path based on the third time T3. The third time T3 is the end time of the write-back phase, which is the phase of writing data back to the register.

[0096] It should be noted that "based on time xx" can be understood as: at time xx, or at a later time slightly later than time xx, or at the time indicated by the sum of time xx and the delay time. The delay time includes the time required for the load memory unit 40 or write-back unit 80 to generate the dependency release signal.

[0097] In different embodiments, the processor includes all or some of the candidate paths from the three candidate paths described above. This application provides at least the following embodiments:

[0098] • The first type of pathway is the first pathway①, and the second type of pathway is the second pathway②;

[0099] • The first type of pathway is the first pathway①, and the second type of pathway is the third pathway③;

[0100] • The first type of pathway is the second pathway ②, and the second type of pathway is the third pathway ③.

[0101] The following describes the various embodiments described above.

[0102] Figure 9 illustrates a dependency removal diagram of a loading instruction provided in an exemplary embodiment of this application. It is assumed that the first type of path includes first path ①, and the second type of path includes third path ③.

[0103] For the load instruction, the execution phase includes three sub-phases: dependency processing, reading the control class source operand, and memory address calculation. After the load storage unit 40 reads the control class source operand, subsequent phases of the current instruction do not need to use the first type register corresponding to the control class source operand. At the end time T1 of reading the control class operand, the load storage unit 40 sends a first dependency release signal to the dependency processing unit 30 using the first path ①. The dependency processing unit 30 releases the dependency relationship corresponding to the first type register based on the first dependency release signal.

[0104] Taking the load instruction `if p, load src dst` as an example, referring to Figures 3 and 9, in the read control operand sub-stage, the load storage unit 40 reads the control operand `p` from the predicate register to determine whether loading is necessary. The read control operand `p` is cached in the load storage unit 40. Since the predicate register is no longer needed in subsequent stages of the load instruction, at the end time T1 of the read control operand stage, the load storage unit 40 sends a first dependency release signal to the dependency processing unit 30 through the first path ① to trigger the dependency processing unit 30 to release the first dependency relationship corresponding to the predicate register. For example, if the load instruction has a read-then-write dependency with other instructions, after sending the first dependency release signal, other instructions can start or continue execution without waiting for the write-back stage of the load instruction to end.

[0105] At the end of the write-back phase, T3, write-back unit 80 writes the data in memory address src to the general-purpose register corresponding to the target operand dst. At this time, write-back unit 80 sends a second dependency release signal to dependency processing unit 30 through the third path ③. Dependency processing unit 30 releases the second dependency relationship corresponding to the general-purpose register based on the second dependency release signal.

[0106] In related technologies, the dependencies corresponding to the load instruction need to be released uniformly at the third time T3, at which point the predicate register and general-purpose register used by the load instruction will be released simultaneously. Compared with related technologies, in this embodiment, the predicate register can be released at the first time T1, which can greatly advance the release time of the predicate register, thereby improving the utilization efficiency of the predicate register.

[0107] Figure 10 illustrates a dependency removal diagram of storage instructions provided in an exemplary embodiment of this application. It is assumed that the first type of path includes a first path ①, and the second type of path includes a second path ②.

[0108] For store instructions, the execution phase includes four sub-phases: dependency handling, reading control-type source operands, memory address calculation, and reading data-type source operands. After reading the control-type source operands, subsequent phases of the store instruction do not require the use of the first type register corresponding to the control-type source operands. At the first moment T1, the load storage unit 40 sends a first dependency release signal to the dependency handling unit 30 using the first path ①. The dependency handling unit 30 releases the dependency relationship corresponding to the first type register based on the first dependency release signal. In the memory address calculation sub-phase, the load storage unit 40 obtains or calculates the memory address based on the target operand; in the reading data-type source operand sub-phase, it reads data from the general-purpose registers.

[0109] During the memory access phase, the load storage unit 40 issues a memory write request, which carries the data class source operand and memory address. The data class source operand and memory address are first stored in the cache and then written to memory. Therefore, the second type register corresponding to the data class source operand and / or memory address will no longer be needed. At the second moment T2 after the load storage unit 40 issues the memory write request, the load storage unit 40 sends a second dependency release signal to the dependency processing unit 30 using the second path ②. The dependency processing unit 30 releases the dependency relationship corresponding to the second type register based on the second dependency release signal.

[0110] Taking the store instruction `if p, store src dst` as an example, referring to Figures 3 and 9, in the read control operand sub-stage, the load storage unit 40 reads the control source operand `p` from the predicate register to determine whether loading is necessary. The read control source operand `p` is cached in the load storage unit 40. Since the predicate register is no longer needed in subsequent stages of the store instruction, at the end of the read control source operand sub-stage T1, the load storage unit 40 sends a first dependency release signal to the dependency processing unit 30 through the first path ① to trigger the dependency processing unit 30 to release the first dependency relationship corresponding to the predicate register based on the first dependency release signal. For example, if the store instruction has a read-then-write dependency with other instructions, after sending the first dependency release signal, other instructions can start or continue execution without waiting for the recall stage of the load instruction to end. In the read data source operand sub-stage, the load storage unit 40 reads data from the general-purpose register corresponding to the data source operand `src`.

[0111] During the memory access phase, the load storage unit 40 issues a memory write request, which carries the data class source operand src and memory address dst. The data class source operand src and memory address dst are first stored in a cache and then written into memory. Therefore, after issuing the memory write request, the load storage unit 40 uses the second path ② to send a second dependency release signal to the dependency processing unit 30. The dependency processing unit 30 releases the instruction dependency relationship corresponding to the second type register based on the second dependency release signal. This second type register is the general-purpose register corresponding to the data class source operand src.

[0112] In related technologies, the dependencies corresponding to the storage instructions need to be released uniformly at the second time T2, at which point the predicate register and general-purpose register used by the storage instructions will be released simultaneously. Compared with related technologies, in this embodiment, the predicate register can be released at the first time T1, which can greatly advance the release time of the predicate register, thereby improving the utilization efficiency of the predicate register.

[0113] Figure 11 illustrates a dependency removal diagram of a loading instruction provided in an exemplary embodiment of this application. It is assumed that the first type of path includes the second path ②, and the second type of path includes the third path ③.

[0114] For the load instruction, the execution phase includes three sub-phases: dependency processing, reading the control class source operand, and memory address calculation. After the load storage unit 40 reads the control class source operand, subsequent phases of the current instruction do not need to use the first type register corresponding to the control class source operand. However, since there is no first path ①, the load storage unit 40 waits for the second moment T2 after the memory read request is issued, and then uses the second path ② to send a first dependency release signal to the dependency processing unit 30. The dependency processing unit 30 releases the first dependency relationship corresponding to the first type register based on the first dependency release signal.

[0115] Taking the load instruction `if p, load src dst` as an example, referring to Figures 3 and 9, in the read control operand sub-stage, the load storage unit 40 reads the control operand `p` from the predicate register to determine whether loading is necessary. The read control operand `p` is cached in the load storage unit 40. However, since there is no first path ①, the load storage unit 40 waits for the second moment T2 after the memory read request is issued, and then uses the second path ② to send a first dependency release signal to the dependency processing unit 30 to trigger the dependency processing unit 30 to release the first dependency relationship corresponding to the predicate register. For example, if this load instruction has a read-then-write dependency with other instructions, after sending the first dependency release signal, other instructions can start or continue execution without waiting for the write-back stage of this load instruction to end.

[0116] At the end of the write-back phase, T3, write-back unit 80 writes the data in memory address src to the general-purpose register corresponding to the target operand dst. At this time, write-back unit 80 sends a second dependency release signal to dependency processing unit 30 through the third path ③. Dependency processing unit 30 releases the second dependency relationship corresponding to the general-purpose register based on the second dependency release signal.

[0117] In related technologies, the dependencies corresponding to the load instruction need to be released uniformly at the third time T3, at which point the predicate register and general-purpose register used by the load instruction will be released simultaneously. Compared with related technologies, in this embodiment, the predicate register can be released at the second time T2, which can greatly advance the release time of the predicate register, thereby improving the utilization efficiency of the predicate register.

[0118] Since there is no sub-stage for reading data operands during the execution phase of the load instruction, the performance difference between releasing the predicate register at the second time T2 and releasing it at the first time T1 is not significant compared to the embodiment in Figure 9.

[0119] As can be seen from the above embodiments, the embodiments of this application can release registers in advance, reduce the time overhead of actual register occupation, and increase the efficiency of register utilization. Especially in scenarios where two instructions have a read-then-write dependency, the first instruction responsible for reading can immediately release the first type register after reading the first type register corresponding to the control operand, so that the second instruction responsible for writing can use the first type register earlier. Therefore, the embodiments of this application can greatly improve the efficiency of register utilization in scenarios with read-then-write dependency.

[0120] At this point, under the same compilation algorithm bias, the embodiments of this application can further reduce register allocation. The embodiments of this application, working in conjunction with the compilation algorithm, can increase the probability of parallel instruction loading while maintaining the same register usage. For example, consider the following instruction stream:

[0121] / / Start of example code snippet

[0122] Load instruction 1: destination operand, source operand 1, source operand 2;

[0123] (Update the register containing source operand 1)

[0124] Load instruction 2: destination operand, source operand 3, source operand 4; / / Source operand 4 reuses the register where source operand 1 is located.

[0125] (Update the register containing source operand 4)

[0126] Load instruction 3: destination operand, source operand 5, source operand 6; / / Source operand 6 reuses the register where source operand 4 is located.

[0127] Calculation instructions;

[0128] / / End of example code segment

[0129] In the example code segment above, if load instruction 1 uses two dependencies, the register containing source operand 1 can be updated before it is written to the register corresponding to the destination operand after load instruction 1 has finished reading source operand 1. The next load instruction 2 works similarly. Assuming the update operation cost is sufficiently low, memory read requests from load instructions 1, 2, and 3 can be executed in parallel on the storage system.

[0130] Based on the above embodiments, the dependency processing unit 30 is used to process the release of the first dependency relationship corresponding to the first type register using a first dependency release mechanism based on a first dependency release signal; and to process the release of the second dependency relationship corresponding to the second type register using a second dependency release mechanism based on a second dependency release signal.

[0131] Optionally, the first dependency resolution mechanism is the scoreboard mechanism, and the second dependency resolution mechanism is the sleep-wake mechanism.

[0132] The scoreboard mechanism records the dependencies between different instructions. When the scoreboard detects that the dependency between the second instruction and the first instruction has been resolved, it immediately executes the second instruction.

[0133] The sleep-wake mechanism is that if the second instruction depends on the execution result of the first instruction, the second instruction is put into a sleep state while the first instruction has not yet been completed; and the second instruction is woken up to continue execution after the first instruction has been completed.

[0134] Compared to the sleep-wake mechanism, the scoreboard mechanism has lower latency, therefore using the scoreboard mechanism to remove the first dependency can release the first type of registers earlier. This is because, under the scoreboard mechanism, instructions that have not removed dependencies after decoding will wait in the instruction queue, and will be issued directly to the subsequent unit for execution after the dependency is removed; while the sleep-wake mechanism requires rescheduling after the dependency is removed, and can only be issued to the subsequent unit for execution after going through the instruction fetch stage and the decoding stage in sequence. Therefore, using the scoreboard mechanism for the first type of registers that are used up first, and using the sleep-wake mechanism for the second type of registers that are used up later, can make the first type of registers released earlier.

[0135] Based on the above embodiments, the processor further includes a decoding unit 20, used to set a first dependency relationship and a second dependency relationship for the instructions during the decoding stage. Optionally, the decoding unit 20 analyzes the dependency relationships between different instructions, such as at least one of the read-before-write, write-before-write, and write-before-read relationships described above. Assuming the current instruction is a first instruction, if both the first instruction and the second instruction use a first type of register, and the second instruction depends on the first instruction, then a first dependency relationship is configured for the first instruction; if both the first instruction and the third instruction use a second type of register, and the third instruction depends on the first instruction, then a second dependency relationship is configured for the first instruction.

[0136] When configuring the first dependency, the decoding unit 20 allocates the first resource to the first instruction. The first resource is the resource required by the first dependency, such as a counter number used to independently count the first dependency. When configuring the second dependency, the decoding unit 20 allocates the second resource to the first instruction. The second resource is the resource required by the second dependency, such as a counter used to independently count the second dependency.

[0137] In some embodiments, the decoding unit 20 is configured to send a first dependency configuration signal to the dependency processing unit 30, and the dependency processing unit 30 is configured to configure a first dependency relationship for the instruction based on the first dependency configuration signal; the decoding unit 20 is also configured to send a second dependency configuration signal to the dependency processing unit 30, and the dependency processing unit 30 is configured to configure a second dependency relationship for the instruction based on the second dependency configuration signal.

[0138] The decoding unit 20 is also used to resend the address of the (first) instruction to the program counter when resources are insufficient to set the first and second dependencies, and the resend condition is met. The program counter stores the address of the next instruction to be executed by the processor. Taking the first resource as the resource required by the first dependency and the second resource as the resource required by the second dependency as an example, the resend condition is that the first resource required by the instruction is sufficient and the second resource is sufficient.

[0139] There is only one type of resource shortage:

[0140] In some embodiments, if the first resource required by the instruction is insufficient but the second resource is sufficient, the instruction can be set to a sleep state, and the wake-up condition is set to the first resource being available being greater than or equal to the first resource required by the instruction. After the instruction is woken up again when the first resource is sufficient, the retransmission condition is checked again. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter. If the first resource required by the instruction is sufficient but the second resource is insufficient, the instruction can be set to a sleep state, and the wake-up condition is set to the second resource being available being greater than or equal to the second resource required by the instruction. After the instruction is woken up again when the second resource is sufficient, the retransmission condition is checked again. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter.

[0141] In other embodiments, if the first resource required by the instruction is insufficient but the second resource is sufficient, only the second dependency can be configured for the instruction, and the first dependency can be omitted; conversely, if the first resource required by the instruction is sufficient but the second resource is insufficient, only the first dependency can be configured for the instruction, and the second dependency can be omitted. This allows the current instruction to run earlier.

[0142] When both resources are insufficient:

[0143] In some embodiments, if both the first and second resources required by the instruction are insufficient, the instruction can be put into a sleep state. However, due to hardware and software limitations, the wake-up condition cannot be set to have both the first and second resources sufficient (i.e., two conditions cannot be set simultaneously; only one condition can be set). Furthermore, since the time taken to resolve the first dependency of previously running instructions is usually longer than the time taken to resolve the second dependency, the wake-up condition set for this instruction is that the available first resource is greater than or equal to the first resource required by the instruction. After waking the instruction again with sufficient first resources, the retransmission condition is checked again. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter. If one resource is still insufficient, the case with only one resource insufficient can be handled as described above.

[0144] This embodiment configures two dependencies for the instruction through a decoding unit, enabling the same instruction to support two different dependencies, and thus supporting the release of different types of registers at different times. Furthermore, when resources for configuring the two dependencies are insufficient, a sleep-wake mechanism is used to temporarily put the first instruction into a dormant state, resending it to the program counter for execution when resources become sufficient, ensuring the smooth execution of the instruction.

[0145] Based on the above embodiments, the loading storage unit 40 is further configured to terminate the execution of the (first) instruction and release the first and second dependencies in the event of an internal exception. The loading storage unit 40 may encounter an internal exception during the execution phase of the first instruction. When an internal exception occurs, the loading storage unit 40 sends an exception signal to the decoding unit 20 or other exception handling unit to terminate the execution of the instruction. If the instruction simultaneously configures the first and second dependencies, the loading storage unit 40 also needs to notify the dependency handling unit 30 to release the first and second dependencies.

[0146] This embodiment, by loading the storage unit and simultaneously releasing the first and second dependencies in the event of an internal exception, enables the implementation of a corresponding exception handling mechanism in scenarios where the same instruction supports two dependencies, thus ensuring the normal operation of the multi-stage pipeline.

[0147] Figure 12 shows a flowchart of a dependency resolution method provided in an exemplary embodiment of this application. The method is executed by a processor provided in the above embodiments, the processor including: an instruction processing unit, a dependency processing unit, and at least two paths disposed between the instruction processing unit and the dependency processing unit, the at least two paths including a first type path and a second type path. The method includes:

[0148] Step 222: The instruction processing unit sends a first dependency release signal to the dependency processing unit through the first type of path;

[0149] Step 224: The dependency processing unit releases the first dependency relationship corresponding to the first type register based on the first dependency release signal;

[0150] Step 242: The instruction processing unit sends a second dependency release signal to the dependency processing unit through the second type of path;

[0151] Step 244: The dependency processing unit releases the second dependency relationship corresponding to the second type register based on the second dependency release signal;

[0152] In this case, both the first-type register and the second-type register are used by the same instruction. The end time of the use of the first-type register and the second-type register by the same instruction is different.

[0153] Optionally, the instruction processing unit is a unit for executing different instructions. Optionally, the instruction processing unit is a unit that processes instructions after decoding. The instruction processing unit includes at least one of a load-to-memory unit and a write-back unit. It is not excluded that in other embodiments, the instruction processing unit may include a computation unit.

[0154] Optionally, the dependency processing unit is a unit used to handle the dependencies between different instructions. Optionally, the dependency processing unit 30 is used to configure the dependencies between different instructions and to remove the dependencies between different instructions.

[0155] Optionally, the dependency release signal is a signal sent by the instruction processing unit to the dependency processing unit to release the dependency relationship associated with a certain instruction. When an instruction supports at least two dependencies, the dependency release signal is used to release at least one dependency relationship associated with that instruction. Optionally, the dependency release signal carries at least one of the following information: instruction identifier, dependency identifier, register identifier, release reason, status information, timestamp, and resource release information.

[0156] Optionally, the first type register is the register corresponding to the first type of operand, and the second type register is the register corresponding to the second type of operand. Both the first type of operand and the second type of operand are operands of the same instruction. Optionally, the first dependency cancellation signal and the second dependency cancellation signal are sent at different times. For example, the first dependency cancellation signal is sent earlier than the second dependency cancellation signal; or, for example, the second dependency cancellation signal is sent earlier than the first dependency cancellation signal.

[0157] A path is a hardware-based signal transmission path, which includes at least one of the following: circuitry, cache, and other possible electronic devices within the chip. That is, a path is a signal transmission path composed of at least one of the following: metal lines, cache, and other possible electronic devices on the chip. In this embodiment, the path is a logical concept used to represent the signal transmission path through which the instruction processing unit sends a dependency release signal to the dependency processing unit.

[0158] In some embodiments, the dependency processing unit is integrated into the decoding unit; in some embodiments, the dependency processing unit is independent of the decoding unit; in some embodiments, the dependency processing unit includes the decoding unit or a portion of the decoding unit's functionality; in some embodiments, the dependency processing unit and the decoding unit cooperate to complete dependency processing. The implementation form of the dependency processing unit is not limited in the embodiments of this application.

[0159] In some embodiments, the processor further includes at least one of an instruction fetch unit, a decoding unit, a cache, memory, and registers. The embodiments of this application do not limit the other units that the processor may include, or the connection forms between the other units.

[0160] In some embodiments, the signal paths between the instruction processing unit and the dependent processing unit can be three or more, and the first type path and the second type path are any two of the three or more signal paths. In this case, the registers used by the same instruction can be three or more, and they are released separately according to three or more release times. This application embodiment does not limit this.

[0161] In summary, the method provided in this embodiment establishes a first type of path and a second type of path between the instruction processing unit and the dependency processing unit. For two types of registers used by the same instruction, the first type of path is used to remove the first dependency, and the second type of path is used to remove the second dependency. Since the timing and duration of the same instruction's use of different types of registers vary, the dependency of the register that is used first can be removed earlier, thereby reducing the time the instruction occupies the register that is used first and improving the utilization efficiency of this register. Simultaneously, because this part of the register can be removed earlier, the possibility of parallel instructions between different instructions is increased.

[0162] In different embodiments, the first type of pathway and the second type of pathway can have multiple possible design methods. For example, the first type of pathway and the second type of pathway can be any two of the three candidate pathways. The three candidate pathways include: the first pathway, the second pathway, and the third pathway.

[0163] The first path is the signal transmission path between the loading storage unit and the dependency processing unit.

[0164] The second path is another signal transmission path between the loading storage unit and the dependent processing unit.

[0165] The third path is the signal transmission path between the write-back unit and the dependency processing unit.

[0166] The three candidate paths send the transmission dependency release signal at different times.

[0167] The loading storage unit is used to send a first dependency release signal to the dependency processing unit through the first path based on the first time T1, where the first time T1 is the end time of the read control class source operand.

[0168] The loading storage unit is configured to send a first dependency release signal or a second dependency release signal to the dependency processing unit via a second path based on a second time T2, where the second time T2 is the end time of issuing a memory read request or a memory write request. For example, for a load instruction, where the second time T2 is the end time of issuing a memory read request, the loading storage unit sends the first dependency release signal to the dependency processing unit via the second path at the second time T2; for a store instruction, where the second time T2 is the end time of issuing a memory write request, the loading storage unit sends the second dependency release signal to the dependency processing unit via the second path at the second time T2.

[0169] Write-back unit 80 is used to send a second dependency cancellation signal to the dependency processing unit through the third path based on the third time T3. The third time T3 is the end time of the write-back phase, which is the phase of writing data back to the register.

[0170] It should be noted that "based on time xx" can be understood as: at time xx, or at a later time slightly later than time xx, or at the time indicated by the sum of time xx and the delay time. The delay time includes the time required to load the memory unit to generate the dependency release signal.

[0171] In different embodiments, the processor includes all or some of the candidate paths from the three candidate paths described above. This application provides at least the following embodiments:

[0172] • The first type of pathway is the first pathway, and the second type of pathway is the second pathway;

[0173] • The first type of pathway is the first pathway, and the second type of pathway is the third pathway;

[0174] • The first type of pathway is the second pathway, and the second type of pathway is the third pathway.

[0175] The following describes the various embodiments described above.

[0176] In some embodiments, referring to FIG9 and the description related to FIG9, the instruction processing unit includes a load storage unit and a write-back unit; a first type of path includes a first path between the load storage unit and the dependency processing unit; a second type of path includes a third path between the write-back unit and the dependency processing unit; and the instruction includes a load instruction.

[0177] The instruction processing unit sends a first dependency release signal through a first type of path, including:

[0178] The loading memory unit sends a first dependency release signal through the first path based on the first moment, which is the end moment of reading the first type of operand;

[0179] The instruction processing unit sends a second dependency release signal through a second type of path, including:

[0180] The write-back unit sends a second dependency release signal through the third path based on the third time point, which is the end time of the write-back phase;

[0181] The load instruction is executed using a multi-stage pipeline, which includes an execution phase and a write-back phase. The first moment is a moment within the execution phase.

[0182] In related technologies, the dependencies corresponding to the load instruction need to be released uniformly at the third time T3, at which point the predicate register and general-purpose register used by the load instruction will be released simultaneously. Compared with related technologies, in this embodiment, the register corresponding to the first type of operand can be released at the first time T1, which can greatly advance the release time of the register, thereby improving the utilization efficiency of the register.

[0183] In some embodiments, referring to FIG10 and the description related to FIG10, the instruction processing unit includes a load storage unit; a first type of path includes a first path between the load storage unit and the dependency processing unit; a second type of path includes a second path between the load storage unit and the dependency processing unit; the above instruction includes a storage instruction;

[0184] The instruction processing unit sends a first dependency release signal through a first type of path, including:

[0185] The loading memory unit sends a first dependency release signal through the first path based on the first moment, which is the end moment of reading the first type of operand;

[0186] The instruction processing unit sends a second dependency release signal through a second type of path, including:

[0187] The loading storage unit sends a second dependency release signal through a second path based on a second time point, where the second time point is the end time of issuing the memory write request;

[0188] The storage instructions are executed using a multi-stage pipeline, which includes an execution phase and a memory access phase. The first moment is a moment in the execution phase, and the second moment is a moment in the memory access phase.

[0189] In related technologies, the dependencies corresponding to the storage instructions need to be released uniformly at the second time T2, at which point the predicate register and general-purpose register used by the storage instructions will be released simultaneously. Compared with related technologies, in this embodiment, the register corresponding to the first type of operand can be released at the first time T1, which can greatly advance the release time of the register, thereby improving the utilization efficiency of the register.

[0190] In some embodiments, referring to FIG11, the instruction processing unit includes a load storage unit and a write-back unit; the first type of path includes a second path between the load storage unit and the dependency processing unit; the second type of path includes a third path between the write-back unit and the dependency processing unit; the instruction is a load instruction;

[0191] The instruction processing unit sends a first dependency release signal through a first type of path, including:

[0192] The loading storage unit sends the first dependency release signal through the second path based on the second time point, which is the end time of issuing the memory read request;

[0193] The instruction processing unit sends a second dependency release signal through a second type of path, including:

[0194] The write-back unit sends a second dependency release signal through the third path based on the third time point, which is the end time of the write-back phase;

[0195] The load instruction is executed using a multi-stage pipeline, which includes a memory access stage and a write-back stage. The second time step is a moment within the memory access stage.

[0196] In related technologies, the dependencies corresponding to the load instruction need to be released uniformly at the third time T3, at which point the predicate register and general-purpose register used by the load instruction will be released simultaneously. Compared with related technologies, in this embodiment, some registers can be released at the second time T2, which can greatly advance the release time of these registers, thereby improving the utilization efficiency of these registers.

[0197] Since there is no sub-stage for reading data operands during the execution phase of the load instruction, the performance difference between releasing this part of the register at the second time T2 and releasing it at the first time T1 is not significant compared to the embodiment in Figure 9.

[0198] As can be seen from the above embodiments, the embodiments of this application can release registers in advance, reduce the time overhead of actual register occupation, and increase the efficiency of register utilization. Especially in scenarios where two instructions have a read-then-write dependency, the first instruction responsible for reading can immediately release the first type register after reading the first type register corresponding to the control operand, so that the second instruction responsible for writing can use the first type register earlier. Therefore, the embodiments of this application can greatly improve the efficiency of register utilization in scenarios with read-then-write dependency.

[0199] At this point, under the same compilation algorithm bias, the embodiments of this application can further reduce register allocation. By working in conjunction with the compilation algorithm, the embodiments of this application can increase the probability of parallel instruction loading while maintaining the same register usage.

[0200] In some embodiments, the dependency processing unit removes the first dependency relationship corresponding to the first type register based on the first dependency removal signal, including: the dependency processing unit uses a first dependency removal mechanism to process and remove the first dependency relationship corresponding to the first type register based on the first dependency removal signal.

[0201] The dependency processing unit releases the second dependency relationship corresponding to the second type register based on the second dependency release signal, including: the dependency processing unit releases the second dependency relationship corresponding to the second type register using the second dependency release mechanism based on the second dependency release signal.

[0202] The first dependency resolution mechanism is the scoreboard mechanism, and the second dependency resolution mechanism is the sleep-wake mechanism.

[0203] Compared to the sleep-wake mechanism, the scoreboard mechanism has lower latency, therefore using the scoreboard mechanism to remove the first dependency can release the first type of registers earlier. This is because, under the scoreboard mechanism, instructions that have not removed dependencies after decoding will wait in the instruction queue, and will be issued directly to the subsequent unit for execution after the dependency is removed; while the sleep-wake mechanism requires rescheduling after the dependency is removed, and can only be issued to the subsequent unit for execution after going through the instruction fetch stage and the decoding stage in sequence. Therefore, using the scoreboard mechanism for the first type of registers that are used up first, and using the sleep-wake mechanism for the second type of registers that are used up later, can make the first type of registers released earlier.

[0204] In some embodiments, the processor further includes a decoding unit; the method further includes:

[0205] During the decoding stage, the decoding unit sets up a first dependency relationship and a second dependency relationship for the instructions.

[0206] This embodiment configures two dependency relationships for the instruction through the decoding unit, enabling the same instruction to support two different dependency relationships, thereby supporting the release of different types of registers at different times.

[0207] In some embodiments, the method further includes: when the decoding unit is unable to set the first dependency and the second dependency due to insufficient resources, it waits for the retransmission condition to be met before retransmitting the address of the instruction to the program counter, whereby the program counter stores the address of the next instruction to be executed by the processor. For example, if the first resource is the resource required by the first dependency and the second resource is the resource required by the second dependency, the retransmission condition is that both the first and second resources required by the instruction are sufficient.

[0208] There is only one type of resource shortage:

[0209] In some embodiments, if the first resource required by the instruction is insufficient but the second resource is sufficient, the decoding unit sets the instruction to a sleep state and sets the wake-up condition to be that the idle first resource is greater than or equal to the first resource required by the instruction. After the instruction is woken up again when the first resource is sufficient, the unit checks again whether the above retransmission condition is met. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter. If the first resource required by the instruction is sufficient but the second resource is insufficient, the decoding unit sets the instruction to a sleep state and sets the wake-up condition to be that the idle second resource is greater than or equal to the second resource required by the instruction. After the instruction is woken up again when the second resource is sufficient, the unit checks again whether the above retransmission condition is met. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter.

[0210] In other embodiments, if the first resource required by the instruction is insufficient but the second resource is sufficient, the decoding unit configures only the second dependency for the instruction and does not configure the first dependency; if the first resource required by the instruction is sufficient but the second resource is insufficient, the decoding unit configures only the first dependency for the instruction and does not configure the second dependency. This allows the current instruction to run earlier.

[0211] When both resources are insufficient:

[0212] In some embodiments, if both the first and second resources required by the instruction are insufficient, the decoding unit sets the instruction to a sleep state. However, due to hardware and software limitations, the wake-up condition cannot be set to have both the first and second resources sufficient (i.e., two conditions cannot be set simultaneously; only one condition can be set). Meanwhile, since the time taken to resolve the first dependency of previously running instructions is usually longer than the time taken to resolve the second dependency, the wake-up condition set for this instruction is that the available first resource is greater than or equal to the first resource required by the instruction. After waking the instruction again with sufficient first resources, the retransmission condition is checked again. If the retransmission condition is met, the address of the instruction is retransmitted to the program counter. If one resource is still insufficient, the case with only one resource insufficiency can be handled as described above.

[0213] In this embodiment, when resources for configuring the two dependencies are insufficient, a sleep-wake mechanism is used to temporarily put the first instruction into a dormant state, and then resend it to the program counter for execution when resources are sufficient, so as to ensure the smooth execution of the first instruction.

[0214] In some embodiments, the instruction processing unit includes a loading storage unit; the method further includes:

[0215] In the event of an internal exception, the execution of the above instructions is terminated when the storage unit is loaded, and the first and second dependencies are released.

[0216] This embodiment, by loading the storage unit and simultaneously releasing the first and second dependencies in the event of an internal exception, enables the implementation of a corresponding exception handling mechanism in scenarios where the same instruction supports two dependencies, thus ensuring the normal operation of the pipeline.

[0217] In some embodiments, the first type of register is the register corresponding to control operands, and the second type of register is the register corresponding to data operands.

[0218] On the other hand, embodiments of this application provide a graphics card that includes the processor described in the above embodiments. Optionally, the processor is a GPU.

[0219] On the other hand, embodiments of this application provide a computer device, which includes the processor described above. Optionally, the processor is a GPU. The computer device can be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. The AI ​​computing cluster can also be simply referred to as an intelligent computing cluster or a smart computing cluster.

[0220] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A processor, comprising: The processor comprises an instruction processing unit and a dependency processing unit, at least two paths are arranged between the instruction processing unit and the dependency processing unit, and the at least two paths comprise a first type path and a second type path; The instruction processing unit is configured to send a first dependency release signal to the dependency processing unit through the first type path; and the dependency processing unit is configured to release a first dependency relationship corresponding to a first type register based on the first dependency release signal. The instruction processing unit is configured to send a second dependency release signal to the dependency processing unit through the second type path; and the dependency processing unit is configured to release a second dependency relationship corresponding to a second type register based on the second dependency release signal. The first type register and the second type register are registers used by the same instruction.

2. The processor of claim 1, wherein, The instruction processing unit comprises a load store unit; The first type path comprises a first path between the load store unit and the dependency processing unit; The second type path comprises a second path between the load store unit and the dependency processing unit.

3. The processor of claim 2, wherein, The instruction comprises a store instruction; The load store unit is configured to send the first dependency release signal to the dependency processing unit through the first path at a first time point, and the first time point is an end time point of reading a first type operand; The load store unit is configured to send the second dependency release signal to the dependency processing unit through the second path at a second time point, and the second time point is an end time point of sending a memory write request; The store instruction is executed by using a multi-stage pipeline, the multi-stage pipeline comprises an execution stage and a memory access stage, the first time point is one time point in the execution stage, and the second time point is one time point in the memory access stage.

4. The processor of claim 1, wherein, The instruction processing unit comprises a load store unit and a write back unit; The first type path comprises a first path between the load store unit and the dependency processing unit; The second type path comprises a third path between the write back unit and the dependency processing unit.

5. The processor of claim 4, wherein, The instruction comprises a load instruction; The load store unit is configured to send the first dependency release signal to the dependency processing unit through the first path at a first time point, and the first time point is an end time point of reading a first type operand; The write back unit is configured to send the second dependency release signal to the dependency processing unit through the third path at a third time point, and the third time point is an end time point of a write back stage; The load instruction is executed by using a multi-stage pipeline, the multi-stage pipeline comprises an execution stage and the write back stage, and the first time point is one time point in the execution stage.

6. The processor of claim 1, wherein, The instruction processing unit comprises a load store unit and a write back unit; The first type path comprises a second path between the load store unit and the dependency processing unit; The second type path comprises a third path between the write back unit and the dependency processing unit.

7. The processor of claim 6, wherein, The instruction is a load instruction; The load store unit is configured to send the first dependency release signal to the dependency processing unit through the second channel at a second time, the second time being an end time of sending a memory read request; The write back unit is configured to send the second dependency release signal to the dependency processing unit through the third channel at a third time, the third time being an end time of a write back stage. The load instruction is executed by using a multi-stage pipeline, the multi-stage pipeline includes a memory access stage and the write back stage, and the second time is a time in the memory access stage.

8. The processor of any one of claims 1-7, wherein The dependency processing unit is configured to process and release the first dependency relationship corresponding to the first type of register by using a first dependency release mechanism based on the first dependency release signal, and process and release the second dependency relationship corresponding to the second type of register by using a second dependency release mechanism based on the second dependency release signal.

9. The processor of claim 8, wherein, The first dependency release mechanism is a scoreboard mechanism, and the second dependency release mechanism is a sleep-wake mechanism.

10. The processor of any one of claims 1 to 7, wherein, The processor further includes a decoding unit. The decoding unit is configured to set the first dependency relationship and the second dependency relationship for the instruction respectively in a decoding stage.

11. The processor of claim 10, wherein The decoding unit is further configured to resend an address of the instruction to a program counter when a reissue condition is met in a case where resources are insufficient to set the first dependency relationship and the second dependency relationship, the program counter being configured to store an address of a next instruction to be executed by the processor.

12. The processor of any one of claims 1 to 7, wherein, The instruction processing unit includes a load store unit. The load store unit is further configured to end execution of the instruction and release the first dependency relationship and the second dependency relationship in a case where an internal exception occurs.

13. The processor of any one of claims 1 to 7, wherein, The first type of register is a register corresponding to a control class operand, and the second type of register is a register corresponding to a data class operand.

14. A graphics card, characterized by The graphics card includes the processor of any one of claims 1-13.

15. A computer device, comprising: The computer device includes the processor of any one of claims 1-13.

16. A method of relying on a release, comprising: The method is performed by a processor, the processor including an instruction processing unit and a dependency processing unit, at least two channels being provided between the instruction processing unit and the dependency processing unit, the at least two channels including a first type of channel and a second type of channel, and the method including: The instruction processing unit sends a first dependency release signal to the dependency processing unit through the first type of channel, and the dependency processing unit releases a first dependency relationship corresponding to a first type of register based on the first dependency release signal. The instruction processing unit sends a second dependency release signal to the dependency processing unit through the second type of channel, and the dependency processing unit releases a second dependency relationship corresponding to a second type of register based on the second dependency release signal. The first type of register and the second type of register are registers used by a same instruction.

17. The method of claim 16, wherein, The instruction processing unit comprises a load store unit; The first type of path comprises a first path between the load store unit and the dependent processing unit; the second type of path comprises a second path between the load store unit and the dependent processing unit; the instruction comprises a store instruction; The instruction processing unit sends a first dependent release signal to the dependent processing unit through the first type of path, comprising: The load store unit sends the first dependent release signal to the dependent processing unit through the first path based on a first time, which is an end time of reading a first type of operand; The instruction processing unit sends a second dependent release signal to the dependent processing unit through the second type of path, comprising: The load store unit sends the second dependent release signal to the dependent processing unit through the second path based on a second time, which is an end time of issuing a memory write request; The store instruction is executed by a multi-stage pipeline, the multi-stage pipeline comprises an execution stage and a memory access stage, the first time is one time in the execution stage, and the second time is one time in the memory access stage.

18. The method of claim 16, wherein, The instruction processing unit comprises a load store unit and a write back unit; the first type of path comprises a first path between the load store unit and the dependent processing unit; the second type of path comprises a third path between the write back unit and the dependent processing unit; the instruction comprises a load instruction; The instruction processing unit sends a first dependent release signal to the dependent processing unit through the first type of path, comprising: The load store unit sends the first dependent release signal through the first path based on a first time, which is an end time of reading a first type of operand; The instruction processing unit sends a second dependent release signal to the dependent processing unit through the second type of path, comprising: The write back unit sends the second dependent release signal to the dependent processing unit through the third path based on a third time, which is an end time of a write back stage; The load instruction is executed by a multi-stage pipeline, the multi-stage pipeline comprises an execution stage and the write back stage, and the first time is one time in the execution stage.

19. The method of claim 16, wherein, The instruction processing unit comprises a load store unit and a write back unit; the first type of path comprises a second path between the load store unit and the dependent processing unit; the second type of path comprises a third path between the write back unit and the dependent processing unit; the instruction is a load instruction; The instruction processing unit sends a first dependent release signal to the dependent processing unit through the first type of path, comprising: The load store unit sends the first dependent release signal to the dependent processing unit through the second path based on a second time, which is an end time of issuing a memory read request; The instruction processing unit sends a second dependent release signal to the dependent processing unit through the second type of path, comprising: The write back unit sends the second dependent release signal to the dependent processing unit through the third path based on a third time, which is an end time of a write back stage. The write-back unit sends the second dependency release signal to the dependency processing unit through the third path based on a third time, which is an end time of the write-back stage; The load instruction is executed by a multi-stage pipeline, the multi-stage pipeline includes a memory access stage and the write-back stage, and the second time is a time in the memory access stage.

20. The method of any one of claims 16 to 19, wherein, The dependency processing unit releases a first dependency relationship corresponding to a first type register based on the first dependency release signal, including: The dependency processing unit processes the first dependency relationship corresponding to the first type register by using a first dependency release mechanism based on the first dependency release signal. The dependency processing unit releases a second dependency relationship corresponding to a second type register based on the second dependency release signal, including: The dependency processing unit processes the second dependency relationship corresponding to the second type register by using a second dependency release mechanism based on the second dependency release signal.

21. The method of claim 20, wherein, The first dependency release mechanism is a scoreboard mechanism, and the second dependency release mechanism is a sleep-wakeup mechanism.

22. The method of any one of claims 16 to 19, wherein, The processor further includes a decoding unit, and the method further includes: The decoding unit sets the first dependency relationship and the second dependency relationship for the instruction respectively in a decoding stage.

23. The method of claim 22, wherein, The method further includes: In a case where resources are insufficient to set the first dependency relationship and the second dependency relationship, the decoding unit waits until a reissue condition is met to reissue an address of the instruction to a program counter, and the program counter is used to store an address of a next instruction to be executed by the processor.

24. The method of any one of claims 16 to 19, wherein, The instruction processing unit includes a load store unit, and the method further includes: In a case where an internal exception occurs, the load store unit ends execution of the instruction and releases the first dependency relationship and the second dependency relationship.

25. The method of any one of claims 16 to 19, wherein, The first type register is a register corresponding to a control class operand, and the second type register is a register corresponding to a data class operand.

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