Memory pooling system, control method and power-on method and device thereof and electronic equipment

Abstract

The invention discloses a memory pooling system, a control method thereof, a power-on method, a power-on device and electronic equipment, and relates to the technical field of computers, through a multiplexer dynamic selection mechanism of a memory expansion unit, a first management link of a controller module for managing a memory buffer or a second management link of the controller module for managing a memory card is constructed, and the memory expansion unit is used for storing the memory. An external device to be expanded does not need to participate in memory device management, under the condition that the number of physical pins is limited, large-capacity memory expansion can be achieved only by connecting a memory buffer and a memory card, a memory board forms a pooling resource pool for capacity expansion by configuring the memory card, meanwhile, a multiplexer efficiently multiplexes a limited signal channel of the switching module, and the expansion efficiency is improved. The controller module can intelligently switch management paths according to instruction attributes, and finally the to-be-expanded device breaks through the limitation of physical pins and synchronously obtains the large-capacity and high-bandwidth memory expansion capacity.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory pooling system and a control method, a power-on method, a device, and an electronic device thereof. Background Art

[0002] In the intelligent era, the memory system of devices needs larger capacity and higher bandwidth to meet computing power requirements. However, due to the limitations of the number and size of physical pins of the devices, it is impossible to increase the number of external memory units connected to the devices based on the physical pins indefinitely to achieve memory expansion with larger capacity and higher bandwidth. As a result, the memory capacity of artificial intelligence accelerators has grown slowly, which directly leads to the widening gap between computing power and storage capacity, slowing down the implementation of large models and the speed of intelligent innovation. Summary of the Invention

[0003] The present application provides a memory pooling system and its control method, power-on method, device, and electronic device to at least solve the technical problem of how to achieve large-capacity and high-bandwidth memory expansion in the related art.

[0004] The present application provides a memory pooling system, comprising: a memory expansion unit, the memory expansion unit comprising a memory board, a controller module, a multiplexer, and a switching module, the memory board comprising a memory buffer, the memory buffer being interconnected with a plurality of memory cards;

[0005] The controller module is connected to the multiplexer via the input signal channel and the output signal channel of the adapter module;

[0006] The multiplexer is connected to the memory buffer and the memory card respectively to establish a first management link between the controller module and the memory buffer, or to establish a second management link between the controller module and the memory card;

[0007] In response to a memory management instruction, the controller module selects the first management link or the second management link to respond to the memory management instruction according to attribute information of the memory management instruction.

[0008] This application provides a control method for a memory pooling system, including:

[0009] In response to a memory management instruction to the memory card or the memory buffer, determining attribute information of the memory management instruction;

[0010] Determining a target link corresponding to the memory management instruction from a plurality of management links according to the attribute information;

[0011] The memory card or the memory buffer is managed according to the target link.

[0012] This application provides a power-on method for a memory pooling system, comprising:

[0013] Determining a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system;

[0014] When it is determined that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, powering on the memory expansion unit and the host to be expanded by using a first power-on mode;

[0015] When it is determined that the connection mode is that the memory expansion unit is indirectly connected to the host to be expanded via a switching unit, the switching unit, the host to be expanded, and the memory expansion unit are powered on by a second power-on mode.

[0016] This application provides a control device for a memory pooling system, comprising:

[0017] a first determining unit, configured to determine attribute information of a memory management instruction in response to a memory management instruction to a memory card or a memory buffer;

[0018] The first determining unit is further configured to determine, according to the attribute information, a target link corresponding to the memory management instruction from a plurality of management links;

[0019] A management unit is configured to manage the memory card or the memory buffer according to the target link.

[0020] The present application provides a power-on device for a memory pooling system, comprising:

[0021] A second determining unit is configured to determine a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system;

[0022] a first power-on unit, configured to, when determining that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, power on the memory expansion unit and the host to be expanded using a first power-on mode;

[0023] The second power-on unit is used to power on the adapter unit, the host to be expanded and the memory expansion unit through a second power-on method when it is determined that the connection method is that the memory expansion unit is indirectly connected to the host to be expanded via the adapter unit.

[0024] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for controlling a memory pooling system, or the steps of any of the above-mentioned methods for powering on a memory pooling system, when executing the computer program.

[0025] The present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned methods for controlling a memory pooling system, or the steps of any of the above-mentioned methods for powering on a memory pooling system.

[0026] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned methods for controlling a memory pooling system, or the steps of any of the above-mentioned methods for powering on a memory pooling system.

[0027] The memory pooling system and its control method, power-on method, device, and electronic device of the present application use a dynamic selection mechanism of the multiplexer of the memory expansion unit, that is, constructing a first management link for the controller module to manage the memory cache or a second management link for the controller module to manage the memory card, so that the external device to be expanded does not need to participate in the management of the memory device. When the number of physical pins is limited, large-capacity memory expansion can be achieved by simply connecting the memory cache and the memory card. The memory board expands the capacity by configuring the memory card to form a pooled resource pool. At the same time, the multiplexer efficiently multiplexes the limited signal channels of the adapter module, so that the controller module can intelligently switch the management path according to the instruction attributes, quickly access the memory cache through the first management link to optimize high-frequency interaction, or directly connect to the memory card through the second management link to achieve high-bandwidth parallel data access. Ultimately, the device to be expanded breaks through the physical pin limitation and simultaneously obtains large-capacity and high-bandwidth memory expansion capabilities, effectively bridging the computing-storage gap of the artificial intelligence accelerator. Therefore, it can solve the technical problem of how to achieve large-capacity and high-bandwidth memory expansion, and achieve the technical effect of providing greater memory bandwidth and higher memory capacity density. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A schematic diagram of the structure of a memory pooling system provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of the connection topology of a controller module provided in an embodiment of the present application;

[0031] Figure 3 A top view of a memory expansion unit provided in an embodiment of the present application;

[0032] Figure 4An exploded diagram of a memory expansion unit provided in an embodiment of the present application;

[0033] Figure 5 An interconnection topology diagram of a memory expansion unit provided in an embodiment of the present application;

[0034] Figure 6 An interconnection topology diagram of a memory board provided in an embodiment of the present application;

[0035] Figure 7 A layout diagram of a memory buffer provided in an embodiment of the present application;

[0036] Figure 8 A physical diagram of a memory expansion unit provided in an embodiment of the present application;

[0037] Figure 9 A schematic diagram of the connection topology of a host to be expanded provided in an embodiment of the present application;

[0038] Figure 10 A schematic diagram of a topology of direct interconnection between a host to be expanded and a memory expansion unit provided in an embodiment of the present application;

[0039] Figure 11 A schematic diagram of a topology of an embodiment of the present application providing a host to be expanded that is indirectly connected to a memory expansion unit via a switching unit;

[0040] Figure 12 A schematic diagram of another topology of an embodiment of the present application showing an indirect interconnection between a host to be expanded and a memory expansion unit via a switching unit;

[0041] Figure 13 A power supply block diagram of a memory expansion unit directly interconnected with a host to be expanded provided in an embodiment of the present application;

[0042] Figure 14 A backup power-on flow chart of a memory expansion unit directly interconnected with a host to be expanded provided in an embodiment of the present application;

[0043] Figure 15 A main power-on flow chart of a memory expansion unit directly interconnected with a host to be expanded provided in an embodiment of the present application;

[0044] Figure 16 A power supply block diagram of a memory expansion unit provided in an embodiment of the present application, in which the memory expansion unit is indirectly interconnected with the host to be expanded via a switching unit;

[0045] Figure 17 A backup power-on flow chart of a memory expansion unit provided in an embodiment of the present application, in which the memory expansion unit is indirectly connected to the host to be expanded via a switching unit;

[0046] Figure 18A main power-on flow chart of a memory expansion unit provided in an embodiment of the present application, in which the memory expansion unit is indirectly connected to the host to be expanded via a switching unit;

[0047] Figure 19 A schematic diagram of a front window of a memory expansion unit provided in an embodiment of the present application;

[0048] Figure 20 A schematic diagram of a rear window of a memory expansion unit provided in an embodiment of the present application;

[0049] Figure 21 A schematic block diagram of a whole cabinet provided in an embodiment of the present application;

[0050] Figure 22 A flowchart of a control method for a memory pooling system provided in an embodiment of the present application;

[0051] Figure 23 A flowchart of a method for powering on a memory pooling system provided in an embodiment of the present application;

[0052] Figure 24 A schematic diagram of the structure of a control device for a memory pooling system provided in an embodiment of the present application;

[0053] Figure 25 A schematic diagram of the structure of a power-on device of a memory pooling system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0056] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0057] Figure 1A schematic diagram of the structure of a memory pooling system provided in an embodiment of the present application is described in detail in conjunction with the structure of the memory pooling system.

[0058] like Figure 1 As shown, the memory pooling system includes:

[0059] A memory expansion unit, comprising a memory board, a controller module, a multiplexer, and a switching module, wherein the memory board comprises a memory buffer interconnected with a plurality of memory cards;

[0060] The controller module is connected to the multiplexer via the input signal channel and the output signal channel of the adapter module;

[0061] The multiplexer is connected to the memory buffer and the memory card respectively to establish a first management link between the controller module and the memory buffer, or to establish a second management link between the controller module and the memory card;

[0062] In response to a memory management instruction, the controller module selects the first management link or the second management link to respond to the memory management instruction according to attribute information of the memory management instruction.

[0063] Among them, the memory expansion unit of this application provides large-capacity, high-bandwidth memory resource pooling capabilities for devices such as artificial intelligence accelerators and high-performance computing servers through hardware-level resource reconstruction and path dynamic management mechanism, while maintaining the constraint condition of maintaining the physical interface of the host device to be expanded unchanged.

[0064] The memory expansion unit is a physical implementation carrier of the system, and adopts a modular structure and an electrical interconnection design. The memory expansion unit includes a pluggable memory board, a controller module (such as a baseboard management controller (BMC)) that bears core control logic, a multiplexer that implements signal path switching, and a conversion module that provides interface adaptation. The memory board is a multi-layer printed circuit board (PCB) that has a memory buffer integrated on its surface. The memory buffer is a dedicated integrated circuit chip that performs physical layer conversion and data buffering between a high-speed serial protocol and a standard memory protocol. The memory buffer establishes direct electrical connections with a plurality of memory cards through on-board wiring. The memory cards can be fifth-generation double data rate synchronous dynamic random-access memory (DDR5 RDIMM) memory modules that meet the Joint Electron Device Engineering Council (JEDEC) standard. The interfaces of the memory cards are physically coupled to preset dual in-line memory module (DIMM) slots of the memory board.

[0065] The controller module is disposed inside the memory expansion unit and can be implemented by using a field-programmable gate array (FPGA) or a dedicated processor. The controller module transmits memory management instructions through an input signal channel of the conversion module and outputs memory management instructions through an output signal channel. The conversion module includes a high-speed signal relay circuit and an impedance matching network to ensure signal integrity during long-distance transmission. The controller module is connected to the multiplexer through a bidirectional control bus of the conversion module. The multiplexer is essentially a multi-channel data selector integrated circuit, and its input ports are connected to configuration interfaces of the memory buffer and serial management buses (I2C / I3C) of the memory cards.

[0066] Driven by the controller module, the multiplexer constructs two independent management paths: when the first management link is activated, the multiplexer routes the memory management instructions issued by the controller module directly to the internal control registers of the memory buffer, establishing a configuration channel for the buffer operating parameters (such as refresh policy and queue depth); when switching to the second management link, the multiplexer redirects the control path to the presence detection (SPD) interface and status monitoring bus of the memory card, allowing the controller module to directly read the physical parameters of the memory module, such as temperature and fault status.

[0067] When the system is running, the controller module continuously parses memory management instructions or other signal instructions from the external host. The memory management instructions contain attribute information, such as: operation type code, target address space identifier and access priority tag, etc. The state machine built into the controller module dynamically selects the link path based on the attribute information: for cache control instructions that require nanosecond responses (such as prefetch policy updates), the first management link is enabled to directly connect to the memory cache to reduce processing delays; for non-real-time memory status monitoring instructions (such as error log reading), it switches to the second management link directly connected to the memory card to avoid occupying cache processing resources. The path selection mechanism based on instruction characteristics ensures that management traffic is efficiently diverted on two physically isolated paths, fundamentally eliminating bandwidth competition between control instructions and data access.

[0068] The memory cache centrally drives and converts protocols for multiple memory cards, achieving a memory module integration density far exceeding that of traditional architectures within a unit of physical space. The dual-path management mechanism implemented by the multiplexer enables the controller module to dynamically optimize access paths based on instruction characteristics, ensuring real-time responsiveness to cache configuration operations while maintaining direct monitoring of physical memory status. The signal integrity design of the adapter module ensures reliable transmission of high-speed control instructions in complex interconnected environments. Through the synergistic effect of multiple modules, the external host achieves a breakthrough in obtaining a large, elastically scalable memory resource pool while maintaining the same number of physical interfaces, providing underlying hardware support for memory-intensive computing workloads.

[0069] In order to facilitate understanding of the topology information of the present application, an embodiment of the present application provides a connection topology diagram of a controller module, such as Figure 2As shown, the memory board introduces the BMC (controller module) command signal through a slim connector (Slimline connector). For memory management instructions with high access frequency and timeliness and the clock chip that is not used by default, they are directly hung under the I2C bus of the Slimline connector, thereby improving I2C access efficiency; through a transfer module (such as an I2C switch (SW)), it is divided into 8 I2C output signal channels, each channel is connected to a CXL memory buffer and its extended DIMM (memory card), and each memory card is connected to a MUX (multiplexer). In addition, the 8 channels use the same I2C topology design. It is only necessary to switch the I2C channel during the I2C access process. The same module can be used to scan the devices under the channel for monitoring and management, which is convenient for monitoring and management software and improves access efficiency.

[0070] The multiple multiplexers (MUX) are key signal selection devices. Each multiplexer has multiple input channels and one output channel. Its function is to connect the signal of a specific input channel to the output channel according to the control signal. On the memory board, the multiple memory buffers are each connected to the multiplexer, specifically, the management interface of each memory buffer (such as: I2C signal line) is connected to the input channel of the corresponding multiplexer. At the same time, the multiple multiplexers are each connected to the multiple memory cards, which means that the output channel of each multiplexer is connected to the management interface (such as I3C / I2C bus) of a group of memory cards (DDR5 RDIMM slots) it is responsible for. This makes the multiplexer an intermediate node for routing memory management instructions between the memory buffer and the memory card.

[0071] The adapter module (typically an I2C switch chip) acts as a memory management instruction hub and router. It includes multiple output signal channels (i.e., independent I2C bus ports), each of which is connected to the multiplexer. Specifically, each downstream channel port of the adapter module is connected to a control input of the multiplexer. The upstream end of the adapter module is connected to the controller module via a signal line (the I2C bus carried by Slimline).

[0072] The controller module is also used to dynamically switch the management link of the management instruction according to the memory management instruction. The memory management instruction refers to the instruction initiated by the controller module for management, and its core is the management target (memory buffer or memory card) and attribute information. Dynamic switching refers to the controller module selecting the optimal instruction transmission path in real time before each management or based on the policy. The memory management instruction refers to the data stream (such as reading the status register, writing the configuration parameters) sent or received by the controller module for managing or monitoring the device (memory buffer or memory card). The management link refers to the physical and logical path that the memory management instruction passes through from the controller module to the target device.

[0073] The memory pooling system of the present application, through the dynamic selection mechanism of the multiplexer of the memory expansion unit, that is, the first management link of the controller module managing the memory buffer or the second management link of the controller module managing the memory card, makes the external device to be expanded not need to participate in the management of the memory device. In the case of limited number of physical pins, only the memory buffer and the memory card need to be connected to realize large-capacity memory expansion. The memory board forms a pooling resource pool by configuring the memory card for expansion, and the multiplexer efficiently multiplexes the limited signal channels of the switching module, so that the controller module can intelligently switch the management path according to the instruction attribute, quickly access the memory buffer through the first management link to optimize high-frequency interaction, or directly connect the memory card through the second management link to realize high-bandwidth parallel data access. Ultimately, the device to be expanded breaks through the physical pin limit and synchronously obtains large-capacity and high-bandwidth memory expansion capability, effectively bridging the algorithm and storage gap of artificial intelligence accelerators. Therefore, the technical problem of how to realize large-capacity and high-bandwidth memory expansion can be solved, and the technical effect of providing greater memory bandwidth and higher memory capacity density can be achieved.

[0074] In an implementable manner of an embodiment of the present application, the memory buffer is connected with the host to be expanded, and the memory card is used for memory expansion of the host to be expanded.

[0075] The memory buffer accesses the corresponding target memory card according to the memory card identifier carried in the memory access instruction in response to the memory access instruction initiated by the host to be expanded.

[0076] Among them, the host to be expanded refers to a computing device that needs to expand memory resources, including but not limited to artificial intelligence accelerator cards, high-performance computing servers, or general-purpose processor platforms, which establish physical connection with the memory expansion unit through high-speed serial interfaces (such as Compute Express Link (CXL) protocol interfaces).

[0077] The memory buffer acts as a protocol conversion hub and directly carries electrical signal interaction from the host to be expanded. Its physical interface is coupled with the host interface using high-speed differential signal pairs to realize signal level matching and timing synchronization. The memory buffer internally integrates a protocol conversion engine to decode the serialized memory operation instructions sent by the host into a parallel instruction set recognizable by the standard memory controller, and repackage the parallel data returned by the memory card into a high-speed serial format.

[0078] Memory cards, as carriers of actual physical memory resources, implement memory expansion for the host through memory buffers. This expansion process is implemented at two levels of abstraction: at the electrical level, the memory card's standard DDR5 RDIMM signals undergo impedance transformation and driver enhancement to meet long-distance transmission requirements; at the logical level, the memory buffers dynamically map the continuous virtual address space accessed by the host to the discrete physical address segments of multiple memory cards, allowing the host operating system to recognize multiple memory cards as a uniformly addressed memory pool.

[0079] When the host to be expanded initiates a memory access instruction, the memory access instruction contains the virtual address of the target data and the operation type (read / write). After receiving the instruction, the memory cache parses the implicit memory card identifier. The memory card identifier is dynamically generated by the address mapping table and is specifically expressed as a preset code in the high-order segment of the address, which is used to indicate the physical location of the target memory card on the memory board (such as the DIMM slot number). The memory cache activates the chip select signal of the corresponding memory card based on the identification code, and at the same time converts the virtual address in the memory access instruction into the physical row / column address inside the target memory card, and finally sends the operation instruction to the target memory card through the DDR5 RDIMM command bus.

[0080] During the access process, the memory buffer performs a key intermediary function: for read operations, it receives data returned by the target memory card and caches it in an internal queue, then returns it to the host after protocol encapsulation. For write operations, it reassembles the serial data stream sent by the host into a DDR5 RDIMM data burst sequence and writes it to the specified address according to the timing requirements of the target memory card. A directional access mechanism based on identification codes enables a single memory buffer to efficiently schedule the parallel operations of multiple memory cards, achieving flexible expansion of physical memory resources while maintaining host interface protocol consistency.

[0081] The memory pooling system decouples computing and memory resources through an innovative hardware architecture, providing a large, sharable memory resource pool for hosts waiting for expansion. The memory expansion unit, a physical carrier independent of the host, carries the core functionality of memory resource pooling. The memory expansion unit comprises multiple memory boards and a management backplane, forming the key hardware foundation.

[0082] The multiple memory boards are arranged in a vertical stacking configuration, and this spatial layout significantly improves the memory component carrying density within a unit rack space. Each memory board is integrated with multiple memory components, which are the basic units that constitute the memory resource pool. Each memory component is equipped with a first interface, which serves as a physical channel for high-speed communication and is used to receive memory access requests and data streams from the host to be expanded. In the specific implementation of this system, the first interface specifically refers to a CDFP interface that complies with the CXL (Compute Express Link) high-speed interconnection standard, which establishes a physical link with the host to be expanded through a first cable (i.e., a DAC copper cable that carries the CXL protocol).

[0083] The memory buffer at least supports dual-mode clock input, and the dual-mode clock at least includes a local asynchronous clock source and a host synchronous clock source.

[0084] The core functions of the memory expansion unit are implemented by the memory board. Each memory board, based on its multiple integrated first interfaces (CDFP interfaces), provides high-speed interconnection with one or more hosts to be expanded (i.e., computing devices requiring additional memory resources, such as central processing units (CPUs) or graphics processing units (GPUs)) via a first cable. The memory board, through its multiple memory components, provides the hosts with memory resource expansion capabilities far beyond their local limitations. The memory components comprise a key functional chip, the memory buffer, and the standard memory module slots (supporting general-purpose DDR5 RDIMMs) driven by it. Its operating principle is as follows: the memory board receives a first signal (i.e., a high-speed serial electrical signal compliant with the CXL protocol) input via the first interface. The memory buffer in each memory component performs the core signal conversion operation. The memory buffer decodes the input CXL protocol signal (first signal) and regenerates it into parallel memory signals compliant with the standard DDR5 RDIMM specification, thereby driving the connected standard DDR5 RDIMM memory module. The conversion process realizes the protocol adaptation and electrical matching from the high-speed serial interface to the universal memory interface, so that the host to be expanded can transparently access the massive memory resources pooled in the memory expansion unit just like accessing local memory.

[0085] The host to be expanded only needs to connect to the memory cache through a limited high-speed serial interface to transparently access pooled resources that far exceed its local memory capacity; the memory card identification mechanism enables memory access instructions issued by the host to be accurately routed to a specific physical memory module, avoiding address conflicts when multiple cards operate concurrently; the protocol conversion and address mapping functions of the memory cache completely encapsulate the operational differences of heterogeneous memory hardware (host serial interface and memory card parallel bus), providing unified memory access semantics for upper-level applications.

[0086] In one implementation of the embodiment of the present application, the controller module is further configured to:

[0087] In response to a memory management instruction to the memory buffer or the memory card, determining attribute information corresponding to the memory management instruction;

[0088] When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory card, managing the memory card based on the second management link;

[0089] When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory buffer, the memory buffer is managed based on the first management link.

[0090] When the memory expansion unit receives a memory management instruction from an external management entity (such as the host BMC or remote management software), the controller module first performs an instruction decoding operation. This operation extracts attribute information embedded in the instruction, including but not limited to: a target device identifier, which distinguishes whether the instruction is targeting internal registers of the memory cache or the physical memory card hardware unit; and an operation type code, which identifies whether the instruction belongs to a management category such as configuration update, status query, or fault diagnosis. The controller module's built-in instruction classifier parses this attribute information based on a preset set of rules and generates a path selection decision signal.

[0091] If a memory management instruction is determined to be performing a management operation on the memory card (including but not limited to reading memory card temperature sensor data, querying the error status register, or updating SPD configuration parameters), the controller module activates the second management link. At this point, the multiplexer switches to the physical path connected to the memory card management bus, and the controller module directly accesses the memory card's I2C / I3C interface through this link. For status query instructions, the controller module reads the physical parameters returned by the memory card and encapsulates them into a management response message. For configuration update instructions, the controller module writes the configuration data to the specified register address of the memory card. This direct path avoids interference from the protocol conversion layer, ensuring the authenticity of the physical status monitoring data.

[0092] When attribute information indicates that memory management instructions apply to the memory buffer itself (including but not limited to adjusting the buffer refresh policy, setting queue depth parameters, or updating the address mapping table), the controller module activates the first management link. The multiplexer then establishes a direct connection between the controller module and the internal control registers of the memory buffer: the controller module modifies the buffer operating parameters through write operations and obtains the internal status of the buffer (such as queue occupancy and protocol error counters) through read operations. This path skips the memory card access link, significantly reducing the latency of configuration operations.

[0093] The controller module accurately distinguishes management objects through attribute information, enabling high-frequency cache configuration operations to achieve nanosecond response capabilities through the first management link, while ensuring that the physical status monitoring of the memory card maintains the integrity of the original data through the second management link; the dual-path physical isolation design completely eliminates resource competition between management instructions, preventing key configuration instructions from being blocked by batch status queries; the dynamic routing mechanism based on instruction type maximizes the utilization of limited management channel bandwidth, improving the monitoring and management efficiency of large-scale memory pools.

[0094] In one implementation of the embodiment of the present application, the memory expansion unit further includes: a management baseboard,

[0095] The controller module is configured on the management baseboard, the management baseboard is connected to the memory board, and the controller module exchanges information with the memory board based on the management baseboard;

[0096] The controller module receives the status information transmitted by the memory board, and monitors the status of the memory board according to the status information to generate monitoring data;

[0097] The controller module is further configured to generate a monitoring log based on the monitoring data and the status information.

[0098] The controller module is configured on the management baseboard in the form of a snap-on, and exchanges information with the memory board through the communication bus preset on the management baseboard. The communication bus includes parallel data channels, control signal lines, and interrupt request lines, and uses impedance matching wiring to ensure high-speed signal integrity. As the core processing unit of the management baseboard, the controller module continuously obtains status information transmitted by the memory board through polling or event triggering mechanisms. The status information specifically includes but is not limited to: operating parameters from the memory cache (such as: protocol error counter value, queue occupancy); physical sensor data from the memory card (such as: temperature sampling value, power supply voltage fluctuation); interconnection interface status (such as: CXL link training results, bit error rate statistics).

[0099] The controller module performs real-time analysis and processing of status information. It verifies data validity through built-in state machine logic, converts raw sensor readings into engineering units (e.g., Celsius), and compares them against preset thresholds. When an anomaly is detected (e.g., a memory card temperature exceeding a certain limit or a surge in buffer error counts), the controller module immediately generates corresponding monitoring data, including the anomaly type, occurrence timestamp, physical location code, and severity level, and simultaneously triggers an alarm flag update.

[0100] Based on continuously collected status information and dynamically generated monitoring data, the controller module constructs a time series database and synthesizes monitoring logs according to a pre-set log format. Log entries contain, but are not limited to, fixed headers (timestamp, event identifier (ID)) and variable payloads (specific parameters) and can be stored in non-volatile memory using a circular buffer mechanism. The log generation process performs data compression and key event tagging to ensure that key anomalies can be quickly located during fault diagnosis.

[0101] The management backplane serves as the central control and coordination hub within the memory expansion unit. The controller module on it integrates a baseboard management controller (BMC) and a complex programmable logic device (CPLD). The management backplane provides a stable power supply to the controller module through a dedicated power backplane and signal routing circuits. It also facilitates electrical connections and protocol conversion for various management, monitoring, and control signals between the controller module and the memory board. This design ensures the effective transmission of management commands and the real-time collection of status information throughout the system.

[0102] The management backplane provides a unified hardware platform to achieve physical layer decoupling of the controller module and memory board, enhancing system maintainability. The centralized collection and processing of status information enables the controller module to perceive the working status of the memory board in real time and identify potential failure risks in advance. The structured storage of monitoring logs provides a complete data chain for system health analysis, significantly improving the observability and operation and maintenance efficiency of the memory pooling system.

[0103] In order to facilitate understanding of the structure of the memory expansion unit, the embodiment of the present application provides a top view of the entire memory expansion unit, as shown in FIG. Figure 3 As shown, and a whole machine explosion diagram of a memory expansion unit, such as Figure 4 shown.

[0104] The memory expansion unit further includes: a power backplane, a power supply unit, and a fan module.

[0105] The power supply unit supplies power to the management baseboard through the power backplane, wherein the power supply unit is redundantly designed in the memory expansion unit;

[0106] The fan module is used to dissipate heat for the memory expansion unit. The fan module is designed with rotor redundancy and is configured in the memory expansion unit in a hot-swappable manner.

[0107] The controller module is used to perform logic control on the memory expansion unit and fan control on the fan module, wherein the controller module is configured on the management baseboard in the form of a daughter card;

[0108] The management baseboard is connected to the multiple memory boards through power lines and first signal lines respectively. The controller module is further configured to perform signal transmission processing based on the management baseboard and the multiple memory boards through the first signal lines respectively.

[0109] The power supply unit can adopt a common redundant power supply (CRPS) to provide power distribution for the entire memory expansion unit through a dedicated power backplane. The power backplane serves as the hub of power transmission, efficiently and safely routing the input power from the power supply unit to the management backplane and other power-requiring components. The power supply unit implements a redundant design in the system, specifically by configuring two independent power supply units and operating in a 1+1 redundant mode. When any power supply unit fails, the other unit can seamlessly take over the entire load, ensuring that the memory expansion unit continues to receive a stable power supply, thereby significantly enhancing the system's ability to resist power failures and ensuring the continuity of pooled memory services.

[0110] To address the heat dissipation challenges brought about by high-density memory expansion, the system integrates a highly efficient fan module. This module consists of multiple fans and adopts a rotor redundancy design (commonly known as N+1 redundancy). Even if a single fan fails and stops working, the remaining fans can still provide sufficient forced airflow to prevent the system from shutting down due to local overheating, effectively ensuring that key memory components operate at an appropriate temperature. In addition, the fan module supports hot-swappable configuration and replacement, allowing administrators to directly remove the faulty fan and insert a new one without powering off the system or interrupting service. This greatly simplifies maintenance operations, significantly improves the serviceability of the system, and reduces the complexity of operation and maintenance.

[0111] The controller module's functionality extends further to encompass the entire system's logic and fan control. Using its embedded complex programmable logic device (CPLD), the module performs low-level hardware logic control, such as driving system status indicators and managing power sequencing. Simultaneously, its baseboard management controller (BMC) implements fan control strategies. By monitoring temperature sensor data from the memory boards and memory components in real time, it dynamically adjusts fan speed, meeting cooling requirements while optimizing system noise and energy consumption.

[0112] At the physical connection level, the management backplane not only hosts the controller module but also connects to the multiple stacked memory boards via dedicated power cables, providing them with the necessary operating power. Signal lines also establish a high-speed, reliable memory management instruction channel between the management backplane and each memory board. One of the core functions of the controller module is to perform signal transmission processing with the multiple memory boards via the signal lines based on the management backplane. This includes, but is not limited to: real-time collection of status information (such as temperature, voltage, fault alarms) of each memory board and memory component, memory error logs; issuing configuration instructions or firmware upgrade packages to the memory boards; transmitting fan control signals; and collaboratively processing memory resource access and management tasks. Through a centralized and standardized signal transmission architecture, the complexity of internal system communications is greatly simplified, ensuring the efficient execution of management instructions and real-time status monitoring.

[0113] By introducing a power backplane, redundant power supply units, redundant fan modules, and enhancing the functionality and connectivity of controller modules, this system achieves multiple technical benefits: The redundant power supply and fan design significantly improves overall system reliability and availability, ensuring robust fault tolerance for memory pool services in the face of component failures; the centralized power distribution of the power backplane optimizes internal power supply efficiency and safety; the hot-swappable fan feature combined with intelligent speed control significantly enhances maintainability and optimizes heat dissipation efficiency; and centralized signal transmission and processing via the Slimline connector strengthens the controller's global awareness and precise control of system-wide status, laying a solid management foundation for the stable and efficient operation of large-scale memory pools.

[0114] Furthermore, in order to facilitate understanding of the structure of the memory expansion unit, an embodiment of the present application provides an interconnection topology diagram of the memory expansion unit, such as Figure 5 As shown, and a memory board interconnection topology diagram, such as Figure 6 As shown in the figure, the key boards include two memory boards and one management baseboard. The separate design of the memory board and the management baseboard increases the utilization rate of the modular design and greatly increases the maintainability of the entire machine, making board maintenance more convenient.

[0115] The memory board's chip-to-chip embedded processor interface (CDFP) is connected to the retimer card on the host to be expanded via a CDFP cable. The memory expansion for each host is achieved via the Compute Express Link (CXL) high-speed serial interface.

[0116] All key management, control, and status monitoring signals for the memory board are connected to the RunBMC module (controller module) on the backplane via a slimline connector. RunBMC indicates that the controller module is snap-fitted to the management baseboard. This module monitors the status of the memory board in real time. If an abnormality (chip malfunction, CXL link error alarm, memory error alarm) occurs, the RunBMC module transmits the data to the upper level and simultaneously detects the signal's detailed timescale, saving it as a log to a TransFlash (TF) card. This allows users to easily retrieve and analyze the cause of the abnormality.

[0117] The RunBMC's serializer (Serdes) signals are connected to the memory board's physical layer (PHY) chip via a Slimline connector. The media-dependent interface (MDI) signals output by the PHY are connected to the RJ45 (Registered Jack-45) connector, which serves as the RunBMC management network port for inter-device communication. The RunBMC and CPLD are responsible for overall system management, including heat dissipation control, system power on and off, status indication, and interaction with other cabinet devices.

[0118] Each memory board contains multiple memory buffers (for example, 8 CXL memory buffer chips). Each memory buffer is connected to the HOST through a CDFP interface. Each memory buffer can expand a set of CXL signals into 4 standard DDR5 RDIMM interface signal memories. A single memory board can expand universal DDR5 RDIMMs (for example, 32 universal DDR5 RDIMMs can expand the entire machine to 64), enabling high-density and large-capacity universal memory expansion. The CXL memory buffer can choose a local asynchronous clock and a synchronous clock sent by the HOST to meet the different clock topology requirements of different customers. The I2C management interface of each memory buffer is connected to the management baseboard through a slimline connector and is centrally managed by RunBMC. Cache configuration and firmware upgrades can be implemented according to customer needs. The memory board is also designed with a management network port to the front panel for accepting management from RunBMC on the memory board.

[0119] It should be noted that each of the multiple memory boards is configured with a physical layer chip and a second interface, and the physical layer chip is connected to the second interface; the controller module is connected to the physical layer chip through a signal line, and transmits the communication signal to the physical layer chip through the signal line; the physical layer chip is used to convert the communication signal into a physical layer signal, and transmit the physical layer signal to the second interface to enable inter-device communication between the memory expansion unit and other devices.

[0120] The multiple memory boards further integrate key communication interface hardware to enhance the overall manageability of the memory expansion unit and its ability to interact with the external environment. Specifically, each memory board is equipped with a physical layer chip and a second interface. The physical layer chip and the second interface are directly electrically connected, forming the physical foundation for inter-device communication.

[0121] The physical layer chip (typically a PHY chip compliant with Ethernet standards) is the core integrated circuit responsible for processing the underlying electrical signal conversion of network communications. Its core function is to convert logical signals at the data link layer into analog signals actually transmitted by the physical medium. In this context, the second interface specifically refers to a standard RJ45 connector, a modular physical receptacle interface widely used in Ethernet communications that supports the insertion of standard network cables.

[0122] To enable communication between the memory expansion unit and other network devices, the controller module (RunBMC) acts as a communication signal source. The controller module establishes an electrical connection with the physical layer chip on the memory board via a second signal line (specifically, an MDI signal line that complies with the Media Dependent Interface specification). The controller module generates communication signals (i.e., high-level logical data packets) representing attribute information, status reports, or control instructions, and transmits these communication signals to the physical layer chip via the second signal line (MDI line).

[0123] After receiving the communication signal from the controller module, the physical layer chip performs its core conversion function. It encodes, modulates, and drives the incoming MDI-compliant communication signal (essentially a digital logic level) according to the requirements of the Ethernet physical layer protocol, generating a physical layer signal (i.e., an analog differential electrical signal) that can be stably transmitted over the twisted pair medium. The physical layer chip then outputs the converted physical layer signal directly to the second interface (RJ45 connector) connected to it.

[0124] Through the second interface (RJ45), these physical layer signals are injected into the standard Ethernet cable, thereby achieving inter-device communication between the memory expansion unit and other devices. Other devices mainly refer to switches or hosts to be expanded. The specific connotations of inter-device communication include: the controller module (RunBMC) uses this channel to achieve remote out-of-band management (for example: receiving management commands, reporting system status, transmitting alarm information); the memory expansion unit and the second controller of the Host or Switch BOX (transfer unit) exchange attribute information (such as: power-on status synchronization, topology identification); and possible communication with other chassis or central management platforms.

[0125] By introducing a physical layer chip (PHY) and a second interface (RJ45) driven by a controller module, a standardized network communication interface (RJ45) is directly integrated on the memory board, providing an independent and reliable out-of-band management channel for the entire memory expansion unit, significantly enhancing the system's remote manageability and integrability. Efficient signal conversion is achieved using the physical layer chip, ensuring that management communications generated by the controller module can be transmitted stably and at high speed on a common Ethernet physical medium. The network interface function is distributed to the memory board and connected to the controller module on the backplane via a second signal line (MDI). While maintaining a centralized management architecture, the complexity and reliability of inter-board signal routing are optimized, allowing the memory expansion unit to be efficiently monitored and managed as a standard node in the data center network, greatly simplifying operation and maintenance operations in large-scale deployment environments.

[0126] In one implementation of the embodiment of the present application, multiple memory buffers are layout-processed in the memory expansion unit in the form of layout groups, wherein each layout group includes two memory buffers, and the wiring methods in different layout groups are the same.

[0127] In order to facilitate understanding of the layout of the memory buffer, the embodiment of the present application provides a layout diagram of the memory buffer, such as Figure 7 As shown, and a physical picture of a memory expansion unit, such as Figure 8 shown.

[0128] The physical implementation of the multiple memory buffers utilizes a highly optimized organizational strategy. The memory buffers can be arranged within the memory expansion unit in the form of layout groups. A layout group refers to a simple layout method and has no functional connection. For example, each layout group includes two memory buffers.

[0129] The routing scheme within each layout group is the same. The routing scheme refers to the electrical interconnect implementation scheme, including but not limited to: signal lines (such as high-speed CXL, memory bus, clock lines, control lines, power / horizontal lines), routing paths on each PCB layer, line width, line spacing, via usage, reference plane design, impedance control strategy (such as 100 ohm differential impedance), equal length matching requirements, and anti-interference shielding measures. Each layout group follows a completely consistent design template and rule set, ensuring a high degree of symmetry and predictability in the electrical characteristics of different layout groups.

[0130] By organizing multiple memory buffers into layout groups containing two buffers and ensuring that all layout groups use the same routing method, the design cycle is significantly shortened and design risks are reduced. This consistency also greatly facilitates system debugging and tuning, eliminating the need for repetitive work for each local area, significantly improving debugging efficiency. Consistent physical implementation also enhances the standardization of manufacturing and testing, which helps improve product yield and simplify the production test process. This approach based on layout groups and unified routing can improve system consistency, facilitate debugging and tuning, and enhance system stability.

[0131] In one implementation of the embodiment of the present application, the memory expansion unit is directly interconnected with the host to be expanded through a first cable, or the memory expansion unit is indirectly interconnected with the host to be expanded through the first cable via a switching unit;

[0132] The first cable is provided with an information storage device for storing a cable identification and a cable status of the first cable and a topological relationship between the memory expansion unit and the host to be expanded, wherein the cable status includes at least a connection status between the first cable and the host to be expanded.

[0133] The memory pooling system offers two optional connection modes: direct connection mode, in which the memory expansion unit establishes a point-to-point connection with the host to be expanded via a first cable; and in indirect connection mode, in which the memory expansion unit forms a star topology connection with the host to be expanded via a switching unit (such as a CXL switch). Both modes share the same underlying communication protocol and signal transmission specifications.

[0134] The first cable can adopt a high-speed differential signal transmission structure, and an electromagnetic shielding layer is externally wrapped to reduce signal crosstalk. High-density connectors (such as CDFP interfaces) are assembled at both ends of the cable to ensure the physical connection stability of the host and the expansion unit through a mechanical locking mechanism. An information storage is integrated in the middle of the cable or inside the connector. The information storage is a non-volatile storage chip (such as an Electrically Erasable Programmable Read-Only Memory (EEPROM)), and the data interface of the information storage is coupled with the connector pin through a dedicated auxiliary channel (such as an I2C bus).

[0135] The information storage internally stores at least three kinds of data:

[0136] 1. Cable identification, including at least a globally unique identification code (such as a 48-bit Media Access Control (MAC) address), a manufacturer code, and cable specification parameters (length, bandwidth level);

[0137] 2. Cable status, including at least a physical connection state flag bit (connected / disconnected), a signal integrity indicator (error rate history value), and a hot plug event counter;

[0138] 3. Topology relationship, including at least a current connection topology type identification code (direct connection / relay), a relay unit device code (in indirect mode), and a host port logical address mapping information.

[0139] The management controller (first controller or second controller) of the host to be expanded or the relay unit reads the information storage data through the auxiliary channel. The controller module synchronously acquires the information, dynamically adjusts the working mode by analyzing the topology relationship data: in the direct connection mode, a simplified communication protocol stack is enabled to reduce transmission delay; in the indirect connection mode, a multi-hop routing table is activated to adapt to the relay characteristics of the relay unit. At the same time, the controller module continuously monitors the cable status data, and when detecting connection state abnormalities (such as repeated hot plug) or signal quality degradation (error rate exceeding threshold), triggers a warning event and records it to the monitoring log.

[0140] Among them, the device to be expanded acts as a demand side: directly connecting a memory buffer (for data channel) or a memory card (for data channel), and connecting a controller module (for control signal interaction).

[0141] The controller module acts as an internal scheduling hub of the memory expansion unit: dynamically selecting a link (first / second management link) through a multiplexer; and deciding the optimal data path according to the instruction attribute.

[0142] Capacity expansion: The device to be expanded only needs to connect to the memory board to access the pooled memory card resources (no need to add independent pins for each memory card); Bandwidth guarantee: The link selection mechanism of the controller module enables the same set of physical pins to serve both the memory cache (low latency) and the memory card (high throughput), maximizing pin utilization; Computing and storage bridging: External devices can simultaneously improve memory capacity and access efficiency without changing the pins, supporting the computing needs of large artificial intelligence models.

[0143] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a connection topology diagram of the host to be expanded, such as Figure 9 As shown, each CDFP is equipped with an I2C bus expander (such as PCA9554). The BMC (first controller) on the host side reads the SDFPID through the I2C link (CDFP_0_HOST_I2C) on the CDFP cable, and then notifies the controller module of the CDFP ID information connected to the host through the signal line, thereby identifying the host connected to each CDFP interface and realizing the recognition of the memory expansion topology of the entire cabinet.

[0144] Further, in order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a topology diagram of direct interconnection between the host to be expanded and the memory expansion unit, such as Figure 10 As shown in FIG, and a topology diagram of an indirect interconnection between a host to be expanded and a memory expansion unit via a transfer unit, as shown in FIG. Figure 11 As shown in FIG, another topology diagram of the host to be expanded is indirectly connected to the memory expansion unit through the adapter unit, as shown in FIG. Figure 12 shown.

[0145] The switching unit refers to a switch device (such as CXLSwitchBOX), whose core function is to establish a configurable high-speed interconnection path between multiple hosts to be expanded and multiple memory expansion units, so as to realize the centralized pooling and dynamic allocation of memory resources.

[0146] The memory board is interconnected with external devices via a first cable (e.g., a CXL direct attach cable (DAC)) based on multiple integrated CDFP interfaces, specifically in two optional connection modes:

[0147] The first mode is direct interconnection: the memory board is directly connected to the host to be expanded via a first cable using the CDFP interface. This method offers the greatest advantage in that it minimizes signal paths, resulting in relatively minimal access latency. The response speed of the host to access the expanded memory approaches that of local memory. However, its scalability is limited by the number of CXL interfaces available to a single host. Typically, it can only provide fixed allocations of memory expansion resources to one or a limited number of hosts, and cannot dynamically share and redistribute memory resources across multiple hosts.

[0148] The second mode involves interconnection via an adapter unit: the memory board is connected to the adapter unit via a first cable based on the CDFP interface, and is then interconnected with the host to be expanded through the adapter unit. Although this approach increases access latency due to the added switching link, it offers significant advantages: First, the adapter unit provides far more interfaces than a single host, supporting the connection of a larger number of hosts to be expanded and memory expansion units, thereby achieving a larger pool of memory resources. Second, the adapter unit typically supports cascading expansion, allowing for connection to multiple levels of switches or memory expansion units, further expanding the absolute capacity of the memory pool. Third, the adapter unit offers extremely high connection flexibility, and the ratio of its uplink ports (for connecting hosts) to its downlink ports (for connecting memory expansion units) can be flexibly configured based on actual application requirements. Fourth, the adapter unit's intelligent switching capabilities enable dynamic allocation of memory resources. Specifically, the range or quota of the downlink memory expansion unit resource pool accessible to each host to be expanded is dynamically adjusted based on the real-time memory requirements of each host to be expanded, achieving true on-demand allocation and resource sharing.

[0149] The two interconnection modes of the First Cable provide physical layer flexibility for different application scenarios. The direct connection mode meets low latency requirements, and the indirect mode supports large-scale pooling expansion. The embedded information storage device enables the cable to have identity authentication and status self-diagnosis capabilities, significantly improving the reliability of system deployment. The automatic identification of topological relationships eliminates manual configuration steps, ensuring that the memory expansion unit can be plug-and-play connected to heterogeneous computing environments.

[0150] In one implementation of the embodiment of the present application, if the memory expansion unit is directly interconnected with the host to be expanded through the first cable, the memory expansion unit and the host to be expanded are powered on using a first power-on method;

[0151] If the memory expansion unit is indirectly interconnected with the host to be expanded through the first cable, the memory expansion unit, the switching unit, and the host to be expanded are powered on using a second power-on method.

[0152] When the memory expansion unit establishes direct interconnection with the host to be expanded through the first cable (i.e. point-to-point connection without intermediate switching device), a first power-on mode is enabled. In the first power-on mode, the first controller of the host to be expanded and the controller module of the memory expansion unit establish a communication session through a network management interface. After the host to be expanded completes self standby power supply stabilization, the host to be expanded sends a standby power supply ready signal to the controller module of the memory expansion unit; after the controller module confirms that the local standby power supply is normal, the controller module continuously monitors the physical button state. When the user triggers the power button of the memory expansion unit, the main power-on is performed and the main power supply completion signal is sent to the first controller of the host to be expanded through the controller module, and the host to be expanded performs main power-on after receiving the signal. The main power-on timing of the memory expansion unit is strictly ahead of the initialization phase of the host to be expanded, avoiding system startup failure caused by unready memory resources.

[0153] When the memory expansion unit forms indirect interconnection with the host to be expanded through the first cable via the switching unit, the system switches to a second power-on mode. At this time, the host to be expanded, the switching unit and the memory expansion unit form a three-level cascading architecture, and the second controller of the switching unit is designated as the master node. After self-checking in the standby power supply stage, the three parties respectively send the standby power supply ready state to the second controller of the switching unit. When the user triggers the power button of the switching unit, the second controller coordinates the power-on process in two steps: first, sends a main power supply enable instruction to the internal controller module, and after confirming that the main power supply of the memory expansion unit is stable, sends a main power supply enable instruction to the second controller of the host to be expanded. The segmented power-on mechanism ensures that the memory expansion unit completes initialization first, the switching unit second, and the host to be expanded last, forming a strict bottom-up power supply ready chain.

[0154] By automatically identifying the topology relationship data stored in the first cable, the power-on strategy suitable for the current connection mode is dynamically selected, and the manual configuration link is eliminated; the bidirectional handshake mechanism in the direct interconnection mode guarantees the rapid collaborative startup of the point-to-point topology; the three-level segmented power-on design in the indirect interconnection mode completely solves the timing conflict risk in the multi-device cascading, and ensures that the memory resources are completely ready before the host initialization.

[0155] In an implementable manner of the embodiment of the application, the memory expansion unit comprises a first programmable device for power-on, and the host to be expanded comprises a second programmable device for power-on and a first controller;

[0156] The power-on processing of the memory expansion unit and the host to be expanded through the first power-on mode comprises:

[0157] The memory expansion unit and the host to be expanded respectively perform backup power-on processing by turning on power, and generate a first backup power completion signal corresponding to the memory expansion unit and a second backup power completion signal corresponding to the host to be expanded;

[0158] The first programmable device is used to obtain the first backup power completion signal and send the first backup power completion signal to the controller module;

[0159] The second programmable device is used to obtain the second backup power completion signal and send the second backup power completion signal to the first controller, and the first controller sends the second backup power completion signal to the controller module;

[0160] The controller module is further configured to determine the power-on status of the memory expansion unit and the host to be expanded as a backup power completion status according to the first backup power completion signal and the second backup power completion signal.

[0161] Among them, a first programmable device (such as a complex programmable logic device CPLD) is deployed inside the memory expansion unit, and the power timing control function is realized through hardware description language programming; the host side to be expanded is correspondingly configured with a second programmable device and a first controller (that is, the baseboard management controller BMC of the host to be expanded), and the three work together to complete distributed power status management.

[0162] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a power supply block diagram in which a memory expansion unit is directly interconnected with a host to be expanded, such as Figure 13 As shown, and a standby power-on flow chart of a memory expansion unit directly interconnected with the host to be expanded, as shown Figure 14 shown.

[0163] The first power-on method includes backup power-on processing and main power-on processing. The backup power-on processing process specifically includes but is not limited to the following steps:

[0164] When external power is input, the memory expansion unit's power supply unit (PSU) first converts it into standby power (i.e., standby power STBY), which provides the basic operating voltage for the control circuit. The first programmable device continuously monitors the standby power output voltage of the standby voltage regulator (STBYVR). When it detects that the voltage value is stable within a preset threshold range and persists for a minimum hold time, it generates a first standby power completion signal. The first standby power completion signal is an active-high digital pulse and is transmitted via a parallel bus to the controller module's general-purpose input / output interface.

[0165] Synchronously, the same operation is performed on the host to be expanded: after the power module generates independent backup power, the second programmable device verifies the stability of the power supply through the voltage comparator circuit, and generates a second backup power completion signal. The second backup power completion signal is sent to the first controller through the serial peripheral interface of the second programmable device, and the first controller encapsulates it into a network data packet and transmits it to the controller module of the memory expansion unit via the management network.

[0166] The controller module performs logical verification on the double-ended signal: when the first backup power completion signal and the second backup power completion signal are received at the same time, and the timestamp difference between the two is less than a preset synchronization window (for example, 200 milliseconds), the global state register of the memory expansion unit and the host to be expanded is updated to a backup power completion state, and the controller module encodes this state and broadcasts it to the system management bus, providing a prerequisite for subsequent main power enablement.

[0167] Through the distributed monitoring mechanism of the double programmable devices, the risk of power state misjudgment caused by single point failure is eliminated; the time domain verification of the controller module on the double-ended signal ensures the strict synchronization of the power state across devices; the state encoding mechanism provides a unified state judgment reference for multi-node systems, avoiding cascading failures caused by local power anomalies.

[0168] In an implementation manner of the embodiment of the application, the memory expansion unit further comprises a first power chip, and the host to be expanded further comprises a second power chip;

[0169] The power-on processing of the memory expansion unit and the host to be expanded through the first power-on mode further comprises:

[0170] In response to the memory expansion unit and the host to be expanded being in a backup power completion state, and the first startup signal triggered by the memory expansion unit, the first programmable device controls the first power chip to perform main power-on processing on the memory expansion unit and generates a first main power completion signal;

[0171] The controller module forwards the first main power completion signal to the second programmable device through the first controller;

[0172] The second programmable device controls the second power chip to perform main power-on processing on the host to be expanded in response to the received first main power completion signal, and generates a second main power completion signal;

[0173] The second programmable device forwards the second main power completion signal to the controller module through the first controller;

[0174] The controller module is also configured to determine the power-on state of the memory expansion unit and the host computer to be expanded as a main power completion state according to the received first main power completion signal and the second main power completion signal.

[0175] For the convenience of understanding the embodiments of the present application, the embodiments of the present application provide a main power-on flowchart of a memory expansion unit and a host computer to be expanded directly interconnected, as shown in Figure 15

[0176] The main power-on processing process includes but is not limited to the following steps:

[0177] When the system is in a standby power completion state and a user triggers a physical power button of the memory expansion unit, a first boot signal is generated, which is a rising edge triggered digital pulse. After the first programmable device captures the first boot signal, an active level is output to the enable pin of the first power chip, starting the main power conversion process of the memory expansion unit. After the output voltage of the first power chip (such as a main voltage regulator (Main VR) and a STBY VR) stabilizes to reach a nominal value and lasts for more than a preset time length (such as 10 milliseconds), a first main power completion signal is returned to the first programmable device through a power good (PG) pin.

[0178] The controller module obtains the first main power completion signal through a local bus, encapsulates it as a management message, and sends it to the first controller of the host computer to be expanded through a network management interface. The first controller analyzes the message content and forwards the first main power completion signal through a serial configuration interface of the second programmable device.

[0179] After the second programmable device receives the first main power completion signal, an active instruction is output to the enable pin of the second power chip, triggering the main power-on sequence of the host computer to be expanded. After the second power chip completes the voltage stabilization output, a second main power completion signal is returned to the second programmable device through the PG pin. The second main power completion signal is returned to the controller module of the memory expansion unit through the first controller.

[0180] The controller module performs a cooperative check on the double-ended main power state: when the first main power completion signal and the second main power completion signal are both valid, and the time interval between the two is less than the maximum deviation window allowed by the system, the global state register is updated to a main power completion state.

[0181] ​Through the cascaded main power enable mechanism, the memory expansion unit is strictly guaranteed to complete the main power initialization before the host to be expanded, eliminating the risk of host memory controller access delay; the closed-loop verification of the dual main power completion signal ensures the atomic switching of power states across devices; the timing control based on the hardware signal chain avoids the uncertainty introduced by software delays, improving the startup reliability of large-scale memory pool systems.

[0182] In one implementation of the embodiment of the present application, the switching unit includes a third programmable device for powering on and a second controller;

[0183] The memory expansion unit, the adapter unit, and the host to be expanded are powered on by the second power-on method, including:

[0184] The memory expansion unit and the host to be expanded respectively perform backup power-on processing by turning on power, and generate a third backup power completion signal corresponding to the memory expansion unit and a fourth backup power completion signal corresponding to the host to be expanded;

[0185] The first programmable device is used to obtain the third backup power completion signal and send the third backup power completion signal to the controller module, and the controller module sends the third backup power completion signal to the second controller;

[0186] The second programmable device is used to obtain the fourth backup power completion signal and send the fourth backup power completion signal to the first controller, and the first controller sends the fourth backup power completion signal to the second controller;

[0187] The second controller is further configured to determine the power-on status of the memory expansion unit and the host to be expanded as a backup power completion state according to the received third backup power completion signal and the fourth backup power completion signal.

[0188] Among them, the transfer unit (such as: CXL switching equipment) is internally configured with a third programmable device (CPLD) and a second controller (BMC), which together with the memory expansion unit and the host to be expanded constitute a three-level distributed power supply monitoring network.

[0189] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a power supply block diagram in which a memory expansion unit is indirectly interconnected with a host to be expanded via a transfer unit, such as Figure 16 As shown, and a standby power-on flow chart of a memory expansion unit indirectly interconnected with a host to be expanded through a switching unit, as shown Figure 17 shown.

[0190] The second power-on method also includes backup power-on processing and main power-on processing. The backup power-on processing process specifically includes but is not limited to the following steps:

[0191] When an external power source is connected, the memory expansion unit's power module generates a standalone backup power supply (STBY). The first programmable device continuously monitors the output voltage ripple and load response characteristics. When it determines that the power supply stability continues to meet preset conditions, it generates a third backup power supply completion signal. This third backup power supply completion signal is encapsulated into a network data packet via the controller module's serial management interface and transmitted via the management network to the second controller of the adapter unit.

[0192] Simultaneously, the host to be expanded performs the same operation: after verifying that the local backup power meets the requirements, the second programmable device generates a fourth backup power completion signal, which is forwarded to the second controller of the switching unit via the network protocol stack of the first controller. The second controller performs a time domain alignment check on the received dual signals: when the difference between the timestamps of the third and fourth backup power completion signals is less than the system fault tolerance window (e.g., 500 milliseconds) and the signal validity flags are both set, a backup power completion status instruction is broadcast to the memory expansion unit and the host to be expanded.

[0193] Centralized state arbitration of the second controller of the transfer unit solves the clock drift problem in multi-node distributed systems; the triple-state latch mechanism eliminates the risk of system hang caused by single-point signal transmission failure; and networked command broadcasting significantly reduces the design complexity of traditional hard-wired synchronization solutions.

[0194] In one possible implementation of the embodiment of the present application, the switching unit includes a third power supply chip for powering on;

[0195] The memory expansion unit, the adapter unit, and the host to be expanded are powered on by the second power-on method, further comprising:

[0196] In response to the memory expansion unit and the host to be expanded being in a standby power completion state and the second power-on signal triggered by the adapter unit, the third programmable device controls the third power chip to perform main power-on processing on the adapter unit and generates a third main power completion signal;

[0197] The third programmable device forwards the second power-on signal to the first programmable device via the controller module;

[0198] In response to the received second power-on signal, the first programmable device controls the first power chip to perform a main power-on process on the memory expansion unit and generate a fourth main power-on completion signal;

[0199] The controller module forwards the fourth main power completion signal to the second programmable device via the first controller;

[0200] In response to the received fourth main power completion signal, the second programmable device controls the second power supply chip to perform main power-on processing on the host to be expanded, and generates a fifth main power completion signal.

[0201] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a main power-on flow chart of a memory expansion unit indirectly interconnected with a host to be expanded through a transfer unit, such as Figure 18 shown.

[0202] The main power-on process includes but is not limited to the following methods:

[0203] When the system is in the backup power-on state and the user triggers the physical power button on the adapter unit, a second power-on signal is generated. This signal triggers the third programmable device to output an activation level to the enable pin of the third power chip, initiating the main power transition of the adapter unit. After the output voltage of the third power chip stabilizes, the third main power-on completion signal is returned to the third programmable device via the power good (PG) pin.

[0204] Simultaneously, the third programmable device encapsulates the second power-on signal into a control command and transmits it via the management network to the controller module of the memory expansion unit. The controller module parses the command and forwards it to the first programmable device via the local bus. In response to the command, the first programmable device outputs an enable signal to the first power chip, initiating the main power-up sequence for the memory expansion unit. When the output voltage of the first power chip reaches the specified level and remains stable, a fourth main power-up completion signal is generated and fed back to the first programmable device.

[0205] After receiving the fourth main power-on completion signal, the controller module encapsulates it into a network message and sends it via the management network to the first controller of the host to be expanded. The first controller forwards the signal to the second programmable device via a serial interface. The second programmable device, in response to this signal, triggers the second power chip to enable, initiating the main power-on process for the host to be expanded. After the second power chip completes voltage regulation, it generates a fifth main power-on completion signal and returns it to the second programmable device.

[0206] By strictly following the enabling sequence of the adapter unit, memory expansion unit, and host to be expanded, memory resources are initialized before the host controller. The second power-on signal is synchronized across devices via network transmission, eliminating the risk of timing deviation in traditional architectures. Each level of main power completion signal is independently generated and verified to avoid cascading failures caused by single-point failures.

[0207] In an implementation manner of the embodiment of the present application, the first programmable device is further configured to forward the fourth main power completion signal to the second controller via the controller module;

[0208] The second programmable device is further configured to forward the fifth main power completion signal to the second controller via the first controller;

[0209] The third programmable device is further configured to forward the third main power completion signal to the second controller;

[0210] The second controller is further configured to determine the power-on status of the memory expansion unit, the adapter unit, and the host to be expanded as a main power completion status based on the received third main power completion signal, the fourth main power completion signal, and the fifth main power completion signal.

[0211] Among them, after the first programmable device generates the fourth main power completion signal (indicating that the main power of the memory expansion unit is stable), it transmits it to the controller module through the local bus. The controller module encapsulates it into a management message with a timestamp and sends it to the second controller of the adapter unit through the network management interface. Synchronously, after the second programmable device generates the fifth main power completion signal on the host side to be expanded, it forwards it to the second controller through the network protocol stack of the first controller. The third programmable device directly transmits the third main power completion signal (indicating that the main power of the adapter unit is stable) to the second controller through the board-level serial bus.

[0212] The second controller's built-in triple-check logic performs a coordinated analysis of the received signals: first, it verifies that the validity flags of all three signals are set; second, it compares whether the timestamp deviation of the three signals is less than the system's fault tolerance window (e.g., 100 milliseconds); and finally, it checks the integrity of the signal sequence to prevent packet loss. When all conditions are met, the second controller updates the global status register to the main power-on completion status and notifies all nodes via a broadcast message. This status triggers three key actions: sending a memory initialization command to the memory expansion unit, starting the routing table loading of the adapter unit, and allowing the host to be expanded to perform a memory controller self-test.

[0213] Three main power lines enable networked signal convergence and hardware-level direct transmission, creating redundant signal paths to mitigate single-point communication failures. The centralized time-domain verification of the secondary controller eliminates clock accumulation errors in distributed systems, ensuring atomic switching of power states across devices. A global state broadcast mechanism provides a unified state determination baseline for all three levels of devices, avoiding system startup conflicts caused by inconsistent local states. This significantly improves the power-on reliability of large-scale pooled memory systems in complex topologies, providing underlying security for shared memory resources across multiple hosts.

[0214] In one implementation of the embodiment of the present application, the memory expansion unit includes: a memory chassis, and a mounting ear, wherein the mounting ear is configured on the outside of the memory chassis, and the mounting ear is configured with at least a button, a debugging interface, and an indicator light;

[0215] The interior of the memory chassis is used to carry the multiple memory boards, the management baseboard, the power backplane, the power supply unit, and the fan module. The first interface and the second interface are exposed at the rear window of the memory chassis.

[0216] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a front window schematic diagram of a memory expansion unit, such as Figure 19 As shown, and a rear window schematic diagram of a memory expansion unit, as shown Figure 20 shown.

[0217] The memory chassis is a rigid shell structure that accommodates all core functional components. It adopts a standardized 2U height design (approximately 87mm high) and has a specified width and depth, making it seamlessly compatible with a general 19-inch cabinet installation environment. The internal space of the chassis has been carefully planned to stably support the multiple memory boards, management backplane, power backplane, power supply unit (PSU) and fan module detailed in claims 2 and 5. This internal centralized load-bearing design ensures that all key components work together in a protected physical environment. More importantly, the first interface for high-speed interconnection (i.e., 16 CDFP interfaces) and the second interface for inter-device communication (i.e., RJ45 management network port) are both designed to be exposed on the rear window of the memory chassis. The rear window refers to a dedicated opening area on the back panel of the chassis, where all external interfaces are centrally arranged to facilitate centralized cable layout and management. This design of exposed interfaces on the rear window allows external devices (such as hosts, switches, management networks) to directly and conveniently connect to the memory expansion unit through corresponding cables (CDFP DAC cables, Ethernet cables) without opening the chassis.

[0218] Mounting ears are metal or high-strength plastic components fixed to the front of the memory chassis (usually located at the left and right ears). They serve as the mounting connection point between the chassis and the cabinet rails. In addition to providing mechanical mounting functions, mounting ears are also endowed with rich human-computer interaction and status indication functions. Specifically, the mounting ears are equipped with at least the following key elements:

[0219] Buttons: These specifically refer to the physical buttons on the mounting ears, including the Unit Identification (UID) button and the illuminated power button. The UID button is used to physically identify the chassis (e.g., lighting the location light), allowing administrators to quickly identify specific devices in a densely populated cabinet. The illuminated power button is used to locally power on and off the chassis. Its integrated indicator light visually displays the current power status (e.g., a solid light indicates power on, a flashing light indicates standby or a fault).

[0220] Debug port: A physical port reserved for on-site maintenance or diagnosis. This port allows engineers to connect directly to a management device (such as a laptop) via a cable to perform low-level access, debugging, or firmware burning to the controller module (RunBMC) in the chassis, providing a direct channel for in-depth troubleshooting.

[0221] Indicator: This refers to a series of multi-colored (typically green, yellow, and red) LEDs mounted on the mounting ears. These indicators include at least those for critical status indications, such as memory fault, CXL link fault, fan fault, power supply fault, system overheating, and network status. Each indicator uses a different color or blinking pattern to intuitively convey real-time health and alarm information about the core subsystem of the memory expansion unit.

[0222] In one implementation of the embodiment of the present application, the memory pooling system further includes: a whole cabinet, the whole cabinet including a routing layer and a device layer;

[0223] The device layer is at least used to carry the memory expansion unit, the host to be expanded, and the switching unit, and the routing layer is at least used to carry the first cable.

[0224] In order to facilitate understanding of the embodiment of the present application, the embodiment of the present application provides a schematic block diagram of an entire cabinet, such as Figure 21 shown.

[0225] The cabinet, as the data center's infrastructure unit, provides unified installation space, power distribution, cooling ducts, and management access points for memory expansion units, host computers to be expanded, and optional adapter units. The interior of the cabinet is divided into two functional areas: the cabling layer and the equipment layer, both of which contribute to stable system operation and efficient maintenance.

[0226] The equipment layer is the core area of ​​the entire cabinet, and its main function is to carry, i.e., physically install and support the memory expansion unit, the host to be expanded (such as a CPU server or GPU accelerator), and the optional switching unit (CXL SwitchBOX). The equipment layer usually occupies the main part of the vertical space of the cabinet (such as most of the height of a standard 42U cabinet) and is equipped with standard cabinet slide rails or trays. The memory expansion unit, the host to be expanded, and the switching unit are independent rack-mounted devices. They are firmly installed on these slide rails of the equipment layer in a specific order and spacing according to the design plan or actual needs. The centralized carrying method not only optimizes space utilization and achieves high-density deployment, but also makes it possible for the physical proximity between the devices, thereby minimizing the length of the interconnecting cables, which is crucial to ensuring the integrity of high-speed signals. The equipment layer also carries the power distribution unit or bus slot that supplies power to each device.

[0227] Working closely with the equipment layer is the cabling layer. It is designed specifically for the orderly routing, securing, concealing, and protecting of cables. The cabling layer is used to carry at least the first cables (i.e., cables connecting the memory expansion unit, the host to be expanded, and the adapter unit). It is typically located at the front, rear, or side of the cabinet (e.g., on either side of the cabinet columns or inside the front and rear doors) and is equipped with dedicated cable management channels, cable management arms, fixing points, or cable troughs. By carefully planning the routes, neatly bundling, and securing a large number of first cables in the cabling layer, cables are prevented from draping, tangling, or piling up inside the equipment layer. This significantly improves air circulation within the cabinet, eliminates obstacles that could block heat dissipation airflow, and enhances the heat dissipation efficiency of the equipment. It also reduces the risk of cables accidentally falling off or being touched, enhancing the reliability of physical connections. It facilitates cable identification and manipulation during installation and maintenance, improving serviceability. By properly controlling cable length, signal transmission quality is optimized while meeting connection requirements, reducing signal attenuation and reflection. In addition, the cabling layer typically also carries other cables, such as Ethernet management cables and power cables.

[0228] Figure 22 A flow chart of a control method for a memory pooling system provided in an embodiment of the present application is shown as follows: Figure 22 As shown, the control method of the memory pooling system includes:

[0229] Step 2201: In response to a memory management instruction to a memory card or a memory buffer, determine attribute information of the memory management instruction.

[0230] In the embodiments of the present application, when an external management entity (such as a to-be-expanded host BMC or remote control software) initiates an operation request, i.e., a memory management instruction, for a memory card or a memory buffer, the controller module captures the memory management instruction and performs protocol decoding to obtain key attribute information, which includes but is not limited to: an operation type identifier (configuration / monitoring / diagnosis), a target device address space (a memory buffer register domain / a memory card physical address domain), a timeliness level (real-time / non-real-time), and a security policy marker.

[0231] The attribute information can be encoded as a bit field and stored in the instruction header, and the controller module generates a decision vector by bit-by-bit parsing of a shift register.

[0232] In step 2202, the target link corresponding to the memory management instruction is determined from a plurality of management links according to the attribute information.

[0233] In the embodiments of the present application, the controller module selects the target link from a plurality of management links. The selection logic can follow a preset priority rule, which includes but is not limited to: for instructions involving internal parameter adjustment of the memory buffer (such as refresh rate setting), the first management link (controller module, multiplexer, memory buffer path) is preferentially selected; for instructions requiring access to the physical state of the memory card (such as temperature reading), the second management link (controller module, multiplexer, memory card management bus) is enabled. In a complex instruction scenario (such as batch configuration of multiple memory cards), the controller module performs link load balancing calculation and selects the current idle link according to historical delay data.

[0234] In step 2203, the memory card or the memory buffer is managed according to the target link.

[0235] In the embodiments of the present application, if the first management link is selected, the controller module converts the operation instruction into a memory buffer access sequence, writes it into the memory buffer through the pass-through path established by the multiplexer, and reads the response value of the memory buffer; if the second management link is selected, the controller module generates a transaction frame in accordance with the I2C / I3C protocol specification, routes it to the management bus of the target memory card through the multiplexer, and obtains the response data after performing the read / write operation. The execution result is returned to the instruction initiator after being encapsulated by the protocol, and the link selection record in the system log is updated at the same time.

[0236] Through attribute-driven dynamic link selection, high real-time instructions can obtain nanosecond-level response capability through the first management link, while ensuring that physical state monitoring instructions maintain data originality through the second management link; the load-aware link allocation mechanism avoids management channel congestion, significantly improving the concurrent management efficiency of large-scale memory pools; the transparent recording of the instruction execution path provides data support for system optimization, enhancing the maintainability of the pooled memory system.

[0237] In one possible implementation of the embodiment of the present application, when determining the target link corresponding to the memory management instruction from multiple management links, it can also be implemented in but not limited to the following manner: when it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory buffer, the first management link is determined as the target link, and the memory buffer is managed through the first management link, wherein the multiple management links include the first management link and the second management link; when it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory card, the second management link is determined as the target link, and the memory card is managed through the second management link.

[0238] In an embodiment of the present application, after the controller module parses the attribute information of the memory management instruction, it first extracts the target device identification field. When the target device identification field points to the register address space of the memory buffer (such as: 0xB000-0xBFFF), it is determined that the instruction is a memory buffer exclusive operation (including but not limited to refresh policy update, queue depth configuration or error counter clearing). At this time, the controller module sets the first management link as the target link, and the first management link is a physical path that directly connects the controller module to the memory buffer through the multiplexer. When the first management link is enabled, the internal switch of the multiplexer is switched to the memory buffer interface direction, so that the controller module can directly read and write the registers of the memory buffer in a memory mapping manner, eliminating the protocol conversion overhead and ensuring the real-time performance of the configuration operation.

[0239] When the target device field in the attribute information falls within the memory card's physical address range (e.g., 0xA000-0xAFFF) and the operation type is status monitoring (e.g., temperature sensor reading, error log retrieval, or SPD parameter writing), the controller module selects the second management link as the target link. At this point, the multiplexer switches the path to the memory card management bus. The controller module generates transaction frames according to the I2C / I3C protocol specifications and directly accesses the memory card's serial interface through the second management link, avoiding intermediary interference from the memory buffer and ensuring the original accuracy of collected analog data such as voltage and temperature.

[0240] Hard-decision logic based on the device address space enables zero-latency link switching, enabling high-frequency cache configuration operations to achieve nanosecond response capabilities through the first management link, while ensuring that physical status monitoring instructions maintain data originality through the second management link. The dual-path physical isolation design completely eliminates mutual interference between different types of management traffic, preventing critical configuration instructions from being blocked by batch status queries. The precise matching of instructions and links maximizes the utilization of limited hardware resources, providing a scalable management channel architecture for ultra-large-scale memory pools.

[0241] In an implementation manner of the embodiment of the application, when the memory pooling system is controlled, the following methods can be used, but are not limited to: monitoring logs are generated according to monitoring data of the memory pooling system, wherein the monitoring data at least includes state information of the memory buffer and the memory card; and cable identification, cable state and topological relationship of the memory pooling system are stored in a preset information storage, wherein the cable state at least includes a connection state of a cable between a memory expansion unit and a host to be expanded in the memory pooling system.

[0242] In the embodiment of the application, the controller module periodically collects monitoring data, including but not limited to: data in an internal state register of the memory buffer (such as: queue depth counter, protocol error flag bit, temperature sensor reading); data of a physical layer sensor of the memory card (voltage fluctuation data, thermistor value and error check state obtained through the second management link).

[0243] After the data is collected, timestamp alignment and format standardization processing can be performed to generate structured record items. The log synthesis engine aggregates the record items into monitoring logs according to a preset strategy (such as: event triggering or timing archiving), the monitoring logs are stored in a local non-volatile memory of the controller module in a circular buffer, and each record contains an event type code, a severity level mark, a timestamp accurate to microseconds and a binary original data snapshot. When the log storage reaches a capacity threshold, an automatic trigger overwrite or network upload operation is triggered.

[0244] The cable information solidification mechanism is independently operated in the system deployment stage, and after the cable physical connection is ready, the controller module reads the inherent properties in the cable information storage. The cable identification includes a globally unique code and electrical specification parameters; the cable state dynamically records connection persistence indicators and signal integrity data; the topological relationship explicitly identifies the direct or switching interconnection mode. The controller module information is written into the non-volatile memory to form a persistent topological mapping table. During operation, the cable state data is continuously updated (such as: connector plug detection pin level sampling every second), to ensure that the physical connection reliability is reflected in real time.

[0245] The multi-source data fusion mechanism of the monitoring log provides a complete evidence chain for system abnormal diagnosis, and the accurate event sequence of the timestamp can quickly locate the intermittent fault root cause; the persistent storage of the cable information enables the system to automatically recover the topological configuration after restart, eliminating the need for manual repeated identification; the dynamically updated cable state parameters provide data support for connection reliability warning, avoiding implicit performance degradation caused by physical connection degradation. These capabilities cooperatively build a self-management framework for the memory pooling system, greatly reducing the operation and maintenance complexity of large-scale deployment.

[0246] Figure 23A flowchart of a method for powering on a memory pooling system provided in an embodiment of the present application is shown in FIG. Figure 23 As shown, the power-on method of the memory pooling system includes:

[0247] Step 2301: Determine a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system.

[0248] In an embodiment of the present application, the controller module reads the information memory and parses the topological relationship data stored therein. When the topological relationship is marked as DIRECT, it is determined to be in direct connection mode (the memory expansion unit is directly connected to the host to be expanded via a cable); when it is marked as SWITCHED, it is determined to be in indirect connection mode (the memory expansion unit is connected to the host via a switching unit). The identification result is stored in the system configuration register as the decision basis for the subsequent power-on logic.

[0249] Step 2302: When it is determined that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, power on the memory expansion unit and the host to be expanded using a first power-on mode.

[0250] In an embodiment of the present application, in direct connection mode, the first power-on method is enabled: the host to be expanded and the memory expansion unit are powered on synchronously with the backup power, and the programmable devices of both parties exchange ready signals after the local backup power is stable; after the user triggers the power button of the memory expansion unit, the memory expansion unit starts the main power conversion first; the main power ready signal of the memory expansion unit triggers the main power enable of the host to be expanded, forming a cascade power startup chain, strictly ensuring that the memory resources are prepared before the host memory controller is initialized, eliminating the risk of access timeout.

[0251] Step 2303: When it is determined that the connection mode is that the memory expansion unit is indirectly connected to the host to be expanded via a switching unit, power on the switching unit, the host to be expanded, and the memory expansion unit using a second power-on mode.

[0252] In an embodiment of the present application, in the indirect connection mode, the second power-on method is executed: the adapter unit acts as a coordination hub, first collecting the standby power ready status of the memory expansion unit and the host to be expanded; after the user triggers the power button of the adapter unit, the adapter unit activates the internal main power-on chip, and then cascades the main power in the order of the adapter unit, the memory expansion unit, and the host to be expanded; the adapter unit verifies the three-level main power completion signal and broadcasts the global ready status. The hierarchical mechanism avoids multiple devices from competing for power-on resources, ensuring that the adapter unit with strict signal integrity requirements is initialized first.

[0253] The automatic recognition mechanism based on the cable storage topology eliminates manual configuration and realizes plug-and-play deployment. The cascade power-on design in the direct connection mode maximizes the startup efficiency under the premise of ensuring timing. The three-stage segmented control of indirect connection completely solves the power competition problem in complex topology, especially eliminating the risk of reverse current between cascade devices. The high-reliability memory pooling system startup framework is jointly constructed to provide basic support for super-large-scale computing clusters.

[0254] In an implementation manner of the embodiment of the application, when power is turned on through the first power-on manner, the following manner, but not limited to, can also be used: in response to the first power-on signal of the memory expansion unit and the host to be expanded, the memory expansion unit and the host to be expanded are powered on by standby power, and a first power-on signal is generated, wherein the first power-on signal at least includes a first standby power completion signal of the memory expansion unit and a second standby power completion signal of the host to be expanded; the first standby power completion signal and the second standby power completion signal are transmitted to the memory expansion unit, so as to determine the power-on state of the host to be expanded as a standby power completion state by the memory expansion unit.

[0255] In the embodiment of the application, when the external power supply is input, the memory expansion unit and the host to be expanded respectively respond to the local first power-on signal (that is, the physical power switch trigger signal) and start independent standby power-on sequences in parallel. The memory expansion unit verifies the standby power stability by the internal voltage monitoring circuit, generates the first standby power completion signal representing the local standby power readiness; synchronously, the host to be expanded executes the same self-checking process, and generates the second standby power completion signal.

[0256] The double-ended signal is aggregated and transmitted through the system-level management interface: the host to be expanded encapsulates the second standby power completion signal into a network management packet, and sends the network management packet to the management interface of the memory expansion unit via the auxiliary channel of the cable. After receiving the second standby power completion signal, the memory expansion unit performs logical AND operation on the first standby power completion signal generated locally, generates a comprehensive first power-on signal, and triggers the system state machine of the memory expansion unit to update, so as to synchronize the power-on state of the host to be expanded and the state of the memory expansion unit to the standby power completion state, and write the standby power completion state into the global state register.

[0257] The double-ended autonomous standby power detection mechanism avoids the system suspension risk caused by single-point failure; the networked signal transmission realizes cross-device state synchronization and eliminates complex hardwired design; the centralized update of the global state register provides a unified coordination benchmark for subsequent main power-on, and ensures the strict timing relationship between the memory resource pool initialization and the host startup sequence.

[0258] In one implementation method of the embodiment of the present application, the power-on processing is performed through the first power-on method, and can also be implemented in but not limited to the following methods: in response to the memory expansion unit and the host to be expanded being in the standby power completion state, and the first power-on signal is triggered to the memory expansion unit, the memory expansion unit is subjected to main power-on processing, and a first main power completion signal is generated, and the first main power completion signal is transmitted to the host to be expanded; in response to the first main power completion signal, the host to be expanded is subjected to main power-on processing, and a second main power completion signal is generated, and the second main power completion signal is transmitted to the memory expansion unit, so that the power-on state of the host to be expanded is determined as the main power completion state through the memory expansion unit.

[0259] In an embodiment of the present application, when the system is in a standby power-on state and the user triggers the physical power button of the memory expansion unit, a first power-on signal is generated. This first power-on signal initiates the memory expansion unit's local main power power-up sequence, generating a stable core operating voltage through internal voltage conversion and voltage regulation. Once the main power-on process is fully operational, the memory expansion unit generates a first main power-on completion signal, indicating that its main power supply is stable, and transmits it to the host to be expanded via the system-level management interface.

[0260] Upon receiving the primary power-on completion signal, the host to be expanded immediately initiates the local main power supply power-up sequence. The host's internal power control module performs a phased voltage conversion, ultimately generating a core operating voltage specific to the host. Once the main power supply stabilizes and meets the required standards, the host generates a secondary power-on completion signal and transmits it back to the memory expansion unit via the management interface.

[0261] The memory expansion unit performs coordinated verification of dual-end signals: When both the first and second main power-on completion signals are confirmed valid, the global status register is updated with the main power-on completion status. This main power-on completion status is broadcast to both devices simultaneously, triggering the memory expansion unit to initiate memory resource pool initialization and the memory controller self-test process on the host to be expanded.

[0262] A strict cascade enable chain is established through the cross-device transmission of the first main power completion signal to ensure that the memory resource pool is ready before the host computing unit. The closed-loop verification mechanism of the dual-end main power completion signal eliminates the risk of timing deviation and prevents the host from initiating access when the memory is not ready. The atomic switching of the global main power completion state provides a synchronization benchmark for system startup, significantly improving the startup reliability of large-scale memory pool systems.

[0263] In one implementable manner of the embodiment of the present application, when power-on is performed through the second power-on manner, it can also be implemented by, but not limited to, the following manner: in response to the second power-on signal of the memory expansion unit and the host to be expanded, the memory expansion unit and the host to be expanded are subjected to standby power-on processing to generate a second power-on signal, wherein the second power-on signal at least includes a third standby power completion signal of the memory expansion unit and a fourth standby power completion signal of the host to be expanded; the third standby power completion signal and the fourth standby power completion signal are transmitted to the switching unit, so as to determine the power-on status of the memory expansion unit and the host to be expanded as a standby power completion status through the switching unit.

[0264] In an embodiment of the present application, upon input of external power, the memory expansion unit and the host to be expanded each initiate independent standby power-up sequences in parallel in response to a local second power-on signal (i.e., a physical power switch trigger event). The memory expansion unit verifies the stability of its standby power supply via an internal power monitoring system and generates a third standby power completion signal indicating that the local standby power supply is ready. Simultaneously, the host to be expanded performs the same self-test process, generating a fourth standby power completion signal.

[0265] Dual-ended signals are transmitted and aggregated via the system-level management network: the memory expansion unit encapsulates its third backup power-on completion signal into a management protocol data unit (MPDU) and transmits it via the connecting cable to the management interface of the adapter unit. Similarly, the host to be expanded sends its fourth backup power-on completion signal to the adapter unit. After receiving both signals, the adapter unit performs logical aggregation to generate a comprehensive second power-on signal. Using its internal state coordination mechanism, it uniformly identifies the power-on status of both the memory expansion unit and the host to be expanded as backup power-on completion, writing this information into the global status register.

[0266] Centralized signal aggregation and status arbitration of the switching unit eliminates clock synchronization errors in multi-device distributed systems. The independent transmission mechanism of dual-channel signals avoids the risk of system hang caused by single-channel failure. The atomic identification of the global backup power completion status provides a coordinated benchmark for subsequent hierarchical main power-on, ensuring strict timing alignment of the three-level device startup sequence.

[0267] In one implementation method of the embodiment of the present application, when power-on is performed through the second power-on method, it can also be implemented by but not limited to the following methods: in response to the memory expansion unit and the host to be expanded being in the standby power completion state, and the second power-on signal triggered by the adapter unit, the second power-on signal is transmitted to the memory expansion unit, and the adapter unit is subjected to main power-on processing to generate a third main power completion signal; in response to the second power-on signal, the memory expansion unit is subjected to main power-on processing, and a fourth main power completion signal is generated, and the fourth main power completion signal is transmitted to the host to be expanded and the adapter unit respectively; in response to the fourth main power completion signal, the host to be expanded is subjected to main power-on processing, and a fifth main power completion signal is generated, and the fifth main power completion signal is transmitted to the adapter unit, so that the power-on state of the memory expansion unit and the host to be expanded is determined to be the main power completion state through the adapter unit.

[0268] In an embodiment of the present application, when the system is in a standby power-on state and the user triggers the physical power button of the adapter unit, a second power-on signal is generated. This second power-on signal triggers two parallel operations: the adapter unit initiates a local main power power-on sequence, generates a core operating voltage through its internal voltage conversion system, and ultimately outputs a third main power-on completion signal indicating that its own main power is ready; and the second power-on signal is transmitted via the system management network to the memory expansion unit, triggering the main power power-on sequence of the memory expansion unit.

[0269] After the memory expansion unit completes stable main power output, it generates a fourth main power completion signal and transmits it to the host computer to be expanded and the adapter unit via the management network. Upon receiving the fourth main power completion signal, the host computer to be expanded immediately initiates the local main power supply power-up sequence, completes voltage conversion, and generates a fifth main power completion signal, which is then transmitted back to the adapter unit.

[0270] The adapter unit, acting as the status coordination hub, aggregates the third, fourth, and fifth main power-on completion signals and performs a global check: verifying the validity of the three-terminal signals, confirming that timing deviations are within the fault tolerance window, and checking the integrity of the signal sequence. Once the check passes, the adapter unit updates the power-on status of the memory expansion unit and the host to be expanded to the main power-on completion status and broadcasts the system ready command.

[0271] The networked distribution of the second power-on signal enables cross-device wake-up synchronization, avoiding the cumulative delays in traditional cascade architectures. The bidirectional transmission of the fourth main power signal establishes a direct coordination channel between the memory expansion unit and the host to be expanded, breaking through the single-point bottleneck of the adapter unit. The centralized status verification of the adapter unit ensures the atomic switching of the power status of the three-level devices, providing a millisecond-level precise synchronization startup framework for ultra-large-scale memory pools.

[0272] In summary, the embodiments of the present application can achieve the following technical effects:

[0273] Through the dynamic selection mechanism of the multiplexer of the memory expansion unit, that is, building the first management link for the controller module to manage the memory cache or the second management link for the controller module to manage the memory card, the external device to be expanded does not need to participate in the management of the memory device. When the number of physical pins is limited, large-capacity memory expansion can be achieved by connecting the memory cache and the memory card. The memory board expands the capacity by configuring the memory card to form a pooled resource pool. At the same time, the multiplexer efficiently reuses the limited signal channels of the adapter module, so that the controller module can intelligently switch the management path according to the instruction attributes, quickly access the memory cache through the first management link to optimize high-frequency interaction, or directly connect to the memory card through the second management link to achieve high-bandwidth parallel data access. Ultimately, the device to be expanded breaks through the physical pin limitation and simultaneously obtains large-capacity and high-bandwidth memory expansion capabilities, effectively bridging the computing and storage gap of artificial intelligence accelerators.

[0274] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0275] The embodiment of the present application also provides a control device for a memory pooling system, Figure 24 A schematic diagram of the structure of a control device for a memory pooling system provided by this application is shown as follows: Figure 24 Shown, including:

[0276] A first determining unit 2401 is configured to determine attribute information of a memory management instruction in response to a memory management instruction for a memory card or a memory buffer;

[0277] The first determining unit 2401 is further configured to determine, according to the attribute information, a target link corresponding to the memory management instruction from a plurality of management links;

[0278] The management unit 2402 is configured to manage the memory card or the memory buffer according to the target link.

[0279] In one embodiment of the present application, the first determining unit 2401 is further configured to:

[0280] When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory buffer, determining the first management link as the target link, and managing the memory buffer through the first management link, wherein the multiple management links include the first management link and the second management link;

[0281] When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory card, the second management link is determined as the target link, and the memory card is managed through the second management link.

[0282] In one embodiment of the present application, the management unit 2402 is further configured to:

[0283] generating a monitoring log according to monitoring data of the memory pooling system, wherein the monitoring data includes at least status information of the memory buffer and the memory card;

[0284] The cable identification, cable status, and topological relationship of the memory pooling system are stored in a preset information storage, wherein the cable status at least includes the connection status of the cable between the memory expansion unit and the host to be expanded in the memory pooling system.

[0285] For descriptions of features in the embodiments corresponding to the control device of the memory pooling system, reference may be made to the descriptions of the embodiments corresponding to the control method of the memory pooling system, which will not be detailed here.

[0286] The embodiment of the present application also provides a power-on device for a memory pooling system. Figure 25 A schematic diagram of the structure of a power-on device for a memory pooling system provided in this application is shown as follows: Figure 25 Shown, including:

[0287] The second determining unit 2501 determines a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system;

[0288] A first power-on unit 2502 is configured to, when determining that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, power on the memory expansion unit and the host to be expanded using a first power-on mode;

[0289] The second power-on unit 2503 is used to power on the adapter unit, the host to be expanded and the memory expansion unit through a second power-on method when it is determined that the connection method is that the memory expansion unit is indirectly connected to the host to be expanded via the adapter unit.

[0290] In one embodiment of the present application, the first power-on unit 2502 is further configured to:

[0291] In response to a first power-on signal of the memory expansion unit and the host to be expanded, performing a standby power-on process on the memory expansion unit and the host to be expanded, and generating a first power-on signal, wherein the first power-on signal at least includes a first standby power completion signal of the memory expansion unit and a second standby power completion signal of the host to be expanded;

[0292] The first backup power completion signal and the second backup power completion signal are transmitted to the memory expansion unit, so that the power-on state of the host to be expanded is determined as the backup power completion state through the memory expansion unit.

[0293] In one embodiment of the present application, the first power-on unit 2502 is further configured to:

[0294] In response to the memory expansion unit and the host to be expanded being in a standby power-on completion state and a first power-on signal being triggered for the memory expansion unit, performing a main power-on process on the memory expansion unit, generating a first main power-on completion signal, and transmitting the first main power-on completion signal to the host to be expanded;

[0295] In response to the first main power completion signal, main power-on processing is performed on the host to be expanded, and a second main power completion signal is generated, and the second main power completion signal is transmitted to the memory expansion unit, so that the power-on status of the host to be expanded is determined as the main power completion status through the memory expansion unit.

[0296] In one embodiment of the present application, the second power-on unit 2503 is further configured to:

[0297] In response to the second power-on signal of the memory expansion unit and the host to be expanded, performing standby power-on processing on the memory expansion unit and the host to be expanded, and generating a second power-on signal, wherein the second power-on signal at least includes a third standby power completion signal of the memory expansion unit and a fourth standby power completion signal of the host to be expanded;

[0298] The third backup power completion signal and the fourth backup power completion signal are transmitted to the switching unit, so that the switching unit determines the power-on status of the memory expansion unit and the host to be expanded as the backup power completion status.

[0299] In one embodiment of the present application, the second power-on unit 2503 is further configured to:

[0300] In response to the memory expansion unit and the host to be expanded being in a standby power completion state and the second power-on signal being triggered by the adapter unit, the second power-on signal is transmitted to the memory expansion unit, and the adapter unit is powered on by a main power supply, thereby generating a third main power completion signal;

[0301] In response to the second power-on signal, performing a main power-on process on the memory expansion unit, generating a fourth main power-on completion signal, and transmitting the fourth main power-on completion signal to the host to be expanded and the adapter unit respectively;

[0302] In response to the fourth main power completion signal, main power-on processing is performed on the host to be expanded, and a fifth main power completion signal is generated, and the fifth main power completion signal is transmitted to the adapter unit, so that the power-on status of the memory expansion unit and the host to be expanded is determined as the main power completion status through the adapter unit.

[0303] For descriptions of features in the embodiments corresponding to the power-on device of the memory pooling system, reference may be made to the descriptions of the embodiments corresponding to the power-on method of the memory pooling system, which will not be described in detail here.

[0304] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute any of the aforementioned control methods for a memory pooling system, or the steps in any of the aforementioned power-on methods for a memory pooling system.

[0305] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein the computer program is configured to execute, when running, any of the aforementioned control methods for a memory pooling system, or any of the steps in any of the aforementioned power-on method embodiments for a memory pooling system.

[0306] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0307] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned control methods for the memory pooling system or any of the above-mentioned power-on methods for the memory pooling system.

[0308] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, implements any of the aforementioned control methods for a memory pooling system, or the steps in any of the aforementioned power-on methods for a memory pooling system.

[0309] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0310] The above is a detailed introduction to a memory pooling system and its control method, power-on method, device, and electronic device provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory pooling system, characterized in that: include: A memory expansion unit, comprising a memory board, a controller module, a multiplexer, and a switching module, wherein the memory board comprises a memory buffer interconnected with a plurality of memory cards; The controller module is connected to the multiplexer via the input signal channel and the output signal channel of the adapter module; The multiplexer is connected to the memory buffer and the memory card respectively to establish a first management link between the controller module and the memory buffer, or to establish a second management link between the controller module and the memory card; In response to a memory management instruction, the controller module selects the first management link or the second management link to respond to the memory management instruction according to attribute information of the memory management instruction.

2. The memory pooling system according to claim 1, characterized in that: The memory buffer is connected to the host to be expanded, and the memory card is used to expand the memory of the host to be expanded; The memory buffer responds to the memory access instruction initiated by the host to be expanded and accesses the corresponding target memory card according to the memory card identifier carried in the memory access instruction.

3. The memory pooling system according to claim 2, characterized in that: The controller module is further configured to: In response to a memory management instruction to the memory buffer or the memory card, determining attribute information corresponding to the memory management instruction; When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory card, managing the memory card based on the second management link; When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory buffer, the memory buffer is managed based on the first management link.

4. The memory pooling system according to claim 2, wherein: The memory expansion unit further includes: a management baseboard, The controller module is configured on the management baseboard, the management baseboard is connected to the memory board, and the controller module exchanges information with the memory board based on the management baseboard; The controller module receives the status information transmitted by the memory board, and monitors the status of the memory board according to the status information to generate monitoring data; The controller module is further configured to generate a monitoring log based on the monitoring data and the status information.

5. The memory pooling system according to claim 4, characterized in that: The memory expansion unit is directly interconnected with the host to be expanded through a first cable, or the memory expansion unit is indirectly interconnected with the host to be expanded through the first cable via a switching unit; The first cable is provided with an information storage device for storing a cable identification and a cable status of the first cable and a topological relationship between the memory expansion unit and the host to be expanded, wherein the cable status includes at least a connection status between the first cable and the host to be expanded.

6. The memory pooling system according to claim 5, characterized in that: If the memory expansion unit is directly interconnected with the host to be expanded through the first cable, the memory expansion unit and the host to be expanded are powered on using a first power-on method; If the memory expansion unit is indirectly interconnected with the host to be expanded through the first cable, the memory expansion unit, the switching unit, and the host to be expanded are powered on using a second power-on method.

7. The memory pooling system according to claim 6, characterized in that: The memory expansion unit includes a first programmable device for powering on, and the host to be expanded includes a second programmable device for powering on and a first controller; The memory expansion unit and the host to be expanded are powered on in a first power-on manner, including: The memory expansion unit and the host to be expanded respectively perform backup power-on processing by turning on power, and generate a first backup power completion signal corresponding to the memory expansion unit and a second backup power completion signal corresponding to the host to be expanded; The first programmable device is used to obtain the first backup power completion signal and send the first backup power completion signal to the controller module; The second programmable device is used to obtain the second backup power completion signal and send the second backup power completion signal to the first controller, and the first controller sends the second backup power completion signal to the controller module; The controller module is further configured to determine the power-on status of the memory expansion unit and the host to be expanded as a backup power completion status according to the first backup power completion signal and the second backup power completion signal.

8. The memory pooling system according to claim 7, characterized in that: The memory expansion unit further includes a first power chip, and the host to be expanded further includes a second power chip; The memory expansion unit and the host to be expanded are powered on in a first power-on manner, further comprising: In response to the memory expansion unit and the host to be expanded being in a standby power-on completion state and the memory expansion unit triggering a first power-on signal, the first programmable device controls the first power chip to perform a main power-on process on the memory expansion unit and generates a first main power-on completion signal; The controller module forwards the first main power completion signal to the second programmable device via the first controller; The second programmable device controls the second power supply chip to perform main power-on processing on the host to be expanded in response to the received first main power completion signal, and generates a second main power completion signal; The second programmable device forwards the second main power completion signal to the controller module via the first controller; The controller module is further configured to determine the power-on status of the memory expansion unit and the host to be expanded as a main power-on completion status according to the received first main power-on completion signal and the second main power-on completion signal.

9. The memory pooling system according to claim 8, characterized in that: The switching unit includes a third programmable device for powering on and a second controller; The memory expansion unit, the adapter unit, and the host to be expanded are powered on by the second power-on method, including: The memory expansion unit and the host to be expanded respectively perform backup power-on processing by turning on power, and generate a third backup power completion signal corresponding to the memory expansion unit and a fourth backup power completion signal corresponding to the host to be expanded; The first programmable device is used to obtain the third backup power completion signal and send the third backup power completion signal to the controller module, and the controller module sends the third backup power completion signal to the second controller; The second programmable device is used to obtain the fourth backup power completion signal and send the fourth backup power completion signal to the first controller, and the first controller sends the fourth backup power completion signal to the second controller; The second controller is further configured to determine the power-on status of the memory expansion unit and the host to be expanded as a backup power completion state according to the received third backup power completion signal and the fourth backup power completion signal.

10. The memory pooling system according to claim 9, characterized in that: The switching unit includes a third power chip for powering on; The memory expansion unit, the adapter unit, and the host to be expanded are powered on by the second power-on method, further comprising: In response to the memory expansion unit and the host to be expanded being in a standby power completion state and the second power-on signal triggered by the adapter unit, the third programmable device controls the third power chip to perform main power-on processing on the adapter unit and generates a third main power completion signal; The third programmable device forwards the second power-on signal to the first programmable device via the controller module; In response to the received second power-on signal, the first programmable device controls the first power chip to perform a main power-on process on the memory expansion unit and generate a fourth main power-on completion signal; The controller module forwards the fourth main power completion signal to the second programmable device via the first controller; In response to the received fourth main power completion signal, the second programmable device controls the second power supply chip to perform main power-on processing on the host to be expanded, and generates a fifth main power completion signal.

11. The memory pooling system according to claim 10, wherein: The first programmable device is further configured to forward the fourth main power completion signal to the second controller via the controller module; The second programmable device is further configured to forward the fifth main power completion signal to the second controller via the first controller; The third programmable device is further configured to forward the third main power completion signal to the second controller; The second controller is further configured to determine the power-on status of the memory expansion unit, the adapter unit, and the host to be expanded as a main power completion status based on the received third main power completion signal, the fourth main power completion signal, and the fifth main power completion signal.

12. A control method for a memory pooling system, characterized in that: The method is applied to the memory pooling system according to any one of claims 1 to 11, comprising: In response to a memory management instruction to the memory card or the memory buffer, determining attribute information of the memory management instruction; Determining a target link corresponding to the memory management instruction from a plurality of management links according to the attribute information; The memory card or the memory buffer is managed according to the target link.

13. The control method of the memory pooling system according to claim 12, characterized in that: Determining the target link corresponding to the memory management instruction from multiple management links according to the attribute information includes: When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory buffer, determining the first management link as the target link, and managing the memory buffer through the first management link, wherein the multiple management links include the first management link and the second management link; When it is determined according to the attribute information that the memory management instruction is a memory management instruction corresponding to the memory card, the second management link is determined as the target link, and the memory card is managed through the second management link.

14. The control method of the memory pooling system according to claim 13, characterized in that: The method further comprises: generating a monitoring log according to monitoring data of the memory pooling system, wherein the monitoring data includes at least status information of the memory buffer and the memory card; The cable identification, cable status, and topological relationship of the memory pooling system are stored in a preset information storage, wherein the cable status at least includes the connection status of the cable between the memory expansion unit and the host to be expanded in the memory pooling system.

15. A method for powering on a memory pooling system, characterized in that: The method is applied to the memory pooling system according to any one of claims 1 to 11, comprising: Determining a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system; When it is determined that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, powering on the memory expansion unit and the host to be expanded by using a first power-on mode; When it is determined that the connection mode is that the memory expansion unit is indirectly connected to the host to be expanded via a switching unit, the switching unit, the host to be expanded, and the memory expansion unit are powered on by a second power-on mode.

16. The power-on method of the memory pooling system according to claim 15, characterized in that: The powering on the memory expansion unit and the host to be expanded by using the first power-on method includes: In response to a first power-on signal of the memory expansion unit and the host to be expanded, performing a standby power-on process on the memory expansion unit and the host to be expanded, and generating a first power-on signal, wherein the first power-on signal at least includes a first standby power completion signal of the memory expansion unit and a second standby power completion signal of the host to be expanded; The first backup power completion signal and the second backup power completion signal are transmitted to the memory expansion unit, so that the power-on state of the host to be expanded is determined as the backup power completion state through the memory expansion unit.

17. The power-on method of the memory pooling system according to claim 16, characterized in that: The powering on the memory expansion unit and the host to be expanded by using the first power-on method further includes: In response to the memory expansion unit and the host to be expanded being in a standby power-on completion state and a first power-on signal being triggered for the memory expansion unit, performing a main power-on process on the memory expansion unit, generating a first main power-on completion signal, and transmitting the first main power-on completion signal to the host to be expanded; In response to the first main power completion signal, main power-on processing is performed on the host to be expanded, and a second main power completion signal is generated, and the second main power completion signal is transmitted to the memory expansion unit, so that the power-on status of the host to be expanded is determined as the main power completion status through the memory expansion unit.

18. The power-on method of the memory pooling system according to claim 15, characterized in that: The powering-on process of the adapter unit, the host to be expanded, and the memory expansion unit by using the second power-on mode includes: In response to the second power-on signal of the memory expansion unit and the host to be expanded, performing standby power-on processing on the memory expansion unit and the host to be expanded, and generating a second power-on signal, wherein the second power-on signal at least includes a third standby power completion signal of the memory expansion unit and a fourth standby power completion signal of the host to be expanded; The third backup power completion signal and the fourth backup power completion signal are transmitted to the switching unit, so that the switching unit determines the power-on status of the memory expansion unit and the host to be expanded as the backup power completion status.

19. The power-on method of the memory pooling system according to claim 18, characterized in that: The powering on the adapter unit, the host to be expanded, and the memory expansion unit by using the second power-on method further includes: In response to the memory expansion unit and the host to be expanded being in a standby power completion state and the second power-on signal being triggered by the adapter unit, the second power-on signal is transmitted to the memory expansion unit, and the adapter unit is powered on by a main power supply, thereby generating a third main power completion signal; In response to the second power-on signal, performing a main power-on process on the memory expansion unit, generating a fourth main power-on completion signal, and transmitting the fourth main power-on completion signal to the host to be expanded and the adapter unit respectively; In response to the fourth main power completion signal, main power-on processing is performed on the host to be expanded, and a fifth main power completion signal is generated, and the fifth main power completion signal is transmitted to the adapter unit, so that the power-on status of the memory expansion unit and the host to be expanded is determined as the main power completion status through the adapter unit.

20. A control device for a memory pooling system, characterized in that: include: a first determining unit, configured to determine attribute information of a memory management instruction in response to a memory management instruction to a memory card or a memory buffer; The first determining unit is further configured to determine, according to the attribute information, a target link corresponding to the memory management instruction from a plurality of management links; A management unit is configured to manage the memory card or the memory buffer according to the target link.

21. A power-on device for a memory pooling system, characterized in that: include: A second determining unit is configured to determine a connection mode between a memory expansion unit and a host to be expanded in the memory pooling system; a first power-on unit, configured to, when determining that the connection mode is a direct connection between the memory expansion unit and the host to be expanded, power on the memory expansion unit and the host to be expanded using a first power-on mode; The second power-on unit is used to power on the adapter unit, the host to be expanded and the memory expansion unit through a second power-on method when it is determined that the connection method is that the memory expansion unit is indirectly connected to the host to be expanded via the adapter unit.

22. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for controlling the memory pooling system according to any one of claims 12 to 14, or the steps of the method for powering on the memory pooling system according to any one of claims 15 to 19, when executing the computer program.

23. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein, when the computer program is executed by a processor, the computer program implements the steps of the method for controlling the memory pooling system according to any one of claims 12 to 14, or the steps of the method for powering on the memory pooling system according to any one of claims 15 to 19.

24. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the control method of the memory pooling system according to any one of claims 12 to 14, or the steps of the power-on method of the memory pooling system according to any one of claims 15 to 19.

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