Power semiconductor chip crimping packaging structure and manufacturing method
By forming a soft layer area on the collector and emitter electrodes and using technologies such as laser annealing and brazing to compensate for processing errors, a uniform distribution of pressure and current is achieved in the power semiconductor chip packaging structure, thereby improving operational reliability and production efficiency.
Patent Information
- Application Number
- CN202410364724.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-10-10
AI Technical Summary
The existing power semiconductor chip packaging structure has the problem of uneven pressure and current distribution inside the device, which affects the operational reliability of the module.
The collector and emitter electrodes are respectively in contact with the chip sub-units through the soft layer area. Laser annealing is used to form the soft layer area to compensate for processing errors by creep deformation. Brazing or diffusion welding is combined to achieve interconnection of materials of different hardness to form chip sub-units in parallel.
It achieves uniform pressure and current distribution inside semiconductor devices, improves conductivity and heat dissipation, enhances module operation reliability, simplifies production processes, and reduces failure rates.
Smart Images
Figure CN120767259A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a power semiconductor chip compression packaging structure and a manufacturing method. Background Art
[0002] Power semiconductor modules are the foundation and core of power electronics technology. Currently, power electronics are increasingly being used in every aspect of power systems, including power generation, transmission, distribution, and consumption. New energy sources such as photovoltaic and wind power generation rely on power semiconductor modules to convert and control electrical energy. By increasing voltage levels and converting electrical energy forms, they enable long-distance, high-capacity, low-loss, and flexible power transmission.
[0003] As a typical packaging method for power semiconductor modules, press-fit power semiconductor modules achieve electrical connections and heat transfer within their internal structures through applied pressure. They feature high current capacity, no solder joints, double-sided heat dissipation, high operating junction temperatures, and failure short circuit resistance. They are widely used in high-voltage direct current transmission systems, wind power generation, and high-voltage, high-power industrial equipment drives, offering significant competitive advantages. Press-fit power semiconductor modules include press-fit IGBTs, MOSFETs, and diodes. The electrodes of an IGBT are described as collector, emitter, and gate, respectively. The electrodes of a MOSFET are described as drain, source, and gate, respectively. A diode lacks a gate, only an anode and cathode. The following description uses a press-fit IGBT as an example.
[0004] Currently, there are two packaging technology routes in the field of press-fit power semiconductor packaging: hard press-fit and soft press-fit.
[0005] The existing power semiconductor chip hard press packaging structure, such as Figure 1 As shown, the outer shell is similar to that of a conventional press-fit thyristor, typically using a traditional ceramic press-fit package. Internally, pressure is used to achieve electrical and thermal connections. The entire power semiconductor, from top to bottom, consists of a collector metal electrode 1, a collector molybdenum sheet 2, a connection layer 3, a chip 4, a connection layer 5, an emitter molybdenum sheet 6, an emitter metal electrode 7, and a tube shell 8. Existing hard-pressed packaging structures are characterized by their simplicity and ease of implementation. However, they suffer from uneven pressure and current distribution within the device due to processing errors among the various components, making it difficult to improve the operational reliability of the power semiconductor module.
[0006] In addition, the prior art power semiconductor chip soft press-fit packaging structure, such as Figure 2As shown, the package structure consists of an emitter metal electrode 1, a submodule frame 2, a disc spring assembly 3, a chip 4, a collector metal electrode 5, and a tube frame 6. This is also a press-fit power semiconductor package structure with pure pressure contact. While soft press-fit packaging offers the advantage of uniform pressure and current distribution within the device, it is complex and inconvenient for mass production. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a power semiconductor chip compression packaging structure and a manufacturing method, so that the pressure distribution and current distribution inside the semiconductor device are more uniform, thereby improving the operating reliability of the power semiconductor module.
[0008] The present invention provides a power semiconductor chip compression packaging structure, comprising: a collector electrode, the collector electrode including a soft layer region 1 located on the surface; and An emitter electrode, the emitter electrode includes a soft layer area 2 located on the surface, a plurality of chip sub-units are arranged between the emitter electrode and the collector electrode, the plurality of chip sub-units form a parallel relationship, and the collector and emitter of the chip sub-unit are respectively attached to and conductively connected to the soft layer area 1 and the soft layer area 2.
[0009] Optionally, the collector electrode is made of pure copper, a copper-based alloy or a copper-based composite material, and the collector electrode further includes a hard layer region 1 located outside the soft layer region 1.
[0010] Optionally, the emitter electrode is made of pure copper, a copper-based alloy or a copper-based composite material, and the emitter electrode further includes a second hard layer region located outside the second soft layer region.
[0011] Optionally, the copper-based alloy is a copper-zinc alloy, a copper-tin alloy, a copper-aluminum alloy, a copper-nickel alloy or a copper-nickel-zinc alloy.
[0012] Optionally, the copper-based composite material is a copper-molybdenum composite material, a copper-tin composite material, a copper-titanium composite material or a copper-nickel composite material.
[0013] Optionally, the method for preparing the copper-based composite material comprises the following steps: Pure copper powder, a mixture of copper powder and another metal powder and / or another metal powder are stacked in sequence; then pressed into shape in a mold, and then sintered to obtain a copper-based composite material.
[0014] Optionally, the power semiconductor chip press-fit packaging structure also includes a plurality of boss structures arranged on the side of the emitter electrode close to the chip sub-unit, at least one boss structure is arranged between each chip sub-unit and the emitter electrode, and the boss structure includes a soft layer area three connected to the chip sub-unit.
[0015] Optionally, the power semiconductor chip press-fit packaging structure further includes a tube shell frame made of insulating material and arranged between the collector electrode and the emitter electrode.
[0016] Optionally, the emitter electrode and the collector electrode are in the shape of a rectangular plate or a circular plate.
[0017] Optionally, the thickness of the collector electrode ranges from 3 to 6 mm, the thickness of the soft layer region 1 ranges from 0.05 to 2 mm; the thickness of the emitter electrode ranges from 3 to 6 mm, the thickness of the soft layer region 2 ranges from 0.05 to 2 mm; and the thickness of the soft layer region 3 ranges from 0.05 to 1 mm.
[0018] Optionally, the hardness of the hard layer zone 1 and the hard layer zone 2 is 100-180 HV; the hardness of the soft layer zone 1, the soft layer zone 2 and the soft layer zone 3 is 30-60 HV.
[0019] Optionally, the chip subunit includes a collector, a connection layer, a chip body, a connection layer and an emitter stacked in sequence, and can be electrically connected and mechanically fixedly connected by, but not limited to, connection processes such as sintering, welding and pressure.
[0020] Optionally, the collector and emitter are made of molybdenum sheets, and the connection layer can be made of nano-scale silver powder particles through low-temperature sintering to form a pure silver layer, or can also be formed by using, but not limited to, solder such as SAC through a vacuum reflow process to form a solder layer.
[0021] Optionally, the type of the chip body includes but is not limited to power semiconductor chips such as IGBT, FRD, and MOSFET.
[0022] A method for manufacturing a power semiconductor chip compression packaging structure comprises the following steps: The materials for the collector electrode and the emitter electrode are processed into a desired shape; then, a soft layer region 1 and a soft layer region 2 are formed on one side of the prepared material by laser annealing, or the prepared material is divided into two parts, one part is subjected to heat treatment annealing to reduce the hardness, and then the annealed prepared material and the unheat treated prepared material are tightly connected together by brazing or diffusion welding to prepare the collector electrode and the emitter electrode; Buffer pads are attached to the two poles of each chip sub-unit, and then multiple chip sub-units are arranged between the collector electrode and the emitter electrode in a designed distribution form and spacing, and then a press-fit packaging structure is obtained by a press-fit method.
[0023] A method for manufacturing a power semiconductor chip compression packaging structure comprises the following steps: The collector electrode, the emitter electrode and the plurality of boss structures are processed into a desired shape; then laser annealing is used to form the soft layer area one, the soft layer area two and the soft layer area three on the corresponding single side of the prepared material, or the prepared material is divided into two parts, one part is annealed by heat treatment to reduce the hardness, and then the prepared material after annealing treatment and the prepared material without heat treatment are tightly connected by brazing or diffusion welding to obtain the collector electrode, the emitter electrode and the boss structure; The plurality of boss structures are arranged on the surface of the soft layer area two of the emitter electrode in a designed distribution form and spacing; or the emitter electrode and the plurality of boss structures are integrally formed, and the soft layer area three is formed on the upper layer of the boss structure by laser annealing; The buffer gasket is attached to both poles of each chip subunit, and then a plurality of chip subunits are arranged between the soft layer area three of the collector electrode and each boss structure, and then the collector electrode, the emitter electrode, the boss structure and the chip subunit are tightly connected into an integral structure by crimping; The shell frame is welded between the collector electrode and the emitter electrode to obtain a crimping package junction.
[0024] It should be noted that the local laser annealing is realized by inputting laser energy to keep the metal above the recrystallization temperature for a period of time, promoting the growth of metal grains, and realizing the effect of local softening; the recrystallization temperature of pure copper is generally lower than 300℃, and the tensile strength of pure copper with an average grain size of 30 microns is lower than that of pure copper with an average grain size of 5 microns by more than 25%; The interconnection of the two materials with different hardness is realized by brazing or diffusion welding, and the brazing can be selected based on the metal substrate to ensure that the brazing and the metal substrate form a compound, such as Sn-based solder; diffusion welding can realize the mutual diffusion of the surface metal layer by depositing or electroplating one or more layers of metal on the surface of the substrate under certain temperature or pressure, and then forming an interconnection, such as physical and chemical vapor deposition of a layer of nano silver particles; for example, the interconnection of C11000 and C19010 two substrates can be realized by welding, the former has a hardness of about 80HV, and the latter has a hardness of about 130HV; The composition of different regions is adjusted and controlled by a mold, for example, pure copper powder can be added to one region, and Cu-Sn composite powder can be added to another region, and the hardness of Cu-Sn is about 190HV, and the hardness of pure copper can be as low as about 60HV.
[0025] The beneficial effects of the present application are that, since the collector electrode and the emitter electrode are respectively in contact with the two poles of the chip subunit through the soft layer area one and the soft layer area two, the hardness of the soft layer area one and the soft layer area two is low, in the process of crimping, the surface of the soft layer area one and the soft layer area two will creep and deform to fill the uneven surface of the two poles of the chip subunit due to machining errors, so that the collector electrode and the emitter electrode are more fully in contact with the two poles of the chip subunit, thereby making the internal pressure distribution and current distribution of the semiconductor device more uniform, also improving the internal conductivity and heat dissipation, and further improving the operation reliability of the power semiconductor module; in addition, the parts in the power semiconductor chip crimping packaging structure of the present application are simple in structure and few in number, which not only facilitates production and improves production efficiency, but also helps to reduce the internal failure rate of the semiconductor device.
[0026] The manufacturing method of the power semiconductor chip crimping packaging structure forms the soft layer area one and the soft layer area two on the inner side of the collector electrode and the emitter electrode through the method of local annealing by laser, which can automatically compensate for the height difference in the crimping packaging structure due to machining errors when the semiconductor chip is crimped, so as to obtain a semiconductor device with more uniform internal pressure distribution and current distribution, and the method is simple and efficient and suitable for mass production. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 It is a schematic diagram of the prior art power semiconductor chip hard crimping packaging structure; Figure 2 It is a schematic diagram of the prior art power semiconductor chip soft crimping packaging structure; Figure 3 It is a structure schematic diagram of the crimping packaging structure of the embodiment one of the present application; Figure 4 It is a structure schematic diagram of the crimping packaging structure of the embodiment two of the present application; Figure 5 It is a structure schematic diagram of the crimping packaging structure of the embodiment three of the present application; Figure 6 It is a structure schematic diagram of the crimping packaging structure of the chip subunit.
[0028] In the figure: 11, collector electrode; 111, soft layer area one; 12, emitter electrode; 121, soft layer area two; 13, boss structure; 131, soft layer area three; 14, buffer gasket; 15, tube shell frame; 20, chip subunit; 21, collector; 22, chip body; 23, emitter; 24, connection layer. DETAILED DESCRIPTION
[0029] As Figure 3-6As shown, the present invention provides a power semiconductor chip press-fit packaging structure, including: a collector electrode and an emitter electrode, the collector electrode includes a soft layer area 1 located on the surface; the emitter electrode includes a soft layer area 2 located on the surface, a plurality of chip sub-units are arranged between the emitter electrode and the collector electrode, the plurality of chip sub-units form a parallel relationship, and the collector and emitter of the chip sub-unit are respectively adhered to and conductively connected to the soft layer area 1 and the soft layer area 2.
[0030] Compared with the prior art, the power semiconductor chip press-fit packaging structure provided by the present invention has a collector electrode and an emitter electrode that contact the two poles of the chip sub-unit through soft layer area one and soft layer area two respectively. The hardness of soft layer area one and soft layer area two is relatively low. During the press-fitting process, the surfaces of soft layer area one and soft layer area two will creep and deform to fill the uneven surfaces of the two poles of the chip sub-unit due to processing errors, so that the collector electrode and the emitter electrode are in more sufficient contact with the two poles of the chip sub-unit, thereby making the internal pressure distribution and current distribution of the semiconductor device more uniform, and also improving the internal conductivity and heat dissipation, thereby improving the operating reliability of the power semiconductor module; in addition, the various parts in the power semiconductor chip press-fit packaging structure are simple in structure and small in number, which not only facilitates production and improves production efficiency, but also helps to reduce the failure rate inside the semiconductor device.
[0031] In this embodiment, the material of the collector electrode and the emitter electrode is pure copper, copper-based alloy or copper-based composite material. The collector electrode also includes a hard layer area one located outside the soft layer area one; the emitter electrode also includes a hard layer area two located outside the soft layer area two. With this arrangement, the outer sides of the collector electrode and the emitter electrode are not easily deformed during crimping, which is beneficial to the stability and accuracy of the overall shape of the crimped packaging structure.
[0032] It should be noted that the hard layer area 1 and the soft layer area 1 can be a continuous integral structure or a tightly connected split structure; the hard layer area 2 and the soft layer area 2 can be a continuous integral structure or a tightly connected split structure.
[0033] In this embodiment, the copper-based alloy may be, but is not limited to, a copper-zinc alloy, a copper-tin alloy, a copper-aluminum alloy, a copper-nickel alloy, or a copper-nickel-zinc alloy.
[0034] In this embodiment, the copper-based composite material may be, but is not limited to, a copper-molybdenum composite material, a copper-tin composite material, a copper-titanium composite material, or a copper-nickel composite material.
[0035] In one embodiment, the method for preparing the copper-molybdenum composite material comprises the following steps: First, pure copper powder is spread flat in the mold, and then a mixture of copper powder and molybdenum powder is spread flat on top of the pure copper powder; then pressure is applied with a punch to press and form the blanks. The pressed blanks are taken out and placed in a sintering furnace in batches. In a nitrogen atmosphere, isostatic pressing is performed. The temperature is first raised to 700°C and kept warm for 1 hour, then raised to 900°C and kept warm for 2 hours, and then cooled. After turning and grinding, a copper-molybdenum composite material that meets the design requirements is obtained, which is in the shape of a square flat plate.
[0036] In another embodiment, the method for preparing the copper-tin composite material comprises the following steps: First, pure copper powder is spread flatly in a mold, and then a mixture of copper powder and tin powder is spread flatly on the pure copper powder; then, a punch is used to apply pressure for pressing and molding, and the pressed blanks are taken out and placed in a sintering furnace in batches. In a nitrogen atmosphere, the blanks are isostatically pressed and sintered, first heated to 160°C and kept warm for 1 hour, then heated to 210°C and kept warm for 2 hours, and then cooled. After turning and grinding, a copper-tin composite material that meets the design requirements is obtained, which is in the shape of a round flat plate; the pure copper area of the copper-tin composite material can be used to make soft layer area one or soft layer area two, and the copper-tin mixed area can be used to make hard layer area one or hard layer area two.
[0037] In one embodiment, the power semiconductor chip press-fit packaging structure also includes multiple boss structures arranged on the side of the emitter electrode close to the chip sub-unit, at least one boss structure is arranged between each chip sub-unit and the emitter electrode, and the boss structure includes a soft layer area three connected to the chip sub-unit.
[0038] Specifically, the shape of the boss structure is a cube or a cuboid, and it is made of the same material as the emitter electrode. A continuous, regularly shaped material can be used to form the emitter electrode and the boss structure through machining, or the emitter electrode and the boss structure can be integrally formed by casting. It should be noted that the side where the boss structure is connected to the chip sub-unit is the soft layer area three. The method for obtaining the soft layer area three is described below. Since power semiconductor modules usually use multi-chip parallel packaging, there are height differences between the components of each chip due to processing accuracy, which will lead to pressure and current imbalance in the power semiconductor module, and thus cause malfunction or failure of the power semiconductor module. The role of the boss structure is to act as a pressure buffer to improve or compensate for the height difference caused by the uneven thickness of each chip component.
[0039] In this embodiment, the power semiconductor chip press-fit packaging structure further includes a tube shell frame made of insulating material and arranged between the collector electrode and the emitter electrode.
[0040] Specifically, the shell frame can be made of, but not limited to, ceramic or engineering plastic. The shell frame surrounds the area where the chip sub-unit is located, and both ends of the shell frame are sealed and packaged with the collector electrode and the emitter electrode respectively by cold pressure welding or argon arc welding.
[0041] In this embodiment, please refer to Figure 6 The chip subunit includes a collector, a connection layer, a chip body, a connection layer, and an emitter, which are stacked in sequence. Electrical and mechanical connections can be achieved through, but are not limited to, sintering, welding, and crimping. The collector and emitter are made of molybdenum sheets. The connection layer can be formed by low-temperature sintering of nano-sized silver powder particles to form a pure silver layer. Alternatively, a solder layer can be formed using, but is not limited to, a vacuum reflow process using solder such as SAC. The connection layer serves to electrically and mechanically connect the collector to the collector molybdenum sheet, and the emitter to the emitter molybdenum sheet.
[0042] In this embodiment, the types of chip bodies include but are not limited to power semiconductor chips such as IGBT, FRD, and MOSFET.
[0043] Example 1 See also Figure 3 A method for manufacturing a power semiconductor chip press-fit packaging structure comprises the following steps: S1. Pure copper is used as the preparation material for the collector electrode and the emitter electrode, and is machined into rectangular flat plates to obtain pure copper plates of two thicknesses; S2. Laser annealing is then performed on one side of the two pure copper plates to soften them, forming soft layer regions 1 and 2, respectively, to form the collector and emitter electrodes. The purpose of annealing is to reduce hardness and eliminate residual stress. The laser annealing employed in this embodiment begins by laying the pure copper plates flat in an annealing furnace and heating them to a set temperature (50-100°C below the critical temperature of the pure copper plates). After reaching the set temperature, the plates are held at this temperature for approximately 1 hour to achieve uniform internal temperature. Finally, the plates are removed from the annealing furnace and allowed to cool naturally. After machining and visual inspection, the collector and emitter electrodes that meet the design requirements are produced.
[0044] S3. Attach buffer pads made of silver material to both electrodes of each chip sub-unit by means of compression bonding. First, place the tube shell frame between the collector electrode and the emitter electrode. Then, evenly distribute the three chip sub-units within the tube shell frame between the collector electrode and the emitter electrode. Finally, connect the chip sub-units to the soft layer area 1 of the collector electrode and the soft layer area 2 of the emitter electrode by means of compression bonding. S4. Connect the collector electrode and the emitter electrode to the tube shell frame by cold pressure welding to achieve sealed packaging.
[0045] Example 2 See also Figure 4 A method for manufacturing a power semiconductor chip press-fit packaging structure comprises the following steps: S1. Using a copper-tin composite material as the preparation material for the collector electrode and the emitter electrode, and machining it into a rectangular flat plate to obtain two thicknesses of copper-tin composite plates, the thicker one being used to make the emitter electrode; S2. forming a soft layer region 1 on one side of the copper-tin composite plate for forming the collector electrode by laser annealing to obtain the collector electrode; S3, turning three evenly distributed boss structures on one side of the copper-tin composite plate for making the emitter electrode, and then forming a second soft layer region on top of the boss structure by laser annealing to obtain an emitter electrode and boss structure of an integrally formed structure; S4. Buffer pads made of heat-annealed pure copper are attached to both electrodes of each chip sub-unit by means of compression bonding. A tube shell frame is first placed between the collector electrode and the emitter electrode. A chip sub-unit is then placed between the collector electrode and each boss structure. Finally, the collector electrode, emitter electrode, boss structure, and chip sub-unit are compressed to form a tightly connected integral structure. Among them, the use of a buffer gasket can creep and deform during the crimping process, realizing automatic compensation of machining errors in the chip sub-unit, making the pressure distribution and current distribution inside the chip sub-unit more uniform; S5. Connect the collector electrode and the emitter electrode to the tube shell frame by argon arc welding to achieve sealed packaging.
[0046] Example 3 See also Figure 5 A method for manufacturing a power semiconductor chip press-fit packaging structure comprises the following steps: S1. Casting a copper-zinc alloy and then machining and shaping it to obtain a first hard layer region of the collector electrode, a second hard layer region of the emitter electrode, and a third hard layer region of the boss structure; S2, sequentially casting, heating annealing, and machining the copper-zinc alloy to obtain a first soft layer region of the collector electrode, a second soft layer region of the emitter electrode, and a third soft layer region of the boss structure; S3, connecting the hard layer region 1, the emitter electrode hard layer region 2, and the hard layer region 3 of the boss structure to the soft layer region 1, the soft layer region 2, and the soft layer region 3 respectively by brazing to obtain a collector electrode, an emitter electrode, and a boss structure; S4. Arrange the tube shell frame between the collector electrode and the emitter electrode, stack the collector electrode, three chip sub-units, three boss structures, and the emitter electrode, and then press-fit the collector electrode, emitter electrode, boss structure, and chip sub-unit to form a tightly connected integral structure; S5. Connect the collector electrode and the emitter electrode to the tube shell frame by argon arc welding to achieve sealed packaging.
[0047] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.
[0048] The one or more embodiments of this application are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this application should be included in the scope of protection of this application.
Claims
1. A power semiconductor chip press-fit packaging structure, characterized in that: include: a collector electrode, the collector electrode including a soft layer region 1 located on the surface; as well as An emitter electrode, the emitter electrode includes a soft layer area 2 located on the surface, a plurality of chip sub-units are arranged between the emitter electrode and the collector electrode, the plurality of chip sub-units form a parallel relationship, and the collector and emitter of the chip sub-unit are respectively attached to and conductively connected to the soft layer area 1 and the soft layer area 2.
2. The power semiconductor chip press-fit packaging structure according to claim 1, characterized in that: The material of the collector electrode is pure copper, copper-based alloy or copper-based composite material, and the collector electrode also includes a hard layer area 1 located outside the soft layer area 1.
3. The power semiconductor chip press-fit packaging structure according to claim 1, characterized in that: The emitter electrode is made of pure copper, copper-based alloy or copper-based composite material, and the emitter electrode further includes a second hard layer region located outside the second soft layer region.
4. The power semiconductor chip press-fit packaging structure according to claim 2 or 3, characterized in that: The copper-based alloy is a copper-zinc alloy, a copper-tin alloy, a copper-aluminum alloy, a copper-nickel alloy or a copper-nickel-zinc alloy.
5. The power semiconductor chip press-fit packaging structure according to claim 2 or 3, characterized in that: The copper-based composite material is a copper-molybdenum composite material, a copper-tin composite material, a copper-titanium composite material or a copper-nickel composite material.
6. The power semiconductor chip press-fit packaging structure according to claim 5, characterized in that: The preparation method of the copper-based composite material comprises the following steps: Pure copper powder, a mixture of copper powder and another metal powder and / or another metal powder are stacked in sequence; then pressed into shape in a mold, and then sintered to obtain a copper-based composite material.
7. The power semiconductor chip press-fit packaging structure according to any one of claims 1 to 3 and 6, characterized in that: It also includes a plurality of boss structures arranged on the side of the emitter electrode close to the chip sub-unit, at least one boss structure is arranged between each chip sub-unit and the emitter electrode, and the boss structure includes a soft layer area three connected to the chip sub-unit.
8. The power semiconductor chip press-fit packaging structure according to claim 7, characterized in that: It also includes a tube shell frame made of insulating material and arranged between the collector electrode and the emitter electrode.
9. A method for manufacturing a power semiconductor chip press-fit packaging structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: Processing the materials for the collector electrode and the emitter electrode into required shapes; Then, a soft layer region 1 and a soft layer region 2 are formed on one side of the prepared material by laser annealing, or the prepared material is divided into two parts, one part is subjected to heat treatment annealing to reduce the hardness, and then the annealed prepared material and the unheat treated prepared material are tightly connected together by brazing or diffusion welding to form a collector electrode and an emitter electrode; Buffer pads are attached to the two poles of each chip sub-unit, and then multiple chip sub-units are arranged between the collector electrode and the emitter electrode in a designed distribution form and spacing, and then a press-fit packaging structure is obtained by a press-fit method.
10. A method for manufacturing a power semiconductor chip press-fit packaging structure according to claim 8, characterized in that: The following steps are involved: The preparation materials of the collector electrode, the emitter electrode and the plurality of boss structures are processed into the required shapes; then, a soft layer region 1, a soft layer region 2 and a soft layer region 3 are formed respectively on one side of the corresponding preparation material by laser annealing, or the preparation material is divided into two parts, one part is subjected to heat treatment annealing to reduce the hardness, and then the annealed preparation material and the unheat treated preparation material are tightly connected together by brazing or diffusion welding to obtain the collector electrode, the emitter electrode and the boss structure; Arranging a plurality of boss structures on the surface of the second soft layer region of the emitter electrode in a designed distribution form and spacing; or forming the emitter electrode and the plurality of boss structures as an integrally formed structure, and forming the third soft layer region on the upper layer of the boss structures by laser annealing; Buffer pads are attached to both electrodes of each chip sub-unit, and then several chip sub-units are arranged between the collector electrode and the soft layer area 3 of each boss structure. Then, the collector electrode, emitter electrode, boss structure and chip sub-unit are pressed together to form a tightly connected integral structure. A tube shell frame is welded at the edge between the collector electrode and the emitter electrode to obtain a press-fit packaging structure.