Source degeneration harmonic rejection frequency doubler

Abstract

The application discloses a source degeneration type harmonic suppression frequency doubler, which comprises an input transformer, a transistor pair and a source degeneration network and an output transformer connected with the transistor pair in sequence, wherein the gate of the transistor pair is connected with the output end of the input transformer, the drain is connected with the output transformer, and the source is connected with the input end of the source degeneration network respectively. The application can realize high fundamental wave suppression ratio in the output frequency of more than 30GHz and a wide output frequency range by suppressing the output harmonic of the frequency doubler through the internally integrated source degeneration structure, and can simultaneously improve the fourth harmonic suppression ability through the harmonic impedance shaping technology while maintaining the wideband input matching characteristics.

Description

Technical Field

[0001] This invention relates to a technology in the field of communication, specifically a source-degraded harmonic suppression frequency multiplier. Background Technology

[0002] Existing harmonic suppression schemes for millimeter-wave frequency multipliers mainly employ either injection-locked or cascaded filter schemes. Injection-locked schemes suppress harmonics through the frequency selectivity of the resonant cavity; however, the limited Q value of the resonant cavity leads to significant bandwidth compression of the frequency multiplier, failing to meet the high bandwidth requirements of millimeter-wave communication systems. Furthermore, the additional injection-locked stage increases circuit hardware complexity and power consumption. Cascaded filter schemes suppress harmonics by connecting a bandpass filter in series at the output, but due to the limited Q value of filters in the millimeter-wave band, achieving a high harmonic rejection ratio is difficult. Simultaneously, it attenuates the conversion gain, requiring an additional compensation amplifier, which reduces system efficiency. Summary of the Invention

[0003] This invention addresses the bottleneck problem of insufficient fundamental frequency leakage suppression in existing millimeter-wave frequency multipliers under input balun phase / amplitude mismatch, and the limited harmonic suppression performance of existing broadband frequency multipliers which only achieves limited harmonic suppression through the frequency selection characteristics of the output matching network, and whose harmonic suppression performance is limited by the finite Q value of passive networks in the millimeter-wave band. It proposes a source-degraded harmonic suppression frequency multiplier, which suppresses output harmonics through an internally integrated source-degraded structure, achieving a high fundamental frequency rejection ratio at output frequencies above 30 GHz and over a wide output frequency range. Furthermore, it simultaneously enhances fourth-order harmonic suppression capability through harmonic impedance shaping technology while maintaining broadband input matching characteristics.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a source degradation type harmonic suppression frequency multiplier, comprising: an input transformer, a transistor pair, a source degradation network connected in sequence to the transistor pair, and an output transformer, wherein: the gate of the transistor pair is connected to the output terminal of the input transformer, the drain is connected to the output transformer, and the source is connected to the input terminal of the source degradation network.

[0006] This invention relates to a fundamental frequency suppression method based on the above-mentioned source-degraded harmonic suppression frequency multiplier, comprising:

[0007] Step 1: Model the transformer phase mismatch as the mismatch voltage v of the transistor pair. offset ;

[0008] Step 2: The mismatch voltage is converted into the single-ended fundamental leakage current v of the transistor pair. offset* g m , where: g m Transconductance of a transistor;

[0009] Step 3: Due to the high impedance characteristic of the fundamental frequency of the source degradation network, the single-ended fundamental leakage current cannot completely flow to ground due to the obstruction of the source degradation network. The transfer function from the transistor gate mismatch voltage to the output fundamental leakage voltage is... Where: Ld is the load inductance of the frequency multiplier; Ls is the parallel inductance of the source degradation network; Cs is the parallel capacitance of the source degradation network; and s is a complex variable in the Laplace transform. From the equation, it can be deduced that when Ls and Cs resonate at the fundamental frequency, since the source impedance is infinite at the fundamental frequency, the single-ended fundamental leakage current generated by the mismatch voltage cannot flow to ground. Therefore, the numerator term in the transfer function... Theoretically, infinite suppression of the fundamental frequency can be achieved when the fundamental frequency is 0.

[0010] Technical effect

[0011] This invention employs a source-degraded harmonic suppression architecture. By constructing a high-impedance network at the transistor source, it directs the fundamental current caused by input mismatch to an internal loop path, suppressing the generation of the fundamental voltage at the output node. This network exhibits high impedance characteristics at the fundamental frequency to achieve harmonic suppression, while maintaining low impedance characteristics at the second harmonic to avoid conversion gain loss. It eliminates the need for additional cascaded filter circuits or injection-locked modules, and does not significantly increase hardware complexity or system power consumption. Compared to existing technologies, this invention achieves high harmonic suppression by exhibiting high impedance at the fundamental frequency. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of the present invention;

[0013] Figure 2 and Figure 3 This is a schematic diagram illustrating the effect of an example. Detailed Implementation

[0014] like Figure 1 As shown, this embodiment relates to a source degradation type harmonic suppression frequency multiplier, including: an input transformer, transistor pairs M1 and M2 connected in sequence, a source degradation network connected to the transistor pairs respectively, and an output transformer, wherein: the gate of the transistor pair is connected to the output terminal of the input transformer, the drain is connected to the output transformer, and the source is connected to the input terminal of the source degradation network respectively.

[0015] The input transformer includes: a primary winding L1 and a parallel capacitor C1 forming the primary terminal, and a secondary winding L2 and a parallel capacitor C1 forming the secondary terminal. 31 C 32 The secondary terminal, consisting of the center tap capacitor C2 of the secondary coil, and the capacitors and inductors in the input transformer form a fourth-order magnetically coupled resonant cavity structure for broadband input matching.

[0016] The transistors M1 and M2 have a second-order nonlinearity used to generate a second-harmonic current. The second-harmonic current is transmitted to the frequency multiplier output through the output transformer, thereby completing the frequency multiplication function.

[0017] The output transformer includes a primary coil L3, a secondary coil L4, and a parallel capacitor C4 for the primary coil. One end of the primary coil L3 is grounded, and the other end is connected to the drain of the transistor pair. One end of the secondary coil L4 is grounded, and the other end is the output terminal of the frequency multiplier. The grounded end of the primary coil L3 is coupled to the output terminal of the frequency multiplier of the secondary coil L4.

[0018] The source degradation network includes: mutually coupled differential source degradation inductor pairs L sd capacitors in parallel and inductor Among them: inductance pair One end is connected to the source of transistor pair M1 and M2, and the other end is connected to a capacitor in parallel. and inductor Capacitors connected in series and in parallel and inductor The other end is grounded, and the inductor is connected to the ground. The end connected to the source is connected in parallel with a capacitor. and inductor The connected ends are coupled.

[0019] The parallel capacitor ,inductance The parallel resonant frequency is set at the fundamental frequency. Therefore, it exhibits high impedance characteristics at the fundamental frequency.

[0020] This embodiment relates to a fundamental frequency suppression method based on the above-mentioned source-degraded harmonic suppression frequency multiplier, including:

[0021] Step 1: Model the input transformer phase mismatch as the mismatch voltage of the gate of transistor M1 or M2;

[0022] Step 2: The mismatch voltage is converted into the single-ended fundamental leakage current of the M1 or M2 transistor channel;

[0023] Step 3, by , The resonant frequency is taken as the input frequency where high fundamental frequency suppression is required. Due to the obstruction of the source degradation network, the single-ended fundamental frequency leakage current cannot flow completely into the ground, thus achieving high harmonic suppression at the input frequency and in the close frequency band.

[0024] The transfer function from the gate mismatch voltage to the output fundamental leakage voltage. ,in: This represents the load inductance value of the frequency multiplier. The value of the parallel inductance of the source degradation network. The value of the parallel capacitance of the source degradation network. For the complex variables of the Laplace transform, This refers to the transconductance of the transistor.

[0025] Through specific experiments, circuit simulation was performed using the SpectraRF simulator in the Cadance environment. The transistor model adopted the TSMCN40 process library NMOS transistor with a transistor size of 16*2um / 40nm. The passive device adopted the INDQ model, with Ls set to 400pH, Q value set to 15, and Cs set to 120fF. The leakage harmonic energy of the present invention with respect to the input frequency was obtained through simulation. Figure 2 As shown, the frequency multiplier conversion gain of the present invention is as follows with respect to the input frequency: Figure 3 As shown.

[0026] like Figure 2 As shown in the figure, the simulation results of the fundamental frequency energy leakage of the frequency multiplier as a function of the input frequency are presented. It can be seen from the figure that, compared with the fundamental frequency energy leakage of the traditional frequency multiplier (set as a relative value of 0dB) shown by the black line, the proposed frequency multiplier can achieve a fundamental frequency energy suppression of more than 25dB at a single frequency point of 20GHz, and a fundamental frequency energy suppression of more than 10dB in the frequency band from 16GHz to 24GHz. The corresponding output bandwidth (32GHz to 48GHz) is sufficient to cover the high frequency band of 5G FR2 (37GHz to 43GHz), which proves the broadband characteristics of the fundamental frequency energy suppression scheme proposed in this invention.

[0027] like Figure 3 As shown, after adopting the present invention, the conversion gain in the 16GHz to 24GHz frequency band drops by less than 2.5dB, proving that the resonant network proposed in this invention has no significant impact on the gain of the frequency multiplier.

[0028] Compared with existing technologies, the source degradation network of this invention exhibits high impedance characteristics at the fundamental frequency, which can prevent the fundamental current caused by input transformer mismatch from flowing to ground, thereby suppressing the generation of fundamental signal at the output and producing a better fundamental suppression effect.

[0029] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A source-degraded harmonic suppression frequency multiplier, characterized in that, include: An input transformer, a pair of transistors, and a source degradation network and an output transformer connected in sequence are arranged in sequence, wherein: the gate of the transistor pair is connected to the output terminal of the input transformer, the drain is connected to the output transformer, and the source is connected to the input terminal of the source degradation network. The source degradation network includes: mutually coupled differential source degradation inductor pairs L sd A parallel capacitor C s and inductor L s Where: inductance to L sd One end is connected to the source of transistor pair M1 and M2, and the other end is connected to the parallel capacitor C. s and inductor L s Capacitors C connected in parallel s and inductor L s The other end is grounded, and the inductor is connected to L. sd The end connected to the source is connected in parallel with a capacitor C. s and inductor L s The connected ends are coupled.

2. The source-degraded harmonic suppression frequency multiplier according to claim 1, characterized in that, The parallel capacitor C s Inductor L s The parallel resonant frequency is set at the fundamental frequency to exhibit high impedance characteristics at the fundamental frequency.

3. The source-degraded harmonic suppression frequency multiplier according to claim 1, characterized in that, The input transformer includes: a primary winding L1 and a parallel capacitor C1 forming the primary terminal, and a secondary winding L2 and a parallel capacitor C1 forming the secondary terminal. 31 C 32 The secondary terminal, consisting of the center tap capacitor C2 of the secondary coil, and the capacitors and inductors in the input transformer form a fourth-order magnetically coupled resonant cavity structure for broadband input matching.

4. The source-degraded harmonic suppression frequency multiplier according to claim 1, characterized in that, The transistors M1 and M2 have a second-order nonlinearity used to generate a second-harmonic current. The second-harmonic current is transmitted to the frequency multiplier output through the output transformer, thereby completing the frequency multiplication function.

5. The source-degraded harmonic suppression frequency multiplier according to claim 1, characterized in that, The output transformer includes a primary coil L3, a secondary coil L4, and a parallel capacitor C4 for the primary coil. One end of the primary coil L3 is grounded, and the other end is connected to the drain of the transistor pair. One end of the secondary coil L4 is grounded, and the other end is the output terminal of the frequency multiplier. The grounded end of the primary coil L3 is coupled to the output terminal of the frequency multiplier of the secondary coil L4.

6. A method for fundamental frequency suppression based on the source-degraded harmonic suppression frequency multiplier according to any one of claims 1-5, characterized in that, include: Step 1: Model the input transformer phase mismatch as the mismatch voltage of the gate of transistor M1 or M2; Step 2: The mismatch voltage is converted into the single-ended fundamental leakage current of the M1 or M2 transistor channel; Step 3: By taking the resonant frequencies of Ls and Cs as the input frequencies where high fundamental frequency suppression is required, the single-ended fundamental leakage current will not be able to flow completely into ground due to the obstruction of the source degradation network, thereby achieving high harmonic suppression at the input frequency and in the similar frequency band.

7. The fundamental frequency suppression method according to claim 6, characterized in that, The transfer function from the gate mismatch voltage to the output fundamental leakage voltage. Where: Ld is the load inductance of the frequency multiplier; Ls is the parallel inductance of the source degradation network; Cs is the parallel capacitance of the source degradation network; s is the complex variable of the Laplace transform; and gm is the transconductance of the transistor.

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