Beacon-based approach guidance system

Abstract

A beacon-based approach guidance system is disclosed. The disclosed method includes digitizing at least one signal received at an antenna array of a receiver of a vehicle into a digitized data stream of I and Q samples, the at least one signal received from a beacon, the at least one signal modulated at the beacon with a pseudo-random code, the I and Q samples are associated with a locally generated pseudo-random code of the receiver to recover the carrier signal, and a direction of arrival of the at least one signal from the beacon in the vehicle reference frame is calculated based on a relative phase characteristic of the recovered carrier signal.

Description

Technical Field

[0001] The present disclosure relates generally to vehicle guidance and, more particularly, to a beacon-based approach guidance system. Background Art

[0002] Vertical take-off and landing (VTOL) aircraft may require guidance for landing. Specifically, autonomous commercial VTOL aircraft carrying passengers may require precise positioning and attitude determination to meet regulatory certification requirements. Additionally, some passenger aircraft may require redundant and / or secondary guidance systems. Summary of the Invention

[0003] An example method includes digitizing at least one signal received at an antenna array of a receiver of a vehicle into a digitized data stream of I and Q samples, the at least one signal being received from a beacon, the at least one signal being modulated with a pseudorandom code at the beacon; correlating the I and Q samples with a locally generated pseudorandom code at the receiver to recover a carrier signal; and calculating a direction of arrival of the at least one signal from the beacon in a vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0004] An example apparatus for guiding a vehicle includes an interface circuit system communicatively coupled to an antenna array of the vehicle, the antenna array including respective antennas for receiving a signal transmitted from a beacon, the transmitted signal modulated at the beacon with a pseudorandom code; machine-readable instructions; and at least one processor circuit programmed with the machine-readable instructions to downconvert and digitize the signal received at the antenna array into baseband I and Q samples, correlate the I and Q samples with a locally generated pseudorandom code to align the received signal in time, despread the received signal by modulating the received signal with a synchronized pseudorandom noise (PRN) code to recover the carrier signal, and calculate a heading and elevation of a direction of arrival of the signal transmitted from the beacon in a vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0005] An example receiver for guiding a vehicle includes an antenna array for receiving a signal transmitted from a beacon, the transmitted signal being modulated with a pseudorandom code at the beacon; a digitizer for digitizing the signal received at the antenna into a digitized signal having I and Q samples, the digitized signal being modulated with a locally generated pseudorandom code; and a software-defined radio for correlating the I and Q samples with the locally generated pseudorandom code to recover a carrier signal from the digitized signal and to calculate a direction of arrival of the signal from the beacon in the vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0006] An example non-transitory machine-readable storage medium includes instructions for causing at least one processor circuit to digitize a signal received at an antenna array of a receiver of a vehicle into at least a stream of I and Q samples, the received signal corresponding to a transmitted signal from a beacon, the transmitted signal modulated at the beacon with a pseudo-random code; correlate the I and Q samples with a locally generated pseudo-random code of the receiver to align the received signal in time, despread the received signal by modulating the signal with a synchronized pseudo-random noise (PRN) code to recover a carrier signal; and compute a heading and an elevation of a direction of arrival of the vehicle relative to the beacon in a vehicle reference frame based on a relative phase characteristic of the recovered carrier signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is an example beacon-based vehicle guidance system in accordance with the teachings of this disclosure.

[0008] Figure 2 is an example method that can be implemented in the examples disclosed herein.

[0009] Figure 3 is a schematic overview of an example beacon circuit in accordance with the teachings of this disclosure.

[0010] Figure 4 is a schematic overview of an example receiver in accordance with the teachings of this disclosure.

[0011] Figure 5 is a schematic overview of an example receiver circuit in accordance with the teachings of this disclosure.

[0012] Figure 6 is a schematic overview of another example receiver circuit in accordance with the teachings of this disclosure.

[0013] Figure 7 shows an example calculation in a beacon reference frame that can be implemented in the examples disclosed herein.

[0014] Figure 8 shows an example signal that can be implemented in the examples disclosed herein.

[0015] Figure 9 is a schematic overview of another example beacon circuit in accordance with the teachings of this disclosure.

[0016] Figure 10 shows an example quadrant antenna that can be implemented in the examples disclosed herein.

[0017] Figure 11 shows an example directivity pattern that can be implemented in the examples disclosed herein.

[0018] Figure 12is a schematic overview of an alternative example receiver processing according to the teachings of the present disclosure.

[0019] Figure 13 Example multipath control that may be implemented in the examples disclosed herein is shown.

[0020] Figures 14A-14C Example antenna configurations are shown that may be implemented in the examples disclosed herein.

[0021] Figure 15 is a flow chart representing an example method of operating a beacon according to the teachings of the present disclosure.

[0022] Figure 16 is a block diagram of an example receiver analysis system in accordance with the teachings of the present disclosure.

[0023] Figure 17 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed by example programmable circuitry to implement Figure 16 Receiver 102.

[0024] Figure 18 is a block diagram of an example processing platform including programmable circuitry configured to run, instantiate, and / or execute example machine-readable instructions and / or perform Figure 17 Example operations to implement Figure 16 Receiver 102.

[0025] Figure 19 yes Figure 18 A block diagram of an example implementation of a programmable circuit system.

[0026] Figure 20 yes Figure 18 A block diagram of another example implementation of a programmable circuit system.

[0027] Generally, the same reference numerals will be used throughout the drawings and accompanying written description to refer to the same or similar parts. The figures are not necessarily drawn to scale. Rather, the thickness of layers or regions may be exaggerated in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or irregular. DETAILED DESCRIPTION

[0028] A beacon-based approach guidance system is disclosed. A vertiport is a landing site that enables aircraft, such as rotary-wing aircraft, unmanned aerial vehicles (UAVs), manned vehicles, and the like, to land. Some of these aircraft can carry passengers, which can require the necessary accuracy and / or assisted guidance implementation.

[0029] Examples disclosed herein implement an approach and landing guidance system for aerial vehicles, such as vertical take-off and landing (VTOL) aircraft. Examples disclosed herein can significantly reduce the complexity and cost of ground-based infrastructure. Moreover, examples disclosed herein can also be highly portable and easy to deploy. Examples disclosed herein do not require a processor. Examples disclosed herein can be implemented on circuitry that can be controlled with a deterministic state machine, thus eliminating the need to develop or certify complex software, which can be time-consuming and expensive. By implementing a relatively hassle-free analysis of potential failure modes, examples disclosed herein can be highly reliable. Examples disclosed herein can be implemented on an application-specific integrated circuit (ASIC). According to some examples disclosed herein, only a single selection of a pseudo-random noise (PRN) code to be generated is input to the system. In some such examples, the selection can be implemented, for example, by a dip switch or a soldered link on a circuit board.

[0030] Examples disclosed herein utilize a ground-based beacon that transmits at least one signal over a carrier. The signal is modulated with a PRN code via a signal generator and includes the carrier signal. In turn, an antenna array of a receiver of a vehicle, such as an aircraft, that can be manned or unmanned receives the signal. The signal received at the vehicle is down-converted and digitized into data streams of digitized signals that define respective I and Q samples of a baseband signal. The I and Q samples are correlated with a locally generated PRN code to align the local code with the code received from the beacon. In turn, the input signal is demodulated with the aligned code and, thus, the carrier signal is recovered for each element of the antenna array. Based on the phase of the recovered carrier signal, at least one of a relative heading, orientation, and / or position of the vehicle with respect to the beacon is determined. Additionally or alternatively, a direction of arrival of the signal with respect to a vehicle / antenna frame of reference is determined. In turn, a position of the vehicle, such as a position of the vehicle in a frame of reference of the beacon, can be determined with an independent measurement of an altitude above a landing site in combination with a pitch, roll, and heading of the aircraft. In some examples, the data streams are provided to a discriminator and, in turn, an average signal error is determined with an output of the discriminator. According to some examples disclosed herein, the average signal error is utilized to drive a single code generator to recover the carrier signal.

[0031] In some examples, the beacon transmits multiple signals for detection by the antenna array of the vehicle. In some such examples, the beacon transmits the signals through directional beams that effectively form quadrants of the beacon coverage area. In some such examples, the signal power of the code of the carrier wave is estimated and compared to obtain information related to the orientation of the vehicle relative to the beacon.

[0032] Figure 1 An example beacon-based vehicle guidance system 100 in accordance with the teachings of the present disclosure. The beacon-based vehicle guidance system 100 of the illustrated example can be referred to as a vertiport approach and landing system (VALS) and includes a vehicle 101 carrying a receiver or receiver circuitry / hardware 102 (hereinafter referred to as receiver 102) and an antenna array 104. Although the vehicle 101 is implemented as an aircraft in this example, the vehicle 101 can be implemented as any other suitable vehicle including, but not limited to, a ground-based vehicle, a watercraft, a submersible, a spacecraft, etc. In Figure 1 In the illustrated example, a landing area (e.g., landing pad, vertiport, etc.) is defined on a surface (e.g., ground) 108. In turn, the surface 108 of the landing area (e.g., vertiport, landing spot, etc.) 109 supports a beacon 110, which is ground-based in this example. In turn, the example beacon 110 includes a transmitter 112 and can include a battery 114.

[0033] The beacon 110 of the illustrated example is generally circular in shape (e.g., similar to a disc shape) and also has a relatively low profile height. In this particular example, the beacon 110 has a height of approximately 1.5 inches (in) to 2.5 inches relative to the surface 108. However, the beacon can be any other suitable shape, geometry, and / or size. According to some examples disclosed herein, the beacon 110 includes the battery 114 described above to enable its portability and relatively quick deployment. According to some other examples, the beacon 110 can be powered by connection to a conventional power infrastructure that is permanently fixed installed. In some examples, the signals transmitted from the beacon 110 include a relatively high chip rate (e.g., 50.9 Mchips). In some examples, multiple transmission orthogonal codes (e.g., from a family of orthogonal codes) are used in the beacon 110 to reduce and / or eliminate interference from neighboring beacons. For example, the beacon 110 can transmit a CDMA signal. The example beacon 110 can be self-monitoring.

[0034] According to examples disclosed herein, the example receiver 102 is to receive at least one signal from a beacon 110 supported by (e.g., resting on) the ground 108. According to examples disclosed herein, the receiver 102 is to determine and / or measure a direction of arrival of the at least one signal transmitted from the beacon 110. The direction of arrival can be determined with respect to a vehicle frame of reference (e.g., as a unit vector pointing from the antenna array to the beacon). In particular, the example receiver 102 can be used to determine a heading and an elevation of the vehicle 101 with respect to the beacon 110. Thus, the direction of arrival can be utilized to determine a position of the vehicle 101 (e.g., a position of the vehicle 101 with respect to the beacon 110, a position of the vehicle 101 in a beacon frame of reference, etc.).

[0035] The antenna array 104 of the illustrated example includes an antenna array having a plurality of elements, including but not limited to three elements, four elements, five elements, six elements, etc. According to examples disclosed herein, the antenna array 104 is oriented in a general direction of the beacon 110. In some examples, the antenna array 104 utilizes a plurality of transmitters.

[0036] In some examples, the beacon 110 transmits a code division multiple access (CDMA) signal (e.g., from a series of orthogonal codes). According to some examples disclosed herein, the beacon 110 can transmit a plurality of signals (e.g., from a quadrant of the beacon 110). In some examples, an altitude of the vehicle 101 is maintained via a barometer (e.g., when in flight), a radio, a laser altimeter, etc. In some examples, the receiver 102 determines a bearing to the beacon 110 based on the heading information.

[0037] Figure 2 is an example method 200 that can be implemented in examples disclosed herein. However, any other example approach and / or landing method can be alternatively implemented. In this example, the vehicle 101 is shown approaching the beacon 110 at different phases. As Figure 2 As seen in the illustrated example of, the initial path 202 is shown in conjunction with an intermediate path 204 and a final approach path 206, which in this example is defined by a landing window 208 at approximately 30 feet (ft) above the ground. In this example, the intermediate path 204 is defined by an intermediate holding area 210. Further, a beacon frame of reference 212 of the respective beacon 110 is depicted as having a north, east, and vertical component.

[0038] Figure 3 is a schematic overview of an example beacon circuit 300 according to the teachings of the present disclosure. The example beacon circuit 300 can be implemented by the beacon 110 of Figure 11 and / or transmitter 112. The example beacon circuit 300 includes an oscillator (e.g., a carrier signal oscillator) 302, a chip clock 304, a PRN code generator 306, a modulator 308 (implemented as a bi-phase shift keying (BPSK) modulator in this example), an amplifier 310 (e.g., a power amplifier), a filter 312, and an antenna 314. In other examples, the modulator 308 can be implemented as a quadrature phase shift keying (QPSK) modulator, an eight-phase shift keying (8PSK) modulator, or M-ary modulation, etc.

[0039] To guide the vehicle 101 via a carrier transmission signal, an oscillator 302 corresponding to the carrier signal drives a chipping clock 304. In turn, the example chipping clock 304 provides a signal to clock and / or time a PRN code generator 306. In this example, the input and / or signal from the chipping clock 304 to the PRN code generator 306 specifies which code in a series of codes the PRN code generator 306 is to generate. Figure 3 In the example shown, a PRN code generator 306 provides a PRN code to a modulator 308, and the modulator 308 modulates the PRN code onto a signal before the signal is filtered at a filter 312 and transmitted via an antenna 314. Additionally, an oscillator 302 provides a carrier input to the modulator 308.

[0040] In the example shown, the example oscillator 302 operates at a primary carrier frequency. In some examples, the carrier signal can be derived from another clock operating at a different frequency via frequency synthesis. Furthermore, the carrier signal is then divided by a number (e.g., an integer) to obtain a chip clock that is phase-coherent with the carrier signal. Therefore, the examples disclosed herein do not rely heavily on precise timing, thereby reducing the need for clocks and / or clock circuitry / hardware, which can be relatively costly. According to some examples disclosed herein, the signal only needs to be stable enough to be tracked by a receiver (e.g., an airborne receiver), and the examples disclosed herein do not require synchronization with GPS or any external system, nor do they require system-level time measurements. According to the examples disclosed herein, information from the beacon is at the source of its transmission, unlike known implementations that utilize tracking PRN codes to develop pseudoranges between a receiver and transmitter. In contrast, the examples disclosed herein do not utilize pseudorange measurements. In this example, the PRN code generator 306 is clocked by the chip clock 304. The resulting PRN sequence is a pseudorandom bit string used to modulate the carrier. The resulting modulated signal is a wide bandwidth signal in which the carrier has been spread by the chip code. The modulated signal is amplified, filtered, and sent to the antenna for broadcast. The filtering ensures that only the main lobe of the spread spectrum signal is transmitted, thus preventing unwanted emissions outside the frequency band of interest.

[0041] The examples disclosed herein can broadcast a single direct sequence spread spectrum (DSSS) signal via an antenna having an almost omnidirectional (or hemispherical) circularly polarized radiation pattern. In some examples, the DSSS signal for each beacon within radio range is assigned a different coding sequence so that CDMA is used to ensure that multiple beacons at or near a particular vertical takeoff and landing airport can operate without interfering with each other while utilizing the same frequency band. For example, the beacon signal can be a DSSS signal with a relatively high chip rate (e.g., 50.9 Mega Chips per second). The DSSS signal grouping can be carefully selected for favorable autocorrelation characteristics and relatively favorable correlation characteristics when compared to each other code in the series. This ensures that when a receiver receives and acquires a signal from a beacon, it can determine that the desired beacon is actually the beacon being tracked.

[0042] Utilizing CDMA over DSSS can serve multiple purposes within the system. This implementation enables multiple beacons to operate near a vertiport without significant interference. Furthermore, this implementation enables the elimination or rejection of most multipath signals received at the vehicle due to reflection or refraction from objects in the area. With a relatively high chip rate and relatively narrow correlators in the receiver, the correlation process can reject multipath signals with differential path delays greater than a fraction of a chip in the wavelength. The PRN code will also have a long length, so that even very long-delay multipath signals can be eliminated during the decorrelation process. This exemplary signal structure ensures that the receiver can track the desired signal with minimal impairment from multipath. Furthermore, the CDMA arrangement enables beacon signals to share spectrum with other services in the band. For example, the 5030 MHz to 5090 MHz band is planned for use by command and control (CC) links for unmanned or autonomous aerial vehicles. Similarly, the 5090 MHz to 5150 MHz band is allocated for use by the AeroMACS data link system.

[0043] Figure 4 is a schematic overview of an example receiver implementation 400 according to the teachings of the present disclosure. The example receiver implementation 400 may be Figure 1 The example receiver implementation 400 shown includes an antenna array 402 having antennas 404, an amplifier 406 implemented as a low noise amplifier 406, a digitizer 408, and a software defined radio 410.

[0044] To determine the heading and elevation of the vehicle 101, the example software defined radio 410 modulates the signal from Figure 1 and Figure 3101. The example software-defined radio 410 utilizes the PRN code on the signal transmitted by the illustrated beacon 110 to recover the carrier signal. To this end, the signal received at antenna 404 is amplified by amplifier 406, downconverted, and digitized into a data stream 409 comprising I and Q samples of the signal at baseband. In turn, the I and Q samples are provided to a software-defined radio 410, which recovers the carrier signal received at antenna 402 by despreading the signal using a synchronized local replica of the PRN code. The example software-defined radio 410 then utilizes the I and Q samples of data stream 409 to determine the azimuth and elevation of the beacon source relative to the vehicle 101. Additionally or alternatively, the software-defined radio 410 determines the direction of arrival (DoA) of the beacon signal relative to the vehicle 101.

[0045] According to examples disclosed herein, the software-defined radio 410 of the receiver 102 utilizes code tracking and carrier phase tracking loops. Thus, code tracking can be performed using a delay-locked loop (DLL), while carrier tracking can utilize a Costas phase-locked loop (or equivalent). In some examples, a separate delay-locked loop is not required for each antenna element. Figure 4 The example of illustrates a specific example of code tracking and carrier recovery that can be implemented in the examples disclosed herein. In this example, the software-defined radio 410 of the illustrated example utilizes a stream of digitized I and Q samples from a digitized stream. In turn, the I and Q sample streams from all four antennas 404 are provided to a processor and / or processor circuitry that associates the I and Q samples with a locally generated version of the PRN code. When the local copies are synchronized with the received code, the carrier in each of the four channels is recovered. This is accomplished via the software-defined radio 410, allowing block processing techniques to be used to initially acquire the long code sequence and synchronize the delay-locked loop with the input signal. The phase of the recovered carrier can be used to determine the direction of arrival of the signal (e.g., taking into account knowledge of the antenna array geometry). In this way, the receiver 102 determines the azimuth and elevation of the beacon signal relative to the antenna array 402. This can be equivalent to measuring a unit vector from the phase center of the onboard array pointing to the beacon 100 on the ground in the aircraft body reference frame.

[0046] Although four antennas 404 are included in antenna array 402, any other suitable number of antennas (e.g., three, five, six, seven, eight, nine, ten, twenty, fifty, etc.) may be implemented instead. In some examples, the software-defined radio may utilize independently measured altitudes above beacon 110 and the pitch / roll / heading of vehicle 101. According to some examples disclosed herein, software-defined radio 410 may determine guidance instructions / commands and / or the orientation of vehicle 101 in the beacon's reference frame.

[0047] Figure 5 is a schematic overview of an example receiver circuit 500 according to the teachings of the present disclosure. The example receiver circuit 500 may be Figure 1 The receiver 102 and / or Figure 4 The software defined radio 410 is shown as being implemented in the Figure 5 In the example shown in FIG, an example receiver circuit 500 is used to receive a digitized signal stream corresponding to each antenna element. The example receiver circuit 500 includes a PRN code generator 502, an integrator 504, a discriminator 506, a summing device 508, a divider 510, a filter 512, a code numerically controlled oscillator (NCO) 514, and a modulator 516, which in this example is implemented as a BPSK modulator.

[0048] To recover and / or despread the carrier signal 518 from the data streams 501, an example PRN code generator 502 provides a PRN code to each of the data streams 501, and an integrator (e.g., an integrating and cleaning filter) 504 and a discriminator 506 act as a delay-locked loop (DLL) to track and synchronize with the incoming PRN-coded signal. The combination of correlations between the early and late copies of the PRN code enables determination of the error in synchronization between the local PRN hint copy and each incoming PRN data stream 501. According to some examples disclosed herein, a summing device 508 and a divider 510 are implemented to determine an average error in synchronization of the data streams 501. The average error is, in turn, provided to a numerically controlled oscillator (NCO), which clocks the PRN code generator 502, which generates the PRN code generator 502, which is provided to a bi-phase modulator 516 to despread the signal for recovering the carrier 518. In this arrangement, four DLLs are used, one for each input signal. The error signals generated by the four DLLs are averaged to form an error signal that drives the NCO, which clocks the individual PRN generators that drive each DLL.

[0049] The examples disclosed herein advantageously utilize a signal PRN code generator such that each of the four digitized streams 501 {x1, x2, x3, x4} of I and Q samples is provided to a delay locked loop (defined by an integrator 504 and a discriminator 506) where the signal is multiplied with a locally generated copy of the code that has its early and late offsets by some fraction of a chip. For example, the early and late copies of the PRN code may be delayed by one tenth of a chip interval relative to the prompt code. According to the examples disclosed herein, the signal is correlated with an integrate and clean filter and the result of the correlator is provided to the discriminator 506. According to the examples disclosed herein, the outputs {d1, d2, d3, d4} of the discriminator 506 for the four different branches are summed and then divided by four so that the result is an average error signal The average error signal The NCO 514 is used to drive the code generator 502. In turn, the four input signals {x1, x2, x3, x4} are then despread using the hinted version of the code to recover the carrier set 518, {c1, c2, c3, c4}. The recovered carrier set 518 then forms the basis for the direction of arrival (DoA) determination. Many suitable DoA techniques are available and well known in the literature, such as MUSIC (Multiple Signal Classification), beam scanning, minimum squared error distortionless response, 2-D MUSIC, root-MUSIC, etc. Since the measurement is made using the average of the four delay-locked loop correlations, the noise on the four channels is averaged while increasing the desired signal power.

[0050] Figure 6 is a schematic overview of another example receiver circuit 600 according to the teachings of the present disclosure. The example receiver circuit 600 may be Figure 1 The receiver 102 and / or Figure 4 The software defined radio 410 is shown as being implemented with Figure 5 Similar to the example receiver circuit 500 of FIG. , example receiver circuit 600 receives a digitized signal stream 601 corresponding to each antenna element. However, in contrast to example receiver circuit 500, receiver circuit 600 determines the error and / or delay from one of signal streams 601. Example receiver circuit 600 includes a PRN code generator 602, an integrator 604, a discriminator 606, a filter 608, a code NCO 610, and a modulator 612, which in this example is implemented as a BPSK modulator. In this example, a single DLL is applied to one of the four input signals to synchronize the locally generated PRN code with the PRN encoding of the input signal. The synchronized PRN code is then used to despread the four input signals.

[0051] exist Figure 6In the example shown of FIG. 6, the PRN code generator 602 provides the PRN code to multiple branches 614 of one of the signal streams 601. Thus, the discriminator feeds the error to the filter 608 and the NCO 610. In turn, the PRN code generator 602 drives the modulator 612 to recover the carrier signal 616 from the signal stream 601 described above.

[0052] Figure 7 An example calculation in a beacon reference frame that can be implemented in examples disclosed herein is shown. In this example, the reference frame 700 is shown with an origin 701 at the beacon 703 relative to the vehicle 101. Further, a vector 702 is shown between the beacon origin 701 and the vehicle 101. Further, a vector 704 represents the height difference between the beacon origin 701 and the vehicle 101, while a vector 706 corresponds to the approximate heading / direction between the beacon origin 701 and the vehicle 101.

[0053] In this example, the vehicle receiver (e.g., the receiver 102 of FIG. 1) measures the DoA based on the DoA measurements Figure 1 That is, the unit vector from the vehicle antenna to the beacon. In this example, the unit vector is defined in the vehicle reference frame. According to some examples disclosed herein, the pitch, roll, and heading of the platform are provided by an external system and used to compute the transformation matrix T AC→BRF from the vehicle reference frame to a local level North East Down reference frame.

[0054] According to examples disclosed herein, the receiver computes This is the measured vector from the airborne antenna to the ground beacon (transformed to the beacon’s reference frame). As a result, the unit vector from the beacon to the vehicle in the beacon reference frame is obtained. Note example equation 1:

[0055] Compute:

[0056] And from example equation 2, note the following:

[0057] Compute:

[0058] Example equation 3 can be used to compute the height difference:

[0059] Ah = R sin(0), compute:

[0060] Example equation 4 can be used to compute the distance:

[0061] D = R cos(0), compute:​

[0062] Then, example Equation 5 can be obtained as follows:

[0063]

[0064] Therefore, y and z can be calculated as shown in example equations 6 and 7:

[0065]

[0066] z=-Δh (7)

[0067] The example calculations shown are examples only, and any other suitable calculations and / or methods may be implemented instead. Likewise, without loss of generality, the calculations discussed herein may be performed with the receiver as described or in some external system that has been provided with the unit vectors performed by the receiver. Observation.

[0068] Figure 8 1 shows example signals that may be implemented in the examples disclosed herein. Figure 8 In the illustrated example of FIG, example graph 800 depicts receiver noise floor 802 relative to other / external signals 804, and a spread spectrum beacon signal 806. Similarly, example graph 810 depicts a spread spectrum signal 812 of other / external signal 804 along with a carrier signal 814 recovered from a beacon constructed according to the teachings of the present disclosure.

[0069] According to some examples disclosed herein, the utilization of direct sequence spread spectrum (DSSS) or code division multiple access (CDMA) signals enables the examples disclosed herein to share frequencies in a frequency band. To illustrate this, example signal structures are described herein. However, any other suitable signal structure may be implemented instead. The examples disclosed herein may transmit a signal having the following characteristics: a carrier BPSK modulated with a PRN code, a carrier frequency of approximately 5090 MHz, a chip clock obtained by dividing the carrier by 100 (e.g., 50.9 megachips per second). Therefore, reflections with a differential path delay greater than 5.89 meters (m) will be rejected. In some examples, for example, a long code repetition interval, such as 2 16 chips (i.e., 65,536 chips). This means that all multipaths with a differential path delay less than 386.26 kilometers (km) will be rejected. No data is modulated onto the carrier, so a very narrow post correlation bandwidth can be used. Assuming that 10 Hz is sufficient for the carrier tracking loop bandwidth, the processing gain can be equal to 10*log10((50.0*10 6 / 10))=67dB. Therefore, a relatively low power (10dBm or 0.01 watt) is used for the beacon. As a result, Figure 8 As shown, this wideband spread spectrum signal can enable sharing of the frequency band with other users. In some examples, a low power beacon (0.01 watt EIRP) is spread over + / - 50.9 MHz and is well below the noise floor of other services and will not significantly degrade the signal-to-noise ratio (S / N) of these services. Spread spectrum processing rejects the signals of other services (assuming they are interfering signals) by spreading them. In some examples, after acquiring the code and despreading the desired signal, the undesired signals from other services are spread and will increase the noise floor of the carrier to the ratio of thermal noise plus interference, C / (No+I). However, according to the examples disclosed herein, given the relatively high processing gain, there should still be sufficient signal-to-noise ratio to support signal tracking and recovery of the carrier, and subsequently determine the direction of arrival of the signal.

[0070] Figure 9 is a schematic overview of an alternative example beacon circuit 900 according to the teachings of the present disclosure. The example beacon circuit 900 may be Figure 1 The beacon 110 and / or transmitter 112 are shown as being implemented in FIG. Figure 9 In the example shown, the beacon circuit 900 includes a code chip clock 902, a PRN code generator 904, an oscillator or carrier clock 906, a modulator 908 implemented as a BPSK modulator in this example, an amplifier (e.g., a power amplifier) ​​910, a beamforming network 912, and an antenna array 914 having an antenna 916.

[0071] exist Figure 9 In the illustrated example, the beacon circuit 900 generates a beam 920 having four phase-locked CDMA signals that utilize orthogonal (e.g., fully orthogonal) codes with a relatively high chip rate. All of the signal design considerations described above still apply. The example beacon circuit 900 has an antenna array that is implemented to radiate in four quadrants. The four codes are broadcast along the four quadrants. Thus, a corresponding receiver (e.g., an airborne receiver) can demodulate the four signals and can determine the relative bearing of the vehicle 101 by comparing the received power on each of the four codes corresponding to the signals. The example four-quadrant antenna is aligned with the cardinal directions so that the vehicle 101 can determine the approximate direction of the beacon based on the amplitude of the signals, which can be tracked in a generally difficulty-free manner.

[0072] According to some examples disclosed herein, clock 906 and chip clock 902 are derived from a common oscillator so that the resulting signals are relatively coherent. Specifically, chip clock 902 simultaneously clocks different code generators, each of which is programmed to generate a different pseudo-random bit stream from, for example, an orthogonal series. Each bit stream is used to individually modulate a carrier. In turn, the individual modulated signals are amplified and fed to different inputs of beamforming network 912. Example beamforming network 912 can generate appropriate phase and amplitude profiles to excite an NxN array of elements to generate four beams 920. For example, beams 920 are arranged to be substantially orthogonal and generate four quadrants, each with a code, and each code aligned with a cardinal direction. Figure 10 One such example arrangement is shown in .

[0073] Although Figure 9 Examples include four signals and four quadrants, but any other suitable number of signals and beams, from 2 to N, may be implemented instead. Furthermore, the N resulting beams need not be aligned in any particular manner with respect to the cardinal directions. The N beams will define N radial directions, where typically equal power is received for two different codes in adjacent beams. If the order of the beams and associated codes, as well as the overall relationship of the beams to the beacon reference frame, is known, a receiver can determine its relative angle to that beacon.

[0074] In another example, the beacon may be used with a receiver having a single antenna, and DoA processing and / or calculations would not be performed at the vehicle. In such an example, the receiver may generate guidance based on differences in received signal power, such as Figure 10 As described above. In such an example, a capture radial and following it to the zenith point can be employed. Such an example does not produce a rough x, y, and z position relative to the beacon reference frame. This operation is closer to operating an instrument landing system (ILS), in which a vehicle can fly a specific procedure and be provided with guidance to bring it to a position generally directly above the landing zone. In turn, the vertical descent of the vehicle can then be completed based on calibrated barometry, radio or laser altimetry.

[0075] Figure 10 Figure 2 shows example results for a quadrant antenna that can be implemented in the examples disclosed herein. Figure 10In the illustrated diagram of FIG, an origin 1002 corresponding to a beacon (e.g., beacon circuit 900) is shown relative to a radiation beam 1004 along different headings relative to a vehicle 101, which is shown at four different orientations relative to the beacon. In this example, different carrier signals and / or power readings are indicated for different orientations of the vehicle 101. Thus, a receiver of the vehicle 101 can determine the DoA and / or heading / elevation angle toward the beacon. In some examples, the angle relative to the beacon can be determined by comparing the amplitude of the received signal.

[0076] In this example, four beams are generated using a 4x4 array of circular patch elements. In addition, amplitude tapering is used to suppress side lobes, allowing a single beam to dominate in any given quadrant. Figure 10 As shown, the x-axis of the array reference system is aligned with the cardinal direction East. Figure 10 Further depicted are examples of the aircraft at different orientations toward the beacon, and the relative signal levels that the vehicle 101 can receive at these positions are shown. Figure 10 An example shown in is vehicle 101 at 45 degrees from north. An example convention employed is that the beacon reference system has an x-axis aligned with east, a y-axis aligned with north, and a z-axis aligned with the vertical (pointing upward to complete a right-handed coordinate system). Thus, in this example, vehicle 101 would be at an azimuth of 135 degrees in the defined beacon coordinate system. For example, when the received signal powers for signal 2 and signal 3 are equal, a radial extending in a northwest direction is formed. Furthermore, when the received powers on these two signals are equal, the receiver detects that it is on a radial, and the fact that it is receiving signal 2 and signal 3 indicates that the receiver is north and west of the beacon, such that an unambiguous direction to the beacon can be obtained.

[0077] According to some examples disclosed herein, the accuracy of the direction estimate may depend on the direction. For example, a vehicle 101 shown west of the beacon (e.g., at an azimuth of 180 degrees in the beacon's reference frame) will only receive signal 3, which has a significant amount of power. For example, within an angular range from approximately 165 degrees to approximately 195 degrees, the relative signal power of signals 2 and 4 is 20 dB to 30 dB or more lower than that of signal 1. Therefore, within this range, vehicle 101 can only determine that it is west of the beacon. To obtain a more accurate indication of relative direction, vehicle 101 would need to maneuver to an azimuth where it can receive both frequencies, leveraging knowledge of the order of the signals. After acquiring the first signal, vehicle 101 can fly in a pattern that will result in the acquisition of one of the radials of equal signal strength, similar to how a localizer course is acquired using an ILS. For example, a four-quadrant beacon can provide four potential localizer-type references toward the beacon. Similarly, an eight-beam system can generate eight radials toward the beacon, and so on. However, additional beams may require the onboard equipment to search an increasing number of codes for initial acquisition. However, once a code is acquired, only two codes need to be tracked at a time to obtain the azimuth. Vertical guidance from a multi-sector beacon may be relatively weak. However, an exception is when vehicle 101 is positioned above the beacon. As a result, the signal strength of each code can be relatively equal.

[0078] Figure 11 Example directional patterns that can be implemented in the examples disclosed herein are shown. Figure 11 In the illustrated view of FIG, a graph 1100 is shown having four beams 1102, 1104, 1106, 1108 transmitted from a beacon with corresponding beam directivities. In this example, adjacent beams 1102, 1104, 1106, 1108 have approximately equal amplitudes in a 45-degree radial direction, and each of beams 1102, 1104, 1106, 1108 has approximately the same amplitude at zenith. In some examples, a 4x4 array of circular patch elements is utilized.

[0079] exist Figure 11In the example of FIG, a three-dimensional view of the radiation pattern of the aforementioned four-quadrant array is depicted. For example, the four beams 1102, 1104, 1106, and 1108 are oriented at azimuth angles of 0, 90, 180, and 270 degrees, with each beam pointing at an elevation angle of 45 degrees. It can be seen that when vehicle 101 is on the corresponding radial direction, adjacent codes / beams 1102, 1104, 1106, and 1108 are received with relatively equal amplitudes. It can also be seen that the amplitudes of all beams 1102, 1104, 1106, and 1108 converge to relatively similar values. Furthermore, when vehicle 101 approaches zenith, similar levels are measured for all four signals 1102, 1104, 1106, and 1108. Therefore, the accuracy of vertical estimation improves as vehicle 101 approaches zenith. In some cases, only a maximum of two codes / beams are received at lower elevation angles, and thus, no vertical information is available. Therefore, another strategy for using a beacon constructed according to the teachings of the present disclosure is to acquire and / or identify a radial, and then follow the radial and begin searching for the other two codes. Once a code is received, the receiver can generate guidance so that the vehicle 101 is maneuvered to an orientation where all four signals are relatively equal. In some examples, if more than four sectors / beams are utilized, a subset of the beams from opposite hemispheres of the pattern can be utilized so that the receiver only needs to track up to four codes to equalize its received pattern.

[0080] Figure 12 is a schematic overview of an alternative example receiver circuit 1200 according to the teachings of the present disclosure. The example receiver circuit 1200 may be Figure 1 The receiver 102 and / or Figure 4 The software defined radio 410 is shown as being implemented in the Figure 12 In the example shown, the example receiver circuit 1200 is to receive Figure 1 A digitized signal stream 1201 corresponding to each antenna element of the vehicle 101 is shown. The example receiver circuit 1200 includes a PRN code generator 1202, a discriminator 1204, a summing device 1206, a divider 1208, weights 1209, a summing device 1210, a filter 1212, a code NCO 1214, a modulator 1216 (implemented as a BPSK modulator in this example), and a power estimator 1218.

[0081] To determine a power estimate for each code of the carrier, the recovered carrier from modulator 1216 is provided to power estimator 1218. In this example, the corresponding receiver tracks two to four different codes and estimates the relative received power between these two to four codes. Because all codes are synchronized at the beacon, only a single code clock is required. In this example, individual signals on individual elements are not tracked individually. Figure 5Similar to the example of , the delay locked loops (DLLs) of all four antennas are processed individually and the output of the discriminator 1204 is averaged over the four channels. Figure 5 A similar process is applied to each code and four channels in the example. To do this, the discriminator weights for the two channels are weighted according to the estimated C / No for each code and summed together so that they drive a single code NCO 1214. The example PRN generator 1202 is driven by the same clock signal from the code NCO 1214. In this example, because all codes are synchronized, only one code needs to be acquired, and the proper synchronization of the other codes is therefore immediately known. The power of all antennas contributes to the code delay locked loop (DLL) tracking. In turn, the hint PRN code from each PRN generator 1202 is used to despread the signal and recover the carrier 1220. This aspect of the process is the same as for DoA estimation. However, for multi-sectional beacon tracking, the recovered, despread, and / or recovered carrier 1220 is provided to a power estimation algorithm and / or power estimator 1218 to generate a power estimate for each coded signal. However, many well-known techniques can be used to estimate the power in the signal. In the example shown, the power estimates corresponding to the codes are compared and used to obtain information about the orientation of the vehicle 101 relative to the beacon.

[0082] The examples disclosed herein can achieve relatively simple acquisition, where only a single code is searched. This can be accomplished using various well-known techniques, such as, but not limited to, sequential delays, Doppler bin searches using block processing techniques, such as computing a complex ambiguity function (CAF), and the like. Once the acquisition algorithm finds the appropriate code phase and Doppler frequency, the code and carrier tracking loops can be initialized and engaged to accurately track the code and carrier for the incoming signal. All code phases of the multiple PRN signals from the ground are synchronized. Therefore, knowing the correct phase of one signal enables immediate demodulation / despreading of the other codes.

[0083] In this example, the receiver implementation is more complex, but most of the processing is similar to Figure 5 The example is similar in scale but replicated N times, where N is the maximum number of codes to be tracked.

[0084] According to the examples disclosed herein, the calculations may be performed as follows: 1.) The receiver measures / estimates based on the direction of arrival measurement results This is the unit vector from the vehicle's antenna to the beacon. Since the antenna is mounted in a fixed and known orientation relative to the aircraft's reference frame, the vector can be easily converted to the aircraft reference frame; 2.) The receiver measures / estimates the relative signal strength in the codes received from the multi-sector beacons That is, the unit vector in the beacon reference frame (BRF) pointing from the beacon to the vehicle; 3.) The pitch, roll, and heading of the vehicle are provided by an external system and used to calculate the transformation matrix T from the vehicle reference frame to the beacon reference frame AC→BRF ; 4.) Receiver calculation: This is the measurement vector from the vehicle's antenna to the ground-based beacon (converted to the beacon reference frame). Therefore, the unit vector from the beacon to the aircraft in the beacon reference frame is determined; 5.) The receiver will calculate the expected relative accuracy of the measurement results based on the expected relative accuracy of the measurement results. Calculated as and For example, due to the low elevation angle, The vertical component of may have relatively low accuracy or be absent, so The vertical component of The vertical component of After the best estimate of , the step of calculating the orientation in the beacon reference frame can be combined with the step corresponding to the above Figure 7 The steps described in equations 1 to 7 are the same.

[0085] Figure 13 Example multipath control that can be implemented in the examples disclosed herein is shown. Figure 13 In the example shown, vehicle 1301 is receiving a signal from antenna 1302 of a beacon. Specifically, vehicle 1301 includes a receiving antenna 1304 for receiving at least one signal from antenna 1302. In this example, reflection sources 1303 and 1306 are also shown. Furthermore, direct path 1310 and multipath 1312 are shown. In this example, region 1314 depicts the Fresnel zone, which defines the volume within which reflections will have a delay less than a specified differential path. Therefore, reflection sources within Fresnel zone 1314 will result in multipath signals that are not eliminated by the despreading of the DSSS signal. Multipath signals from objects outside Fresnel zone 1314 will be eliminated by the despreading of the DSSS signal. The direction of arrival measurement made at aircraft 1301 depends on the relative phases of the signals received at the elements in receive antenna array 1304. Multipath signals will mix with the direct path signal and cause errors in determining the direction of arrival of the signal. Therefore, multipath should be eliminated to the greatest extent possible to ensure an accurate determination of the signal's DoA. The Fresnel zone must be protected in the following sense: no multipath sources should be present within the Fresnel zone throughout the approach operation.

[0086] Multipath from the structure of vehicle 1301 can be a problem but can be mitigated through antenna placement and directionality.

[0087] Figures 14A-14C Example antenna configurations that can be implemented in the examples disclosed herein are shown. Figure 14A In this example, a vehicle (e.g., an aircraft, an unmanned or manned aerial vehicle, etc.) 1400 includes an antenna array 1401 mounted on a nose 1402 of the vehicle 1400. The antenna array 1401 includes a corresponding coordinate system having coordinate axes 1404, 1406. The array is positioned so that all structures of the aircraft are behind the array (e.g., below the horizon of the ground plane in the antenna reference system).

[0088] Figure 14B A detailed view of a hypothetical representative antenna array 1401 is depicted, having four elements, namely three spirals 1410, spaced in a rectangular pattern on a ground plane or body 1412. According to some examples disclosed herein, assuming a wavelength of approximately 5.9 centimeters (cm), and taking into account the effects of the ground plane, the dimensions (e.g., width, height, etc.) of the array 1401 with the ground plane can be between approximately 10 centimeters (cm) and 15 cm. Such an array can be housed within a ray dome to provide improved aerodynamic performance.

[0089] Figure 14C An example graph 1420 is depicted, which illustrates example directivity for an example antenna element (i.e., a spiral or helix) used in array 1401. In this example, profile 1422 corresponds to a 90-degree azimuth cut at all elevation angles in the antenna reference frame. Multipath from the fuselage will enter from below in the xy plane and should be at least 20 dB lower than signals from within the field of view defined by 45 to 135 degrees elevation. Therefore, any fuselage multipath signal will be at least 20 dB lower than the direct signal received from the beacon within the field of view.

[0090] Figure 15 is a flow chart representing an example method 1500 of operating a beacon, such as beacon 110, according to the teachings of the present disclosure. Example method 1500 is implemented to transmit at least one signal from the beacon to guide vehicle 101.

[0091] At block 1501, a carrier signal is divided to generate a clock signal. In some examples, the carrier frequency is divided by 100 to generate a PRN code or a chip clock (or chip rate clock).

[0092] At block 1502, a clock signal is provided to a PRN code generator (e.g., PRN code generator 306, PRN code generator 904). In this example, the clock signal is provided to the PRN code generator from a chip clock (e.g., chip clock 304, chip clock 902).

[0093] At block 1504 , a carrier of the signal is modulated with the aforementioned PRN code via a modulator (eg, modulator 308 , modulator 908 ).

[0094] At block 1506, the signal is amplified and filtered.

[0095] At block 1508, the signal is transmitted via the antenna and / or antenna array, and the process ends. In some examples, multiple signals are transmitted (e.g., via beamforming).

[0096] Figure 16 It is used to recover the carrier signal to guide the vehicle (such as vehicle 101) Figure 1 Block diagram of an example receiver analysis system 1600 for receiver 102. Figure 16 The example receiver analysis system 1600 may be instantiated (e.g., have an instance of, be realized for any length of time, embody, implement, etc.) by programmable circuitry (such as a central processing unit (CPU)) executing first instructions. Additionally or alternatively, Figure 16 The example receiver analysis system 1600 may be instantiated (e.g., have an instance of, be realized for any length of time, embodied, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) (which is constructed and / or configured to perform operations corresponding to first instructions in response to execution of second instructions). It should be understood that, therefore, Figure 16 Some or all of the circuitry may be instantiated at the same or different times. For example, Figure 16 Some or all of the circuitry may be instantiated in one or more threads that execute concurrently on hardware and / or serially on hardware. Figure 16 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0097] Example receiver analysis system 1600 includes example signal digitizer circuitry 1602 , example signal analyzer circuitry 1604 , example carrier recovery circuitry 1605 , example range / orientation calculator circuitry 1606 , and example navigation control circuitry 1608 .

[0098] exist Figure 16In the illustrated example, the example signal digitizer circuitry 1602 is implemented to digitize at least one signal received from a beacon (e.g., beacon 110) into a digitized signal and / or digital data stream corresponding to a corresponding antenna element. In the illustrated example, the example signal digitizer circuitry 1602 digitizes the signal from the beacon to define and / or generate I and Q samples thereof. According to the examples disclosed herein, the signal is amplified and down-converted. In some examples, the signal digitizer circuitry 1602 is instantiated by a programmable circuitry that executes signal digitizer instructions and / or is configured to perform operations such as Figure 17 The operations are those represented by the flowcharts.

[0099] The example signal analyzer circuitry 1604 is implemented to perform a delay locked loop such that a signal is multiplied with a locally generated code replica whose early and late offsets are defined fractions of a chip. The example signal analyzer circuitry 1604 may utilize at least one discriminator in conjunction with an integrator (e.g., an integrate and clean block). In this example, at least one error of the signal is utilized to recover the carrier signal. In some such examples, the errors are averaged to recover the carrier signal. Additionally or alternatively, the signal and / or the error are weighted. In some examples, the signal analyzer circuitry 1604 is instantiated by a programmable circuitry that executes signal analyzer instructions and / or is configured to perform operations such as Figure 17 The operations are those represented by the flowcharts.

[0100] For example, the example carrier recovery circuitry 1605 recovers the carrier from the signal via at least one modulator, such as a BPSK modulator. Figure 16 In the example shown, each signal for each antenna element is modulated with at least one modulator to recover the carrier. In some examples, the recovered carrier is used to determine the power of the signal. In some examples, carrier recovery circuitry 1605 is instantiated by programmable circuitry that executes carrier recovery instructions and / or is configured to perform operations such as Figure 17 The operations are those represented by the flowcharts.

[0101] The illustrated example distance / orientation calculator circuitry 1606 determines the vehicle's direction of arrival (relative to the beacon) based on the recovered carrier wave. Additionally or alternatively, the recovered carrier wave is used to determine the vehicle's elevation angle and heading. In some examples, the distance / orientation calculator circuitry 1606 determines the vehicle's orientation in the beacon's reference frame. In some examples, the distance / orientation calculator circuitry 1606 is instantiated by programmable circuitry that executes distance / orientation calculator instructions and / or is configured to perform operations such as Figure 17 The operations are those represented by the flowcharts.

[0102] The navigation control circuitry 1608 of the illustrated example is implemented to control and / or guide the vehicle based on the arrival direction. In some examples, the vehicle is guided toward a beacon based on the arrival direction and then caused to descend (e.g., descend vertically) toward the beacon. In some examples, the navigation control circuitry 1608 is instantiated by programmable circuitry that executes navigation control instructions and / or is configured to perform operations such as Figure 17 The operations are those represented by the flowcharts.

[0103] Although Figure 16 The implementation is shown in Figure 16 The example receiver analysis system 1600 is provided in an exemplary manner, but Figure 16 One or more of the elements, processes, and / or devices shown in can be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Furthermore, example signal digitizer circuitry 1602, example signal analyzer circuitry 1604, example carrier recovery circuitry 1605, example distance / orientation calculator circuitry 1606, example navigation control circuitry 1608, and / or more generally, Figure 16 The example receiver analysis system 1600 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, the example signal digitizer circuitry 1602, the example signal analyzer circuitry 1604, the example carrier recovery circuitry 1605, the example distance / orientation calculator circuitry 1606, the example navigation control circuitry 1608, and / or more generally, any of the example receiver analysis system 1600 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPUs), digital signal processor(s) (DSPs), ASIC(s), programmable logic device(s) (PLDs), and / or field programmable logic device(s) (FPLDs) such as FPGAs. Further, Figure 16 The example receiver analysis system 1600 may include Figure 16 One or more elements, processes and / or devices other than those shown in, or in place of Figure 16 One or more of the elements, processes and / or devices shown in the drawings, and / or may include more than one of any or all of the elements, processes and devices shown.

[0104] Figure 171 and 2. There are shown flow charts representing example machine-readable instructions and / or representing example operations, which may be executed by programmable circuitry to implement and / or instantiate Figure 16 The example receiver analysis system 1600, example operations may be performed by programmable circuitry to implement and / or instantiate Figure 16 The example receiver analysis system 1600. The machine readable instructions may be for use by programmable circuitry (e.g., in conjunction with Figure 18 The programmable circuit system 1812 shown in the example processor platform 1800 discussed herein may be one or more executable programs or portions of one or more executable programs, and / or may be one or more functions or portions of functions, which will be described below in conjunction with Figure 19 and / or Figure 20 In some examples, machine-readable instructions cause operations, tasks, and the like to be performed and / or executed in an automated manner in the real world. As used herein, "automated" means without human involvement.

[0105] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray Discs, Compact Discs (CDs), Digital Versatile Discs (DVDs), etc.), Redundant Array of Independent Disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may program and / or be executed by programmable circuitry located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuitry. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communications between the server and the endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, while reference is made to Figure 17The flowchart shown in describes an example procedure, but many other methods of implementing the example receiver analysis system 1600 may alternatively be used. For example, the order of execution of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are constructed to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed across one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (such as multi-core CPUs, XPUs, etc.) at different network locations and / or locally. For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0106] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, an encapsulated format, and the like. The machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as part(s) of instructions, code, code representation, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations on a network or a collection of networks (e.g., in a cloud, an edge device, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, and the like so that they are directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are separately compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that together may form a program such as the program described herein.

[0107] In another example, the machine-readable instructions may be stored in a state in which they can be read by a programmable circuit system, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or corresponding program may need to be configured (e.g., to store settings, input data, record network addresses, etc.) before the machine-readable instructions and / or corresponding program can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, and / or machine-readable media may include instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or program(s).

[0108] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0109] As mentioned above, Figure 17Example operations of the can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are defined as including any type of computer- readable storage device and / or storage disk, and exclude propagating signals and transitory media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, cache memory, any type of RAM, registers, and / or any other storage devices or storage disks that hold information in any temporal manner (e.g., for extended periods of time, permanently, for brief instances of time, for temporary buffering, and / or for caching of the information). As used herein, the terms “non-transitory computer-readable storage device” and “non-transitory machine-readable storage device” are defined as including any physical (mechanical, magnetic, and / or electrical) hardware that holds information in a temporal manner, but exclude propagating signals and transitory media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term “device” refers to a physical structure such as a mechanical and / or electrical apparatus, hardware, and / or circuitry that can or can not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to perform computer-readable instructions, machine-readable instructions, etc.

[0110] Figure 17 The example operations of the can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are defined as including any type of computer- readable storage device and / or storage disk, and exclude propagating signals and transitory media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, cache memory, any type of RAM, registers, and / or any other storage devices or storage disks that hold information in any temporal manner (e.g., for extended periods of time, permanently, for brief instances of time, for temporary buffering, and / or for caching of the information). As used herein, the terms “non-transitory computer-readable storage device” and “non-transitory machine-readable storage device” are defined as including any physical (mechanical, magnetic, and / or electrical) hardware that holds information in a temporal manner, but exclude propagating signals and transitory media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term “device” refers to a physical structure such as a mechanical and / or electrical apparatus, hardware, and / or circuitry that can or can not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to perform computer-readable instructions, machine-readable instructions, etc. Figure 17 The example machine-readable instructions and / or example operations 1700 of the begin at block 1702, where the example signal analyzer 1604 receives signals received and / or acquired at elements of an antenna array of a vehicle, the signals transmitted from beacons (e.g., beacons 110) in a landing zone.

[0111] At block 1704, the example signal digitizer circuitry 1602 and / or the example signal analyzer circuitry 1604 cause the signals to be amplified. In this example, each signal is amplified with a low noise amplifier.

[0112] At block 1706, the example signal digitizer circuitry 1602 downconverts and digitizes the signal. As a result, a digital stream of each signal defining I and Q samples is generated.

[0113] At block 1707, the example signal analyzer circuitry 1604 acquires the signal. According to examples disclosed herein, the signal is associated with a locally generated PRN code.

[0114] At block 1708, the example signal digitizer circuitry 1606 tracks the signal to associate the signal with the locally generated PRN code. In particular, the I and Q samples are associated with the locally generated PRN code, and a delay locked loop (DLL) is used to synchronize the incoming PRN encoded signal with the locally generated copy of the PRN code in the on-board receiver.

[0115] At block 1710, the example carrier recovery circuitry 1605 causes the signal to be demodulated with a modulator. In particular, the signal is demodulated with the synchronized copy of the code using a delay locked loop.

[0116] At block 1714, the example carrier recovery circuitry 1605 recovers the carrier signal. In some examples, the carrier signal is used to determine a unit vector (e.g., a directional unit vector in the vehicle reference frame) from the vehicle to the beacon.

[0117] At block 1716, the example range / orientation calculator circuitry 1606 determines an azimuth and elevation of the arrival of the beacon signal relative to the vehicle frame. Additionally or alternatively, the range / orientation calculator circuitry 1606 determines a direction of arrival of the beacon signal at the antenna array on the vehicle. In some examples, the range / orientation calculator circuitry 1606 determines a vector (e.g., a unit vector) pointing from the on-board antenna array to the beacon location.

[0118] At block 1718, in some examples, the range / orientation calculator circuitry 1606 determines a bearing and / or relative bearing of the vehicle. In some such examples, the range / orientation calculator circuitry 1606 can determine a bearing of the vehicle in the beacon reference frame.

[0119] At block 1720, in some examples, the navigation control circuitry 1608 guides the vehicle toward the beacon, and the process ends. In some such examples, the navigation control circuitry 1608 can utilize the direction of arrival to guide the vehicle. In one particular example, the vehicle is guided to a position above the beacon and caused to descend at that position.

[0120] Figure 18 is a block diagram of an example programmable circuitry platform 1800 that is structured to execute and / or instantiate Figure 17Example machine-readable instructions and / or example operations to implement Figure 16 The example receiver analysis system 1600 of the programmable circuit system platform 1800 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, an iPad, etc.). TM tablet), personal digital assistant (PDA), internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, head-mounted device (such as augmented reality (AR) headset, virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0121] The example programmable circuitry platform 1800 shown includes a programmable circuitry 1812. The example programmable circuitry 1812 shown is hardware. For example, the programmable circuitry 1812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuitry 1812 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuitry 1812 implements the example signal digitizer circuitry 1602, the example signal analyzer circuitry 1604, the example carrier recovery circuitry 1605, the example distance / orientation calculator circuitry 1606, and the example navigation control circuitry 1608.

[0122] The programmable circuit system 1812 of the illustrated example includes a local memory 1813 (e.g., cache, registers, etc.). The programmable circuit system 1812 of the illustrated example communicates with main memories 1814, 1816, including volatile memory 1814 and non-volatile memory 1816, via a bus 1818. The volatile memory 1814 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1816 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 1814, 1816 of the illustrated example is controlled by a memory controller 1817. In some examples, the memory controller 1817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 1814, 1816.

[0123] The example programmable circuit system platform 1800 also includes an interface circuit system 1820. The interface circuit system 1820 can be implemented by hardware that conforms to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0124] In the example shown, one or more input devices 1822 are connected to the interface circuitry 1820. The input device(s) 1822 allow a user (e.g., a human user, a machine user, etc.) to enter data and / or commands into the programmable circuitry 1812. The input device(s) 1822 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0125] One or more output devices 1824 are also connected to the interface circuit system 1820 of the illustrated example. The output device(s) 1824 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuit system 1820 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system (such as a GPU).

[0126] The interface circuitry 1820 of the illustrated example also includes communication devices (such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces) to facilitate the exchange of data with external machines (e.g., any type of computing device) over a network 1826. Communications can be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0127] The example programmable circuit system platform 1800 shown also includes one or more mass storage disks or devices 1828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0128] Machine readable instructions 1832 (which may beFigure 17 The machine-readable instructions implemented in the computer program product (or the like) may be stored in the mass storage device 1828, in the volatile memory 1814, in the non-volatile memory 1816, and / or on at least one non-transitory computer-readable storage medium that may be removable, such as a CD or DVD.

[0129] Figure 19 yes Figure 18 1812. In this example, Figure 18 The programmable circuit system 1812 is implemented by the microprocessor 1900. For example, the microprocessor 1900 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 1900 executes Figure 17 Some or all of the machine readable instructions of a flowchart to effectively Figure 16 In some such examples, the circuit system is instantiated as logic circuits to perform operations corresponding to these machine-readable instructions. Figure 16 The circuit system is instantiated by the hardware circuits of the microprocessor 1900 in combination with machine-readable instructions. For example, the microprocessor 1900 can be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of example cores 1902 (for example, 1 core), the microprocessor 1900 of this example is a multi-core semiconductor device including N cores. The cores 1902 of the microprocessor 1900 can operate independently, or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to the firmware program, embedded software program, or software program can be executed by one of the cores 1902, or can be executed by multiple cores in the core 1902 at the same or different times. In some examples, the machine code corresponding to the firmware program, embedded software program, or software program is divided into threads and executed in parallel by dual cores or multiple cores in the core 1902. The software program may correspond to a program executed by Figure 17 A flowchart represents a portion or all of machine-readable instructions and / or operations.

[0130] The cores 1902 can communicate via a first example bus 1904. In some examples, the first bus 1904 can be implemented by a communication bus to enable communications associated with (one or more) cores in the cores 1902. For example, the first bus 1904 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1904 can be implemented by any other type of computing or electrical bus. The cores 1902 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit system 1906. The cores 1902 can output data, instructions, and / or signals to one or more external devices via the interface circuit system 1906. While the cores 1902 of this example include example local memory 1920 (e.g., a level 1 (L1) cache that may be divided into an L1 data cache and an L1 instruction cache), the microprocessor 1900 also includes example shared memory 1910 that may be shared by the cores (e.g., a level 2 (L2 cache)) for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1910. The local memory 1920 and the shared memory 1910 of each of the cores 1902 may be a plurality of levels of cache memory and main memory (e.g., Figure 18 Cache memory is part of a hierarchy of storage devices (e.g., main memory 1814, 1816). Typically, memories higher in the hierarchy exhibit lower access times and have smaller storage capacities than memories at lower levels. Changes to each level of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0131] Each core 1902 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuitry. Each core 1902 includes a control unit circuitry 1914, an arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 1916, a plurality of registers 1918, a local memory 1920, and a second example bus 1922. Other configurations are possible. For example, each core 1902 may include a vector unit circuitry, a single instruction, multiple data (SIMD) unit circuitry, a load / store unit (LSU) circuitry, a branch / jump unit circuitry, a floating point unit (FPU) circuitry, and the like. The control unit circuitry 1914 includes semiconductor-based circuitry configured to control (e.g., coordinate) data movement within the corresponding core 1902. The AL circuitry 1916 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1902. Some examples of the AL circuitry 1916 perform integer-based operations. In other examples, the AL circuitry 1916 also performs floating-point operations. In still other examples, AL circuitry 1916 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 1916 may be referred to as an arithmetic logic unit (ALU).

[0132] The registers 1918 are semiconductor-based structures for storing data and / or instructions (e.g., the results of one or more operations performed by the AL circuit system 1916 of the corresponding core 1902). For example, the registers 1918 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1918 may be, for example, vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Figure 19 The registers 1918 are shown arranged in banks. Alternatively, the registers 1918 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 1902 to reduce access time. The second bus 1922 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0133] Each core 1902 and / or more generally, the microprocessor 1900 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry. The microprocessor 1900 is a semiconductor device that is fabricated to include many transistors that are interconnected to implement the above-described structures in one or more integrated circuits (ICs) contained in one or more packages.

[0134] The microprocessor 1900 may include one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.) and / or collaborate with the one or more accelerators. In some examples, the accelerator is implemented by a logic circuitry to perform certain tasks faster and / or more efficiently than can be accomplished by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on the microprocessor 1900, in the same chip package as the microprocessor 1900, and / or in one or more separate packages from the microprocessor 1900.

[0135] Figure 20 yes Figure 18 FIG. 1 is a block diagram of another example embodiment of programmable circuitry 1812. In this example, programmable circuitry 1812 is implemented by FPGA circuitry 2000. For example, FPGA circuitry 2000 can be implemented by an FPGA. FPGA circuitry 2000 can be used, for example, to perform operations that could otherwise be performed by Figure 19 1900 executes the corresponding machine-readable instructions. However, once configured, FPGA circuitry 2000 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware and, therefore, can typically perform these operations / functions faster than a general-purpose microprocessor executing corresponding software could perform the operations / functions.

[0136] More specifically, Figure 19 The microprocessor 1900 (which is a general-purpose device that can be programmed to perform Figure 17 In contrast, some or all of the machine-readable instructions may be represented by a flowchart, but the interconnections and logic circuitry are fixed once manufactured. Figure 20 The example FPGA circuit system 2000 includes interconnect and logic circuit systems that can be configured, structured, programmed and / or interconnected in different ways after fabrication to instantiate, for example,Figure 17 The FPGA circuit system 2000 may be thought of as an array of logic gates, interconnects, and switches. The switches may be programmed to change the way the logic gates are interconnected via the interconnects, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit system 2000 is reprogrammed). The configured logic circuits enable the logic gates to work together in different ways to perform different operations on the data received by the input circuit system. These operations may correspond to Figure 17 Thus, FPGA circuit system 2000 can be configured and / or constructed to effectively connect to Figure 17 Some or all operations / functions corresponding to the machine-readable instructions of the flowchart are instantiated into dedicated logic circuits, thereby performing the operations / functions corresponding to these software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit system 2000 can perform the same operations / functions as a general-purpose microprocessor. Figure 17 Some or all of the machine-readable instructions corresponding to operations / functions perform these operations / functions faster.

[0137] exist Figure 20 In some examples, the FPGA circuit system 2000 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in the HDL; the code / program can be converted into a low-level language as needed; and the code / program (e.g., code / program in the low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Figure 20 The FPGA circuitry 2000 may access and / or load binary files to cause Figure 20 The FPGA circuit system 2000 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be generated by Figure 20 FPGA circuit system 2000 is implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Figure 20 FPGA circuit system 2000 or part thereof is configured and / or constructed.

[0138] In some examples, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can convert first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 20 The FPGA circuitry 2000 may access and / or load binary files to cause Figure 20 The FPGA circuit system 2000 is configured and / or constructed to perform one or more operations / functions. For example, a binary file may be generated by Figure 20 FPGA circuit system 2000 is implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Figure 20 FPGA circuit system 2000 or part thereof is configured and / or constructed.

[0139] Figure 19 The FPGA circuit system 2000 includes an example input / output (I / O) circuit system 2002 for obtaining and / or outputting data to / from the example configuration circuit system 2004 and / or external hardware 2006. For example, the configuration circuit system 2004 can be implemented by an interface circuit system (which can obtain a binary file, which can be implemented by a bitstream, data and / or machine-readable instructions) to configure the FPGA circuit system 2000 or a portion thereof. In some such examples, the configuration circuit system 2004 can obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), the like, and / or any combination thereof. In some examples, the external hardware 2006 can be implemented by an external hardware circuit system. For example, the external hardware 2006 can be implemented by Figure 17 The present invention is implemented by the microprocessor 1900.

[0140] FPGA circuitry 2000 also includes an array of example logic gate circuitry 2008, a plurality of example configurable interconnects 2010, and example memory circuitry 2012. Logic gate circuitry 2008 and configurable interconnects 2010 may be configured to instantiate one or more operations / functions that may correspond to Figure 20 At least some of the machine-readable instructions and / or other desired operations.Figure 20 The logic gate circuitry 2008 of the illustrated example is fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that are configurable as logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controlled switches (e.g., transistors) are present within each of the logic gate circuitry 2008 to enable configuration of the electrical structures and / or logic gates to form circuits for performing desired operations / functions. The logic gate circuitry 2008 can include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0141] The configurable interconnect 2010 of the illustrated example is an electrically conductive pathway, trace, via, etc., that can include electrically controlled switches (e.g., transistors) whose state can be changed through programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 2008 to program the desired logic circuit.

[0142] The storage circuitry 2012 of the illustrated example is structured to store results of one or more operations performed by respective logic gates. The storage circuitry 2012 can be implemented by registers, etc. In the illustrated example, the storage circuitry 2012 is distributed among the logic gate circuitry 2008 to facilitate access and improve execution speed.

[0143] Figure 19 The example FPGA circuitry 2000 also includes example special-purpose operational circuitry 2014. In this example, the special-purpose operational circuitry 2014 includes special-purpose circuitry 2016 that can be invoked to implement commonly used functions to avoid the need to program these functions on the fly. Examples of such special-purpose circuitry 2016 include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special-purpose circuitry can be present. In some examples, the FPGA circuitry 2000 can also include example general-purpose programmable circuitry 2018, such as example CPU 2020 and / or example DSP 2022. Other general-purpose programmable circuitry 2018 can additionally or alternatively be present, such as GPUs, XPU, etc., that can be programmed to perform other operations.

[0144] Although Figure 20 and Figure 18 shows Figure 19These are two example implementations of programmable circuitry 1812, but many other approaches are contemplated. For example, an FPGA circuitry may include an onboard CPU, such as Figure 18 One or more of the example CPUs 2020. Therefore, Figure 19 The programmable circuit system 1812 may additionally be configured by combining at least Figure 20 An example microprocessor 1900 and Figure 19 In some such hybrid examples, Figure 17 One or more cores 1902 may execute Figure 20 The flowchart represents a first portion of machine-readable instructions to perform(s) first operation / function, Figure 17 The FPGA circuitry 2000 may be configured and / or constructed to perform with Figure 17 The second operation / function(s) corresponding to the second portion of the machine-readable instructions represented by the flowchart of the present invention and / or the ASIC may be configured and / or constructed to perform the same Figure 16 The third portion of the machine-readable instructions represented by the flowchart corresponds to(s) third operation / function.

[0145] It should be understood, therefore, Figure 19 Some or all of the circuitry may be instantiated at the same or different times. For example, Figure 20 The same and / or different portions of the microprocessor 1900 can be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, Figure 16 The same and / or different(s) portions of FPGA circuit system 2000 may be configured and / or constructed to perform operations / functions corresponding to(s) portions of the machine-readable instructions at the same and / or different times.

[0146] In some examples, Figure 19 Some or all of the circuitry of may be instantiated (e.g., in one or more threads of execution concurrently and / or serially). Figure 20 The microprocessor 1900 can execute machine-readable instructions in one or more threads of execution concurrently and / or serially. In some examples, Figure 16 The FPGA circuit system 2000 can be configured and / or constructed to perform operations / functions concurrently and / or serially. In addition, in some examples, Figure 19 Some or all of the circuitry may be in Figure 18 The microprocessor 1900 is executed on one or more virtual machines and / or containers.

[0147] In some examples, Figure 19The programmable circuit system 1812 can be in one or more packages. For example, Figure 20 The microprocessor 1900 and / or Figure 18 The FPGA circuit system 2000 can be in one or more packages. In some examples, the XPU can be composed of Figure 19 The XPU may be implemented by programmable circuitry 1812, which may be in one or more packages. For example, the XPU may include a CPU in a package (e.g., Figure 20 Microprocessor 1900, Figure 20 CPU2020, etc.), a DSP in another package (e.g. Figure 20 DSP 2022), a GPU in yet another package, and an FPGA in yet another package (e.g. ​ FPGA circuit system 2000).

[0148] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "including" or "comprising" (e.g., includes, contains, having, etc.) as antecedent or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transition term, such as in the antecedent of a claim, it is open-ended in the same manner that the terms "including" and "comprising" are open-ended. For example, when used in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0149] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plural reference. As used herein, the term "a" or "an" object refers to one or more of that object. The terms "a" (or "an," "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple devices, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these features may be combined together, and inclusion in different examples or claims does not mean that a combination of features is not feasible and / or disadvantageous.

[0150] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one portion between the Earth and the first part. Similarly, as used herein, a first part is "below a second part" when the first part is closer to the Earth than the second part. As described above, a first part can be above or below a second part, with one or more other parts in between, without other parts in between, with the first and second parts in contact, or with the first and second parts not in direct contact with each other.

[0151] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any manner over another part (e.g., positioned on, located on, disposed on, or formed on, etc.) means that the referenced part is either in contact with the other part or the referenced part is over the other part with one or more intermediate parts located therebetween.

[0152] As used herein, unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and engagement) may include intermediate members between the elements to which the connection reference refers and / or relative movement between such elements. Thus, a connection reference does not necessarily infer that two elements are directly connected and / or in a fixed relationship to each other. As used herein, a statement that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0153] Unless otherwise specifically stated, the use of descriptors (such as "first," "second," "third," etc.) herein does not in any way imply or otherwise describe any meaning of priority, physical order, arrangement in a list, and / or ordering, but is merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (such as "second" or "third") in the claims. In such cases, it should be understood that these descriptors are only used to clearly identify these elements in the context of the discussion (e.g., within the claims), where these elements might, for example, otherwise share the same name.

[0154] As used herein, "approximately" and "about" modify their subject matter / values ​​to recognize the potential for variations that occur in real-world applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections as will be understood by one of ordinary skill in the art. For example, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified herein.

[0155] As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be real-world delays for computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + 1 second.

[0156] As used herein, the phrase "in communication," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-time events.

[0157] As used herein, "programmable circuitry" is defined as including (i) one or more specialized circuits (e.g., application specific circuits (ASICs)) that are configured to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed by instructions to perform specific function(s) and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include a programmable microprocessor, such as a central processing unit (CPU) that can execute a first instruction to perform one or more operations and / or functions, a field programmable gate array (FPGA) that can be programmed by a second instruction to cause the configuration and / or construction of an FPGA to instantiate one or more operations and / or functions corresponding to the first instruction, a graphics processor unit (GPU) that can execute a first instruction to perform one or more operations and / or functions, a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions, an XPU, a network processing unit (NPU), one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions, and / or integrated circuits such as application specific integrated circuits (ASICs). For example, the XPU may be implemented through a heterogeneous computing system including multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and orchestration technology (e.g., (multiple) application programming interfaces (APIs)) that may distribute (multiple) computing tasks to any programmable circuit system among the multiple types of programmable circuit systems that is suitable and available for performing the computing tasks.

[0158] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0159] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for achieving cost-effective and highly portable vehicle guidance. Further examples and combinations thereof include the following:

[0160] Example 1 includes a method comprising digitizing at least one signal received at an antenna array of a receiver of a vehicle into a digitized data stream of I and Q samples, the at least one signal being received from a beacon, the at least one signal being modulated at the beacon with a pseudo-random code, correlating the I and Q samples with a locally generated pseudo-random code of the receiver to recover a carrier signal, and computing a direction of arrival of the at least one signal from the beacon in a vehicle reference frame based on a relative phase characteristic of the recovered carrier signal.

[0161] Example 2 includes the method as defined in example 1, further comprising determining at least one signal error of the digitized data stream.

[0162] Example 3 includes the method as defined in example 2, further comprising driving a numerically controlled oscillator based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

[0163] Example 4 includes the method as defined in example 2, further comprising determining the at least one signal error by averaging errors of the digitized data stream.

[0164] Example 5 includes the method as defined in example 1, further comprising utilizing a delay locked loop (DLL) to track a pseudo-random noise (PRN) sequence with signals received at an antenna of the array, and demodulate or de-spread signals of other antennas of the array by the PRN sequence.

[0165] Example 6 includes the method as defined in example 1, further comprising synchronizing the digitized data stream with a locally generated copy of the pseudo-random code with a delay locked loop.

[0166] Example 7 includes the method as defined in example 1, further comprising determining a position of the vehicle in a beacon reference frame by combining the direction of arrival in the vehicle reference frame based on the recovered carrier signal with measurements of pitch, roll, heading, and altitude.

[0167] Example 8 includes an apparatus for guiding a vehicle, the apparatus comprising an interface circuit system communicatively coupled to an antenna array of the vehicle, the antenna array including respective antennas for receiving a signal transmitted from a beacon, the transmitted signal being modulated with a pseudorandom code at the beacon, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to downconvert and digitize the signal received at the antenna array into baseband I and Q samples, correlate the I and Q samples with a locally generated pseudorandom code to align the received signal in time, recover a carrier signal by modulating the received signal with a synchronized pseudorandom noise (PRN) code to despread the received signal, and calculate a heading and elevation angle of a direction of arrival of the signal transmitted from the beacon in a vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0168] Example 9 includes an apparatus as defined in Example 8, wherein one or more of the at least one processor circuit is to determine at least one signal error of the digitized signal.

[0169] Example 10 includes an apparatus as defined in Example 9, wherein one or more of the at least one processor circuits is used to drive a numerically controlled oscillator based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

[0170] Example 11 includes an apparatus as defined in Example 9, wherein one or more of the at least one processor circuits is to determine the at least one signal error by averaging errors of the digitized signal.

[0171] Example 12 includes the apparatus as defined in Example 8, wherein one or more of the at least one processor circuits is to synchronize the locally generated pseudorandom code with the pseudorandom code corresponding to the beacon.

[0172] Example 13 includes the apparatus as defined in Example 8, wherein one or more of the at least one processor circuits is to synchronize the digitized signal with a locally generated code replica via a delay locked loop.

[0173] Example 14 includes an apparatus as defined in Example 8, wherein one or more of the at least one processor circuits is used to determine the orientation of the vehicle in a beacon reference frame by combining the direction of arrival based on the recovered carrier signal in the vehicle reference frame with measurements of pitch, roll, heading, and altitude.

[0174] Example 15 includes a receiver for guiding a vehicle, the receiver comprising an antenna array for receiving a signal transmitted from a beacon, the transmitted signal being modulated with a pseudorandom code at the beacon, a digitizer for digitizing the signal received at the antenna into a digitized signal having I and Q samples, the digitized signal being modulated with a locally generated pseudorandom code, and a software-defined radio for correlating the I and Q samples with the locally generated pseudorandom code to recover a carrier signal from the digitized signal and calculating a direction of arrival of the signal from the beacon in a vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0175] Example 16 includes a receiver as defined in Example 15, wherein the software defined radio is to determine at least one signal error of the digitized signal.

[0176] Example 17 includes a receiver as defined in Example 16, wherein the software defined radio is to drive a numerically controlled oscillator based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

[0177] Example 18 includes a receiver as defined in Example 15, wherein the software defined radio is used to utilize a delay locked loop (DLL) to track a PRN sequence through a signal received at an antenna of the array and to demodulate or despread signals of other antennas of the array through the PRN sequence.

[0178] Example 19 includes a receiver as defined in Example 15, wherein the software defined radio is to synchronize the digitized signal with a locally generated code replica via a delay locked loop.

[0179] Example 20 includes a receiver as defined in Example 15, wherein the software defined radio is used to determine the position of the vehicle based on the recovered carrier signal.

[0180] Example 21 includes a non-transitory machine-readable storage medium comprising instructions that cause at least one processor circuit to digitize a signal received at an antenna array of a receiver of a vehicle into at least a data stream of I and Q samples, the received signal corresponding to a transmitted signal from a beacon, the transmitted signal being modulated with a pseudorandom code at the beacon, correlating the I and Q samples with a locally generated pseudorandom code of the receiver to align the received signal in time, recovering a carrier signal by modulating the signal with a synchronized pseudorandom noise (PRN) code to despread the received signal, and calculating a heading and an elevation angle of the vehicle relative to a direction of arrival of the beacon in a vehicle reference frame based on relative phase characteristics of the recovered carrier signal.

[0181] Example 22 includes a non-transitory machine-readable storage medium as defined in Example 21, wherein the instructions cause one or more of the at least one processor circuit to determine at least one signal error of the digitized signal.

[0182] Example 23 includes a non-transitory machine-readable storage medium as defined in Example 22, wherein the instructions cause one or more of the at least one processor circuits to drive a numerically controlled oscillator based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

[0183] Example 24 includes a non-transitory machine-readable storage medium as defined in Example 21, wherein the instructions cause one or more of the at least one processor circuits to synchronize the digitized signal with a locally generated copy of the pseudorandom code via a delay locked loop.

[0184] Example 25 includes a non-transitory machine-readable storage medium as defined in Example 21, wherein the instructions cause one or more of the at least one processor circuits to determine the orientation of the vehicle in a beacon reference frame by combining the direction of arrival based on the recovered carrier signal in the vehicle reference frame with measurements of pitch, roll, heading, and altitude.

[0185] From the foregoing, it will be appreciated that example systems, apparatuses, articles of manufacture, and methods have been disclosed that achieve cost-effective and highly portable guidance support. Furthermore, the examples disclosed herein can efficiently utilize spectrum. The disclosed systems, apparatuses, articles of manufacture, and methods improve the efficiency of using computing devices by reducing necessary computations. Thus, the disclosed systems, apparatuses, articles of manufacture, and methods are directed to one or more improvements in the operation of machines, such as computers or other electronic and / or mechanical devices.

[0186] The appended claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles of manufacture, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A method comprising: digitizing at least one signal received at an antenna array (104) of a receiver (102) of a vehicle (101) into a digitized data stream of I and Q samples, the at least one signal being received from a beacon at which the at least one signal was modulated with a pseudorandom code; correlating the I and Q samples with a locally generated pseudorandom code for the receiver to recover a carrier signal; and A direction of arrival of the at least one signal from the beacon in a vehicle reference frame is calculated based on the relative phase characteristics of the recovered carrier signal. 2 . The method of claim 1 , further comprising determining at least one signal error of the digitized data stream.

3. The method of claim 2, further comprising driving a numerically controlled oscillator (610) based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

4. The method of claim 2, further comprising determining the at least one signal error by averaging errors of the digitized data stream.

5. The method according to claim 1, further comprising: utilizing a delay locked loop (DLL) to track a pseudorandom noise sequence (PRN sequence) via signals received at antennas of the array, and The signals of the other antennas of the array are demodulated or despread by the PRN sequence.

6. The method of claim 1, further comprising synchronizing the digitized data stream with a locally generated copy of the pseudorandom code via a delay locked loop.

7. The method of claim 1 further comprising determining the orientation of the vehicle in a beacon reference frame by combining the direction of arrival based on the recovered carrier signal in the vehicle reference frame with measurements of pitch, roll, heading, and altitude.

8. A device for guiding a vehicle, the device comprising: an interface circuitry (1820) communicatively coupled to an antenna array of the vehicle, the antenna array including respective antennas for receiving a signal transmitted from a beacon, the transmitted signal being modulated with a pseudorandom code at the beacon; machine-readable instructions (1832); and at least one processor circuit (1800) programmed by the machine-readable instructions to: down-converting and digitizing signals received at the antenna array into baseband I and Q samples; correlating the I and Q samples with a locally generated pseudorandom code to time align the received signal; Despreading the received signal by modulating it with a synchronized pseudorandom noise (PRN) code to recover the carrier signal; and The heading and elevation angle of the direction of arrival of the signal transmitted from the beacon in the vehicle reference frame are calculated based on the relative phase characteristics of the recovered carrier signal.

9. The device according to claim 8, wherein One or more of the at least one processor circuit is configured to determine at least one signal error of the digitized signal.

10. The device according to claim 9, wherein One or more of the at least one processor circuit is configured to drive a numerically controlled oscillator based on the at least one signal error to recover the carrier signal via at least one modulator of the receiver.

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