Parallel storage system and method of data stream architecture and medium

Abstract

The invention discloses a parallel storage system and method of a data stream architecture and a medium, mainly relates to the technical field of parallel storage, and is used for solving the problem that data extraction is disordered in the data execution process of different RV processor cores in an existing scheme. Comprising a plurality of processor cores containing expansion instructions; the processor core is connected with a synchronization control module, a lock distribution module and a lock management module in the data synchronization unit; the synchronization control module is connected with the authority control module in the data synchronization unit, and the authority control module is connected with the priority control module in the data synchronization unit; the priority control module is connected with the plate arbitration module in the parallel storage unit; the lock management module and the plate arbitration module are respectively connected with the multi-plate storage module; the multi-plate storage module is connected with the cache management module in the parallel storage unit, and the multi-plate storage module and the cache management module are respectively connected with the main memory; wherein the multi-plate storage module is composed of a plurality of storage plates.

Description

Technical Field

[0001] The present application relates to the field of parallel storage technology, and in particular to a parallel storage system, method, and medium of a data stream architecture. Background Art

[0002] The dataflow architecture is a computing model driven by the flow of data. Its core concept is "data-driven execution," where computing operations are automatically triggered when the required data is available, rather than relying on the traditional sequential execution of instructions. The dataflow architecture is particularly well-suited for highly parallel, data-intensive computing scenarios. However, highly parallel data exchange places higher demands on storage solutions. The limited parallelism of storage solutions in traditional architectures makes it difficult to meet the frequent data exchange between numerous computing tasks in dataflow architectures.

[0003] In highly parallel storage solutions, data synchronization mechanisms are key technologies for ensuring the correctness of computing tasks. Data exchange between computing tasks is always accompanied by data synchronization issues: when two logically consecutive computing tasks are deployed on different cores in a data flow architecture, if the preceding core begins execution before the preceding core has completed, old data will be retrieved, leading to computational errors. If the preceding core begins execution before the following core has completed execution, data not read by the following core may be overwritten by new data, resulting in data loss. Both of these scenarios involve data security issues caused by data asynchrony, which seriously impacts the parallel performance of the data flow architecture. Summary of the Invention

[0004] The present application provides a parallel storage system, method and medium with a data flow architecture to solve the problem of data extraction confusion in the data execution process of different RV processor cores in the existing solution.

[0005] In a first aspect, the present application provides a parallel storage system with a data flow architecture, characterized in that the system includes: Several RV processor cores with extended instructions; The RV processor core is connected to the synchronization control module, lock allocation module and lock management module in the data synchronization unit; the synchronization control module is connected to the authority control module in the data synchronization unit, and the authority control module is connected to the priority control module in the data synchronization unit; The priority control module is connected to the plate arbitration module in the parallel storage unit; The lock management module and the plate arbitration module are respectively connected to the multi-plate storage module; the multi-plate storage module is connected to the cache management module in the parallel storage unit, and the multi-plate storage module and the cache management module are respectively connected to the main memory; wherein the multi-plate storage module is composed of several storage plates.

[0006] In a second aspect, the application provides a parallel storage method of a data flow architecture, applied to a parallel storage system of the data flow architecture, and the method comprises: A barrier instruction, a load reservation instruction and a conditional storage instruction are extended in a RISC-V instruction set corresponding to the RV processor core; the barrier instruction comprises a global access barrier instruction and a local access barrier instruction; When any RV processor core 0 performs a data access operation, the RV processor core 0 initiates a global access barrier instruction to the synchronization control module and waits for the execution of the initiated data access instruction to be completed; After the execution of the initiated data access instruction is completed, the RV processor core 0 issues a load reservation instruction to the lock allocation module; the load reservation instruction contains a start address field of the accessed data; the lock allocation module allocates a lock address according to an alignment address range corresponding to the start address field, and marks the lock address when the lock address is successfully allocated; After the lock address is successfully allocated, the RV processor core 0 issues a conditional storage instruction to the lock allocation module, and the lock allocation module determines whether the lock address is successfully applied according to whether the lock address in the conditional storage instruction is marked; When the lock address is successfully applied, the RV processor core 0 obtains the lock address; before the RV processor core 0 releases the lock address, the lock address is marked, and any RV processor core 1 cannot successfully apply the lock address through the conditional storage instruction; After the RV processor core 0 obtains the lock address, the RV processor core 0 sends a data access instruction corresponding to the lock address data to the synchronization control module, and the synchronization control module transmits the data access instruction to the permission control module; when a preset requirement in the permission control module is met, the data access instruction is issued to the priority control module; According to the priority of the RV processor core corresponding to each data access instruction, the priority control module sequentially issues the data access instruction to the board arbitration module; the board arbitration module determines a specific storage board to which the data access instruction is issued according to the access address in the data access instruction; when there is new data when the data access instruction is executed, the new data is stored in a preset address; the preset address is in the lock address range; The RV processor core 0 sends a local access barrier instruction containing the lock address to the synchronization control module, waits for the execution of the data access instruction in the lock address range through the local access barrier instruction, and releases the lock address; After the lock address is released, the RV processor core 1 can successfully apply the lock address through the conditional storage instruction, and can further perform a data access operation on the data corresponding to the lock address.

[0007] In an implementation manner of the application, the barrier instruction comprises an instruction distinguishing field, a mode field, a placeholder, an rs1 field and an opcode field. Among them, the mode field represents the barrier type; When the mode field is 00, it corresponds to the barrier of global read and write memory access operations; When the mode field is 01, it corresponds to the barrier of the write memory access operation; When the mode field is 10, it corresponds to the barrier of the read memory operation; When the mode field is 11, it corresponds to the barrier for read and write memory access operations at the specific lock address; The rs1 field represents the lock address. In a barrier with mode 11, it is used to indicate the specific lock address range. The opcode field represents the instruction type and is used to distinguish extended instructions from RISC-V standard instructions.

[0008] In one implementation of the present application, the load reserve instruction includes: an instruction distinguishing field, an rs1 field, an rd field, an aq field, an rl field, a placeholder, and an opcode field; The rs1 field represents the starting address of the lock address; the rd field represents the lock allocation result. If the allocation is successful, the lock address is marked and returned. If the allocation fails, only the 0 address is returned. The aq field and rl field are memory access order control fields. Setting rl to 1 indicates that the memory access instruction before this instruction must be completed first, and setting aq to 1 indicates that the memory access instruction after this instruction must be completed later.

[0009] In one implementation of the present application, the conditional store instruction includes: an instruction distinguishing field, an rs1 field, an rs2 field, an rd field, a placeholder, and an opcode field; Among them, the rs1 field represents the starting address of the lock address; the rs2 field represents the ending address of the lock address; The rd field represents the lock application result; if the load-hold instruction has marked the current lock address and no conditional store instruction other than the current RV processor core has applied for the lock address, the application is successful and returns a value of 0; if the load-hold instruction has not assigned the current lock address or the current lock address has been successfully applied for by a conditional store instruction of another RV processor core, the application fails and returns a non-zero value.

[0010] In one implementation of the present application, the lock allocation module allocates a lock address according to the aligned address range corresponding to the start address field, and marks the lock address when the lock address allocation is successful, specifically including: By formula: , calculate the aligned address range ;in, is the original address, is the bit width of the original address, It is a 16-bit 0 address, used to fill the lower 16 bits of the address; for Assign a lock address; If the lock address is free, the lock address allocation is successful and the lock address will be marked; if the lock address is occupied, the lock address allocation fails.

[0011] In one implementation of the present application, when the preset requirements in the permission control module are met, the data access instruction is sent to the priority control module, specifically including: Detect whether the address involved in the data access instruction is a preset legal address; When it is a preset legal address, the data access instruction is valid and meets the preset requirements in the authority control module; otherwise, the data access instruction is invalid and does not meet the preset requirements in the authority control module.

[0012] In one implementation of the present application, before determining the priority of the RV processor core corresponding to each data access instruction, the method further includes: Get the computational load of the RV processor core and determine the priority order of the RV processor core according to the computational load.

[0013] In one implementation of the present application, the sector arbitration module determines the specific storage sector to which the data access instruction is issued based on the access address in the data access instruction, specifically including: The sector arbitration module determines the specific storage sector to which the data access instruction is issued based on the storage sector where the access address in the data access instruction is located; When the access address in the data access instruction is located in the main memory, the corresponding data is moved to the storage block through the cache management module, and then the storage block where the data is moved is determined to be the specific storage block to which the data access instruction is issued; When the data access instruction is completed, the cache management module writes the data back to the main memory.

[0014] In a third aspect, the present application provides a non-volatile computer storage medium having computer instructions stored thereon, which, when executed, implement a parallel storage method of a data flow architecture as described above.

[0015] It can be seen from the above technical solutions that this application has the following advantages: By constructing a multi-level cascading hardware cooperative control module, the system realizes physical isolation and logical decoupling of data synchronization and storage access. Specifically, (1) hardware level synchronization isolation: the cascading design of the synchronization control module and the permission control module makes the data access instruction pass through double verification (permission verification + priority arbitration), which eliminates the unauthorized core from accessing the lock address region beyond the boundary from the physical layer; (2) dynamic resource partitioning: the cooperation of the multi-plate storage module and the plate arbitration module splits the traditional single storage body into several physically isolated storage plates, and the access requests of different cores can be automatically routed to the corresponding plate according to the address, realizing the physical isolation of the storage bandwidth; (3) lock state full life cycle management: the lock management module and the lock allocation module form a closed loop control, and through the "allocation-occupation-release" state transition mechanism of the lock address, it is ensured that only one core can modify the critical region data at the same time. This hardware-level mutual exclusion solves the data race problem in the multi-core parallel scene.

[0016] In addition, by combining the extended RISC-V instruction set with the hierarchical barrier mechanism, a fine-grained synchronization control capability is formed: (1) double barrier instruction: the global access barrier ensures the visibility of all incomplete access operations, and the local access barrier is synchronized for a specific lock address interval. This hierarchical design saves about a waiting cycle compared to the traditional memory barrier instruction; (2) atomic operation primitization: the load reservation (LR) and conditional storage (SC) instructions form an atomic operation pair, and when the lock address is marked, the conditional storage instruction of other cores will fail directly. This hardware-implemented atomicity reduces pipeline stalls compared to software lock solutions; (3) priority-aware access scheduling: the priority control module dynamically adjusts the instruction issuance order according to core load, so that high-priority cores can quickly acquire storage bandwidth, and through plate arbitration, it is ensured that low-priority requests will not be starved. This design improves the overall throughput of the system while ensuring fairness. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a parallel storage system internal structure schematic diagram of a data flow architecture provided by an embodiment of the present application.

[0019] Figure 2 is a parallel storage method flowchart of a data flow architecture provided by an embodiment of the present application.

[0020] Figure 3This is a schematic diagram of an implementation method provided in an embodiment of the present application.

[0021] Description of reference numerals: 10. RV processor core; 20. Data synchronization unit; 21. Synchronization control module; 22. Permission control module; 23. Priority control module; 24. Lock allocation module; 25. Lock management module; 30. Parallel storage unit; 31. Segment arbitration module; 32. Multi-segment storage module; 33. Cache management module; 40. Main memory. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] It should be understood by those skilled in the art that the embodiments described below are merely preferred embodiments of the present disclosure and do not imply that the present disclosure can only be implemented through these preferred embodiments. These preferred embodiments are merely intended to explain the technical principles of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Based on the preferred embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present disclosure.

[0024] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0025] The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0026] This application Figure 1 A parallel storage system with a data stream architecture is provided in an embodiment of the present application. Figure 1 As shown, the system provided in the embodiment of the present application mainly includes: Several RV processor cores 10 including extended instructions; The RV processor core 10 is connected with a synchronization control module 21, a lock distribution module 24 and a lock management module 25 in the data synchronization unit 20; the synchronization control module 21 is connected with an authority control module 22 in the data synchronization unit 20, and the authority control module 22 is connected with a priority control module 23 in the data synchronization unit 20; The priority control module 23 is connected with a board arbitration module 31 in the parallel storage unit 30. The lock management module 25 and the board arbitration module 31 are respectively connected with a multi-board storage module 32; the multi-board storage module 32 is connected with a cache management module 33 in the parallel storage unit 30, and the multi-board storage module 32 and the cache management module 33 are respectively connected with the main memory 40; wherein the multi-board storage module 32 is composed of a plurality of storage boards.

[0027] Based on the above description, those skilled in the art can understand that the embodiment is composed of the parallel storage unit 30, the data synchronization unit 20, the main memory 40 (DDR) and a plurality of RV processor cores 10. The parallel storage unit 30 is used to provide parallel data exchange function among the RV cores, which is composed of the cache management module 33, the board arbitration module 31 and the multi-board storage module 32: the cache management module 33 is responsible for data update between the main memory 40 and the multi-board storage module 32, the board arbitration module 31 is responsible for managing the memory access order of the cores, and the multi-board storage module 32 is responsible for storing data. The data synchronization unit 20 is used to provide data synchronization function when the data is exchanged among the RV cores, which is composed of the synchronization control module 21, the authority control module 22, the priority control module 23, the lock distribution module 24 and the lock management module 25: the synchronization control module 21 and the authority control module 22 are responsible for ensuring the safety of memory access, the priority control module 23 is responsible for adjusting the rules of the board arbitration module 31, and the lock distribution module 24 and the lock management module 25 are responsible for ensuring the synchronization of data.

[0028] The RV processor core 10 is a computing core conforming to the RISC-V instruction set architecture, which is used to obtain source data from the parallel storage unit 30, and write back to the parallel storage unit 30 after executing a specific computing task. The main memory 40 adopts a DDR memory, which is used to store the initial data of the entire computing task, and the final settlement result will also be written into the main memory 40. The RV processor core 10 and the main memory 40 both adopt a general design.

[0029] As an example, the extended instructions include: barrier instruction, load reservation instruction, conditional storage instruction.

[0030] The synchronization control module 21, the lock distribution module 24 and the lock management module 25 manage the synchronization lock to realize data synchronization among the multiple cores: A. In the synchronization control module 21, the RV processor core 10 sends the ad_fence barrier instruction to the synchronization control module 21. After decoding, the ad_fence barrier instruction controls the execution of the module. Based on the barrier type, it monitors eligible requests from the priority control module 23 to the multi-slab storage module 32 and blocks subsequent requests until all eligible requests are completed. For barriers for local read and write memory access operations, the module queries the lock management module 25 for the address range corresponding to the lock based on the lock address in the instruction. Subsequent requests are blocked until memory access requests within this address range are completed.

[0031] B. In the lock allocation module 24, the RV processor core 10 sends the ad_lr load reserve instruction to the lock allocation module 24, which controls the execution of the module after decoding. The module aligns the starting address field in the instruction to 64k and calculates the aligned address. The address alignment calculation method is shown in the formula ( is the aligned address, is the original address, is the bit width of the original address, The lock allocation unit allocates a lock address for the aligned 64k address range. If the lock address is free, the lock allocation succeeds and the lock address is marked. If the lock address is already occupied, the lock allocation fails.

[0032]

[0033] After decoding, the ad_sc conditional store instruction also enters the lock allocation module 24. The module determines whether the lock address of the instruction is marked. If it is marked, the lock request is successful and the mark is cleared. If it is not marked (the lock is not allocated or has been claimed by another core after the lock is allocated), the lock request fails.

[0034] C. In the lock management module 25, the RV processor core 10 sends the ad_lr instruction to the lock management module 25. After successfully allocating the lock, it records the starting address field in the instruction. After successfully requesting the lock with the ad_sc instruction, it records the ending address field in the instruction summary. The core can initiate a query request to the lock management module 25 to obtain the address range corresponding to the lock address.

[0035] The priority control module 23, the plate arbitration module 31, and the multi-plate storage module 32 respond to memory access requests in parallel to implement data access in the data flow architecture: A. Priority control module 23 assigns different priorities to cores in the data flow architecture based on their computational load. Cores with higher computational loads require more frequent data exchange and are assigned higher priorities. Cores with lower computational loads have relatively lower data exchange rates and are assigned lower priorities. Normal memory access requests enter this module first, and requests from cores with higher priorities are responded to first.

[0036] B. In the block arbitration module 31, memory access requests are arbitrated based on the storage block where the memory access address is located. If each memory access request is located in a different block, each memory access request can be responded to simultaneously. If multiple memory access requests are located in the same block, the memory access requests are responded to sequentially through polling arbitration.

[0037] C. In the multi-block storage module 32, the responded memory access request is written into or read from the memory.

[0038] Furthermore, the permission control module 22 performs a permission check on memory access requests before the priority control module 23: if the request is for a valid address (a valid lock request), the memory access request is valid; if the request is for an illegal address (no lock request, but the address range corresponding to the lock is requested), the memory access request is invalid. The cache management module 33 is located between the multi-slab storage module 32 and the main memory 40. When a memory access request is placed in the main memory 40, the cache management module 33 is responsible for moving data of a specified block size to the multi-slab storage module 32. When the computation task is completed, the cache management module 33 is responsible for writing the data in the multi-slab storage module 32 back to the main memory 40.

[0039] In addition, the embodiment provides a parallel storage method of a data stream architecture, such as Figure 2 As shown, the method provided in the embodiment of the present application mainly includes the following steps: Step 110: Extend barrier instructions, load-reserve instructions, and conditional store instructions in the RISC-V instruction set corresponding to the RV processor core.

[0040] The barrier instructions include global access barrier instructions and local access barrier instructions.

[0041] In some embodiments, as shown in the extended instruction table, the barrier instruction ad_fence includes: an instruction distinguishing field, a mode field, a placeholder, an rs1 field, and an opcode field; The mode field represents the barrier type: 00 corresponds to a global read / write barrier (waiting for all read / write accesses to complete), 01 corresponds to a write barrier (waiting only for all write accesses to complete), 10 corresponds to a read barrier (waiting only for all read accesses to complete), and 11 corresponds to a local read / write barrier (waiting only for read / write accesses within a specified address range to complete). The rs1 field represents the lock address (based on the lock management unit's determination of the address range). In a barrier with mode 11, it indicates the local address range. The opcode field represents the instruction type, distinguishing extended instructions from standard RISC-V instructions. Fields 31-27 distinguish the three extended instructions. Fields 24-20, 14-12, and 11-7 are placeholders and have no special meaning in this instruction. This instruction is a memory barrier, used to wait for an already initiated data access request to complete before initiating a data synchronization request.

[0042] As shown in the extended instruction table, the load reserve instruction ad_lr includes: an instruction distinguishing field, an rs1 field, an rd field, an aq field, an rl field, a placeholder, and an opcode field; The rs1 field represents the starting address of the lock address; the rd field represents the lock allocation result. If the allocation is successful, the lock address is marked and returned. If the allocation fails, only the 0 address is returned. The aq field and rl field are memory access order control fields. Setting rl to 1 indicates that the memory access instruction before this instruction must be completed first, and setting aq to 1 indicates that the memory access instruction after this instruction must be completed later.

[0043] As shown in the extended instruction table, the conditional store instruction ad_sc includes: an instruction distinguishing field, an rs1 field, an rs2 field, an rd field, a placeholder, and an opcode field; Among them, the rs1 field represents the starting address of the lock address; the rs2 field represents the ending address of the lock address; The rd field represents the lock application result; if the load-hold instruction has marked the current lock address and no conditional store instruction other than the current RV processor core has applied for the lock address, the application is successful and returns a value of 0; if the load-hold instruction has not assigned the current lock address or the current lock address has been successfully applied for by a conditional store instruction of another RV processor core, the application fails and returns a non-zero value.

[0044] Extended instruction list

[0045] Step 120: When any RV processor core 0 performs a data memory access operation, the RV processor core 0 initiates a global access barrier instruction to the synchronization control module and waits for the initiated data memory access instruction to be executed.

[0046] Step 130: After the initiated data memory access instruction is executed, the RV processor core 0 sends a load reserve instruction to the lock allocation module; the lock allocation module allocates a lock address according to the aligned address range corresponding to the start address field, and marks the lock address when the lock address allocation is successful.

[0047] The load-reserve instruction includes a start address field for accessing data.

[0048] The lock allocation module allocates a lock address based on the aligned address range corresponding to the start address field. When the lock address is allocated successfully, the lock address is marked. Specifically, the following steps are performed: By formula: , calculate the aligned address range ;in, is the original address, is the bit width of the original address, It is a 16-bit 0 address, used to fill the lower 16 bits of the address; for Assign a lock address; If the lock address is free, the lock address allocation is successful and the lock address will be marked; if the lock address is occupied, the lock address allocation fails.

[0049] Step 140: After the lock address is successfully allocated, the RV processor core 0 sends a conditional store instruction to the lock allocation module. The lock allocation module determines whether the lock address is successfully applied based on whether the lock address in the conditional store instruction is marked. When the lock address is successfully applied, the RV processor core 0 obtains the lock address. Before the RV processor core 0 releases the lock address, the lock address is marked, and any RV processor core 1 cannot successfully apply for the lock address through the conditional store instruction.

[0050] Step 150: After the RV processor core 0 obtains the lock address, the RV processor core 0 sends a data access instruction corresponding to the lock address data to the synchronization control module, and the synchronization control module transmits the data access instruction to the permission control module; when the preset requirements in the permission control module are met, the data access instruction is sent to the priority control module.

[0051] Step 160: Based on the priority of the RV processor core corresponding to each data access instruction, the priority control module sends the data access instruction to the sector arbitration module in sequence; the sector arbitration module determines the specific storage sector to which the data access instruction is sent based on the access address in the data access instruction; when there is new data when the data access instruction is executed, the new data is stored in the preset address.

[0052] The preset address is within the lock address range.

[0053] When the preset requirements in the permission control module are met, the data access instruction is sent to the priority control module, specifically including: Detect whether the address involved in the data access instruction is a preset legal address; When it is a preset legal address, the data access instruction is valid and meets the preset requirements in the authority control module; otherwise, the data access instruction is invalid and does not meet the preset requirements in the authority control module.

[0054] Before determining the priority of the RV processor core corresponding to each data access instruction, the method further includes: Get the computational load of the RV processor core and determine the priority order of the RV processor core according to the computational load.

[0055] The sector arbitration module determines the specific storage sector to which the data access instruction is issued based on the access address in the data access instruction, including: The block arbitration module determines the specific storage block to which the data access instruction is issued based on the storage block where the access address in the data access instruction is located; When the access address in the data access instruction is located in the main memory, the corresponding data is moved to the storage block through the cache management module, and then the storage block where the data is moved is determined to be the specific storage block to which the data access instruction is issued; When the data access instruction is completed, the cache management module writes the data back to the main memory.

[0056] Step 170: RV processor core 0 sends a local access barrier instruction containing a lock address to the synchronization control module, waits for the data memory access instruction within the lock address interval to be executed through the local access barrier instruction, and releases the lock address; after the lock address is released, RV processor core 1 can successfully apply for the lock address through a conditional store instruction, and then can execute the data memory access operation corresponding to the lock address.

[0057] Based on the above description, if Figure 3 As shown, this method can be specifically as follows: 1. (Core 0): The ad_fence instruction initiates a global memory barrier instruction with mode 00, waiting for the initiated data memory access instruction to complete. The global memory barrier does not use the lock address field, so register r0 (a normally zero register, always 0) is used as the lock address; the ad_lr instruction initiates a lock allocation request with register r1 as the starting address, and register r2 stores the allocated lock address; the ad_sc instruction initiates a lock application request, with register r2 as the lock address, register r3 as the end address, and register r5 as the lock application result.

[0058] 2, (core 1): the ad_fence and ad_lr instructions are the same as step 1, but since core 0 has acquired the lock, the lock allocation of the ad_lr instruction of this step fails, and core 1 needs to wait for core 0 to release the lock.

[0059] 3, (core 0): two ld load instructions read the source data in memory addresses A and B into registers t1 and t2 respectively; a mul multiplication instruction performs multiplication on registers t1 and t2, and register t5 stores the calculation result; an sd store instruction writes the calculation result in register t5 into memory address C.

[0060] 4, (core 0): an ad_fence instruction initiates a local memory access barrier instruction with mode 11, and register r2 is the lock address (obtained in step 1), which corresponds to a local interval from a start address to an end address, and this instruction waits for the memory access request in the interval to be executed and releases the synchronization lock.

[0061] 5, (core 1): the ad_sc instruction is the same as step 1, and after core 0 releases the synchronization lock, core 1 successfully applies for the lock.

[0062] 6, (core 1): an ld load instruction reads the calculation result of core 0 from memory address C and stores it in register t1; a softMax activation function instruction performs an activation function calculation on register t1, and the result is stored in register t5; an sd store instruction writes the calculation result in t5 into memory address C; an ad_fence instruction is the same as step 4, and waits for the memory access request in the interval to be executed and releases the synchronization lock.

[0063] In addition, the embodiment of the present application further provides a non-volatile computer storage medium, which has executable instructions stored thereon, and the executable instructions, when executed, implement the parallel storage method of the data flow architecture.

[0064] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel storage system with a data flow architecture, characterized in that: The system comprises: Several RV processor cores with extended instructions; The RV processor core is connected to the synchronization control module, lock allocation module and lock management module in the data synchronization unit; the synchronization control module is connected to the authority control module in the data synchronization unit, and the authority control module is connected to the priority control module in the data synchronization unit; The priority control module is connected to the plate arbitration module in the parallel storage unit; The lock management module and the plate arbitration module are respectively connected to the multi-plate storage module; the multi-plate storage module is connected to the cache management module in the parallel storage unit, and the multi-plate storage module and the cache management module are respectively connected to the main memory; wherein the multi-plate storage module is composed of several storage plates.

2. A parallel storage method for a data stream architecture, applied to the parallel storage system for a data stream architecture according to claim 1, characterized in that: The method comprises: Extending barrier instructions, load-reserve instructions, and conditional store instructions in the RISC-V instruction set corresponding to the RV processor core; wherein barrier instructions include global access barrier instructions and local access barrier instructions; When any RV processor core 0 performs a data memory access operation, the RV processor core 0 initiates a global access barrier instruction to the synchronization control module and waits for the initiated data memory access instruction to be executed; After the initiated data access instruction is executed, the RV processor core 0 sends a load reserve instruction to the lock allocation module; the load reserve instruction contains the starting address field of the accessed data; the lock allocation module allocates a lock address according to the aligned address range corresponding to the starting address field, and marks the lock address when the lock address allocation is successful; After the lock address is successfully allocated, RV processor core 0 sends a conditional store instruction to the lock allocation module. The lock allocation module determines whether the lock address is successfully applied based on whether the lock address in the conditional store instruction is marked. When the lock address is successfully applied, RV processor core 0 obtains the lock address. Before RV processor core 0 releases the lock address, the lock address is marked. Any RV processor core 1 cannot successfully apply for the lock address through the conditional store instruction. After the RV processor core 0 obtains the lock address, the RV processor core 0 sends a data access instruction corresponding to the lock address data to the synchronization control module. The synchronization control module transmits the data access instruction to the permission control module. When the preset requirements in the permission control module are met, the data access instruction is sent to the priority control module. Based on the priority of the RV processor core corresponding to each data access instruction, the priority control module sequentially sends the data access instructions to the block arbitration module. The block arbitration module determines the specific storage block to which the data access instruction is sent based on the access address in the data access instruction. When new data is added during the execution of the data access instruction, the new data is stored in a preset address; the preset address is within the lock address range. RV processor core 0 sends a local access barrier instruction containing the lock address to the synchronization control module, and waits through the local access barrier instruction for the data access instruction in the lock address range to be executed and releases the lock address; after the lock address is released, RV processor core 1 can successfully apply for the lock address through the conditional store instruction, and then can execute the data access operation of the data corresponding to the lock address.

3. The parallel storage method of data stream architecture according to claim 2, characterized in that: The barrier instruction includes: instruction distinguishing field, mode field, placeholder, rs1 field, and opcode field; Among them, the mode field represents the barrier type; When the mode field is 00, it corresponds to the barrier of global read and write memory access operations; When the mode field is 01, it corresponds to the barrier of the write memory access operation; When the mode field is 10, it corresponds to the barrier of the read memory operation; When the mode field is 11, it corresponds to the barrier for read and write memory access operations at the specific lock address; The rs1 field represents the lock address. In a barrier with mode 11, it is used to indicate the specific lock address range. The opcode field represents the instruction type and is used to distinguish extended instructions from RISC-V standard instructions.

4. The parallel storage method of data stream architecture according to claim 2, characterized in that: The load reserve instruction includes: instruction distinguishing field, rs1 field, rd field, aq field, rl field, placeholder, and opcode field; The rs1 field represents the starting address of the lock address; the rd field represents the lock allocation result. If the allocation is successful, the lock address is marked and returned. If the allocation fails, only the 0 address is returned. The aq field and rl field are memory access order control fields. Setting rl to 1 indicates that the memory access instruction before this instruction must be completed first, and setting aq to 1 indicates that the memory access instruction after this instruction must be completed later.

5. The parallel storage method of data stream architecture according to claim 2, characterized in that: The conditional store instruction includes: an instruction distinguishing field, an rs1 field, an rs2 field, an rd field, a placeholder, and an opcode field; Among them, the rs1 field represents the starting address of the lock address; the rs2 field represents the ending address of the lock address; The rd field represents the lock application result; if the load-hold instruction has marked the current lock address and no conditional store instruction other than the current RV processor core has applied for the lock address, the application is successful and returns a value of 0; if the load-hold instruction has not assigned the current lock address or the current lock address has been successfully applied for by a conditional store instruction of another RV processor core, the application fails and returns a non-zero value.

6. The parallel storage method of data stream architecture according to claim 2, characterized in that: The lock allocation module allocates a lock address based on the aligned address range corresponding to the start address field. When the lock address is allocated successfully, the lock address is marked. Specifically, the following steps are performed: By formula: , calculate the aligned address range ;in, is the original address, is the bit width of the original address, It is a 16-bit 0 address, used to fill the lower 16 bits of the address; for Assign a lock address; If the lock address is free, the lock address allocation is successful and the lock address will be marked; if the lock address is occupied, the lock address allocation fails.

7. The parallel storage method of data stream architecture according to claim 2, characterized in that: When the preset requirements in the permission control module are met, the data access instruction is sent to the priority control module, specifically including: Detect whether the address involved in the data access instruction is a preset legal address; When it is a preset legal address, the data access instruction is valid and meets the preset requirements in the authority control module; otherwise, the data access instruction is invalid and does not meet the preset requirements in the authority control module.

8. The parallel storage method of data stream architecture according to claim 2, characterized in that: Before determining the priority of the RV processor core corresponding to each data access instruction, the method further includes: Get the computational load of the RV processor core and determine the priority order of the RV processor core according to the computational load.

9. The parallel storage method of data stream architecture according to claim 2, characterized in that: The sector arbitration module determines the specific storage sector to which the data access instruction is issued based on the access address in the data access instruction, including: The sector arbitration module determines the specific storage sector to which the data access instruction is issued based on the storage sector where the access address in the data access instruction is located; When the access address in the data access instruction is located in the main memory, the corresponding data is moved to the storage block through the cache management module, and then the storage block where the data is moved is determined to be the specific storage block to which the data access instruction is issued; When the data access instruction is completed, the cache management module writes the data back to the main memory.

10. A non-volatile computer storage medium, characterized in that Computer instructions are stored thereon, and when the computer instructions are executed, they implement a parallel storage method of a data stream architecture as described in any one of claims 2 to 9.

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