High-speed camera trigger control device and method

Abstract

The invention provides a high-speed camera trigger control device and method, and is applied to the technical field of camera control. The equipment comprises a trigger threshold adjustment unit, a signal analysis and comparison unit and a camera trigger control and time service unit. The trigger threshold adjusting unit comprises an FPGA control chip and a DAC chip. The FPGA control chip responds to the threshold setting instruction to generate a threshold digital signal and generates a time frame in an ASCII format according to the IRIG-B time signal; the DAC chip generates a trigger threshold according to the threshold digital signal; the signal analysis and comparison unit generates TTL trigger signals when the target pulse signals meet a trigger threshold value, and the TTL trigger signals are used for triggering a plurality of high-speed cameras to carry out image acquisition; and the camera trigger control and time service unit adopts a coaxial cable to send TTL trigger signals to the plurality of high-speed cameras and adopts a twisted-pair cable to send time frames to the plurality of high-speed cameras. The method is suitable for synchronous trigger control and high-precision time synchronization of a plurality of high-speed cameras.

Description

Technical Field

[0001] The present application relates to the field of camera control technology, and in particular to a high-speed camera trigger control device and method. Background Art

[0002] A high-speed camera is a camera capable of shooting at a high frame rate (Frames Per Second, FPS). It can capture fast dynamic processes (such as fluid motion and mechanical vibrations), and is a core device for capturing transient physical processes. The operating efficiency of such a high-speed camera is highly dependent on precise trigger control and a unified time base. Current high-speed camera trigger control devices can capture high-speed moving or transient objects by precisely controlling the shooting timing of multiple high-speed cameras. They are widely used in scenarios requiring high temporal resolution and synchronous control. However, current high-speed camera trigger control devices cannot meet the triggering requirements of microsecond-level transient signals, and the timestamp deviations of multiple high-speed cameras are large, resulting in the inability of these multiple high-speed cameras to synchronously capture high-quality images.

[0003] Therefore, how to develop a high-speed camera trigger control device to meet the triggering requirements of microsecond-level transient signals and control multiple high-speed cameras to synchronously capture high-quality images has become the key to breaking through the bottleneck of collaborative acquisition and processing technology of multiple high-speed cameras. Summary of the Invention

[0004] The embodiments of the present application provide a high-speed camera trigger control device and method, which are suitable for the synchronous trigger control and high-precision time synchronization of multiple high-speed cameras, can meet the triggering requirements of microsecond-level transient signals and control multiple high-speed cameras to synchronously capture images with high quality.

[0005] The present application provides a high-speed camera trigger control device, comprising: a trigger threshold adjustment unit, a signal analysis and comparison unit, and a camera trigger control and timing unit; the trigger threshold adjustment unit comprises a field programmable gate array (FPGA) control chip and a digital-to-analog converter (DAC) chip configured via a serial peripheral interface (SPI); the FPGA control chip is connected to the DAC chip and the camera trigger control and timing unit, respectively; the DAC chip is connected to the signal analysis and comparison unit; and the signal analysis and comparison unit is connected to the camera trigger control and timing unit; The FPGA control chip is used to generate a threshold digital signal in response to a threshold setting instruction input by a user; and generate a time frame in the American Standard Code for Information Interchange ASCII format based on the received IRIG-B time signal of the Range Instrument Group Type B; The DAC chip is used to generate a trigger threshold according to the threshold digital signal; The signal analysis and comparison unit is used to generate a transistor-transistor logic (TTL) trigger signal when the target pulse signal meets the trigger threshold, and the TTL trigger signal is used to trigger multiple high-speed cameras to perform image acquisition; The camera trigger control and timing unit is used to send the TTL trigger signal to the multiple high-speed cameras using a coaxial cable, and to send the time frame to the multiple high-speed cameras using a twisted-pair cable.

[0006] According to an embodiment of the present application, a high-speed camera trigger control device further includes a trigger signal acquisition unit, which is connected to the signal analysis and comparison unit; the trigger signal acquisition unit includes a photoelectric coupler and a signal conditioning circuit; the signal conditioning circuit includes an amplifier circuit and a filter circuit, wherein the amplifier circuit is constructed by an operational amplifier, and the filter circuit is formed by connecting a capacitor in parallel to the amplifier circuit; the photoelectric coupler is connected to the amplifier circuit; and the amplifier circuit is connected to the filter circuit. The photoelectric coupler is used to receive a first pulse signal sent by a signal source through a bayonet coaxial connection BNC interface, and electrically isolate the first pulse signal to obtain a second pulse signal; The amplifier circuit is used to amplify the second pulse signal to obtain a third pulse signal; The filtering circuit is used to perform low-pass filtering on the third pulse signal to obtain the target pulse signal.

[0007] According to a high-speed camera trigger control device provided by an embodiment of the present application, the signal analysis and comparison unit includes a window comparison circuit constructed by a high-speed comparator, and the window comparison circuit supports a rising edge trigger mode and a falling edge trigger mode; the trigger threshold includes a first trigger threshold and a second trigger threshold, and the first trigger threshold is less than the second trigger threshold; When the window comparator circuit supports the rising edge trigger mode, the non-inverting terminal of the window comparator circuit is connected to the DAC chip, and the inverting terminal is connected to the trigger signal acquisition unit. The window comparator circuit is configured to generate the TTL trigger signal when the target pulse signal changes from being less than the first trigger threshold to reaching the second trigger threshold; When the window comparison circuit supports the falling edge trigger mode, the in-phase end of the window comparison circuit is connected to the trigger signal acquisition unit, and the inverting end is connected to the DAC chip. The window comparison circuit is used to generate the TTL trigger signal when the target pulse signal changes from being greater than the second trigger threshold to reaching the first trigger threshold.

[0008] According to the high-speed camera trigger control device provided in the embodiment of the present application, the FPGA control chip is used to generate a time frame in American Standard Code for Information Interchange (ASCII) format according to the received target range instrument group B type IRIG-B time signal, and the time frame includes: The FPGA control chip is specifically used to sample the IRIG-B time signal to obtain a time stamp, analyze the frame structure of the time stamp to obtain binary coded decimal (BCD) code time data, and convert the BCD code time data to generate the time frame in ASCII format.

[0009] According to the high-speed camera trigger control device provided in the embodiment of the present application, the camera trigger control and time service unit is built-in with a constant temperature crystal oscillator clock, and the FPGA control chip is built-in with a phase-locked loop (PLL). The FPGA control chip is specifically used to divide the constant temperature crystal oscillator clock by using the PLL to obtain a sampling clock, and sample the IRIG-B time signal according to the sampling clock to obtain the time stamp.

[0010] According to the high-speed camera trigger control device provided in the embodiment of the present application, the window comparison circuit is used to generate the TTL trigger signal, and includes: The window comparison circuit is specifically used to obtain a ramp signal of the target pulse signal with an edge rate less than a preset rate threshold, and generate the TTL trigger signal in a case where a duration of the ramp signal reaches a preset duration threshold.

[0011] According to the high-speed camera trigger control device provided in the embodiment of the present application, the window comparison circuit is built-in with a hysteresis comparison circuit. The hysteresis comparison circuit is used to set a hysteresis voltage of the target pulse signal through a positive feedback resistor network in a case where the window comparison circuit outputs a state flip in a case where the target pulse signal is greater than the second trigger threshold or less than the first trigger threshold.

[0012] According to the high-speed camera trigger control device provided in the embodiment of the present application, the power management unit includes an input stage, an intermediate stage and a terminal stage. The input stage is used to generate 12 VDC through a step-down module from 28 VDC. The intermediate stage is used to generate 5 VDC through a linear voltage regulator. The terminal stage is used to generate 3.3 VDC through a low dropout voltage regulator.

[0013] According to the high-speed camera trigger control device provided by the embodiment of the present application, the FPGA control chip is used to generate a threshold digital signal in response to a threshold setting instruction input by a user, and the threshold setting instruction includes: The FPGA control chip is specifically configured to receive the threshold setting instruction sent by the host computer, and generate the threshold digital signal, wherein the threshold setting instruction is generated by the host computer in response to an input operation of the user in a graphical threshold setting interface provided by the host computer. The threshold setting instruction input by the user in the graphical threshold setting interface provided by the host computer is used to generate the threshold digital signal.

[0014] The embodiment of the present application also provides a high-speed camera trigger control method, which is applied to the high-speed camera trigger control device described in any one of the above, and the high-speed camera trigger control device includes a trigger threshold adjustment unit, a signal analysis and comparison unit, and a camera trigger control and time service unit; the trigger threshold adjustment unit includes a field programmable gate array (FPGA) control chip and a digital-to-analog converter (DAC) chip configured through a serial peripheral interface (SPI); the FPGA control chip is connected with the DAC chip and the camera trigger control and time service unit respectively; the DAC chip is connected with the signal analysis and comparison unit; the signal analysis and comparison unit is connected with the camera trigger control and time service unit; the method includes the following steps: generating a threshold digital signal in response to a threshold setting instruction input by a user through the FPGA control chip; generating a time frame in American Standard Code for Information Interchange (ASCII) format according to a received target range instrument group B type IRIG-B time signal; generating a trigger threshold according to the threshold digital signal through the DAC chip; generating a transistor-transistor logic (TTL) trigger signal in a case where a target pulse signal meets the trigger threshold through the signal analysis and comparison unit, wherein the TTL trigger signal is used to trigger multiple high-speed cameras to perform image acquisition; and sending the TTL trigger signal to the multiple high-speed cameras through a coaxial cable and sending the time frame to the multiple high-speed cameras through a twisted pair cable through the camera trigger control and time service unit.

[0015] The embodiment of the present application also provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the high-speed camera trigger control method described above when executing the computer program.

[0016] The embodiment of the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the high-speed camera trigger control method described above.

[0017] The embodiment of the present application further provides a computer program product comprising a computer program which, when executed by a processor, implements the high-speed camera trigger control method.

[0018] The high-speed camera trigger control device and method provided by the embodiment of the present application, in the high-speed camera trigger control device, the FPGA control chip 1011 has multifunctionality and high efficiency, specifically, after responding to the threshold setting instruction, the FPGA control chip 1011 can generate a threshold digital signal and send the threshold digital signal to the DAC chip 1012, at the same time, after receiving the IRIG-B time signal, the FPGA control chip 1011 can process the IRIG-B time signal to obtain an ASCII format time frame, the resolution of the time frame is 1 millisecond (ms), and the time frame is sent to the camera trigger control and time service unit 103; then, the DAC chip 1012 generates a trigger threshold according to the threshold digital signal and sends the trigger threshold to the signal analysis and comparison unit 102; at this time, after receiving the trigger threshold and the target pulse signal, the signal analysis and comparison unit 102 determines whether the target pulse signal meets the trigger threshold, and if so, generates a TTL trigger signal and sends the TTL trigger signal to the camera trigger control and time service unit 103; after receiving the TTL trigger signal and the time frame, the camera trigger control and time service unit 103 can realize synchronous transmission of the TTL trigger signal and the time frame, specifically, the TTL trigger signal is sent to multiple high-speed cameras through a TTL trigger signal output channel, that is, a coaxial cable, to realize synchronous triggering, which can effectively shield external electromagnetic interference and prevent internal signals from radiating outward to cause interference, at the same time, the time frame is sent to the multiple high-speed cameras through an IRIG-B time decoding distribution channel, that is, a twisted pair cable, to realize synchronous time service, which can accurately and stably transmit the time frame signal with less signal distortion. The whole process can solve the time sequence consistency problem of multiple devices working together in a complex scene, that is, the synchronous triggering and synchronous time service problem of multiple high-speed cameras in a complex scene, wherein the whole synchronous time service process does not use an independent clock or simple pulse time service, but processes the received IRIG-B time signal through the FPGA control chip 1011 to obtain an ASCII format time frame and sends it to multiple high-speed cameras, so that the timestamp deviation of the multiple high-speed cameras is less than 50 ns, realizing sub-microsecond time synchronization accuracy, which can effectively improve the image sequence space-time calibration accuracy, that is, effectively improve the image quality of subsequent synchronous acquisition. That is, the high-speed camera trigger control device is suitable for synchronous trigger control and high-precision time synchronization of multiple high-speed cameras, which can meet the trigger demand of microsecond-level transient signals and control multiple high-speed cameras to synchronously acquire images with better quality. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 is a structural schematic diagram of a high-speed camera trigger control device provided by an embodiment of the application; Figure 2 is a structural schematic diagram of a high-speed camera trigger control device provided by an embodiment of the application; Figure 3 is a scene schematic diagram of connection of an FPGA control chip and a host computer provided by an embodiment of the application; Figure 4 is a structural schematic diagram of a signal analysis and comparison unit provided by an embodiment of the application; Figure 5 is a structural schematic diagram of a high-speed camera trigger control device provided by an embodiment of the application; Figure 6 is a scene schematic diagram of a three-level conversion architecture provided by an embodiment of the application; Figure 7 is a flow schematic diagram of a high-speed camera trigger control method provided by an embodiment of the application; Figure 8 is a whole architecture diagram of a high-speed camera trigger control method provided by an embodiment of the application; Figure 9 is a configuration flowchart of a trigger threshold curve provided by an embodiment of the application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the application clearer, the technical solutions in the application will be clearly and completely described below in combination with the drawings in the application. Obviously, the described embodiments are some embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0022] In order to better understand the embodiments of the application, the application scenarios of the high-speed camera trigger control device are described in detail first: Optionally, the application scenarios can include scientific research experiments, industrial detection, observation of transient physical phenomena, aerospace testing and other complex scenarios requiring high time resolution and synchronous control.

[0023] Among them, scientific research experiments refer to the use of high-speed camera trigger control equipment to control multiple high-speed cameras to conduct high-precision observation and analysis of dynamic processes under microscopic, macroscopic or extreme conditions in basic scientific research or applied technology development.

[0024] Industrial inspection refers to the use of high-speed camera trigger control equipment to control multiple high-speed cameras to perform non-contact inspection and quality control of high-speed moving parts or transient defects during the operation of production lines or industrial equipment.

[0025] Observation of transient physical phenomena refers to the use of high-speed camera trigger control equipment to control multiple high-speed cameras to perform high-temporal and spatial resolution observations of physical processes with extremely short duration (microseconds to nanoseconds) and drastic state changes.

[0026] Aviation testing refers to the use of high-speed camera trigger control equipment to control multiple high-speed cameras to perform high-precision verification and fault diagnosis of key components or system performance during the aircraft design, manufacturing, testing and flight test stages.

[0027] The following is a detailed description of the high-speed camera trigger control device provided in the embodiment of the present application: like Figure 1 The figure is one of the structural diagrams of the high-speed camera trigger control device provided in the embodiment of the present application. Figure 1 The high-speed camera trigger control device has high precision and high adaptability. The device may include a trigger threshold adjustment unit 101, a signal analysis and comparison unit 102, and a camera trigger control and timing unit 103. The trigger threshold adjustment unit 101 may include a field programmable gate array (FPGA) control chip 1011 and a digital-to-analog converter (DAC) chip 1012 configured via a serial peripheral interface (SPI). The FPGA control chip 1011 is connected to the DAC chip 1012 and the camera trigger control and timing unit respectively. The DAC chip 1012 is connected to the signal analysis and comparison unit 102. The signal analysis and comparison unit 102 is connected to the camera trigger control and timing unit 103. The FPGA control chip 1011 is configured to generate a threshold digital signal in response to a threshold setting instruction input by a user, and generate an American Standard Code for Information Interchange (ASCII) format time frame according to a received Inter-Range Instrumentation Group-B (IRIG-B) time signal. The DAC chip 1012 is configured to generate a trigger threshold according to the threshold digital signal. The signal analysis and comparison unit 102 is configured to generate a Transistor-Transistor Logic (TTL) trigger signal in a case where the target pulse signal meets the trigger threshold, and the TTL trigger signal is configured to trigger a plurality of high-speed cameras to perform image acquisition. The camera trigger control and time distribution unit 103 is configured to send the TTL trigger signal to the plurality of high-speed cameras by using a coaxial cable, and send the time frame to the plurality of high-speed cameras by using a twisted pair cable.

[0028] The trigger threshold adjustment unit 101 is a digital threshold generation circuit based on the FPGA control chip 1011 and the DAC chip 1012, supports dual-interface remote configuration of a Recommended Standard 485 (RS485) bus (such as a MODBUS bus protocol) and Ethernet (such as a Transmission Control Protocol (TCP) / Internet Protocol (IP)), and realizes a trigger threshold setting of 0 Volts Direct Current (VDC / V)-5V continuous adjustable.

[0029] The threshold digital signal refers to an output form of a pulse signal set by a user. Alternatively, the threshold digital signal can be a voltage digital signal or a current digital signal.

[0030] The IRIG-B time signal is a direct current level time synchronization signal based on an IRIG-B time code standard. That is, the IRIG-B time signal is an IRIG-B (DC) time signal.

[0031] The time frame is an RS485 time frame, and contains 7-bit time information of year / month / day / hour / minute / second / millisecond.

[0032] The trigger threshold refers to a critical value for triggering the image acquisition of multiple high-speed cameras. It should be noted that when the threshold digital signal is a voltage digital signal, the trigger threshold is a reference voltage signal, wherein the trigger threshold ranges from 0V to 5V, and the resolution of the trigger threshold can reach 1 millivolt (mV); when the threshold digital signal is a current digital signal, the trigger threshold is a reference current signal.

[0033] The target pulse signal refers to a specific pulse waveform signal that needs to be analyzed and compared, and usually has clear characteristic parameters (such as amplitude, width, and frequency). It should be noted that when the threshold digital signal is a voltage digital signal, the target pulse signal ranges from 0V to 10V.

[0034] The coaxial cable is a transmission line composed of an inner conductor, an insulating layer, an outer conductor (i.e., a shielding layer), and a sheath. The inner and outer conductors are arranged coaxially and used for transmission of high-frequency signals (i.e., TTL trigger signals).

[0035] The twisted pair cable is a cable composed of two independent wires without a shielding layer or simple shielding, and is usually used for transmission of low-frequency signals (i.e., time frames). The twisted pair cable can also be referred to as a twisted pair shielded wire.

[0036] Exemplarily, the FPGA control chip 1011 is an Xilinx Spartan-6.

[0037] Optionally, the DAC chip 1012 is a 16-bit DAC chip that supports a threshold update rate of 1000 times per second. For example, the DAC chip is AD5761 (16-bit).

[0038] Optionally, the resolution of the trigger threshold is less than a preset resolution threshold. For example, the preset resolution threshold is 10mV, which realizes a millivolt-level threshold adjustment resolution, so that the subsequent process can meet the trigger requirements of microsecond-level transient signals.

[0039] Optionally, the edge jitter of the TTL trigger signal is less than a preset jitter threshold. For example, the preset jitter threshold is 5 nanoseconds (ns), which realizes a subsequent nanosecond-level trigger response.

[0040] In the embodiment of the present application, the FPGA control chip 1011 has multifunctionality and high efficiency. Specifically, after responding to the threshold setting instruction, the FPGA control chip 1011 can generate a threshold digital signal and send the threshold digital signal to the DAC chip 1012. Meanwhile, after receiving the IRIG-B time signal, the FPGA control chip 1011 can process the IRIG-B time signal to obtain an ASCII format time frame, the resolution of the time frame being 1 millisecond (ms), and send the time frame to the camera trigger control and time service unit 103. Then, the DAC chip 1012 generates a trigger threshold according to the threshold digital signal and sends the trigger threshold to the signal analysis and comparison unit 102. At this time, after receiving the trigger threshold and the target pulse signal, the signal analysis and comparison unit 102 can compare the target pulse signal with the trigger threshold to determine whether to generate a TTL trigger signal. If the target pulse signal meets the trigger threshold, a TTL trigger signal is generated, otherwise, a new target pulse signal is continuously acquired until the final new target pulse signal meets the trigger threshold, and the finally generated TTL trigger signal is sent to the camera trigger control and time service unit 103. After receiving the TTL trigger signal and the above-mentioned time frame, the camera trigger control and time service unit 103 can realize synchronous transmission of the TTL trigger signal and the time frame. Specifically, the TTL trigger signal is sent to multiple high-speed cameras through a TTL trigger signal output channel, i.e., a coaxial cable, to realize synchronous triggering, which can effectively shield external electromagnetic interference and prevent internal signals from radiating outward to cause interference. Meanwhile, the time frame is sent to the multiple high-speed cameras through an IRIG-B time decoding distribution channel, i.e., a twisted pair cable, to realize synchronous time service, which can accurately and stably transmit the time frame signal with less signal distortion. The whole process can solve the timing consistency problem of multiple devices working together in a complex scene, i.e., solve the problems of synchronous triggering and synchronous time service of multiple high-speed cameras in a complex scene. In the whole synchronous time service process, an independent clock or a simple pulse time service is not used, but the FPGA control chip 1011 processes the received IRIG-B time signal to obtain an ASCII format time frame and sends it to multiple high-speed cameras, so that the timestamp deviation of the multiple high-speed cameras is less than 50 ns, sub-microsecond time synchronization accuracy is achieved, and the image sequence space-time calibration accuracy is effectively improved, i.e., the image quality of subsequent synchronous acquisition is effectively improved.

[0041] That is, the above-mentioned high-speed camera trigger control device is suitable for synchronous triggering control and high-precision time synchronization of multiple high-speed cameras.

[0042] It should be noted that in the process of sending TTL trigger signals to multiple high-speed cameras through the TTL trigger signal output channel, the camera trigger control and timing unit 103 can drive a 50Ω coaxial cable with a buffer (such as 74LVC1G17) to output a standard TTL trigger signal (3.3V / 5V optional) with an edge jitter of <5ns. The load capacity of the buffer is 50 milliamps (mA).

[0043] In the process of sending time frames to multiple high-speed cameras through the IRIG-B time decoding distribution channel, the camera trigger control and timing unit 103 can output RS485 time frames containing year / month / day / hour / minute / second / millisecond through a transceiver chip (such as ADM3485EARZ chip) through twisted shielded wire.

[0044] In some embodiments, as shown in Figure 2 Fig. 2 is a structural schematic diagram of a high-speed camera trigger control device provided by an embodiment of the application. In Figure 2 the high-speed camera trigger control device can further include a trigger signal acquisition unit 104, which is connected with the signal analysis and comparison unit 102; the trigger signal acquisition unit 104 can include an optoelectronic coupler 1041 and a signal conditioning circuit 1042; the signal conditioning circuit 1042 can include an amplification circuit 10421 and a filter circuit 10422, wherein the amplification circuit 10421 is constructed by an operational amplifier, and the filter circuit 10422 is formed after connecting a capacitor in parallel with the amplification circuit 10421; the optoelectronic coupler 1041 is connected with the amplification circuit 10421; the amplification circuit 10421 is connected with the filter circuit 10422; The optoelectronic coupler 1041 is configured to receive a first pulse signal sent by a signal source through a Bayonet Nut Connector (BNC) interface and electrically isolate the first pulse signal to obtain a second pulse signal. The amplification circuit 10421 is configured to amplify the second pulse signal to obtain a third pulse signal. The filter circuit 10422 is configured to low-pass filter the third pulse signal to obtain a target pulse signal 10421.

[0045] Optionally, the trigger signal acquisition unit 104 supports 50 ohm (Ω) / 1 mega (M)Ω input impedance switching and adapts to voltage type (such as 0.1V-10V) and current type (such as 4mA-20mA) trigger pulse signal input. That is, the trigger signal acquisition unit 104 supports BNC interface access to voltage type / current type trigger pulse signals, and configures input 50Ω impedance or 1MΩ impedance through a hardware dial switch to adapt to different sensor output characteristics and have input compatibility.

[0046] Optionally, the optocoupler 1041 (such as HCPL-063L) is a sensor having a response time less than a preset duration threshold, for example, 150 ns, enabling nanosecond-level precise control of the signal duration or event window.

[0047] Optionally, an operational amplifier (such as an AD8065 high-speed operational amplifier) ​​has a slew rate of 2000 V / μs. The AD8065 high-speed operational amplifier can be used to construct an amplifier circuit 10421 with a gain of ×10. In the amplifier circuit 10421, a first resistor R1 is 1 kilo-ohm (kΩ) and a second resistor R2 is 10 kΩ.

[0048] Optionally, filter circuit 10422 is formed by integrating a 100 nanofarad (nF) ceramic filter capacitor and a 50Ω matching resistor with amplifier circuit 10421, capable of achieving 10 MHz low-pass filtering. It should be noted that filter circuit 10422 is an RC low-pass filter, a passive filter composed of a resistor (R) and a capacitor (C). The core function of this RC low-pass filter is to allow low-frequency signals to pass while suppressing high-frequency signals, that is, to suppress high-frequency noise.

[0049] In an embodiment of the present application, the optocoupler 1041 is connected to a signal source. After the signal source sends an external pulse signal, i.e., a first pulse signal, to the optocoupler 104 through a BNC interface, the optocoupler 1041 can receive the first pulse signal through the BNC interface, and cooperate with the signal conditioning circuit 1042 to perform signal preprocessing processes such as electrical isolation, amplification, and filtering on the first pulse signal to obtain a target pulse signal with higher stability and accuracy. Specifically, the optocoupler 1041 electrically isolates the first pulse signal to achieve noise isolation, obtains a second pulse signal, and sends the second pulse signal to the amplifier circuit 10421. The second pulse signal is 0.1V-1V; after receiving the second pulse signal, the amplifier circuit 10421 amplifies the second pulse signal, enhances the amplitude of the second pulse signal, obtains a third pulse signal, and sends the third pulse signal to the filter circuit 10422. The third pulse signal is 1V-10V; after receiving the third pulse signal, the filter circuit 10422 performs low-pass filtering on the third pulse signal to filter out high-frequency interference and obtain the target pulse signal. This can achieve noise suppression and waveform optimization of the above-mentioned first pulse signal, ensure the stability and accuracy of the final target pulse signal, and provide a reliable data basis for subsequent signal analysis and processing. In addition, the above-mentioned target pulse signal has high compatibility and achieves wide-range input signal compatibility (voltage type / current type). The entire signal processing process has an intelligent anti-interference mechanism and can effectively adapt to complex environments.

[0050] Optionally, the trigger threshold adjustment unit 101 is connected to a host computer, and the trigger threshold adjustment unit 101 supports the software in the host computer to display a threshold-signal waveform dynamic curve in real time.

[0051] The above-mentioned host computer refers to a computer or embedded system that plays a dominant role and is responsible for overall monitoring and management in the automation control, data acquisition or equipment communication system.

[0052] The above threshold-signal waveform dynamic curve refers to the target pulse signal waveform and the trigger threshold curve.

[0053] Optionally, the software in the host computer is developed based on vs2012+C++, which has the advantages of high performance, low latency and direct hardware control.

[0054] Optionally, the host computer can set the hysteresis comparison parameters and set the hysteresis voltage adjustable from 50mV to 500mV, which can effectively avoid false triggering caused by critical signal jitter.

[0055] In some embodiments, as Figure 3 The figure is a schematic diagram of the scene where the FPGA control chip provided by the embodiment of the present application is connected to the host computer. Figure 3 In the embodiment, FPGA control chip 1011 is connected to a host computer via a communication converter. FPGA control chip 1011 is configured to generate a threshold digital signal in response to a threshold setting instruction input by a user. The FPGA control chip 1011 may include: FPGA control chip 1011 is specifically configured to receive a threshold setting instruction sent by the host computer and generate the threshold digital signal. The threshold setting instruction is generated by the host computer in response to a user input operation in a graphical threshold setting interface provided by the host computer.

[0056] Among them, the above-mentioned communication converter is an RS485 communication converter (such as MAX485), which is a chip used to realize the conversion between TTL level and RS485 differential signal. The core function of this RS485 communication converter is to support long-distance, multi-node and anti-interference serial communication requirements in industrial scenarios.

[0057] The above-mentioned graphical threshold setting interface is set in the software of the host computer, and can display the threshold-signal waveform dynamic curve in real time.

[0058] In the embodiment of the present application, the user can set the trigger threshold through the sliding bar of the trigger threshold curve in the graphical threshold setting interface. Specifically, the user can slide the sliding bar of the trigger threshold curve, and the upper computer responds to the input operation of sliding to generate a threshold setting instruction and send the threshold setting instruction to the FPGA control chip 1011. After receiving the threshold setting instruction, the FPGA control chip 1011 responds to the threshold setting instruction to extract the threshold information that the user wants to set, and generates a corresponding threshold digital signal for subsequent generation of a trigger threshold. The threshold information is 16-bit binary data.

[0059] In some embodiments, the FPGA control chip 1011, for generating a time frame in American Standard Code for Information Interchange (ASCII) format according to the received target instrument group B type IRIG-B time signal, can include: the FPGA control chip 1011 is specifically configured to sample the IRIG-B time signal to obtain a time stamp; analyze the frame structure of the time stamp to obtain binary-coded decimal (BCD) code time data; and convert the BCD code time data to generate a time frame in ASCII format.

[0060] In the embodiment of the present application, the signal conditioning is as follows: the BNC interface is supported to input the IRIG-B time signal, the amplitude of the IRIG-B time signal is 0.5V-10V, the built-in signal conditioning circuit realizes automatic switching between alternating current (AC) coupling and direct current (DC) coupling modes, and the IRIG-B time signal is matched to the voltage range that can be collected by the FPGA control chip 1011 through a voltage dividing resistor network. The FPGA control chip 1011 decodes the IRIG-B time signal as follows: the FPGA control chip 1011 internally integrates an IRIG-B decoding intellectual property (IP) core to realize time decoding with a precision of 1μs, specifically, first, the edge of the IRIG-B time signal is detected, that is, the IRIG-B time signal is high-speed sampled to identify the rising edge and falling edge of the pulse per second (1PPS) and time code data bit to obtain a time stamp; then, the frame synchronization of the time stamp is performed, that is, the frame structure of the time stamp is analyzed to extract the universal time code (UTC); and then, the UTC is decoded to obtain BCD code time data, and the BCD code time data is converted to generate a time frame in ASCII format containing millisecond resolution.

[0061] It should be noted that the specific content of signal conditioning is as follows: the IRIG-B time signal is input through the BNC interface, and the amplitude of the IRIG-B time signal is matched to about 1Vpp through a voltage division network composed of a resistor R1=51Ω and a resistor R2=499Ω, and is input to the high-speed ADC sampling channel or the input and output (Input Output, IO) pin of the FPGA control chip 1011, to realize automatic switching of AC coupling / DC coupling mode.

[0062] In some embodiments, the camera trigger control and the time service unit 103 are built-in with a constant temperature crystal oscillator clock; the FPGA control chip 1011 is built-in with a phase-locked loop (Phase-Locked Loop, PLL); the FPGA control chip 1011 is specifically used for sampling the IRIG-B time signal to obtain a time stamp, which can include: the FPGA control chip 1011 is specifically used for frequency division of the constant temperature crystal oscillator clock by using the PLL to obtain a sampling clock; and the IRIG-B time signal is sampled according to the sampling clock to obtain a time stamp.

[0063] Wherein, the constant temperature crystal oscillator clock is a 100MHz constant temperature crystal oscillator clock, which is used to maintain a 1μs / h time keeping accuracy when the external time signal is lost, and to ensure the time synchronization stability of multiple high-speed cameras in a complex electromagnetic environment.

[0064] Optionally, the frequency stability of the constant temperature crystal oscillator clock is ±0.1 parts per million (parts per million, ppm), which is used to quantify the deviation degree of the frequency source relative to the nominal value.

[0065] In the embodiments of the present application, the process of the FPGA control chip 1011 in decoding the IRIG-B time signal is as follows: first, time synchronization is performed on the IRIG-B time signal, that is, the constant temperature crystal oscillator clock is frequency-divided by using the PLL to obtain a 20MHz sampling clock, to realize high-speed sampling of the IRIG-B time signal; then, edge detection is performed on the sampled IRIG-B time signal, that is, the rising edge and the falling edge of the sampled IRIG-B time signal are detected by register delay sampling value, the time point of the edge occurrence is recorded, and a time stamp is obtained; then, frame analysis is performed on the time stamp, and UTC is obtained according to the frame format of the time stamp; then, the UTC is decoded to obtain BCD code time data, and the BCD code time data is converted to generate an ASCII format time frame.

[0066] Optionally, the frame format of the above timestamp is: one frame per second, containing 100 code elements, each code element width is 10ms, where code element 0 is 2ms high level + 8ms low level, code element 1 is 5ms high level + 5ms low level, and the synchronization code element is 8ms high level + 2ms low level.

[0067] Optionally, the BCD code time data includes information such as year, month, day, hour, minute, second and millisecond.

[0068] Optionally, the FPGA control chip 1011 may control a transceiver chip (such as an ADM3485 chip) to send the time frame to the camera trigger control and timing unit 103 via a Universal Asynchronous Receiver / Transmitter (UART) interface.

[0069] Optionally, the counter inside the FPGA control chip 1011 can realize frequency division and counting of the constant temperature crystal oscillator clock, generate a high-precision local time reference, and synchronize and calibrate with the IRIG-B time signal.

[0070] Optionally, when the camera trigger control and timing unit 103 sends a time frame to multiple high-speed cameras, it can distribute it to multiple high-speed cameras through a hub, with a synchronization accuracy of ≤50ns, a twisted pair cable length of ≤100m, and an automatic retransmission mechanism. That is, if the sending duration of the time frame reaches a preset sending duration threshold (such as 50ms), it means that multiple high-speed cameras have not confirmed receipt of the time frame. At this time, the time frame can be resent to these multiple high-speed cameras.

[0071] Optionally, the maximum number of high-speed cameras is 32.

[0072] In some embodiments, as Figure 4 FIG. 1 is a schematic diagram of the structure of the signal analysis and comparison unit provided in the embodiment of the present application. Figure 4 In the embodiment, the signal analysis and comparison unit 102 may include a window comparison circuit 1021 constructed by a high-speed comparator, and the window comparison circuit 1021 may support a rising edge trigger mode and a falling edge trigger mode; the trigger threshold includes a first trigger threshold and a second trigger threshold, and the first trigger threshold is less than the second trigger threshold; When the window comparator circuit 1021 supports the rising edge trigger mode, the non-inverting terminal of the window comparator circuit 1021 is connected to the DAC chip 1012, and the inverting terminal is connected to the trigger signal acquisition unit 104. The window comparator circuit 1021 is configured to generate a TTL trigger signal when the target pulse signal changes from being less than the first trigger threshold to reaching the second trigger threshold. When the window comparison circuit 1021 supports the falling edge trigger mode, the in-phase end of the window comparison circuit 1021 is connected to the trigger signal acquisition unit 104, and the inverting end is connected to the DAC chip 1012. The window comparison circuit 1021 is used to generate a TTL trigger signal when the target pulse signal changes from being greater than the second trigger threshold to reaching the first trigger threshold.

[0073] The propagation delay of the high-speed comparator (such as the LM319 comparator) is 20ms.

[0074] It should be noted that window comparator circuit 1021 provides real-time feedback via a status register on the slope of the target pulse signal and the duration of the slowly varying signal crossing the threshold. Furthermore, window comparator circuit 1021 supports configuration of trigger edge types and a 200ns adjustable delay to prevent false triggers, enabling the generation of highly accurate trigger instructions, namely TTL trigger signals. The slope of the target pulse signal is equivalent to the edge rate.

[0075] For example, taking the case where the window comparator circuit 1021 supports the rising edge trigger mode, when the voltage of the target pulse signal changes from less than the first trigger threshold to reaching the second trigger threshold, the window comparator circuit 1021 outputs a high-level TTL trigger signal.

[0076] For example, taking the case where the window comparator circuit 1021 supports the falling edge trigger mode, when the voltage of the target pulse signal changes from being greater than the second trigger threshold to reaching the first trigger threshold, the window comparator circuit 1021 outputs a low-level TTL trigger signal.

[0077] In the embodiment of the present application, during the comparison between the target pulse signal and the trigger threshold by window comparator circuit 1021, regardless of whether window comparator circuit 1021 supports rising-edge trigger mode or falling-edge trigger mode, a TTL trigger signal is generated when the target pulse signal meets the trigger threshold. After the drive capability of this TTL trigger signal is enhanced by a buffer (e.g., a 74LVC1G17 buffer), it is transmitted as a trigger instruction to the camera trigger control and timing unit 103. This entire data comparison process forms a complete signal discrimination logic chain, effectively ensuring that the trigger action is executed only when the target pulse signal meets the trigger threshold.

[0078] Optionally, the high-speed camera trigger control device adopts dynamic polarity configuration of the signal analysis and comparison unit 102 . Specifically, the polarity of the signal and threshold input to the signal analysis and comparison unit 102 is switched through an analog switch (ADG1419).

[0079] Wherein, the rising edge trigger mode: TTL trigger signal -> inverting terminal (-), trigger threshold -> non-inverting terminal (+); the falling edge trigger mode: TTL trigger signal -> non-inverting terminal (+), trigger threshold -> inverting terminal (-).

[0080] In some embodiments, the window comparison circuit 1021 for generating the TTL trigger signal can comprise: the window comparison circuit 1021, specifically configured to acquire the ramp signal with the edge rate of the target pulse signal being less than a preset rate threshold; and in a case where a duration of the ramp signal reaches a preset duration threshold, generate the TTL trigger signal.

[0081] Exemplarily, the preset rate threshold is 5V / μs; and the preset duration threshold is 200ns.

[0082] Optionally, for the ramp signal with the edge rate being less than 5V / μs, the FPGA control chip 1011 is internally provided with a timer, which can automatically start a 200ns adjustable anti-mis-touch delay function.

[0083] In the embodiments of the present application, in a case where the window comparison circuit 1021 outputs a state flip, the window comparison circuit 1021 can first acquire the ramp signal with the edge rate of the target pulse signal being less than the preset rate threshold, and since the edge rate of the ramp signal is less than the preset rate threshold, the FPGA control chip 1011 automatically starts the 200ns adjustable anti-mis-touch delay function, and judges whether the duration of the ramp signal reaches the preset duration threshold, and if the duration reaches the preset duration threshold, the window comparison circuit 1021 confirms valid triggering and generates the TTL trigger signal, which can effectively avoid mis-triggering of interference signals and ensure that only valid transient signals are responded to.

[0084] In some embodiments, the window comparison circuit 1021 is internally provided with a hysteresis comparison circuit 10211, and at this time, the window comparison circuit 1021 can be referred to as a hysteresis comparator. The hysteresis comparison circuit 10211 is configured to, in a case where the window comparison circuit outputs a state flip when the target pulse signal is greater than a second trigger threshold or less than a first trigger threshold, set a hysteresis voltage of the target pulse signal through a positive feedback resistance network.

[0085] Wherein, the positive feedback resistance network is also referred to as an adjustable resistance network, and the resistance R in the positive feedback resistance network is 100kΩ. The positive feedback resistance network is connected to the output end of the inverting terminal and the input end of the non-inverting terminal.

[0086] In the embodiment of the present application, in the case that the target pulse signal is greater than the second trigger threshold or less than the first trigger threshold, the high-speed comparator output signal jumps, i.e., the window comparison circuit 1021 outputs state flip, at this time, the hysteresis comparison circuit 10211 can set the hysteresis voltage of the target pulse signal through the positive feedback resistor network, which can effectively filter out the critical signal jitter.

[0087] Optionally, in the case that the hysteresis voltage is greater than the preset hysteresis voltage threshold, the FPGA control chip 1011 automatically closes the 200ns adjustable anti-mis-touch delay function; in the case that the hysteresis voltage is less than or equal to the preset hysteresis voltage threshold and the edge rate is less than the preset rate threshold, the FPGA control chip 1011 automatically starts the 200ns adjustable anti-mis-touch delay function.

[0088] Exemplarily, the preset hysteresis voltage threshold is 200mV.

[0089] In some embodiments, as Figure 5 Fig. 3 is a structure schematic diagram of a high-speed camera trigger control device provided by an embodiment of the present application. Figure 5 In the embodiment, the high-speed camera trigger control device can further include a power management unit 105; the power management unit 105 can include an input stage 1051, an intermediate stage 1052 and a terminal stage 1053. The input stage 1051 is configured to generate 12VDC through a voltage reduction module from 28VDC. The intermediate stage 1052 is configured to generate 5VDC through a linear voltage regulator. The terminal stage 1053 is configured to generate 3.3VDC through a low-dropout voltage regulator.

[0090] The power management unit 105 is responsible for providing stable power supply for the high-speed camera trigger control device, and the input voltage range of the power management unit 105 is 12VDC-36VDC, the conversion efficiency is ≥90%, and the output voltage ripple is ≤50μV (5VDC output end).

[0091] Specifically, the power management unit 105 uses a high-efficiency power conversion chip to convert the externally input power into different voltage levels required by each module (i.e., the trigger threshold adjustment unit 101, the signal analysis and comparison unit 102, the camera trigger control and timing unit 103 and the trigger signal acquisition unit 104).

[0092] In the embodiment of the present application, the power management unit 105 has a three-stage conversion architecture, i.e., including the input stage 1051, the intermediate stage 1052 and the terminal stage 1053. Figure 6Fig. 1 shows a schematic diagram of a three-stage conversion architecture according to an embodiment of the present application. In Figure 6 In the input of 28VDC, first, the overvoltage protection module (such as LT4363), that is, the transient voltage suppression diode (TVS) tube (such as SMBJ33A) surge protection, prevents the input voltage from exceeding the first preset safety threshold, protecting the subsequent circuit from overvoltage damage; then, the input stage 1051 uses a step-down module (such as LM5146) to convert 28VDC to 12VDC, wherein the 12VDC (output current 2A) is divided into three branch paths: in the 12VDC-5VDC conversion branch, the intermediate stage 1052 uses a linear voltage regulator to convert 12VDC to 5VDC (voltage ripple less than 50μV), and then passes through the 5VDC overcurrent protection module (such as INA226) to prevent the current from exceeding the second preset safety threshold, protecting the subsequent circuit; in the 12VDC-3.3VDC conversion branch, the terminal stage 1053 uses a low dropout regulator to convert 12VDC to 3.3VDC (quiescent current 1μA), and then passes through the 3.3VDC overcurrent protection module (such as INA219) for overcurrent protection; in the 12VDC overcurrent protection branch, the 12VDC is directly overcurrent protected. In this way, the three-stage conversion architecture has an intelligent protection mechanism, integrating an overcurrent detection chip (such as MAX4376, with a response time less than 10μs) and an overvoltage protection circuit (such as TL431), to achieve double hardware protection for input overvoltage (greater than 36VDC) and output overcurrent (greater than 2.5A). That is, the above three-stage conversion architecture (LM2596, LT1085, and XC6206) can provide 12VDC / 5VDC / 3.3VDC multi-voltage output, integrate an overvoltage and overcurrent protection circuit, and achieve double hardware protection. In addition, the terminal stage 1053 supports low-power operation of digital chips such as FPGA control chip 1011 / micro-controller unit (MCU).

[0093] In summary, the high-speed camera trigger control device provided by the embodiments of the present application can achieve nanosecond-level trigger response (edge jitter <5ns), millivolt-level threshold adjustment resolution (1mV), sub-microsecond-level time synchronization accuracy (≤50ns), and wide-range input signals (voltage type / current type).

[0094] Exemplarily, the high-speed camera trigger control device provided by the embodiment of the application is tested, and according to the test result, it can be known that the transmission delay of the TTL trigger signal is ≤8 ns (measured by an oscilloscope), the timestamp deviation of multiple high-speed cameras is less than 30 ns, and the synchronization shooting requirement of multiple high-speed cameras is met. The high-speed camera trigger control device realizes nanosecond-level trigger response, millivolt-level threshold resolution and microsecond-level time synchronization accuracy, flexibly decodes the IRIG-B time signal by using the programmable characteristics of the FPGA control chip 1011, and significantly improves the cooperative working performance of multiple high-speed cameras.

[0095] The high-speed camera trigger control method provided by the embodiment of the application is described in detail below, and the high-speed camera trigger control method described below can be correspondingly referred to the high-speed camera trigger control device described above.

[0096] Figure 7 is a flowchart of the high-speed camera trigger control method provided by the embodiment of the application. As shown in Figure 7 , the method is applied to the high-speed camera trigger control device of any one of the above, and the high-speed camera trigger control device includes a trigger threshold adjustment unit, a signal analysis and comparison unit, and a camera trigger control and time service unit; the trigger threshold adjustment unit includes a field programmable gate array (FPGA) control chip and a digital-to-analog converter (DAC) chip configured through a serial peripheral interface (SPI); the FPGA control chip is connected with the DAC chip and the camera trigger control and time service unit respectively; the DAC chip is connected with the signal analysis and comparison unit; the signal analysis and comparison unit is connected with the camera trigger control and time service unit; and the method can include the following steps 701-704.

[0097] Step 701, generating a threshold digital signal in response to a threshold setting instruction input by a user through the FPGA control chip; and generating an American Standard Code for Information Interchange (ASCII) format time frame according to a received target range instrument group B (IRIG-B) time signal.

[0098] Optionally, the high-speed camera trigger control device further comprises a trigger signal acquisition unit connected with the signal analysis and comparison unit; the trigger signal acquisition unit comprises a photoelectric coupler and a signal conditioning circuit; the signal conditioning circuit comprises an amplification circuit and a filter circuit, wherein the amplification circuit is constructed by an operational amplifier, and the filter circuit is formed after connecting a capacitor in parallel with the amplification circuit; the photoelectric coupler is connected with the amplification circuit; the amplification circuit is connected with the filter circuit; before step 701, the method can further comprise: receiving a first pulse signal sent by a signal source through a BNC interface connected with the photoelectric coupler through a bayonet coaxial connector, and electrically isolating the first pulse signal to obtain a second pulse signal; amplifying the second pulse signal through the amplification circuit to obtain a third pulse signal; and low-pass filtering the third pulse signal through the filter circuit to obtain a target pulse signal.

[0099] Optionally, the time frame in American Standard Code for Information Interchange (ASCII) format generated by the FPGA control chip according to the received target range instrument group B type IRIG-B time signal can comprise: sampling the IRIG-B time signal through the FPGA control chip to obtain a time stamp; analyzing the frame structure of the time stamp to obtain binary-coded decimal (BCD) code time data; and converting the BCD code time data to generate the time frame in ASCII format.

[0100] Optionally, the camera trigger control and time service unit is built-in with a constant temperature crystal oscillator clock; the FPGA control chip is built-in with a phase-locked loop (PLL); and sampling the IRIG-B time signal through the FPGA control chip to obtain a time stamp can comprise: frequency dividing the constant temperature crystal oscillator clock through the FPGA control chip using the PLL to obtain a sampling clock; and sampling the IRIG-B time signal according to the sampling clock to obtain the time stamp.

[0101] Step 702: generating a trigger threshold value through a DAC chip according to a threshold value digital signal.

[0102] Step 703: generating a transistor-transistor logic (TTL) trigger signal through the signal analysis and comparison unit in the case that the target pulse signal meets the trigger threshold value, the TTL trigger signal being used to trigger multiple high-speed cameras to perform image acquisition.

[0103] Optionally, the signal analysis and comparison unit comprises a window comparison circuit constructed by a high-speed comparator, the window comparison circuit supporting a rising edge trigger mode and a falling edge trigger mode; the trigger threshold value comprises a first trigger threshold value and a second trigger threshold value, the first trigger threshold value being smaller than the second trigger threshold value.

[0104] Optionally, the in-phase end of the window comparison circuit is connected with the DAC chip, and the anti-phase end is connected with the trigger signal acquisition unit; the TTL trigger signal is generated by the signal analysis and comparison unit when the target pulse signal meets the trigger threshold, and can include: the TTL trigger signal is generated by the window comparison circuit when the target pulse signal is from less than the first trigger threshold to reach the second trigger threshold.

[0105] Optionally, the in-phase end of the window comparison circuit is connected with the trigger signal acquisition unit, and the anti-phase end is connected with the DAC chip; the TTL trigger signal is generated by the signal analysis and comparison unit when the target pulse signal meets the trigger threshold, and can include: the TTL trigger signal is generated by the window comparison circuit when the target pulse signal is from greater than the second trigger threshold to reach the first trigger threshold.

[0106] Optionally, the TTL trigger signal is generated by the window comparison circuit, and can include: the window comparison circuit acquires a ramp signal of the target pulse signal with an edge rate less than a preset rate threshold; and the TTL trigger signal is generated when the duration of the ramp signal reaches a preset duration threshold.

[0107] Optionally, the window comparison circuit is built-in with a hysteresis comparison circuit; the method can include: the hysteresis comparison circuit is configured to set a hysteresis voltage of the target pulse signal by a positive feedback resistor network when the output state of the window comparison circuit is reversed when the target pulse signal is greater than the second trigger threshold or less than the first trigger threshold.

[0108] In step 704, the TTL trigger signal is sent to the multiple high-speed cameras by the camera trigger control and time service unit through a coaxial cable, and the time frame is sent to the multiple high-speed cameras through a twisted pair cable.

[0109] In the embodiments of the present application, the method can solve the time sequence consistency problem of multiple devices working together in a complex scene, that is, the synchronous triggering and synchronous time service problem of multiple high-speed cameras in a complex scene, wherein the entire synchronous time service process does not use an independent clock or a simple pulse time service, but the received IRIG-B time signal is processed by the FPGA control chip 1011 to obtain an ASCII format time frame and sent to multiple high-speed cameras, so that the timestamp deviation of the multiple high-speed cameras is less than 50ns, achieving sub-microsecond time synchronization accuracy, which can effectively improve the image sequence space-time calibration accuracy, that is, effectively improve the image quality of subsequent synchronous acquisition. That is, the above high-speed camera trigger control method is suitable for synchronous triggering control and high-precision time synchronization of multiple high-speed cameras, can meet the triggering demand of microsecond-level transient signals, and control multiple high-speed cameras to synchronously acquire images with better quality.

[0110] In order to better understand the high-speed camera trigger control method provided by the embodiments of the present application, the overall architecture diagram of the high-speed camera trigger control method is described in detail as follows: As shown in Figure 8 , it is the overall architecture diagram of the high-speed camera trigger control method provided by the embodiments of the present application. In Figure 8 , in the case of detecting the first pulse signal, the signal conditioning circuit is used to pretreat the first pulse signal to obtain a target pulse signal; then, the hysteresis comparator circuit compares the target pulse signal with a reference voltage to generate a digital signal, and sends the digital signal to the MCU; the MCU processes the received digital signal, adjusts the reference voltage through the digital potentiometer / DAC, sets the hysteresis voltage, and then transmits the hysteresis voltage to the upper computer through Ethernet or RS485; after receiving the hysteresis voltage, the upper computer can display the trigger threshold curve in real time and provide a user interface for interaction.

[0111] The configuration of the trigger threshold curve is described in detail as follows: As shown in Figure 9 , it is the configuration flowchart of the trigger threshold curve provided by the embodiments of the present application. In Figure 9 , from the start of the user starting the software, the user inputs a hysteresis voltage ranging from 0 to 500 millivolts to the software, which is used to set the trigger threshold to avoid frequent triggering caused by noise or slight fluctuations; then, the user selects a communication interface, such as RS485 or Ethernet; the upper computer encapsulates the hysteresis voltage according to the user-selected communication interface to obtain encapsulated instructions, specifically, if the communication interface is RS485, the encapsulation is performed according to a specific protocol (such as MODBUS bus protocol), and if the communication interface is Ethernet, the encapsulation is performed according to TCP / IP.

[0112] Then, the encapsulated instructions are sent according to the corresponding communication interface; the high-speed camera trigger control device receives the instructions and analyzes the instructions through the MCU to understand the user's operation intention. Further, the MCU determines the execution mode as a digital potentiometer or a DAC according to the analyzed instructions, specifically, if the execution mode is a digital potentiometer, the target resistance value is calculated and written into the register through SPI, that is, the MCU calculates the target resistance value that the digital potentiometer needs to set according to the input hysteresis voltage, and then writes the calculated target resistance value into the register of the digital potentiometer through SPI to adjust the resistance value of the potentiometer; if the execution mode is a DAC, the target voltage is calculated and output, that is, the MCU calculates the target voltage that the DAC needs to output according to the input hysteresis voltage, and the DAC converts the calculated target voltage into an analog voltage output. Regardless of the execution mode of the digital potentiometer or the DAC, the parameters of the comparator will be updated to set a new hysteresis voltage.

[0113] The high-speed camera trigger control device reads the current real-time state to confirm whether the parameter setting takes effect, and draws a trigger threshold curve according to the real-time state data, to intuitively show the trigger characteristics of the high-speed camera trigger control device, at this time, the high-speed camera trigger control device completes the configuration and can enter the normal working state.

[0114] The device embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0115] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software products, and the computer software products can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0116] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high-speed camera trigger control device, characterized in that: It includes a trigger threshold adjustment unit, a signal analysis and comparison unit, and a camera trigger control and timing unit; the trigger threshold adjustment unit includes a field programmable gate array (FPGA) control chip and a digital-to-analog converter (DAC) chip configured via a serial peripheral interface (SPI); the FPGA control chip is connected to the DAC chip and the camera trigger control and timing unit respectively; the DAC chip is connected to the signal analysis and comparison unit; and the signal analysis and comparison unit is connected to the camera trigger control and timing unit; The FPGA control chip is used to generate a threshold digital signal in response to a threshold setting instruction input by a user; and generate a time frame in the American Standard Code for Information Interchange ASCII format based on the received IRIG-B time signal of the Range Instrument Group Type B; The DAC chip is used to generate a trigger threshold according to the threshold digital signal; The signal analysis and comparison unit is used to generate a transistor-transistor logic (TTL) trigger signal when the target pulse signal meets the trigger threshold, and the TTL trigger signal is used to trigger multiple high-speed cameras to perform image acquisition; The camera trigger control and timing unit is used to send the TTL trigger signal to the multiple high-speed cameras using a coaxial cable, and to send the time frame to the multiple high-speed cameras using a twisted-pair cable.

2. The high-speed camera trigger control device according to claim 1, characterized in that: The system further includes a trigger signal acquisition unit, the trigger signal acquisition unit being connected to the signal analysis and comparison unit; the trigger signal acquisition unit including a photoelectric coupler and a signal conditioning circuit; the signal conditioning circuit including an amplifier circuit and a filter circuit, wherein the amplifier circuit is constructed by an operational amplifier, and the filter circuit is formed by connecting a capacitor in parallel to the amplifier circuit; the photoelectric coupler is connected to the amplifier circuit; and the amplifier circuit is connected to the filter circuit; The photoelectric coupler is used to receive a first pulse signal sent by a signal source through a bayonet coaxial connection BNC interface, and electrically isolate the first pulse signal to obtain a second pulse signal; The amplifier circuit is used to amplify the second pulse signal to obtain a third pulse signal; The filtering circuit is used to perform low-pass filtering on the third pulse signal to obtain the target pulse signal.

3. The high-speed camera trigger control device according to claim 2, characterized in that: The signal analysis and comparison unit includes a window comparison circuit constructed by a high-speed comparator, and the window comparison circuit supports a rising edge trigger mode and a falling edge trigger mode; the trigger threshold includes a first trigger threshold and a second trigger threshold, and the first trigger threshold is less than the second trigger threshold; When the window comparator circuit supports the rising edge trigger mode, the non-inverting terminal of the window comparator circuit is connected to the DAC chip, and the inverting terminal is connected to the trigger signal acquisition unit. The window comparator circuit is configured to generate the TTL trigger signal when the target pulse signal changes from being less than the first trigger threshold to reaching the second trigger threshold; When the window comparison circuit supports the falling edge trigger mode, the in-phase end of the window comparison circuit is connected to the trigger signal acquisition unit, and the inverting end is connected to the DAC chip. The window comparison circuit is used to generate the TTL trigger signal when the target pulse signal changes from being greater than the second trigger threshold to reaching the first trigger threshold.

4. The high-speed camera trigger control device according to claim 1, characterized in that: The FPGA control chip is used to generate a time frame in the American Standard Code for Information Interchange ASCII format based on the received IRIG-B time signal of the Range Instrument Group B, including: The FPGA control chip is specifically used to sample the IRIG-B time signal to obtain a timestamp; parse the frame structure of the timestamp to obtain binary-coded decimal BCD code time data; and convert the BCD code time data to generate the time frame in the ASCII format.

5. The high-speed camera trigger control device according to claim 4, characterized in that: The camera trigger control and timing unit has a built-in constant temperature crystal oscillator clock; the FPGA control chip has a built-in phase-locked loop (PLL); the FPGA control chip is specifically used to sample the IRIG-B time signal to obtain a timestamp, including: The FPGA control chip is specifically configured to use the PLL to divide the frequency of the oven controlled crystal oscillator clock to obtain a sampling clock; and sample the IRIG-B time signal according to the sampling clock to obtain the timestamp.

6. The high-speed camera trigger control device according to claim 3, characterized in that: The window comparison circuit is used to generate the TTL trigger signal, including: The window comparison circuit is specifically used to obtain a slowly varying signal whose edge rate of the target pulse signal is less than a preset rate threshold; and generate the TTL trigger signal when the duration of the slowly varying signal reaches a preset duration threshold.

7. The high-speed camera trigger control device according to claim 3, characterized in that: The window comparison circuit is equipped with a built-in hysteresis comparison circuit; The hysteresis comparison circuit is used to set the hysteresis voltage of the target pulse signal through a positive feedback resistor network when the output state of the window comparison circuit is reversed when the target pulse signal is greater than the second trigger threshold or less than the first trigger threshold.

8. The high-speed camera trigger control device according to any one of claims 1 to 5, characterized in that: Also included is a power management unit; the power management unit includes an input stage, an intermediate stage and a terminal stage; The input stage is used to generate 12VDC from 28VDC through a step-down module; The intermediate stage is used to generate 5VDC through a linear regulator; The terminal stage is used to generate 3.3VDC through a low dropout voltage regulator.

9. The high-speed camera trigger control device according to any one of claims 1 to 5, characterized in that: The FPGA control chip is used to respond to the threshold setting instruction input by the user and generate a threshold digital signal, including: The FPGA control chip is specifically configured to receive the threshold setting instruction sent by the host computer and generate the threshold digital signal, wherein the threshold setting instruction is generated by the host computer in response to the user's input operation in the graphical threshold setting interface provided by the host computer; The threshold digital signal is generated in response to a threshold setting instruction input by the user in a graphical threshold setting interface provided by the host computer.

10. A high-speed camera trigger control method, characterized in that: Applicable to the high-speed camera trigger control device according to any one of claims 1 to 9, the high-speed camera trigger control device comprising a trigger threshold adjustment unit, a signal analysis and comparison unit, and a camera trigger control and timing unit; the trigger threshold adjustment unit comprising a field programmable gate array (FPGA) control chip and a digital-to-analog converter (DAC) chip configured via a serial peripheral interface (SPI); the FPGA control chip being connected to the DAC chip and the camera trigger control and timing unit, respectively; and the DAC chip being connected to the signal analysis and comparison unit; The signal analysis and comparison unit is connected to the camera trigger control and timing unit; the method includes: The FPGA control chip responds to a threshold setting instruction input by a user to generate a threshold digital signal; and generates a time frame in the American Standard Code for Information Interchange ASCII format based on the received IRIG-B time signal of the Range Instrument Group Type B; Generate a trigger threshold value according to the threshold digital signal by the DAC chip; When the target pulse signal meets the trigger threshold, the signal analysis and comparison unit generates a transistor-transistor logic (TTL) trigger signal, wherein the TTL trigger signal is used to trigger multiple high-speed cameras to perform image acquisition; The camera trigger control and timing unit uses a coaxial cable to send the TTL trigger signal to the multiple high-speed cameras, and uses a twisted pair cable to send the time frame to the multiple high-speed cameras.

Images