Semiconductor structure including highly arranged

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a logic wafer; a first front surface redistribution layer (RDL) disposed over the logic wafer; a first memory die disposed over the first front redistribution layer; a second memory die disposed over the first front redistribution layer, where the first memory die and the second memory die are arranged horizontally; and a first interconnect die disposed over the first front redistribution layer between the first memory die and the second memory die, where the first memory die is electrically connected to a first via in the first interconnect die, the second memory die is electrically connected to a second via in the first interconnect die. The invention also provides a preparation method of the semiconductor structure.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 624,371 (i.e., the priority date is "April 2, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure, and more particularly to a semiconductor structure including horizontally arranged memory grains and a method for manufacturing the semiconductor structure. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and patterning these layers using lithography to form circuit components and devices. As the semiconductor industry advances to advanced technology process nodes, the pursuit of greater device density, higher performance, and lower costs has led to the challenge of increasing performance without increasing size.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a logic wafer; a first front-side redistribution layer disposed above the logic wafer; a first memory die disposed above the first front-side redistribution layer; a second memory die disposed above the first front-side redistribution layer, wherein the first memory die and the second memory die are arranged horizontally; and a first interconnect die disposed above the first front-side redistribution layer between the first memory die and the second memory die, wherein the first memory die is electrically connected to a first via in the first interconnect die, and the second memory die is electrically connected to a second via in the first interconnect die.

[0006] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first reconstituted wafer disposed above a logic wafer, and a second reconstituted wafer disposed vertically above the first reconstituted wafer. The first reconstituted wafer includes a first front side redistribution layer, a first memory die disposed above the first front side redistribution layer, a second memory die disposed above the first front side redistribution layer, wherein the second memory die is horizontally aligned with the first memory die, and a first interconnect die disposed above the first front side redistribution layer and between the first memory die and the second memory die. The second reconstituted wafer includes a second front side redistribution layer, a third memory die disposed above the second front side redistribution layer, wherein a thickness of the third memory die is substantially greater than a thickness of the first memory die, and a fourth memory die disposed above the second front side redistribution layer and adjacent to the third memory die, wherein a thickness of the fourth memory die is substantially greater than a thickness of the second memory die.

[0007] Another embodiment of the present disclosure provides a method of fabricating a semiconductor structure. The method includes a plurality of steps. A first reconstituted wafer is formed. A second reconstituted wafer is formed. The first reconstituted wafer is disposed above a logic wafer. The second reconstituted wafer is disposed above the first reconstituted wafer. The formation of the first reconstituted wafer includes a plurality of steps. A first memory die, a first interconnect die, and a second memory die are disposed above a first carrier substrate. A first molding material layer is formed above the first carrier substrate and around the first memory die, the first interconnect die, and the second memory die. A first back side redistribution layer is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die. A first front side redistribution layer is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die opposite the first back side redistribution layer, thereby forming the first reconstituted wafer. The formation of the second reconstituted wafer includes a plurality of steps. A third memory die, a second interconnect die, and a fourth memory die are disposed above a second carrier substrate. A second molding material layer is formed above the second carrier substrate and around the third memory die, the second interconnect die, and the fourth memory die. A second front side redistribution layer is formed above the second molding material layer, the third memory die, the second interconnect die, and the fourth memory die, thereby forming the second reconstituted wafer.

[0008] The foregoing has outlined rather broadly the technical features of the technology of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure can best be understood by referring to the following detailed description of one or more embodiments of the present disclosure given by way of example only, which is made with reference to the accompanying drawings. The present disclosure is not limited in scope by the illustrative examples as can be diverged from the spirit or scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0009] A more complete understanding of the present disclosure can be obtained by reference to the following detailed description when taken in conjunction with the drawings, wherein:

[0010] Figure 1 is a cross-sectional schematic view illustrating a semiconductor structure of some embodiments of the present disclosure.

[0011] Figures 2 to 19 is a cross-sectional schematic view illustrating different stages of a method of fabricating a semiconductor structure of some embodiments of the present disclosure.

[0012] Figure 20 is a cross-sectional schematic view illustrating a semiconductor structure of some embodiments of the present disclosure.

[0013] Figure 21 is a cross-sectional schematic view illustrating a semiconductor structure of some embodiments of the present disclosure.

[0014] Figure 22 is a cross-sectional schematic view illustrating a reconstituted wafer of some embodiments of the present disclosure.

[0015] Figure 23 is a cross-sectional schematic view illustrating a reconstituted wafer of some embodiments of the present disclosure.

[0016] Figure 24 is a cross-sectional schematic view illustrating a semiconductor structure of some embodiments of the present disclosure.

[0017] Figure 25 is a cross-sectional schematic view illustrating a semiconductor package structure of some embodiments of the present disclosure.

[0018] Figure 26 is a flowchart illustrating a method of fabricating a semiconductor structure of some embodiments of the present disclosure.

[0019] Figure 27 is a flowchart illustrating operational steps of a method of fabricating a semiconductor structure of some embodiments of the present disclosure.

[0020] Figure 28is a flowchart illustrating operational steps of a method of fabricating a semiconductor structure in accordance with some embodiments of the present disclosure.

[0021] Wherein the reference numerals are explained as follows:

[0022] 1 : Semiconductor structure

[0023] 1 A: Reconstituted wafer

[0024] 1 B: Reconstituted wafer

[0025] 1 C: Reconstituted wafer

[0026] 1 D: Reconstituted wafer

[0027] 2: Semiconductor structure

[0028] 2A: Reconstituted wafer

[0029] 2B: Reconstituted wafer

[0030] 2C: Reconstituted wafer

[0031] 2D: Reconstituted wafer

[0032] 3: Semiconductor structure

[0033] 3A: Reconstituted wafer

[0034] 3B: Reconstituted wafer

[0035] 3C: Reconstituted wafer

[0036] 3D: Reconstituted wafer

[0037] 4: Semiconductor structure

[0038] 4A: Reconstituted wafer

[0039] 6A: Logic wafer

[0040] 6B: Interposer

[0041] 10: Intermediate wafer

[0042] 11 : Base layer

[0043] 12: Interconnect structure

[0044] 20: Intermediate wafer

[0045] 21 : Base layer

[0046] 22: Through-hole structure

[0047] 22a: Through-hole structure

[0048] 22B: Bottom

[0049] 25: Backside through-hole structure

[0050] 31: base layer

[0051] 32: interconnect structure

[0052] 41: layer of molding material

[0053] 41B: upper surface

[0054] 41a: layer of molding material

[0055] 41b: layer of molding material

[0056] 41c: layer of molding material

[0057] 41d: layer of molding material

[0058] 42: layer of molding material

[0059] 51: bonding layer

[0060] 52: bonding layer

[0061] 53: bonding layer

[0062] 61: front redistribution layer

[0063] 61a: front redistribution layer

[0064] 61b: front redistribution layer

[0065] 61c: front redistribution layer

[0066] 61d: front redistribution layer

[0067] 62: conductive bump

[0068] 63: back redistribution layer

[0069] 63b: back redistribution layer

[0070] 63c: back redistribution layer

[0071] 63d: back redistribution layer

[0072] 64: conductive bump

[0073] 65: front redistribution layer

[0074] 67: back redistribution layer

[0075] 101: first memory die

[0076] 101A: front surface

[0077] 101B: back surface

[0078] 101a: first memory die

[0079] 101b: first memory die

[0080] 101c: first memory die

[0081] 101d: first memory die

[0082] 102: interconnect die

[0083] 102A: front surface

[0084] 102B: back surface

[0085] 102a: interconnect die

[0086] 102b: interconnect die

[0087] 102c: interconnect die

[0088] 102d: interconnect die

[0089] 103: second memory die

[0090] 103A: front surface

[0091] 103B: back surface

[0092] 103a: second memory die

[0093] 103b: second memory die

[0094] 103c: second memory die

[0095] 103d: second memory die

[0096] 120B: back surface

[0097] 121: intermetal dielectric structure

[0098] 123: conductive element

[0099] 321: intermetal dielectric structure

[0100] 323: conductive element

[0101] 611: intermetal dielectric structure

[0102] 612: metal via

[0103] 613: metal line

[0104] 631: intermetal dielectric structure

[0105] 633: metal line

[0106] 651: intermetal dielectric structure

[0107] 652: metal via

[0108] 653: metal line

[0109] 654: conductive segment

[0110] 671: intermetal dielectric structure

[0111] 673: metal line

[0112] 674: conductive segment

[0113] C1: carrier substrate

[0114] C2: carrier substrate

[0115] C3: carrier substrate

[0116] P1: planar surface

[0117] P2: planar surface

[0118] S1: method of manufacture

[0119] S11: step

[0120] S12: step

[0121] S13: step

[0122] S14: step

[0123] S111: step

[0124] S112: step

[0125] S113: step

[0126] S114: step

[0127] S121: step

[0128] S122: step

[0129] S123: step

[0130] T111: thickness

[0131] T112: thickness

[0132] T113: thickness

[0133] T114: thickness

[0134] T211: thickness

[0135] T212: thickness

[0136] T213: thickness

[0137] T214: thickness

[0138] T221: Depth

[0139] T311: thickness

[0140] T312: Thickness

[0141] T313: Thickness

[0142] T314: thickness

[0143] X: Direction

[0144] Y: direction DETAILED DESCRIPTION

[0145] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0146] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0147] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0148] Figure 1 1 is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. The semiconductor structure 1 is a stacked structure or a packaged structure and includes a plurality of reconstructed wafers 1A, 1B, 1C, and 1D vertically stacked on a logic wafer 6A. It should be understood that although Figure 1 The semiconductor structure 1 shown includes four reconstituted wafers (including reconstituted wafers 1A, 1B, 1C, and 1D) positioned above the logic wafer 6A. However, this configuration is merely an exemplary embodiment for illustrative purposes. In other embodiments, more or fewer reconstituted wafers may be positioned above the logic wafer 6A, and the number of reconstituted wafers is not limited.

[0149] Logic wafer 6A may include multiple electronic components for processing information to complete a task. In some embodiments, logic wafer 6A may have a multi-layer structure, or logic wafer 6A may include a multi-layer compound semiconductor structure. In some embodiments, logic wafer 6A includes semiconductor devices, electronic components, electronic elements, or a combination thereof. In some embodiments, logic wafer 6A includes transistors or functional units of transistors. In some embodiments, logic wafer 6A includes active components, passive components, and / or conductive components. Electronic components may include planar transistors, multi-gate transistors, gate-all-around field-effect transistors (GAAFETs), fin field-effect transistors (FinFETs), vertical transistors, nanosheet transistors, nanowire transistors, passive components, capacitors, or a combination thereof for performing various functions. Active components may include logic dies (e.g., system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) dies, sensor dies, microelectromechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), or other active components. Passive components may include capacitors, resistors, inductors, fuses, or other passive components.

[0150] The active and / or passive components described above can be formed in and / or over a semiconductor substrate. The semiconductor substrate can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate can include an elemental semiconductor comprising silicon or germanium in single crystal, polycrystalline, or amorphous form; a compound semiconductor material comprising at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate can be a SiGe alloy having a gradient Si:Ge feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy.

[0151] The logic wafer 6A also includes an interconnect structure disposed above the semiconductor substrate and the active element. In some embodiments, the interconnect structure is located at a front surface of the semiconductor substrate. The interconnect structure may include a plurality of conductive elements configured into multiple layers. The conductive elements may include metal lines, metal islands, conductive vias, contacts or other conductive elements. In some embodiments, the interconnect structure includes a plurality of metal wire layers. The interconnect structure may also include a plurality of metal via layers, alternately disposed between the metal wire layers, for electrical connection between the metal wire layers. In some embodiments, each metal wire layer includes a plurality of metal wires and an intermetallic dielectric (IMD) layer surrounding the metal wires. In some embodiments, each metal via layer includes a plurality of metal vias and an intermetallic dielectric layer surrounding the metal vias.

[0152] The logic wafer 6A may also include a plurality of backside via structures 25 extending from the backside of the semiconductor substrate of the logic wafer 6A for electrically connecting to active or passive components formed on the semiconductor substrate. In some embodiments, the logic wafer 6A also includes a plurality of conductive bumps 64 located on the backside of the semiconductor substrate for electrically connecting to another wafer, substrate, die, or chip. In other embodiments, the conductive bumps 64 may be in the form of pads, balls, or segments. The configuration of the conductive bumps 64 is not limited.

[0153] Each reconstituted wafer 1A, 1B, 1C, and 1D can include two horizontally arranged memory dies and an interconnect die horizontally arranged between the two memory dies. In some embodiments, reconstituted wafer 1A is a top reconstituted wafer in the stack of reconstituted wafers 1A, 1B, 1C, and 1D. In some embodiments, reconstituted wafer 1D is a reconstituted wafer closest to logic wafer 6A in the stack of reconstituted wafers 1A, 1B, 1C, and 1D.

[0154] Reconstituted wafer 1A can include a first memory die 101a, an interconnect die 102a, a second memory die 103a, a front side redistribution layer (RDL) 61a, and a molding material layer 41a. In some embodiments, first memory die 101a, interconnect die 102a, and second memory die 103a are horizontally arranged above front side redistribution layer 61a. In some embodiments, interconnect die 102a is disposed between first memory die 101a and second memory die 103a. In some embodiments, molding material layer 41a is disposed above front side redistribution layer 61a. In some embodiments, molding material layer 41a surrounds each of first memory die 101a, interconnect die 102a, and second memory die 103a. In some embodiments, first memory die 101a and interconnect die 102a are separated by molding material layer 41a. In some embodiments, second memory die 103a and interconnect die 102a are separated by molding material layer 41a.

[0155] Reconstituted wafers 1A, 1B, 1C, and 1D can have similar structures. For ease of illustration and ease of understanding, the number preceding each element number represents the function, and different reconstituted wafers 1A, 1B, 1C, and 1D have similar or identical functions. Similarly, the letter (a, b, c, etc.) after the number of each element number indicates which reconstituted wafer 1A, 1B, 1C, or 1D the element belongs to. For example, reconstituted wafer 1B includes a first memory die 101b, an interconnect die 102b, a second memory die 103b, a front side redistribution layer 61b, and a molding material layer 41b; reconstituted wafer 1C includes a first memory die 101c, an interconnect die 102c, a second memory die 103c, a front side redistribution layer 61c, and a molding material layer 41c; and reconstituted wafer 1D includes a first memory die 101d, an interconnect die 102d, a second memory die 103d, a front side redistribution layer 61d, and a molding material layer 41d.

[0156] The first memory die 101b, the interconnect die 102b, the second memory die 103b, the front side redistribution layer 61b, and the molding material layer 41b can be similarly configured as the first memory die 101a, the interconnect die 102a, the second memory die 103b, the front side redistribution layer 61b, and the molding material layer 41b. Similarly, the first memory die 101c, the interconnect die 102c, the second memory die 103c, the front side redistribution layer 61c, and the molding material layer 41c can be configured by referring to the configuration of the first memory die 101a, the interconnect die 102c, the second memory die 103c, the front side redistribution layer 61c, and the molding material layer 41c; and the first memory die 101d, the interconnect die 102d, the second memory die 103d, the front side redistribution layer 61d, and the molding material layer 41d can be configured by referring to the configuration of the first memory die 101a, the interconnect die 102a, the second memory die 103a, the front side redistribution layer 61a, and the molding material layer 41a. Repetitive descriptions are omitted here.

[0157] To electrically connect to another reconstituted die 1A, 1B, or 1C, each of the reconstituted dies 1B, 1C, and 1D also includes a back side redistribution layer 63b, 63c, and 63d, respectively. In some embodiments, the back side redistribution layer 63d is disposed over the first memory die 101d, the interconnect die 102d, and the second memory die 103d. In some embodiments, the back side redistribution layer 63d covers the molding material layer 41d. In some embodiments, the back side redistribution layer 63d is bonded to the front side redistribution layer 61c. In some embodiments, the back side redistribution layer 63c is disposed over the first memory die 101c, the interconnect die 102c, and the second memory die 103c. In some embodiments, the back side redistribution layer 63c covers the molding material layer 41c. In some embodiments, the back side redistribution layer 63c is bonded to the front side redistribution layer 61b. In some embodiments, the back side redistribution layer 63b is disposed over the first memory die 101b, the interconnect die 102b, and the second memory die 103b. In some embodiments, the back side redistribution layer 63b covers the molding material layer 41b. In some embodiments, the back side redistribution layer 63b is bonded to the front side redistribution layer 61a.

[0158] Semiconductor structure 1 may further include a molding material layer 42 surrounding reconstructed wafers 1A, 1B, 1C, and 1D. In some embodiments, molding material layer 42 fills a space between reconstructed wafers 1A and 1B. In some embodiments, molding material layer 42 fills a space between reconstructed wafers 1B and 1C. In some embodiments, molding material layer 42 fills a space between reconstructed wafers 1C and 1D. In some embodiments, molding material layer 42 fills a space between reconstructed wafer 1D and logic wafer 6A. In some embodiments, an upper surface of molding material layer 42 is substantially aligned with an upper surface of reconstructed wafer 1A. In some embodiments, an upper surface of molding material layer 42 and an upper surface of reconstructed wafer 1A are substantially coplanar.

[0159] Figures 2 to 19 2 is a schematic cross-sectional view illustrating different stages of a method for preparing a semiconductor structure 1 according to some embodiments of the present disclosure.

[0160] Please refer to Figure 2 A first memory die 101, an interconnect die 102, and a second memory die 103 are disposed above a carrier substrate C1. The carrier substrate C1 is used for handling and support purposes during the manufacturing process. In some embodiments, the first memory die 101 is separate from and adjacent to the interconnect die 102. In some embodiments, the second memory die 103 is disposed on a side of the interconnect die 102 opposite the first memory die 101. In some embodiments, the second memory die 103 is separate from and adjacent to the interconnect die 102. In some embodiments, a bonding layer 51 is disposed above the carrier substrate C1. In some embodiments, the first memory die 101 is attached to the carrier substrate C1 via the bonding layer 51. In some embodiments, the interconnect die 102 is attached to the carrier substrate C1 via the bonding layer 51. In some embodiments, the second memory die 103 is attached to the carrier substrate C1 via the bonding layer 51.

[0161] The first memory die 101 may include a base layer 11 and an interconnect structure 12 disposed on a front surface of the base layer 11. The base layer 11 may be a semiconductor substrate similar to the logic wafer 6A described above. In some embodiments, a plurality of memory cells (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.) are formed on the base layer 11. The interconnect structure 12 includes a plurality of conductive elements 123 and an intermetallic dielectric structure 121 surrounding the conductive elements 123. The conductive elements 123 may be divided into a plurality of metal wire layers and a plurality of metal via layers alternately arranged with the metal wire layers, and the intermetallic dielectric structure 121 may include a plurality of intermetallic dielectric layers. For simplicity, the details of the interconnect structure 12 are not shown in the figure. The interconnect structure 12 may be similar to the above-mentioned redistribution layer 61a and will not be described again here.

[0162] The second memory die 103 may be similar to the first memory die 101. The second memory die 103 may include a base layer 31 and an interconnect structure 32 disposed on the front surface of the base layer 31. The base layer 31 may be a semiconductor substrate similar to the logic wafer 6A described above. In some embodiments, a plurality of memory cells (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.) are formed on the base layer 31. The interconnect structure 32 includes a plurality of conductive elements 323 and an intermetallic dielectric structure 321 surrounding the conductive elements 323. The conductive elements 323 may be divided into a plurality of metal wire layers and a plurality of metal via layers alternately arranged with the metal wire layers, and the intermetallic dielectric structure 321 may include a plurality of intermetallic dielectric layers. For simplicity, the details of the interconnect structure 32 are not shown in the figure. The interconnect structure 32 may be similar to the redistribution layer 61a described above, and repeated description is omitted here.

[0163] The interconnect die 102 may include a base layer 21 and a plurality of via structures 22 disposed in the base layer 21. In some embodiments, the base layer 21 comprises a bulk semiconductor base. In some embodiments, the base layer 21 comprises silicon or germanium in single crystal or polycrystalline form. Each via structure 22 extends from a front surface 102A of the base layer 21 to a rear surface 102B of the base layer 21. In some embodiments, the via structure 22 is exposed at the front surface 102A. In some embodiments, the via structure 22 terminates within the base layer 21. In some embodiments, the via structure 22 is separated from the rear surface 120B of the base layer 21.

[0164] It should be understood that the fabrication technology for the via structure 22 may include a front-end-of-line (FEOL) semiconductor manufacturing process (also referred to as an FEOL process). Therefore, compared to other types of via structures, such as a through-mold via structure or a through-dielectric via structure formed by a back-end-of-line (BEOL) semiconductor manufacturing process (also referred to as a BEOL process), the size and quality of the via structure 22 can be effectively controlled. In some embodiments, a depth T221 of the via structure 22 measured from the front surface 102A of the base layer 21 is in a range of 30 to 70 micrometers (μm).

[0165] In some embodiments, at this stage, a thickness T111 of the substrate 11 of the first memory die 101 is substantially equal to a thickness T311 of the substrate layer 31 of the second memory die 103. In some embodiments, thickness T111 or thickness T311 is in a range of 500 μm to 750 μm. In some embodiments, a thickness T211 of the substrate layer 21 of the interconnect die 102 is substantially greater than or equal to thickness T111 or thickness T311. In some embodiments, thickness T211 is in a range of 500 to 750 μm.

[0166] Please refer to Figure 3 A molding material layer 41 is formed over the carrier substrate C1. The molding material layer 41 covers the first memory die 101, the interconnect die 102, and the second memory die 103. In some embodiments, the molding material layer 41 fills a space between the first memory die 101 and the interconnect die 102. In some embodiments, the molding material layer 41 fills a space between the second memory die 103 and the interconnect die 102. In some embodiments, the molding material layer 41 covers a front surface of the carrier substrate C1, wherein the front surface of the carrier substrate C1 faces the first memory die 101, the interconnect die 102, and the second memory die 103. In some embodiments, the molding material layer 41 contacts the bonding layer 51.

[0167] Please refer to Figure 4 , performing a grinding operation. In some embodiments, an upper portion of the molding material layer 41 above the first memory die 101, the interconnect die 102, and the second memory die 103 is removed by the grinding operation. The grinding operation is to planarize and expose the first memory die 101, the interconnect die 102, and the second memory die 103. The thicknesses T111, T211, and T311 of the base layers 11, 21, and 31 of the first memory die 101, the interconnect die 102, and the second memory die 103, respectively, may or may not be reduced by the grinding operation, as long as the rear surfaces 101B, 102B, and 103B of the base layers 11, 21, and 31, respectively, are exposed and a flat surface P1 is obtained after grinding. However, to ensure exposure of each of the first memory die 101, the interconnect die 102, and the second memory die 103, it is preferred to remove each surface portion of the base layers 11, 21, and 31 of the first memory die 101.

[0168] In some embodiments, a surface portion of the base layer 11 of the first memory die 101 is removed by a grinding operation. In some embodiments, the thickness of the base layer 11 of the first memory die 101 is reduced from a thickness T111 (e.g., Figure 3 In some embodiments, a surface portion of the base layer 21 of the interconnect die 102 is removed by a grinding operation. In some embodiments, the thickness of the base layer 21 of the interconnect die 102 is reduced from a thickness of T211 (as shown in FIG. 1 ) to a thickness of T112. Figure 3 In some embodiments, a surface portion of the base layer 31 of the second memory die 103 is removed by a grinding operation. In some embodiments, the thickness of the base layer 31 of the second memory die 103 is reduced from a thickness of T311 (as shown in FIG. 1 ) to a thickness of T212. Figure 3 as shown) is reduced to a thickness T312.

[0169] The thickness T112 of the substrate 11 of the first memory die 101 after the grinding operation is substantially less than the thickness T111 before the grinding operation. The thickness T212 of the substrate layer 21 of the interconnect die 102 after the grinding operation is substantially less than the thickness T211 before the grinding operation. The thickness T312 of the substrate layer 31 of the second memory die 103 after the grinding operation is substantially less than the thickness T311 before the grinding operation.

[0170] In some embodiments, the thickness T112 of the base layer 11 is in the range of 200 to 500 μm. In some embodiments, the thickness T212 of the base layer 21 is in the range of 220 to 520 μm. In some embodiments, the thickness T312 of the base layer 31 is substantially equal to the thickness T112 of the base layer 11. In some embodiments, the thickness T312 of the base layer 31 is in the range of 200 to 500 μm.

[0171] For the purpose of explanation and easy understanding, reference numerals 101B, 102B, and 103B are used throughout the specification to represent the respective rear surfaces of the substrate layers 11, 21, and 31 at different stages of the manufacturing process. However, the rear surfaces 101B, 102B, and 103B of the substrate layers 11, 21, and 31 may be in different planes at different stages of the manufacturing process.

[0172] like Figure 4 As shown, the rear surface 101B of the substrate layer 11 of the first memory die 101 is substantially aligned with the rear surface 102B of the substrate layer 21 of the interconnect die 102, and the rear surface 102B of the substrate layer 21 of the interconnect die 102 is substantially aligned with the rear surface 103B of the substrate layer 31 of the second memory die 103. In other words, the rear surface 101B of the substrate layer 11 of the first memory die 101, the rear surface 102B of the substrate layer 21 of the interconnect die 102, and the rear surface 103B of the substrate layer 31 of the second memory die 103 are substantially in the same plane. In some embodiments, the rear surface 101B of the substrate layer 11 of the first memory die 101, the rear surface 102B of the substrate layer 21 of the interconnect die 102, and the rear surface 103B of the substrate layer 31 of the second memory die 103 are substantially coplanar.

[0173] The molding material layer 41 includes an upper surface 41B that is at the same height as the rear surface 101B of the base layer 11 of the first memory die 101, the rear surface 102B of the base layer 21 of the interconnect die 102, or the rear surface 102B of the base layer 21 of the interconnect die 102. In some embodiments, the upper surface 41B of the molding material layer 41 is substantially coplanar with the rear surface 101B of the base layer 11, the rear surface 102B of the base layer 21, and the rear surface 103B of the base layer 31. This provides a flat surface P1 after the grinding operation. In some embodiments, the flat surface P1 is defined by the upper surface 41B of the molding material layer 41, the rear surface 101B of the base layer 11, the rear surface 102B of the base layer 21, and the rear surface 103B of the base layer 31. For illustrative purposes, after the grinding operation, the first memory die 101 , the interconnect die 102 , the second memory die 103 , and the molding material layer 41 are collectively referred to as an intermediate wafer 10 .

[0174] Please refer to Figure 5 , Figure 4 The carrier substrate C1 is shown separated (or de-bonded), and the intermediate wafer 10 is flipped and attached to the carrier substrate C2. After the carrier substrate C1 is debonded, the front surface 101A of the first memory die 101, the front surface 102A of the interconnect die 102, and the front surface 103A of the second memory die 103 are exposed.

[0175] In some embodiments, a bonding layer 52 is disposed above the carrier substrate C2. The planar surface P1 is attached to the carrier substrate C2 via the bonding layer 52. In some embodiments, the rear surface 101B of the base layer 11 of the first memory die 101 is attached to the carrier substrate C2 via the bonding layer 52. In some embodiments, the rear surface 102B of the interconnect die 102 is attached to the carrier substrate C2 via the bonding layer 52. In some embodiments, the rear surface 103B of the second memory die 103 is attached to the carrier substrate C2 via the bonding layer 52. It should be understood that the rear surface 101B of the base layer 11 defines a rear surface of the first memory die 101, and therefore, the rear surface 101B may also represent the rear surface of the first memory die 101. Similarly, the rear surface 102B of the base layer 21 defines the rear surface of the interconnect die 102, so the rear surface 102B can also represent the rear surface of the interconnect die 102; and the rear surface 103B of the base layer 31 defines the rear surface of the second memory die 103, so the rear surface 103B can also represent the rear surface of the second memory die 103.

[0176] In some embodiments, the intermediate wafer 10 is flipped before the carrier substrate C1 is peeled off. In some embodiments, the carrier substrate C2 is attached to the rear surfaces 101B, 102B, and 103B of the intermediate wafer 10 and the molding material layer 41 before the carrier substrate C1 is peeled off. In some embodiments, the carrier substrate C1 is peeled off while the intermediate wafer 10 is attached to the carrier substrate C2.

[0177] Please refer to Figure 6 A front-side redistribution layer 61 is formed over the intermediate wafer 10. In some embodiments, the front-side redistribution layer 61 covers the front surface 101A of the first memory die 101, the front surface 102A of the interconnect die 102, and the front surface 103A of the second memory die 103. In some embodiments, the front-side redistribution layer 61 also covers the molding material layer 41.

[0178] The front redistribution layer 61 may include a plurality of conductive elements arranged in multiple layers. The conductive elements may include metal lines 613 and metal vias 612. In some embodiments, the metal lines 613 are arranged in multiple metal line layers. In some embodiments, the metal vias 612 are arranged in multiple metal via layers. The metal via layers are alternately arranged between the metal line layers for electrical connection between the metal line layers. In some embodiments, each metal line layer includes a metal line 613 and an intermetallic dielectric layer surrounding the metal line. In some embodiments, each metal via layer includes a metal via and an intermetallic dielectric layer surrounding the metal via. The front redistribution layer 61 includes multiple intermetallic dielectric layers, and the multiple intermetallic dielectric layers are collectively referred to as an intermetallic dielectric structure 611.

[0179] like Figure 6 As shown, a plurality of conductive bumps 62 are formed above the front-side redistribution layer 61. Each conductive bump 62 penetrates a topmost intermetallic dielectric layer of the front-side redistribution layer 61 and is electrically connected to a metal line 613 disposed in a topmost metal line layer. The conductive bumps 62 are used to electrically connect each of the first memory die 101, the interconnect die 102, and the second memory die 103 to another die, die, substrate, or wafer.

[0180] In some embodiments, the via structure 22 is electrically connected to one or more metal lines 613 via metal vias 612. In some embodiments, the conductive element 323 of the interconnect structure 32 is electrically connected to one or more metal lines 613 via metal vias 612. In some embodiments, the conductive element 123 of the interconnect structure 12 is electrically connected to one or more metal lines 613 via metal vias 612. For illustrative purposes, the interposer wafer 10, the front-side redistribution layer 61, and the conductive bumps 62 are collectively referred to as an interposer wafer 20.

[0181] Figure 7 It is along Figure 6 A schematic top view of the intermediate wafer 10 along the cross-section line AA' is shown. In some embodiments, the via structures 22 are arranged in two lines, each extending along a first horizontal direction (e.g., the Y direction). In some embodiments, a first line of via structures 22 is adjacent to the first memory die 101, and a second line of via structures 22 is adjacent to the second memory die 103. In some embodiments, the via structures 22 in the first line are electrically isolated from the via structures 22 in the second line. In some embodiments, the conductive elements at the front surface 101A of the first memory die 101 are arranged in a plurality of lines along a second horizontal direction (e.g., the X direction), and each line extends along the first horizontal direction (e.g., the Y direction).

[0182] In some embodiments, a first line of via structures 22 is electrically connected to a line of conductive elements 123, where the line of conductive elements 123 is the line closest to the interconnect die 102. In some embodiments, each via structure 22 in a first line of the plurality of via structures 22 is aligned with a conductive element 123 in the closest line of the plurality of via structures 22 along a second direction (e.g., the X direction). In some embodiments, each via structure 22 in a first line of the plurality of via structures 22 is connected to each conductive element 123 in the closest line of the plurality of via structures 123 via a metal line 613 (indicated by a dotted line).

[0183] In some embodiments, a second line of via structures 22 is electrically connected to a line of conductive elements 323, where the line of conductive elements 323 is the line closest to the interconnect die 102. In some embodiments, each via structure 22 in the second line of the plurality of via structures 22 is aligned with a conductive element 323 in the closest line of the plurality of conductive elements 323 along a second direction (e.g., the X direction). In some embodiments, each via structure 22 in the second line of the plurality of via structures 22 is connected to each conductive element 323 in the closest line of the plurality of conductive elements 323 via a metal line 613 (indicated by a dotted line).

[0184] Please refer to Figure 8 , Figure 6 The carrier substrate C2 is shown separated (or peeled off), and the intermediate wafer 20 is flipped and attached to the carrier substrate C3. After peeling off the carrier substrate C2, the back surface 101B of the first memory die 101, the back surface 102B of the interconnect die 102, and the back surface 103B of the second memory die 103 are exposed.

[0185] In some embodiments, a bonding layer 53 is disposed over the carrier substrate C3. The middle wafer 20 is attached to the carrier substrate C3 through the bonding layer 52. In some embodiments, the front redistribution layer 61 is attached to the carrier substrate C3 via the bonding layer 53. In some embodiments, the topmost intermetal dielectric layer of the intermetal dielectric structure 611 contacts the bonding layer 53. In some embodiments, the conductive bumps 62 are embedded in the bonding layer 53. The conductive bumps 62 can or can not penetrate the bonding layer 53.

[0186] Please refer to Figure 9 , a planarization operation is performed. The planarization operation can include a lapping operation, a chemical mechanical polishing (CMP) operation, a wet etching operation, a dry etching operation, or a combination thereof. The thicknesses T112, T212, and T312 of the respective base layers 11, 21, and 31 of the first memory die 101, the interconnect die 102, and the second memory die 103, respectively, are reduced by the planarization.

[0187] In some embodiments, a surface portion of the base layer 11 of the first memory die 101 is removed by the planarization operation. In some embodiments, the thickness of the base layer 11 of the first memory die 101 is reduced from the thickness T112 (as shown in Figure 8 ) to a thickness T113 via the planarization operation. In some embodiments, a surface portion of the base layer 21 of the interconnect die 102 is removed by the planarization operation. In some embodiments, the thickness of the base layer 21 of the interconnect die 102 is reduced from the thickness T212 (as shown in Figure 8 ) to a thickness T213 via the planarization operation. In some embodiments, a surface portion of the base layer 31 of the second memory die 103 is removed by the planarization operation. In some embodiments, the thickness of the base layer 31 of the second memory die 103 is reduced from the thickness T312 (as shown in Figure 8 ) to a thickness T313 via the planarization operation. In some embodiments, a surface portion of the molding material layer 41 is removed by the planarization operation, thereby providing a planar surface P2.

[0188] The thickness T113 of the base layer 11 of the first memory die 101 after the planarization operation is substantially less than the thickness T112. The thickness T213 of the base layer 21 of the interconnect die 102 after the planarization operation is substantially less than the thickness T212. The thickness T313 of the base layer 11 of the second memory die 103 after the planarization operation is substantially less than the thickness T312.

[0189] In some embodiments, the thickness T113 of the base layer 11 is in a range from 150 to 300 pm. In some embodiments, the thickness T213 of the base layer 21 is in a range from 170 pm to 400 pm. In some embodiments, the thickness T313 of the base layer 31 is substantially equal to the thickness T113 of the base layer 11. In some embodiments, the thickness T313 of the base layer 31 is in a range from 150 pm to 300 pm.

[0190] After the planarization operation, the bottom 22B of the via structure 22 is located within the base layer 21. In some embodiments, the thickness T213 of the base layer 21 is substantially less than the depth T221 of the via structure 22. Figure 2

[0191] Referring to FIG. 1A, the carrier substrate C3 is separated (or peeled off) and removed. Thereby, a reconstituted wafer 1A is formed, which can be a top reconstituted wafer over a logic wafer as shown in FIG. 1B. Figure 10 Figure 9 Referring to FIG. 1A, the carrier substrate C3 is separated (or peeled off) and removed. Thereby, a reconstituted wafer 1A is formed, which can be a top reconstituted wafer over a logic wafer as shown in FIG. 1B. Figure 1

[0192] Referring to FIG. 1A, the carrier substrate C3 is separated (or peeled off) and removed. Thereby, a reconstituted wafer 1A is formed, which can be a top reconstituted wafer over a logic wafer as shown in FIG. 1B. Figure 11 Figure 8 Instead of the planarization operation shown in FIG. 1C, another planarization operation can be performed after the operation shown in FIG. 1A. Figure 9 Figure 11 The planarization operation shown in FIG. 1C is similar to the planarization operation shown in FIG. 1B, except that the planarization operation shown in FIG. 1C terminates at the point when the via structure 22 is exposed at the back surface 102B of the interconnect die 102 as shown in FIG. 1D. Figure 9 Figure 11 Figure 11 In some embodiments, after the planarization operation shown in FIG. 1C, the base layer 11 has a thickness T114, which is substantially less than the thickness T113 as shown in FIG. 1A or the thickness T112 as shown in FIG. 1B. In some embodiments, after the planarization operation shown in FIG. 1C, the base layer 21 has a thickness T214, which is substantially less than the thickness T213 as shown in FIG. 1A or the thickness T212 as shown in FIG. 1B. In some embodiments, after the planarization operation shown in FIG. 1C, the base layer 31 has a thickness T314, which is substantially less than the thickness T313 as shown in FIG. 1A or the thickness T312 as shown in FIG. 1B.

[0193] Figure 11 Figure 9 Figure 8 Figure 11 Figure 9 Figure 8 Figure 11 Figure 9 Figure 8 ​​​​​​​​​​​​​​​​​

[0194] In some embodiments, thickness T214 is substantially equal to Figure 2 The depth T221 of the through-hole structure 22 is shown. In some embodiments, the thickness T214 is in the range of 30 to 70 μm. In some embodiments, the thickness T114 is substantially less than the thickness T214. In some embodiments, the thickness T114 is in the range of 10 to 50 μm. In some embodiments, the thickness T314 is substantially equal to the thickness T114. In some embodiments, the thickness T314 is in the range of 10 to 50 μm.

[0195] In an alternative embodiment, Figure 11 The planarization operation shown also removes the bottom portion of the via structure 22 to ensure that all of the via structure 22 is exposed. In some embodiments, the thickness T214 is substantially less than Figure 2 The depth T221 of the through hole structure 22 is shown. In such an embodiment, Figure 11 The via structure 22 shown after planarization has a depth substantially greater than 20 μm.

[0196] Please refer to Figure 12 , a backside redistribution layer 63 is formed on Figure 11 In some embodiments, the backside redistribution layer 63 covers the intermediate structure shown. Figure 11 Shown are the back surface 101B of the first memory die 101, the back surface 102B of the interconnect die 102, and the back surface 103B of the second memory die 103. In some embodiments, the backside redistribution layer 63 also covers the molding material layer 41.

[0197] The back redistribution layer 63 includes a plurality of conductive elements arranged in multiple layers. The back redistribution layer 63 may be similar to the front redistribution layer 61, but has a smaller number of layers than the front redistribution layer 61. The detailed structure of the back redistribution layer 63 can refer to the above-mentioned front redistribution layer 61. For the purpose of illustration and simplification of the figure, only the topmost metal line layer (including multiple metal lines 633) surrounded by the intermetallic dielectric structure 631 (including multiple intermetallic dielectric layers) is shown in the figure. However, such a description is not intended to limit the present disclosure. The back redistribution layer 63 may also include another metal line layer and one or more metal through-hole layers, wherein each metal through-hole layer includes multiple metal through-holes. In some embodiments, the metal line 613 in the topmost metal line layer is exposed through the intermetallic dielectric structure 611 so as to be electrically connected to another reconstructed wafer disposed above it during subsequent processing.

[0198] Please refer to Figure 13 , Figure 12 The carrier substrate C3 shown is separated (or peeled off) and removed. Figure 1A reconstituted wafer 1B, 1C, or 1D is shown disposed between the logic wafer 6A and the top reconstituted wafer 1A.

[0199] The reconstituted wafers 1A, 1B, 1C, and 1D can be formed or fabricated in accordance with the methods as described above and Figures 2 to 13 The reconstituted wafer 1A, 1B, 1C, and 1D is then bonded to a logic wafer 6A.

[0200] Referring to Figure 14 , the reconstituted wafer 1D is disposed, attached, or bonded to the logic wafer 6A. In some embodiments, the conductive bumps 62 are electrically connected to the logic wafer 6A. In some embodiments, the logic wafer 6A can include a plurality of conductive pads on a side of the logic wafer 6A facing the reconstituted wafer 1D, and the conductive bumps 62 can contact the conductive pads of the logic wafer 6A, thereby electrically connecting the reconstituted wafer 1D to the logic wafer 6A.

[0201] Referring to Figure 15 , the reconstituted wafer 1C is disposed above the reconstituted wafer 1D. In some embodiments, the reconstituted wafer 1C is vertically aligned with the reconstituted wafer 1D.

[0202] Referring to Figure 16 , the reconstituted wafer 1C is bonded to the reconstituted wafer 1D. In some embodiments, as shown in Figure 15 , after the reconstituted wafer 1C is aligned with the reconstituted wafer 1D, the reconstituted wafer 1C is bonded to the reconstituted wafer 1D. As a result, the first memory die 101c of the reconstituted wafer 1C is vertically aligned with the first memory die 101d of the reconstituted wafer 1D; the interconnect die 102c of the reconstituted wafer 1C is vertically aligned with the interconnect die 102d of the reconstituted wafer 1D; and the second memory die 103c of the reconstituted wafer 1C is vertically aligned with the second memory die 103d of the reconstituted wafer 1D.

[0203] Referring to Figures 17 to 18 , the operations as shown in Figure 15 and Figure 16 are repeated to bond the reconstituted wafer 1B to the reconstituted wafer 1C, and then the reconstituted wafer 1A is bonded to the reconstituted wafer 1B.

[0204] Referring to Figure 19The molding material layer 42 is formed to surround the reconstituted wafer 1A, 1B, 1C, and 1D. In some embodiments, the molding material layer 42 fills a space between the reconstituted wafer 1A and 1B. In some embodiments, the molding material layer 42 fills a space between the reconstituted wafer 1B and 1C. In some embodiments, the molding material layer 42 fills a space between the reconstituted wafer 1C and 1D. In some embodiments, the molding material layer 42 fills a space between the reconstituted wafer 1D and the logic wafer 6A. In some embodiments, an upper surface of the molding material layer 42 is substantially aligned with an upper surface of the reconstituted wafer 1A. In some embodiments, the upper surface of the molding material layer 42 and the upper surface of the reconstituted wafer 1A are substantially coplanar.

[0205] Referring back to Figure 1 and Figure 19 The signals (or data stored in the first memory die 101d) can be transmitted from the first memory die 101d to the logic wafer 6A through the front redistribution layer 61d. In some embodiments, the signals (or data stored in the first memory die 101c) can be transmitted from the first memory die 101c to the logic wafer 6A through the front redistribution layer 61c, the back redistribution layer 63d, the interconnect die 102d, and the front redistribution layer 61d. In some embodiments, the signals (or data stored in the first memory die 101b) can be transmitted from the first memory die 101b to the logic wafer 6A through the front redistribution layer 61b, the back redistribution layer 63c, the interconnect die 102c, the front redistribution layer 61c, the back redistribution layer 63d, the interconnect die 102d, and the front redistribution layer 61d. In some embodiments, the signals (or data stored in the first memory die 101a) can be transmitted from the first memory die 101c to the logic wafer 6A through the front redistribution layer 61a, the back redistribution layer 63b, the interconnect die 102b, the front redistribution layer 61b, the back redistribution layer 63c, the interconnect die 102c, the front redistribution layer 61c, the back redistribution layer 63d, the interconnect die 102d, and the front redistribution layer 61d.

[0206] Similarly, in some embodiments, signals (or data stored in the second memory die 103d) can be transmitted from the second memory die 103d to the logic wafer 6A through the front redistribution layer 61d. In some embodiments, signals (or data stored in the second memory die 103c) can be transmitted from the second memory die 103c to the logic wafer 6A through the front redistribution layer 61c, the back redistribution layer 63d, the interconnect die 102d, and the front redistribution layer 61d. In some embodiments, signals (or data stored in the second memory die 103b) can be transmitted from the second memory die 103b to the logic wafer 6A through the front redistribution layer 61b, the back redistribution layer 63c, the interconnect die 102c, the front redistribution layer 61c, the interconnect die 102c, the front redistribution layer 61b, the back redistribution layer 63c. In some embodiments, signals (or data stored in the second memory die 103a) can be transmitted from the second memory die 103b to the logic wafer 6A through the front redistribution layer 61a, the back redistribution layer 63b, the interconnect die 102b, the front redistribution layer 61b, the back redistribution layer 63c, the interconnect die 102c, the front redistribution layer 61c, the back redistribution layer 63d, the interconnect die 102d, and the front redistribution layer 61d.

[0207] Conventional DRAM stack structures only include DRAM dies arranged vertically, and electrical transmission is achieved through vias arranged within the DRAM dies. However, the DRAM dies cannot be connected horizontally, and thus there is no horizontal arrangement of the DRAM dies. The size of the stack structure cannot be further reduced without reducing the total number of DRAM dies. In addition, the vias arranged in the DRAM dies occupy a certain area, and thus the size of the DRAM cannot be further reduced, and the circuit design of the DRAM dies is also relatively complex.

[0208] Compared with conventional DRAM stack structures, the semiconductor structure of the present disclosure includes DRAM dies arranged horizontally in a reconstituted wafer, and multiple reconstituted wafers can be stacked vertically. Therefore, compared with conventional DRAM stack structures, the semiconductor structure of the present disclosure can provide a reduced size with the same number of DRAM dies, or better performance and more number of DRAM dies with the same size of DRAM dies.

[0209] It should be understood that the via structure 22a in the topmost reconstituted wafer 1A can be considered as a virtual via structure. In other words, the via structure 22a in the topmost reconstituted wafer 1A does not function during operation. In alternative embodiments, the via structure 22a in the interconnect die 102a of the topmost reconstituted wafer 1A can be absent.

[0210] Reference is made to Figure 20, a semiconductor structure 2 according to some embodiments of the present disclosure is provided. The semiconductor structure 2 is similar to the semiconductor structure 1 as shown in Figure 1 and Figure 19 , except that there is no via structure 22a in the interconnect die 102a of the topmost reconstituted wafer 1A.

[0211] It should be understood that in the present disclosure, multiple embodiments of the present disclosure with the same inventive concept as described above are provided. For the purpose of clarity and simplicity, the element numbers of elements with the same or similar functions are repeated in different embodiments. However, such use is not intended to limit the present disclosure to a particular embodiment or a particular element. For the purpose of brevity, only the differences from other embodiments are emphasized in the following description, and the description of similar or identical elements, functions, and features is omitted. In addition, the conditions or parameters described in different embodiments can be combined or modified to form different combinations of embodiments, as long as the parameters or conditions used do not conflict.

[0212] As shown in Figure 20 , the interconnect die 102a of the topmost reconstituted wafer 1A does not include any via structure. In addition, there is no metal via connected to the interconnect die 102a. In Figure 20 embodiments, the interconnect die 102a does not provide electrical transmission functions. The presence of the interconnect die 102a is only for the purpose of requiring fewer changes to the manufacturing process. In some embodiments, the interconnect die 102a can provide better support for the reconstituted wafer 1A. In other embodiments, there is no interconnect die 102a in the topmost reconstituted wafer 1A, and the molding material layer 41a fills a space (not shown) between the first memory die 101a and the second memory die 103a.

[0213] Referring to Figure 21 , a semiconductor structure 3 according to some embodiments of the present disclosure is provided. The semiconductor structure 3 is similar to the semiconductor structure 1 as shown in Figure 1 and Figure 19 , except that the reconstituted wafers 2A, 2B, 2C, and 2D do not include the conductive bumps 62.

[0214] The conductive bumps 62 are used to bond the reconstituted wafers 1A, 1B, 1C, and 1D of the semiconductor structure 1 (as shown in Figure 10 and 13 ). However, the present disclosure is not limited thereto. The semiconductor structure 2 can include the reconstituted wafers 2A, 2B, 2C, and 2D, and the reconstituted wafers 2A, 2B, 2C, and 2D are bonded by hybrid bonding instead of by the conductive bumps 62.

[0215] Referring to Figure 22 , Figure 22A cross-sectional view of an example topmost reconstituted wafer 3A is shown. The reconstituted wafer 3A includes a front redistribution layer 65 instead of the front redistribution layer 61 shown. Figure 10 In some embodiments, the front redistribution layer 65 includes an intermetal dielectric structure 651, a plurality of metal vias 652, a plurality of metal lines 653, and a plurality of conductive segments 654. The front redistribution layer 65 is similar to the front redistribution layer 61, but also includes the conductive segments 654 exposed through the topmost intermetal dielectric layer of the intermetal dielectric structure 651. The conductive segments 654 are used for electrical connection and hybrid bonding to another reconstituted wafer.

[0216] Referring to Figure 23 , Figure 23 A cross-sectional view of an example reconstituted wafer 3B, 3C, or 3D is shown. The reconstituted wafer 3B, 3C, or 3D includes a front redistribution layer 65 similar to the front redistribution layer 65 of the reconstituted wafer 3A shown in Figure 22 In some embodiments, the back redistribution layer 67 includes an intermetal dielectric structure 671, a plurality of metal vias (not shown), a plurality of metal lines 673, and a plurality of conductive segments 674. The back redistribution layer 67 is similar to the back redistribution layer 63 shown in Figure 13 but also includes the conductive segments 674 exposed through the topmost intermetal dielectric layer of the intermetal dielectric structure 671. The conductive segments 674 are used for electrical connection and hybrid bonding to another reconstituted wafer.

[0217] Referring to Figure 24 , a semiconductor structure 4 according to some embodiments of the present disclosure is provided. The semiconductor structure 4 is similar to the semiconductor structure 3 shown in Figure 21 except that there is no via structure 22a in the interconnect die 102a of the topmost reconstituted wafer 1A.

[0218] As shown in Figure 24 , the interconnect die 102a of the topmost reconstituted wafer 4A does not include any via structure. In addition, there is no metal via connected to the interconnect die 102a. In Figure 24 embodiments, the interconnect die 102a does not provide electrical transport function. The presence of the interconnect die 102a is to require less change to the manufacturing process. In some embodiments, the interconnect die 102a can provide better support for the reconstituted wafer 4A. In other embodiments, there is no interconnect die 102a in the topmost reconstituted wafer 4A, and the molding material layer 41a fills a space (not shown) between the first memory die 101a and the second memory die 103a.

[0219] Referring to Figure 25The semiconductor structures 1, 2, 3, or 4 as described above can be applied in a semiconductor package. For example, the semiconductor structure 1 can be bonded to a substrate or an interposer 6B. In some embodiments, the semiconductor package as shown in Figure 25 The semiconductor package as shown in FIG. 1 can further include a central processing unit (CPU).

[0220] To conclude the description of the fabrication procedure of the above embodiments, a fabrication method S1 is provided.

[0221] Figure 26 is a flowchart illustrating the fabrication method S1 of the semiconductor structure of some embodiments of the present disclosure. The fabrication method S1 includes a plurality of steps (S11, S12, S13, and S14), and the description and the figure should not be considered as limiting to the order of the steps. In step S11, a first reconstituted wafer is formed. In step S12, a second reconstituted wafer is formed. In step S13, the first reconstituted wafer is disposed above a logic wafer. In step S14, the second reconstituted wafer is disposed above the first reconstituted wafer.

[0222] Each of the steps S11, S12, S13, and S14 can include a plurality of steps.

[0223] Figure 27 is a flowchart illustrating the step S11 of forming the first reconstituted wafer of some embodiments of the present disclosure. The step S11 includes a plurality of steps (S111, S112, S113, and S114), and the description and the figure should not be considered as limiting to the order of the steps. In step S111, a first memory die, a first interconnect die, and a second memory die are disposed above a first carrier substrate. In step S112, a first molding material layer is formed above the first carrier substrate, wherein the first molding material layer surrounds the first memory die, the first interconnect die, and the second memory die. In step S113, a first front redistribution layer (RDL) is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die. In step S114, a first back redistribution layer opposite to the first front redistribution layer is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die, thereby forming the first reconstituted wafer.

[0224] Figure 27is a flowchart illustrating steps S12 of forming a first reconstituted wafer according to some embodiments of the present disclosure. Steps S12 include a plurality of steps (S121, S122, and S123), and the description and drawings should not be considered limiting on the order of the steps. In step S121, a third memory die, a second interconnect die, and a fourth memory die are disposed over a second carrier substrate. In step S122, a second molding material layer is formed over the second carrier substrate and around the third memory die, the second interconnect die, and the fourth memory die. In step S123, a second front side redistribution layer is formed over the second molding material layer, the third memory die, the second interconnect die, and the fourth memory die, thereby forming the second reconstituted wafer.

[0225] The steps of the fabrication method S1 can be rearranged or otherwise modified within the scope of various aspects. In some embodiments, additional processes are also provided before, during, and after the fabrication method S1, and only some of the other processes are briefly described herein.

[0226] Accordingly, the present disclosure provides novel configurations of stacked memory dies. The semiconductor structure of the present disclosure includes DRAM dies arranged horizontally in a reconstituted wafer, and multiple reconstituted wafers can be stacked vertically. Accordingly, compared to conventional DRAM stacked structures, the semiconductor structure of the present disclosure can provide a smaller size with the same number of DRAM dies, or better performance and more number of DRAM dies with the same size of the final structure.

[0227] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a logic wafer; a first front side redistribution layer (RDL) disposed over the logic wafer; a first memory die disposed over the first front side redistribution layer; a second memory die disposed over the first front side redistribution layer, wherein the first memory die and the second memory die are arranged horizontally; and a first interconnect die disposed over the first front side redistribution layer between the first memory die and the second memory die, wherein the first memory die is electrically connected to a first via in the first interconnect die, and the second memory die is electrically connected to a second via in the first interconnect die.

[0228] In some embodiments, the first memory die is electrically connected to the first via in the first interconnect die through the first front side redistribution layer.

[0229] In some embodiments, the second memory die is electrically connected to the second via in the first interconnect die through the first front side redistribution layer.

[0230] In some embodiments, the first memory die and the second memory die are electrically connected to the logic wafer through the first front redistribution layer, respectively.

[0231] In some embodiments, the first via and the second via penetrate the first interconnect die.

[0232] In some embodiments, a thickness of the first interconnect die is in a range of 30 to 70 micrometers.

[0233] In some embodiments, the first front redistribution layer, the first memory die, the second memory die, and the first interconnect die are disposed in the first reconstituted wafer, and the semiconductor structure further comprises: a second reconstituted wafer disposed above the first reconstituted wafer, wherein the second reconstituted wafer comprises: a second front redistribution layer disposed above and electrically connected to the first reconstituted wafer; a third memory die disposed above the second front redistribution layer; a fourth memory die disposed above the second front redistribution layer, wherein the third memory die and the fourth memory die are horizontally arranged; and a second interconnect die disposed above the second front redistribution layer between the third memory die and the fourth memory die, wherein the third memory die is electrically connected to a third via in the second interconnect die, and the fourth memory die is electrically connected to a fourth via in the second interconnect die.

[0234] In some embodiments, the first reconstituted wafer further comprises: a first back redistribution layer disposed above the first memory die, the first interconnect die, and the second memory die, wherein the second front redistribution layer is electrically connected to the first back redistribution layer.

[0235] In some embodiments, the second front redistribution layer is electrically connected to the first back redistribution layer through a plurality of conductive bumps.

[0236] In some embodiments, the second front redistribution layer is electrically connected to the first back redistribution layer through conductive elements and dielectric layers of the second front redistribution layer and the first back redistribution layer, respectively.

[0237] In some embodiments, the first via and the second via penetrate the first interconnect die, and the third via and the fourth via terminate within the second interconnect die.

[0238] In some embodiments, a thickness of the first interconnect die is substantially less than a thickness of the second interconnect die.

[0239] In some embodiments, the third memory die is electrically connected to the logic wafer through the first via or the second via in the first interconnect die.

[0240] In some embodiments, the third memory die and the first memory die are vertically aligned.

[0241] In some embodiments, the fourth memory die and the second memory die are vertically aligned.

[0242] In some embodiments, the first interconnect die and the second interconnect die are vertically aligned.

[0243] Another embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes a first reconstituted wafer disposed above a logic wafer, and a second reconstituted wafer disposed vertically above the first reconstituted wafer. The first reconstituted wafer includes a first frontside redistribution layer, a first memory die disposed above the first frontside redistribution layer, a second memory die disposed above the first frontside redistribution layer, wherein the second memory die is horizontally aligned with the first memory die, and a first interconnect die disposed above the first frontside redistribution layer and between the first memory die and the second memory die. The second reconstituted wafer includes a second frontside redistribution layer, a third memory die disposed above the second frontside redistribution layer, wherein a thickness of the third memory die is substantially greater than a thickness of the first memory die, and a fourth memory die disposed above the second frontside redistribution layer and adjacent to the third memory die, wherein a thickness of the fourth memory die is substantially greater than a thickness of the second memory die.

[0244] In some embodiments, the first interconnect die includes a first via and a second via adjacent to the first via, and the first via and the second via are electrically isolated from each other.

[0245] In some embodiments, the second reconstituted wafer further includes a second interconnect die disposed above the second frontside redistribution layer and between the third memory die and the fourth memory die, wherein there is no via structure in the second interconnect die.

[0246] In some embodiments, the second reconstituted wafer further includes a second interconnect die disposed above the second frontside redistribution layer and between the third memory die and the fourth memory die, wherein the second interconnect die includes a base layer and a plurality of via structures terminating within the base layer.

[0247] Another embodiment of the present disclosure provides a method of fabricating a semiconductor structure. The method includes a plurality of steps. A first reconstituted wafer is formed. A second reconstituted wafer is formed. The first reconstituted wafer is disposed above a logic wafer. The second reconstituted wafer is disposed above the first reconstituted wafer. The first reconstituted wafer is formed including a plurality of steps. A first memory die, a first interconnect die, and a second memory die are disposed above a first carrier substrate. A first molding material layer is formed above the first carrier substrate and around the first memory die, the first interconnect die, and the second memory die. A first backside redistribution layer is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die. A first frontside redistribution layer is formed above the first molding material layer, the first memory die, the first interconnect die, and the second memory die opposite the first backside redistribution layer, thereby forming the first reconstituted wafer. The second reconstituted wafer is formed including a plurality of steps. A third memory die, a second interconnect die, and a fourth memory die are disposed above a second carrier substrate. A second molding material layer is formed above the second carrier substrate and around the third memory die, the second interconnect die, and the fourth memory die. A second frontside redistribution layer is formed above the second molding material layer, the third memory die, the second interconnect die, and the fourth memory die, thereby forming the second reconstituted wafer.

[0248] In some embodiments, the forming of the first reconstituted wafer further includes performing a lapping operation after the first molding material layer is formed on respective back surfaces of the first memory die, the first interconnect die, and the second memory die, thereby forming a planar surface at the respective back surfaces of the first memory die, the first interconnect die, and the second memory die.

[0249] In some embodiments, the method of fabricating further includes detaching the first carrier substrate from the first memory die, the first interconnect die, and the second memory die; and attaching a second carrier substrate on the planar surface at respective back surfaces of the first memory die, the first interconnect die, and the second memory die prior to forming the first frontside redistribution layer.

[0250] In some embodiments, the method of fabricating further includes detaching the second carrier substrate from the first memory die, the first interconnect die, and the second memory die after forming the first frontside redistribution layer.

[0251] In some embodiments, the forming of the first reconstituted wafer further includes reducing a thickness of the first interconnect die until each of a plurality of vias disposed in the first interconnect die is exposed prior to forming the first backside redistribution layer.

[0252] In some embodiments, after reducing the thickness of the first interconnect die, the thickness of the first interconnect die is in a range of 30 to 70 microns.

[0253] In some embodiments, forming the first reconstituted wafer further comprises: reducing a thickness of the first memory die while reducing a thickness of the first interconnect die.

[0254] In some embodiments, forming the first reconstituted wafer further includes reducing a thickness of the second memory die while reducing a thickness of the first interconnect die.

[0255] In some embodiments, the preparation method further includes: aligning the second reconstructed wafer above the first reconstructed wafer; and bonding the first backside redistribution layer of the first reconstructed wafer to the second frontside redistribution layer of the second reconstructed wafer.

[0256] In some embodiments, forming the second reconstituted wafer further comprises: reducing thicknesses of the first interconnect die, the third memory die, and the fourth memory die after forming the second front-side redistribution layer.

[0257] In some embodiments, after reducing the thicknesses of the second interconnect die, the third memory die, and the fourth memory die, bottoms of the through-vias disposed in the second interconnect die remain covered.

[0258] In some embodiments, after reducing respective thicknesses of the second interconnect die, the third memory die, and the fourth memory die, the thickness of the second interconnect die is in a range of 60 to 200 microns.

[0259] In some embodiments, the preparation method further includes: forming a third molding material layer above the logic wafer and surrounding the first reconstructed wafer and the second reconstructed wafer.

[0260] In some embodiments, the fabrication method also includes attaching the logic wafer to an interposer.

[0261] In some embodiments, the first layer of molding material is the same as the second layer of molding material.

[0262] In view of the foregoing, a semiconductor structure and a method of fabricating the same are disclosed. The disclosure provides a novel configuration of stacked memory dies. The semiconductor structure of the disclosure includes DRAM dies arranged horizontally in a reconstituted wafer, where multiple reconstituted wafers can be stacked vertically. Thus, the semiconductor structure of the disclosure can provide a reduced size with the same number of DRAM dies, or better performance and more number of DRAM dies with the same size of DRAM dies, as compared to conventional DRAM stacked structures.

[0263] While the disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be performed in a different order, and / or the processes described above can be altered or replaced by other processes or combinations thereof.

[0264] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily understand, the disclosure can be practiced with other process, machine, manufacture, composition of matter, means, methods, or steps analogous to those described herein. Accordingly, the disclosure includes all modifications and equivalents of the processes, machine, manufacture, composition of matter, means, methods, and steps as defined by the claims.

Claims

1. A semiconductor structure comprising: a logic wafer; a first front-side redistribution layer disposed above the logic wafer; a first memory die disposed above the first front-side redistribution layer; a second memory die disposed above the first front-side redistribution layer, wherein the first memory die and the second memory die are arranged horizontally; and A first interconnect die is disposed above the first front-side redistribution layer between the first memory die and the second memory die, wherein the first memory die is electrically connected to a first via in the first interconnect die, and the second memory die is electrically connected to a second via in the first interconnect die. 2 . The semiconductor structure of claim 1 , wherein the first memory die is electrically connected to the first via in the first interconnect die through the first front-side redistribution layer. 3 . The semiconductor structure of claim 1 , wherein the second memory die is electrically connected to the second via in the first interconnect die through the first front-side redistribution layer. 4 . The semiconductor structure of claim 1 , wherein the first memory die and the second memory die are respectively electrically connected to the logic wafer through the first front-side redistribution layer. The semiconductor structure as claimed in claim 1 , wherein the first through-via and the second through-via penetrate the first interconnect die. 6 . The semiconductor structure of claim 5 , wherein a thickness of the first interconnect die is in a range of 30 to 70 μm.

7. The semiconductor structure of claim 1 , wherein the first front-side redistribution layer, the first memory die, the second memory die, and the first interconnect die are disposed in a first reconstituted wafer, and the semiconductor structure further comprises: a second reconstructed wafer disposed above the first reconstructed wafer, wherein the second reconstructed wafer comprises: a second front-side redistribution layer disposed above the first reconstituted wafer and electrically connected to the first reconstituted wafer; a third memory die disposed above the second front-side redistribution layer; a fourth memory die disposed above the second front-side redistribution layer, wherein the third memory die and the fourth memory die are arranged horizontally; and A second interconnect die is disposed above the second front-side redistribution layer between the third memory die and the fourth memory die, wherein the third memory die is electrically connected to a third via in the second interconnect die, and the fourth memory die is electrically connected to a fourth via in the second interconnect die.

8. The semiconductor structure of claim 7 , wherein the first reconstituted wafer further comprises: A first backside redistribution layer is disposed above the first memory die, the first interconnect die, and the second memory die, wherein the second frontside redistribution layer is electrically connected to the first backside redistribution layer. 9 . The semiconductor structure of claim 8 , wherein the second front-side redistribution layer is electrically connected to the first back-side redistribution layer through a plurality of conductive bumps. 10 . The semiconductor structure of claim 8 , wherein the second front-side redistribution layer is electrically connected to the first back-side redistribution layer through a plurality of conductive elements and a plurality of dielectric layers of the second front-side redistribution layer and the first back-side redistribution layer. 11 . The semiconductor structure of claim 7 , wherein the first via and the second via penetrate the first interconnect die, and the third via and the fourth via terminate within the second interconnect die. 12 . The semiconductor structure of claim 7 , wherein a thickness of the first interconnect die is substantially smaller than a thickness of the second interconnect die. 13 . The semiconductor structure of claim 7 , wherein the third memory die is electrically connected to the logic wafer through the first via or the second via in the first interconnect die.

14. The semiconductor structure of claim 7, wherein the third memory die and the first memory die are vertically aligned. 15 . The semiconductor structure of claim 7 , wherein the fourth memory die and the second memory die are vertically aligned.

16. The semiconductor structure of claim 7, wherein the first interconnect die and the second interconnect die are vertically aligned.

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